Ð þíú-8ñÌ(añ”6STMicroelectronics STM32MP157C-ED1 SCMI eval daughter9!st,stm32mp157c-ed1-scmist,stm32mp157c-ed1st,stm32mp157cpuscpu@0!arm,cortex-a7,&¾6€;rxtx  disabledaudio-controller@4000c000!st,stm32h7-i2syH@À [3 6=>;rxtx  disabledaudio-controller@4000d000!st,stm32h7-spdifrxyH@ÐL*kclk [a 6]^ ;rxrx-ctrl  disabledserial@4000e000!st,stm32h7-uartH@à P L•d 6+,;rxtx  disabledserial@4000f000!st,stm32h7-uartH@ð P L–d 6-.;rxtx  disabledserial@40010000!st,stm32h7-uartH@ P L—d okayŠdefaultsleepidle˜ ¢ ¬ serial@40011000!st,stm32h7-uartH@ P L˜d 6AB;rxtx  disabledi2c@40012000!st,stm32mp15-i2cH@  eventerror[ L‰rL ¶dÄ  disabledi2c@40013000!st,stm32mp15-i2cH@0 eventerror[!"LŠrL ¶dÄ  disabledi2c@40014000!st,stm32mp15-i2cH@@ eventerror[HIL‹rL ¶dÄ  disabledi2c@40015000!st,stm32mp15-i2cH@P eventerror[klLrL ¶dÄ  disabledcec@40016000 !st,stm32-cecH@` [^Lˆ *cechdmi-cec  disableddac@40017000!st,stm32h7-dac-coreH@pL*pclk  disabledŠdefault˜ Ödac@1 !st,stm32-dacâH okaydac@2 !st,stm32-dacâH okayserial@40018000!st,stm32h7-uartH@€ P Lšd 6OP;rxtx  disabledserial@40019000!st,stm32h7-uartH@ P !L›d 6QR;rxtx  disabledtimer@44000000!st,stm32-timersHD0[brkuptrg-comccLÎ*intp6   ;ch1ch2ch3ch4uptrigcom  disabledpwm !st,stm32-pwmE  disabledtimer@0!st,stm32h7-timer-triggerH  disabledcounter!st,stm32-timer-counter  disabledtimer@44001000!st,stm32-timersHD0[+,-.brkuptrg-comccLÏ*intp6/012345;ch1ch2ch3ch4uptrigcom  disabledpwm !st,stm32-pwmE  disabledtimer@7!st,stm32h7-timer-triggerH  disabledcounter!st,stm32-timer-counter  disabledserial@44003000!st,stm32h7-uartHD0 P L™d 6GH;rxtx  disabledspi@44004000!st,stm32h7-spiHD@ [#L‚rLH 6%&;rxtx  disabledaudio-controller@44004000!st,stm32h7-i2syHD@ [# 6%&;rxtx  disabledspi@44005000!st,stm32h7-spiHDP [TL…rLI 6ST;rxtx  disabledtimer@44006000!st,stm32-timersHD` [tglobalLÐ*int@6ijkl;ch1uptrigcom  disabledpwm !st,stm32-pwmE  disabledtimer@14!st,stm32h7-timer-triggerH  disabledtimer@44007000!st,stm32-timersHDp [uglobalLÑ*int 6mn;ch1up  disabledpwm !st,stm32-pwmE  disabledtimer@15!st,stm32h7-timer-triggerH  disabledtimer@44008000!st,stm32-timersHD€ [vglobalLÒ*int 6op;ch1up  disabledpwm !st,stm32-pwmE  disabledtimer@16!st,stm32h7-timer-triggerH  disabledspi@44009000!st,stm32h7-spiHD [UL†rLJ 6UV;rxtx  disabledsai@4400a000!st,stm32h7-sai D HD D£ð [WrLP  disabledaudio-controller@4400a004y!st,stm32-sai-sub-aH Lž*sai_ck6W  disabledaudio-controller@4400a024y!st,stm32-sai-sub-bH$ Lž*sai_ck6X  disabledsai@4400b000!st,stm32h7-sai D°HD°D³ð [[rLQ  disabledaudio-controller@4400b004y!st,stm32-sai-sub-aH LŸ*sai_ck6Y  disabledaudio-controller@4400b024y!st,stm32-sai-sub-bH$ LŸ*sai_ck6Z  disabledsai@4400c000!st,stm32h7-sai DÀHDÀDÃð [rrLR  disabledaudio-controller@4400c004y!st,stm32-sai-sub-aH L *sai_ck6q  disabledaudio-controller@4400c024y!st,stm32-sai-sub-bH$ L *sai_ck6r  disableddfsdm@4400d000!st,stm32mp1-dfsdmHDÐLœ*dfsdm  disabledfilter@0!st,stm32-dfsdm-adcâH [n6e;rx  disabledfilter@1!st,stm32-dfsdm-adcâH [o6f;rx  disabledfilter@2!st,stm32-dfsdm-adcâH [p6g;rx  disabledfilter@3!st,stm32-dfsdm-adcâH [q6h;rx  disabledfilter@4!st,stm32-dfsdm-adcâH [s6[;rx  disabledfilter@5!st,stm32-dfsdm-adcâH [~6\;rx  disableddma-controller@48000000 !st,stm32-dmaHH`[   /LGrLÀôÿ Sdma-controller@48001000 !st,stm32-dmaHH`[89:;<DEFLHrLÁôÿ Sdma-router@48002000!st,stm32h7-dmamuxHH @ô €#LIrLÂSadc@48003000!st,stm32mp1-adc-coreHH0[ZLJ¢*busadc¢‘  disabled˜Šdefault0;ÖSadc@0!st,stm32mp1-adcâHy[6 ;rx okaychannel@0HGchannel@1HGchannel@6HGadc@100!st,stm32mp1-adcâHy[6 ;rx]ivrefint  disabledchannel@13H zvrefintchannel@14Hzvddcoremmc@48004000(!st,stm32-sdmmc2arm,pl18xarm,primecell€%1€HH@ [‰Lx *apb_pclkrLЗ¨º'  disabledusb-otg@49000000!st,stm32mp15-hsotgsnps,dwc2HI L¦ *otgutmirLÈÈdwc2 [bÔã  õotg   disabled"mailbox@4c001000!st,stm32mp1-ipcc.HL:P =erxtxLSd okayS?dcmi@4c006000!st,stm32-dcmiHL` [NrMLM*mclk6K;tx  disabledrcc@50000000!st,stm32mp1-rcc-securesysconHPER*hsehsicsilselsi(LSpwr@50001000!st,stm32mp1,pwr-regHP0_reg11treg11ƒÈà›Èà  disabledreg18treg18ƒw@›w@  disabledS6usb33tusb33ƒ2Z ›2Z   disabledpwr_mcu@50001014!st,stm32mp151-pwr-mcusysconHPS7interrupt-controller@5000d000!st,stm32mp1-extisyscon¢‘HPÐS syscon@50020000!st,stm32mp157-syscfgsysconHPL3Stimer@50021000!st,stm32-lptimerHP P 0L*muxd  disabledpwm!st,stm32-pwm-lpE  disabledtrigger@1!st,stm32-lptimer-triggerH  disabledcounter!st,stm32-lptimer-counter  disabledtimer@50022000!st,stm32-lptimerHP  P 2L‘*muxd  disabledpwm!st,stm32-pwm-lpE  disabledtrigger@2!st,stm32-lptimer-triggerH  disabledtimer@50023000!st,stm32-lptimerHP0 P 4L’*muxd  disabledpwm!st,stm32-pwm-lpE  disabledtimer@50024000!st,stm32-lptimerHP@ P 5L“*muxd  disabledpwm!st,stm32-pwm-lpE  disabledvrefbuf@50025000!st,stm32-vrefbufHPPƒã`›&% L4  disabledsai@50027000!st,stm32h7-sai PpHPpPsð [’rLˆ  disabledaudio-controller@50027004y!st,stm32-sai-sub-aH L¡*sai_ck6c  disabledaudio-controller@50027024y!st,stm32-sai-sub-bH$ L¡*sai_ck6d  disabledthermal@50028000!st,stm32-thermalHP€ [“L5*pclk³ okayShash@54002000!st,stm32f756-hashHT  [PL r6 ;inÉ okayrng@54003000 !st,stm32-rngHT0Lr okaydma-controller@58000000!st,stm32h7-mdmaHX [zLdr ô#  0Smemory-controller@58002000!st,stm32mp1-fmc2-ebiHX Lyr Ì  disabledP`dhl€nand-controller@4,0!st,stm32mp1-fmc2-nfcHH   [0H6    ;txrxecc  disabledspi@58003000!st,stm32f469-qspiHX0p Öqspiqspi_mm [\06;txrxLzr Î  disabledmmc@58005000(!st,stm32-sdmmc2arm,pl18xarm,primecell€%1€HXP [1Lv *apb_pclkr З¨º' okayŠdefaultopendrainsleep˜¢¬  à!éôÿ !"-#:GTammc@58007000(!st,stm32-sdmmc2arm,pl18xarm,primecell€%1€HXp [|Lw *apb_pclkr Ñ—¨º' okayŠdefaultopendrainsleep˜$%¢&%¬'(n|‚ÿ!)-Šcrc@58009000!st,stm32f7-crcHXLn okayethernet@5800a000#!st,stm32mp1-dwmacsnps,dwmac-4.20aHX   ÖstmmacethP=macirq6*stmmacethmac-clk-txmac-clk-rxeth-ckptp_refethstp0Ligh{©p—¡²»Ö*æ  disabledstmmac-axi-configïÿS*usb@5800c000 !generic-ohciHXÀ Lor Ø [J  disabledS+usb@5800d000 !generic-ehciHXÐ Lor Ø [K+  disableddisplay-controller@5a001000!st,stm32-ltdcHZ[XYL§*lcdr   disabledwatchdog@5a002000!st,stm32mp1-iwdgHZ L: *pclklsi okay# usbphyc@5a006000E!st,stm32mp1-usbphycHZ`Lr /,>-  disabledSusb-phy@0MHXusb-phy@1MHXserial@5c000000!st,stm32h7-uartH\ P L”d  disabledspi@5c001000!st,stm32h7-spiH\ [VL‡r @06"#;rxtx  disabledi2c@5c002000!st,stm32mp15-i2cH\  eventerror[_`L r ¶dÄ okayŠdefaultsleep˜.¢/c¹z,€stpmic@33 !st,stpmic1H3 P0¢‘ okayregulators!st,stpmic1-regulators’1Ÿ1¬1¹1Æ)Ò)Þ2ê1ö))11+3:3buck1tvddcoreƒO€›™pI]tbuck2tvdd_ddrƒ™p›™pI]tS2buck3tvddƒ2Z ›2Z I–]tSbuck4tv3v3ƒ2Z ›2Z It]S)ldo1tvddaƒ,@ ›,@ [Sldo2tv2v8ƒ*¹€›*¹€[ldo3tvtt_ddrƒ¡ › q°Itldo4tvdd_usb[Sldo5tvdd_sdƒ,@ ›,@ [¤S"ldo6tv1v8ƒw@›w@[vref_ddr tvref_ddrIboosttbst_out[S3pwr_sw1 tvbus_otg[ Spwr_sw2tvbus_sw[ ¶onkey!st,stpmic1-onkey[onkey-fallingonkey-risingÑ  okaywatchdog!st,stpmic1-wdt  disabledrtc@5c004000!st,stm32mp1-rtcH\@L *pclkrtc_ck P  okayefuse@5c005000!st,stm32mp15-bsecH\Ppart-number-otp@4Hvrefin-cal@52HRScalib@5cH\calib@5eH^i2c@5c009000!st,stm32mp15-i2cH\ eventerror[‡ˆLŽr C ¶ dÄ  disabledtamp@5c00a000 !st,stm32-tampsysconsimple-mfdH\ S8pinctrl@50002000!st,stm32mp157-pinctrl P ¤y   `ÿäS4gpio@50002000ïÿ¢‘HLT GPIOA okay4S0gpio@50003000ïÿ¢‘HLU GPIOB okay4gpio@50004000ïÿ¢‘H LV GPIOC okay4 gpio@50005000ïÿ¢‘H0LW GPIOD okay40gpio@50006000ïÿ¢‘H@LX GPIOE okay4@gpio@50007000ïÿ¢‘HPLY GPIOF okay4PS@gpio@50008000ïÿ¢‘H`LZ GPIOG okay4`S!gpio@50009000ïÿ¢‘HpL[ GPIOH okay4pgpio@5000a000ïÿ¢‘H€L\ GPIOI okay4€gpio@5000b000ïÿ¢‘HL] GPIOJ okay4gpio@5000c000ïÿ¢‘H L^ GPIOK okay4 adc1-ain-0pins+[ #adc1-in6-0Spins+\adc12-ain-0pins+#\]^adc12-ain-1pins+\]adc12-usb-cc-pins-0pins+cec-0pins+2?Pcec-sleep-0pins+cec-1pins+2?Pcec-sleep-1pins+dac-ch1-0S pins+dac-ch2-0Spins+dcmi-0pins<+xyz{|~„Fwƒ2dcmi-sleep-0pins<+xyz{|~„Fwƒdcmi-1pins,+&z{AK3M2dcmi-sleep-1pins,+&z{AK3Mdcmi-2pins4+ z@A~„†FwZdcmi-sleep-2pins4+ z@A~„†Fwrgmii-0pins1 +e d m n " B  ! 2gPpins2+ 2gPpins3+$ %     2rgmii-sleep-0pins1<+edmn"B!$%rgmii-1pins1 +e d m n " B  ! 2gPpins2+ 2gPpins3+$ % v w   2rgmii-sleep-1pins1<+edmn"B!$%vwrgmii-2pins1 +e d  n " B k ! 2gPpins2+ 2gPpins3+$ % v    2rgmii-sleep-2pins1<+edn"Bk!$%vrgmii-3pins1+e m n " B  ! 2gPpins2+ 2gPpins3+$ % v    2rgmii-sleep-3pins1<+edmn"B!$%vrgmii-4pins1+d m n " B  2gPpins2+$ % v w   2rgmii-sleep-4pins10+dmn"B$%vwrmii-0pins1+m n   ! 2gPpins2 +$ %  2rmii-sleep-0pins1$+mn!$%rmii-1pins1+! m n 2gPpins2+ 2gPpins3 + $ % 2pins4+ rmii-sleep-1pins1$+!$%mnrmii-2pins1+m n    ! 2gPpins2 +$ %  2rmii-sleep-2pins1$+mn!$%fmc-0pins14+4 5 ; < > ? 0 1 G H I J i 2gPpins2+6 Zfmc-sleep-0pins8+45;<>?01GHIJ6ifmc-1pinsT+4 5  > ? 0 1 G H I J K L M N O 8 9 : i l 2gPfmc-sleep-1pinsT+45>?01GHIJKLMNO89:ili2c1-0pins+<_2?Pi2c1-sleep-0pins+<_i2c1-1pins+^_2?Pi2c1-sleep-1pins+^_i2c2-0pins+tu2?Pi2c2-sleep-0pins+tui2c2-1pins+u2?Pi2c2-sleep-1pins+ui2c2-2pins+Qu2?Pi2c2-sleep-2pins+Qui2c5-0pins+  2?Pi2c5-sleep-0pins+  i2c5-1pins+012?Pi2c5-sleep-1pins+01i2s2-0pins +ƒ Pg2i2s2-sleep-0pins +ƒ ltdc-0pinsp+gŠ‰Zrsxyz |OEF}~€‚9lj:„82gPltdc-sleep-0pinsp+gŠ‰Zrsxyz |OEF}~€‚9lj:„8ltdc-1pinsp+ŽŒ§‘’“”•–—˜™š› ¡¢œžŸ£¤¥¦2gPltdc-sleep-1pinsp+ŽŒ§‘’“”•–—˜™š› ¡¢œžŸ£¤¥¦ltdc-2pins1T+  36:KLMOt xyz}…†‰Š2gPpins2+N2gPltdc-sleep-2pins1X+ 36:KLMOtxyz}…†‰ŠNltdc-3pins1+g2gPpins2l+Š‰Mmsxy{|OE}Kt ‹ h9lj:L‡2gPltdc-sleep-3pinsp+gŠ‰Mmsxy{|OE}Kt‹h9lj:L‡mco1-0pins+ 2gPmco1-sleep-0pins+ mco2-0pins+b2gPmco2-sleep-0pins+bm-can1-0pins1+} Pg2pins2+‰ 2m_can1-sleep-0pins+}‰m-can1-1pins1+ Pg2pins2+ 2m_can1-sleep-1pins+  m-can1-2pins1+} Pg2pins2+~ 2m_can1-sleep-2pins+}~m-can2-0pins1+ Pg2pins2+ 2m_can2-sleep-0pins+pwm1-0pins +IKNwgPpwm1-sleep-0pins +IKNpwm1-1pins+IwgPpwm1-sleep-1pins+Ipwm1-2pins+KgPpwm1-sleep-2pins+Kpwm2-0pins+wgPpwm2-sleep-0pins+pwm3-0pins+'wgPpwm3-sleep-0pins+'pwm3-1pins+2gPpwm3-sleep-1pins+pwm4-0pins+>?wgPpwm4-sleep-0pins+>?pwm4-1pins+=wgPpwm4-sleep-1pins+=pwm5-0pins+{wgPpwm5-sleep-0pins+{pwm5-1pins +{|€2gPpwm5-sleep-1pins +{|€pwm8-0pins+‚wgPpwm8-sleep-0pins+‚pwm8-1pins+…†‡)gPpwm8-sleep-1pins+…†‡)pwm12-0pins+vwgPpwm12-sleep-0pins+vqspi-clk-0pins+Z 2gPqspi-clk-sleep-0pins+Zqspi-bk1-0pins+X Y W V 2gPqspi-bk1-sleep-0pins+XYWVqspi-bk2-0pins+r s j g 2gPqspi-bk2-sleep-0pins+rsjgqspi-cs1-0pins+ ZgPqspi-cs1-sleep-0pins+qspi-cs2-0pins+ ZgPqspi-cs2-sleep-0pins+ sai2a-0pins+… † ‡ @ Pg2sai2a-sleep-0pins+…†‡@sai2a-1pins1 +† ‡ = Pg2sai2a-sleep-1pins +†‡=sai2a-2pins += ; < Pg2sai2a-sleep-2pins +=;<sai2b-0pins1 +L M N Pg2pins2+[ 2sai2b-sleep-0pins+[LMNsai2b-1pins+[ 2sai2b-sleep-1pins+[sai2b-2pins1+[ 2sai2b-sleep-2pins+[sai2b-3pins1 +r s Pg2pins2+[ 2sai2b-sleep-3pins1+r s[sai4a-0pins+ Pg2sai4a-sleep-0pins+sdmmc1-b4-0Spins1+( ) * + 2 Pg2pins2+, Pg2sdmmc1-b4-od-0Spins1+( ) * + Pg2pins2+, Pg2pins3+2 P?2sdmmc1-b4-init-0pins1+( ) * + Pg2sdmmc1-b4-sleep-0Spins+()*+,2sdmmc1-b4-1pins1+( ) F + 2 Pg2pins2+, Pg2sdmmc1-b4-od-1pins1+( ) F + Pg2pins2+, Pg2pins3+2 P?2sdmmc1-b4-sleep-1pins+()F+,2sdmmc1-dir-0Spins1 +R '  PgZpins2+D Zsdmmc1-dir-init-0pins1 +R '  PgZsdmmc1-dir-sleep-0S pins+R'Dsdmmc1-dir-1pins1 +R N  PgZpins2+D Zsdmmc1-dir-sleep-1pins+RNDsdmmc2-b4-0S$pins1+    f PgZpins2+C PgZsdmmc2-b4-od-0S&pins1+    PgZpins2+C PgZpins3+f P?Zsdmmc2-b4-sleep-0S'pins+Cfsdmmc2-b4-1pins1+    f Pg2pins2+C Pg2sdmmc2-b4-od-1pins1+    Pg2pins2+C Pg2pins3+f P?2sdmmc2-d47-0S%pins+ E 3 PgZsdmmc2-d47-sleep-0S(pins+ E3sdmmc2-d47-1pins+ & ' Pg2sdmmc2-d47-sleep-1pins+ &'sdmmc2-d47-2pins+  & ' PgZsdmmc2-d47-sleep-2pins+&'sdmmc2-d47-3pins+ E ' sdmmc2-d47-sleep-3pins+ E'sdmmc2-d47-4pins+ & 3 PgZsdmmc2-d47-sleep-4pins+ &3sdmmc3-b4-0pins1+P T U 7 Q PgZpins2+o PgZsdmmc3-b4-od-0pins1+P T U 7 PgZpins2+o PgZpins3+Q P?Zsdmmc3-b4-sleep-0pins+PTU7oQsdmmc3-b4-1pins1+P T 5 7 0 PgZpins2+o PgZsdmmc3-b4-od-1pins1+P T 5 7 PgZpins2+o PgZpins3+0 P?Zsdmmc3-b4-sleep-1pins+PT57o0spdifrx-0pins+l 2spdifrx-sleep-0pins+lspi1-1pins1+2gPpins2+2spi2-0pins1+ƒ2gPpins2+‚2spi2-1pins1+ƒ2gPpins2+‚2spi2-2pins1+ƒ2gpins2+‚wspi4-0pins+LF2gPpins2+M2spi5-0pins1+WY2gPpins2+X2stusb1600-0pins+‹Zuart4-0S pins1+k2gPpins2+ 2uart4-idle-0S pins1+kpins2+ 2uart4-sleep-0S pins+kuart4-1pins1+1 2gPpins2+ 2uart4-2pins1+k2gPpins2+ 2uart4-3pins1+ 2gPpins2+ 2uart4-idle-3pins1+ pins2+ 2uart4-sleep-3pins+ uart5-0pins1+2gPpins2+ 2uart7-0pins1+H2gPpins2 +GJI2uart7-1pins1+W2gPpins2+V2uart7-2pins1+H2gPpins2+GZuart7-idle-2pins1+Hpins2+GZuart7-sleep-2pins+HGuart8-0pins1+A 2gPpins2+@ 2uart8rtscts-0pins+g j 2usart1-0pins1+ 2gPpins2+ 2usart1-idle-0pins1+  usart1-sleep-0pins+  usart2-0pins1+U42gPpins2+632usart2-sleep-0pins+U463usart2-1pins1+U2gPpins2+TO2usart2-sleep-1pins+UTOusart2-2pins1+542gPpins2+632usart2-idle-2pins1+53pins2+42gPpins3+62usart2-sleep-2pins+5463usart3-0pins1+2gPpins2+ 2usart3-idle-0pins1+pins2+ 2usart3-sleep-0pins+usart3-1pins1+h 2gPpins2+ Š Zusart3-idle-1pins1+Špins2+h 2gPpins3+ Zusart3-sleep-1pins+hŠusart3-2pins1+h 2gPpins2+ Zusart3-idle-2pins1+pins2+h 2gPpins3+ Zusart3-sleep-2pins+husart3-3pins1+h 2gPpins2+9;2usart3-idle-3pins1 +h;pins2+92usart3-sleep-3pins+h;9usart3-4pins1+h 2gPpins2+;Zusart3-idle-4pins1+;pins2+h 2gPpins3+Zusart3-sleep-4pins+h;usart3-5pins1+<2gPpins2+ ;2usbotg-hs-0pins+ usbotg-fs-dp-dm-0pins+  pinctrl@54004000!st,stm32mp157-z-pinctrl T@y   `ÿäS5gpio@54004000ïÿ¢‘HL  GPIOZ†  okay5i2c2-0pins+2?Pi2c2-sleep-0pins+i2c4-0S.pins+”•2?Pi2c4-sleep-0S/pins+”•i2c6-0pins+–—2?Pi2c6-sleep-0pins+–—spi1-0pins1+’2gPpins2+‘2spi1-sleep-0pins +‘’usart1-1pins1+—2gPpins2+–2usart1-idle-1pins1+—pins2+–2usart1-sleep-1pins+—–can@4400e000 !bosch,m_canHDàDÖm_canmessage_ram[ int0int1L *hclkcclk •   disabledcan@4400f000 !bosch,m_canHDðD(Öm_canmessage_ram[ int0int1L *hclkcclk •   disabledgpu@59000000 !vivante,gcHY [mLe~ *buscorer Ådsi@5a000000 !st,stm32-dsiHZL£¤*pclkrefpx_clk¤6r Èapb  disabledportsport@0Hendpointport@1Hendpointcryp@54001000!st,stm32mp1-crypHT [OL r okayahb!st,mlahbsimple-bus$³800m4@10000000!st,stm32mp1-m4H08r  Èmcu_rsthold_boot ¾7 Í8Dÿÿÿÿ ß8Hÿÿÿÿ okayò9:;<=> ????vq0vq1shutdowndetachy [Daliases/soc/serial@40010000chosenserial0:115200n8memory@c0000000mcuram@30000000!shared-dma-poolH0&S:retram@38000000!shared-dma-poolH8&S9optee@fe000000Hþ&regulator-sd_switch!regulator-gpio tsd_switchƒw@›,@ -voltageI ã@<Bw@,@ S#vin!regulator-fixedtvinƒLK@›LK@IS1firmwareoptee!linaro,optee-tzŠsmcscmi!linaro,scmi-opteeIprotocol@14HESprotocol@16HRSprotocol@17Hregulatorsregulator@0Htreg11ƒÈà›ÈàS,regulator@1Htreg18ƒw@›w@S-regulator@2Htusb33ƒ2Z ›2Z S #address-cells#size-cellsmodelcompatibleclock-frequencydevice_typeregclocksphandleinterruptsinterrupt-affinityinterrupt-parentmethod#interrupt-cellsinterrupt-controllerpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisst,syscfgstatusrangesinterrupt-namesclock-namesdmasdma-names#pwm-cellsinterrupts-extendedwakeup-sourceresets#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pinctrl-2st,syscfg-fmpi2c-analog-filtervref-supply#io-channel-cells#dma-cellsst,mem2memdma-requestsdma-mastersdma-channelsvdd-supplyvdda-supplyst,min-sample-time-nsnvmem-cellsnvmem-cell-nameslabelarm,primecell-periphidcap-sd-highspeedcap-mmc-highspeedmax-frequencyreset-namesg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modeotg-revusb33d-supplyvbus-supply#mbox-cellsst,proc-id#clock-cells#reset-cellsvdd_3v3_usbfs-supplyregulator-nameregulator-min-microvoltregulator-max-microvolt#thermal-sensor-cellsdma-maxburstreg-namescd-gpiosdisable-wpst,sig-dirst,neg-edgest,use-ckinbus-widthvmmc-supplyvqmmc-supplysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-ddr50non-removableno-sdno-sdiommc-ddr-3_3vst,sysconsnps,mixed-burstsnps,pblsnps,en-tx-lpi-clockgatingsnps,axi-configsnps,tsosnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blencompaniontimeout-secvdda1v1-supplyvdda1v8-supply#phy-cellsphy-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsbuck1-supplybuck2-supplybuck3-supplybuck4-supplyldo1-supplyldo2-supplyldo3-supplyldo4-supplyldo5-supplyldo6-supplyvref_ddr-supplyboost-supplypwr_sw1-supplypwr_sw2-supplyregulator-always-onregulator-initial-moderegulator-over-current-protectionst,mask-resetregulator-boot-onregulator-active-dischargepower-off-time-secst,packagegpio-controller#gpio-cellsst,bank-namengpiosgpio-rangespinmuxbias-disabledrive-open-drainslew-ratebias-pull-updrive-push-pullbias-pull-downst,bank-ioportbosch,mram-cfgphy-dsi-supplydma-rangesst,syscfg-pddsst,syscfg-rsc-tblst,syscfg-m4-statememory-regionmboxesmbox-namesserial0stdout-pathno-mapregulator-typegpios-stateslinaro,optee-channel-id