K}HF(FP EBV SOCrates0!ebv,socratesaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/serial@ffc020004/soc/serial@ffc03000HRdunand@ff900000!altr,socfpga-denali-nand|nand_datadenali_reg  -.nandnand_xecc$ /disabledsram@ffff0000 !mmio-sram|+spi@ff705000!!intel,socfpga-qspicdns,qspi-nor|pP /%/okayflash@0!micron,n25q256ajedec,spi-nor|22/okayrstmgr@ffd05000- !altr,rst-mgr|P:snoop-control-unit@fffec000!arm,cortex-a9-scu|sdr@ffc25000!altr,sdr-ctlsyscon|P=0sdramedac!altr,sdram-edacM0 'spi@fff00000!snps,dw-apb-ssi| ]12spi /disabledspi@fff01000!snps,dw-apb-ssi| ]13spi /disabledsysmgr@ffd08000!altr,sys-mgrsyscon|Ѐ@dЀ%timer@fffec600!arm,cortex-a9-twd-timer|  2timer0@ffc08000!snps,dw-apb-timer |*timer*timertimer1@ffc09000!snps,dw-apb-timer |*timer+timertimer2@ffd00000!snps,dw-apb-timer | timer(timertimer3@ffd01000!snps,dw-apb-timer | timer)timerserial@ffc02000!snps,dw-apb-uart|  t~*33txrx0serial@ffc03000!snps,dw-apb-uart|0 t~*33txrx1usbphy!usb-nop-xceiv/okay5usb@ffb00000 !snps,dwc2| }4otg"dwc25 usb2-phy /disabledusb@ffb40000 !snps,dwc2| 4otg#dwc25 usb2-phy /disabledwatchdog@ffd02000 !snps,dw-wdt|   &/okaywatchdog@ffd03000 !snps,dw-wdt|0  ' /disabledchosen earlyprintkserial0:115200n8memory@0pmemory|@gpio-leds !gpio-ledsled0led:green:heartbeat [6 heartbeatled1 led:green:D7 [7led2 led:green:D8 [7 #address-cells#size-cellsmodelcompatibleserial0serial1timer0timer1timer2timer3ethernet0enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gatesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configphy-modegpio-controller#gpio-cellssnps,nr-gpiosiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedclk-phase-sd-hsreg-namescdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargsstdout-pathlabellinux,default-trigger