G8CD(C Google Chameleon V3L!google,chameleon-v3enclustra,mercury-aa1altr,socfpga-arria10altr,socfpgacpus,altr,socfpga-a10-smpcpu@0!arm,cortex-a9:cpuFJ[cpu@1!arm,cortex-a9:cpuFJ[pmu@ff111000!arm,cortex-a9-pmuct|}F0interrupt-controller@ffffd000!arm,cortex-a9-gicF[soc !simple-bus:soccamba !simple-buspdma@ffda1000!arm,pl330arm,primecellFltSTUVWXYZ[ apb_pclk05 dmadma-ocp["base_fpga_region !fpga-regionclkmgr@ffd04000 !altr,clk-mgrF@clockscb_intosc_hs_div2_clk !fixed-clock[cb_intosc_ls_clk !fixed-clock[ f2s_free_clk !fixed-clock[ osc1 !fixed-clockP[main_pll@40!altr,socfpga-a10-pll-clock  F@[ main_mpu_base_clk!altr,socfpga-a10-perip-clk  @ [main_noc_base_clk!altr,socfpga-a10-perip-clk  D [main_emaca_clk@68!altr,socfpga-a10-perip-clk Fhmain_emacb_clk@6c!altr,socfpga-a10-perip-clk Flmain_emac_ptp_clk@70!altr,socfpga-a10-perip-clk Fpmain_gpio_db_clk@74!altr,socfpga-a10-perip-clk Ftmain_sdmmc_clk@78!altr,socfpga-a10-perip-clk Fx[main_s2f_usr0_clk@7c!altr,socfpga-a10-perip-clk F|main_s2f_usr1_clk@80!altr,socfpga-a10-perip-clk F[main_hmc_pll_ref_clk@84!altr,socfpga-a10-perip-clk Fmain_periph_ref_clk@9c!altr,socfpga-a10-perip-clk F[ periph_pll@c0!altr,socfpga-a10-pll-clock F[ peri_mpu_base_clk!altr,socfpga-a10-perip-clk  @ [peri_noc_base_clk!altr,socfpga-a10-perip-clk  D [peri_emaca_clk@e8!altr,socfpga-a10-perip-clk Fperi_emacb_clk@ec!altr,socfpga-a10-perip-clk Fperi_emac_ptp_clk@f0!altr,socfpga-a10-perip-clk F[peri_gpio_db_clk@f4!altr,socfpga-a10-perip-clk Fperi_sdmmc_clk@f8!altr,socfpga-a10-perip-clk F[peri_s2f_usr0_clk@fc!altr,socfpga-a10-perip-clk Fperi_s2f_usr1_clk@100!altr,socfpga-a10-perip-clk F[peri_hmc_pll_ref_clk@104!altr,socfpga-a10-perip-clk Fmpu_free_clk@60!altr,socfpga-a10-perip-clk F`[noc_free_clk@64!altr,socfpga-a10-perip-clk Fd[s2f_user1_free_clk@104!altr,socfpga-a10-perip-clk Fsdmmc_free_clk@f8!altr,socfpga-a10-perip-clk F[l4_sys_free_clk!altr,socfpga-a10-perip-clk[,l4_main_clk!altr,socfpga-a10-gate-clk ,H[l4_mp_clk!altr,socfpga-a10-gate-clk ,H[l4_sp_clk!altr,socfpga-a10-gate-clk ,H[ mpu_periph_clk!altr,socfpga-a10-gate-clk,H[+sdmmc_clk!altr,socfpga-a10-gate-clk,[#qspi_clk!altr,socfpga-a10-gate-clk, [*nand_x_clk!altr,socfpga-a10-gate-clk, [nand_ecc_clk!altr,socfpga-a10-gate-clk, [%nand_clk!altr,socfpga-a10-gate-clk, [$spi_m_clk!altr,socfpga-a10-gate-clk, [!usb_clk!altr,socfpga-a10-gate-clk,[-s2f_usr1_clk!altr,socfpga-a10-gate-clk,stmmac-axi-config5EU[ethernet@ff8000008!altr,socfpga-stmmac-a10-s10snps,dwmac-3.72asnps,dwmac _DF  t\rmacirq@stmmacethptp_ref (stmmacethahbokayrgmii ['mdio!snps,dwmac-mdioethernet-phy@3$1>KXerDF[ethernet@ff8020008!altr,socfpga-stmmac-a10-s10snps,dwmac-3.72asnps,dwmac _HF  t]rmacirq@stmmacethptp_ref!)stmmacethahb disabledethernet@ff8040008!altr,socfpga-stmmac-a10-s10snps,dwmac-3.72asnps,dwmac _LF@  t^rmacirq@stmmacethptp_ref"*stmmacethahb disabledgpio@ffc02900!snps,dw-apb-gpioF)Xokaygpio-controller@0!snps,dw-apb-gpio-portF tpgpio@ffc02a00!snps,dw-apb-gpioF*Yokaygpio-controller@0!snps,dw-apb-gpio-portF tqgpio@ffc02b00!snps,dw-apb-gpioF+Zokaygpio-controller@0!snps,dw-apb-gpio-portF trfpga-mgr@ffd03000!altr,socfpga-a10-fpga-mgrF0 fpgamgr[i2c@ffc02200!snps,designware-i2cF" ti Hokayaudio-codec@1a !adi,ssm2603Fi2c@ffc02300!snps,designware-i2cF# tj Iokaycrypto@64!atmel,atsha204aFdisl12022@6f!isil,isl12022Fogpio@21 !nxp,pca9535F!SOM_AUD_MUTEDP1_OUT_CEC_ENDP2_OUT_CEC_ENDP1_SOM_PS8469_CADDPD_SOM_PS8469_CADDP_OUT_PWR_ENSTM32_RST_LSTM32_BOOT0FPGA_PROTSTM32_FPGA_COMM0TP119TP120TP121TP122TP123TP124i2c@ffc02400!snps,designware-i2cF$ tk J disabledi2c@ffc02500!snps,designware-i2cF% tl K disabledi2c@ffc02600!snps,designware-i2cF& tm L disabledspi@ffda4000!snps,dw-apb-ssiF@ te!1spi disabledspi@ffda5000!snps,dw-apb-ssiFP tf""!2spi disabledsdr@ffcfb100!altr,sdr-ctlsysconFϱ[&cache-controller@fffff000!arm,pl310-cacheF t+7ET[mmc@ff808000!altr,socfpga-dw-mshcF tb#biuciu' _(okayhy[(nand@ffb90000!altr,socfpga-denali-nandF nand_datadenali_reg tc $%nandnand_xecc% disabledsram@ffe00000 !mmio-sramFeccmgr!altr,socfpga-a10-ecc-manager_tsdramedac!altr,sdram-edac-a10&t1l2-ecc@ffd06010!altr,socfpga-a10-l2-eccF`t ocram-ecc@ff8c3000!altr,socfpga-a10-ocram-eccF0t!emac0-rx-ecc@ff8c0800!altr,socfpga-eth-mac-eccF't$emac0-tx-ecc@ff8c0c00!altr,socfpga-eth-mac-eccF 't%sdmmca-ecc@ff8c2c00!altr,socfpga-sdmmc-eccF,( t/0dma-ecc@ff8c8000!altr,socfpga-dma-eccF"t *usb0-ecc@ff8c8800!altr,socfpga-usb-eccF)t"spi@ff809000!!intel,socfpga-qspicdns,qspi-norF td*&.qspiqspi-ocp disabledrstmgr@ffd05000 !altr,rst-mgrFP [snoop-control-unit@ffffc000!arm,cortex-a9-scuFsysmgr@ffd06000!altr,sys-mgrsysconF`b0[timer@ffffc600!arm,cortex-a9-twd-timerF t +timer0@ffc02700!snps,dw-apb-timer tsF' timerDtimertimer1@ffc02800!snps,dw-apb-timer ttF( timerEtimertimer2@ffd00000!snps,dw-apb-timer tuF,timerBtimertimer3@ffd00100!snps,dw-apb-timer tvF,timerCtimerserial@ffc02000!snps,dw-apb-uartF  tn,6 Pokayserial@ffc02100!snps,dw-apb-uartF! to,6 QokayusbphyC!usb-nop-xceivokay[.usb@ffb00000 !snps,dwc2F t_-otg#dwc2N. Susb2-phyokay]host[)usb@ffb40000 !snps,dwc2F t`-otg$dwc2N. Susb2-phy disabledwatchdog@ffd00200 !snps,dw-wdtF tw,@ disabledwatchdog@ffd00300 !snps,dw-wdtF tx,A disabledaliasese/soc/ethernet@ff800000o/soc/serial@ffc02100w/soc/serial@ffc02000/soc/i2c@ffc02200/soc/i2c@ffc02300memory@0:memoryFchosenserial1:115200n8 #address-cells#size-cellsmodelcompatibleenable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgr#clock-cellsclock-frequencydiv-regfixed-dividerclk-gatesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configstatusphy-modephy-addrmax-frame-sizephy-handletxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiosgpio-line-namesnum-cstx-dma-channelrx-dma-channelcache-unifiedcache-levelprefetch-dataprefetch-instrarm,shared-overridecap-sd-highspeedbroken-cdbus-widthclk-phase-sd-hsreg-namesaltr,sdr-sysconaltr,ecc-parentcdns,fifo-depthcdns,fifo-widthcdns,trigger-address#reset-cellsaltr,modrst-offsetcpu1-start-addrreg-shiftreg-io-width#phy-cellsphysphy-namesdr_modeethernet0serial1serial0i2c0i2c1stdout-path