8( e|google,veyron-tiger-rev8google,veyron-tiger-rev7google,veyron-tiger-rev6google,veyron-tiger-rev5google,veyron-tiger-rev4google,veyron-tiger-rev3google,veyron-tiger-rev2google,veyron-tiger-rev1google,veyron-tiger-rev0google,veyron-tigergoogle,veyronrockchip,rk3288& 7Google Tigeraliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 ,@:Ar[ gcpu@501cpuarm,cortex-a12 ,@:Argcpu@502cpuarm,cortex-a12 ,@:Argcpu@503cpuarm,cortex-a12 ,@:Argopp-table-0operating-points-v2ogopp-126000000z opp-216000000z  opp-408000000zQ opp-600000000z#F opp-696000000z)|~opp-816000000z0,B@opp-1008000000z<opp-1200000000zGopp-1416000000zTfrOopp-1512000000zZJopp-1608000000z_" opp-1704000000zepopp-1800000000zkI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mg timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H :a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр :Drvbiuciuciu-driveciu-sample!  @,reset 8disabledmmc@ff0d0000rockchip,rk3288-dw-mshcр :Eswbiuciuciu-driveciu-sample! ! @,reset8okay?IZg} default btmrvl@2marvell,sd8897-bt& defaultmmc@ff0e0000rockchip,rk3288-dw-mshcр :Ftxbiuciuciu-driveciu-sample! "@,reset 8disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр :Guybiuciuciu-driveciu-sample! #@,reset8okay?!?J}default saradc@ff100000rockchip,saradc $Y:I[saradcapb_pclkW ,saradc-apb 8disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi:ARspiclkapb_pclkk  ptxrx ,default 8disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi:BSspiclkapb_pclkk ptxrx -default ! 8disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi:CTspiclkapb_pclkkptxrx .default"#$%8okayz flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c:Mdefault&8okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c:Odefault'8okay2,touchscreen@10elan,ekth3500&(default)* (++ i2c@ff160000rockchip,rk3288-i2c @i2c:Pdefault,8okay2,ts3a227e@3b ti,ts3a227e;&-default.gi2c@ff170000rockchip,rk3288-i2c Ai2c:Qdefault/ 8disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7%/:MUbaudclkapb_pclkkptxrxdefault 0128okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8%/:NVbaudclkapb_pclkkptxrxdefault38okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9%/:OWbaudclkapb_pclkdefault48okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :%/:PXbaudclkapb_pclkkptxrxdefault5 8disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;%/:QYbaudclkapb_pclkk  ptxrxdefault6 8disableddma-controller@ff250000arm,pl330arm,primecell%@<Gb: apb_pclkgthermal-zonesreserve-thermaly7cpu-thermalyd7tripscpu_alert0ppassiveg8cpu_alert1$passiveg9cpu_crit criticalcooling-mapsmap080map190gpu-thermalyd7tripsgpu_alert04passiveg:gpu_crit criticalcooling-mapsmap0: ;tsadc@ff280000rockchip,rk3288-tsadc( %:HZtsadcapb_pclk ,tsadc-apbinitdefaultsleep<=<>H8okay&=g7ethernet@ff290000rockchip,rk3288-gmac)Xmacirqeth_wake_irq>8:fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB ,stmmaceth8okayhx?input@rgmiiAdefaultBCDE0  'u0 mdio0snps,dwmac-mdioethernet-phy@1g@usb@ff500000 generic-ehciP :F usb8okayusb@ff520000 generic-ohciR ):F usb 8disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T :otg-hostG  usb2-phy58okayLusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X :otg-hostcu@@ H  usb2-phy8okayhzxHLusb@ff5c0000 generic-ehci\ : 8disableddma-controller@ff600000arm,pl330arm,primecell`@<Gb: apb_pclk 8disabledi2c@ff650000rockchip,rk3288-i2ce <i2c:LdefaultI8okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&-default JKL +"/M M9NgregulatorsDCDC_REG1Fvdd_armUi{ q qg regulator-state-memDCDC_REG2Fvdd_gpuUi{ 5qgregulator-state-memDCDC_REG3 Fvcc135_ddrUiregulator-state-memDCDC_REG4Fvcc_18Ui{w@w@gregulator-state-memw@LDO_REG3Fvdd_10Ui{B@B@regulator-state-memB@LDO_REG7 Fvdd10_lcdUi{B@B@regulator-state-memSWITCH_REG1 Fvcc33_lcdUigdregulator-state-memLDO_REG6 Fvcc18_codecUi{w@w@geregulator-state-memLDO_REG2Ui{w@w@ Fvdd18_lcdtregulator-state-memLDO_REG8Ui{2Z2Z Fvcc33_ccdregulator-state-memSWITCH_REG2 Fvcc33_langAi2c@ff660000rockchip,rk3288-i2cf =i2c:NdefaultO8okay2 max98090@10maxim,max98090&Pmclk:qdefaultQgpwm@ff680000rockchip,rk3288-pwmh defaultR:_8okaygpwm@ff680010rockchip,rk3288-pwmh defaultS:_8okaygpwm@ff680020rockchip,rk3288-pwmh  defaultT:_ 8disabledpwm@ff680030rockchip,rk3288-pwmh0 defaultU:_ 8disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsgpower-controller!rockchip,rk3288-power-controllerhhx gipower-domain@9 :chgfdehilkj$,VWXYZ[\]^power-domain@11 :op,_`power-domain@12 :,apower-domain@13 :,bcreboot-modesyscon-reboot-mode3:RBFRBTRB dRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv: xin24m>pHhjk$}#gׄeрxhрxhgsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwg>edp-phyrockchip,rk3288-dp-phy:h24m8okaygyio-domains"rockchip,rk3288-io-voltage-domain8okay+++deusbphyrockchip,rk3288-usb-phy8okayusb-phy@320 :]phyclk ,phy-resetgHusb-phy@3344:^phyclk ,phy-resetgFusb-phy@348H:_phyclk ,phy-resetgGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt:p O8okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif :T mclkhclkkfptx 6defaultg> 8disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  5:Ri2s_clki2s_hclkkffptxrxdefaulth  /8okaygcrypto@ff8a0000rockchip,rk3288-crypto@ 0 :}aclkhclksclkapb_pclk ,crypto-rstiommu@ff900800rockchip,iommu@ : aclkiface I 8disablediommu@ff914000rockchip,iommu @P : aclkiface I V 8disabledrga@ff920000rockchip,rk3288-rga :jaclkhclksclk qi ilm ,coreaxiahbvop@ff930000rockchip,rk3288-vop  :aclk_vopdclk_vophclk_vop qi def ,axiahbdclk j8okayportg endpoint@0 kgendpoint@1 lg{endpoint@2 mgtendpoint@3 ngwiommu@ff930300rockchip,iommu : aclkiface qi  I8okaygjvop@ff940000rockchip,rk3288-vop  :aclk_vopdclk_vophclk_vop qi  ,axiahbdclk o8okayportg endpoint@0 pgendpoint@1 qg|endpoint@2 rguendpoint@3 sgxiommu@ff940300rockchip,iommu : aclkiface qi  I8okaygodsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ :~d refpclk qi > 8disabledportsport@0endpoint@0 tgmendpoint@1 ugrport@1lvds@ff96c000rockchip,rk3288-lvds@:g pclk_lvdslcdcv qi > 8disabledportsport@0endpoint@0 wgnendpoint@1 xgsport@1dp@ff970000rockchip,rk3288-dp@ b:icdppclky dp qi o,dp>8okaydefaultzportsport@0endpoint@0 {glendpoint@1 |gqport@1endpoint@0 }ghdmi@ff980000rockchip,rk3288-dw-hdmi/ > g:hmniahbisfrcec qi 8okaydefaultunwedge~gportsportendpoint@0 gkendpoint@1 gpvideo-codec@ff9a0000rockchip,rk3288-vpu   Xvepuvdpu: aclkhclk  qi iommu@ff9a0800rockchip,iommu : aclkiface I qi giommu@ff9c0440rockchip,iommu @@@ o: aclkiface I 8disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Xjobmmugpu:  qi 8okay g;opp-table-1operating-points-v2gopp-100000000z~opp-200000000z ~opp-300000000zB@opp-400000000zׄopp-600000000z#Fqos@ffaa0000rockchip,rk3288-qossyscon gbqos@ffaa0080rockchip,rk3288-qossyscon gcqos@ffad0000rockchip,rk3288-qossyscon gWqos@ffad0100rockchip,rk3288-qossyscon gXqos@ffad0180rockchip,rk3288-qossyscon gYqos@ffad0400rockchip,rk3288-qossyscon gZqos@ffad0480rockchip,rk3288-qossyscon g[qos@ffad0500rockchip,rk3288-qossyscon gVqos@ffad0800rockchip,rk3288-qossyscon g\qos@ffad0880rockchip,rk3288-qossyscon g]qos@ffad0900rockchip,rk3288-qossyscon g^qos@ffae0000rockchip,rk3288-qossyscon gaqos@ffaf0000rockchip,rk3288-qossyscon g_qos@ffaf0080rockchip,rk3288-qossyscon g`dma-controller@ffb20000arm,pl330arm,primecell@<Gb: apb_pclkgfefuse@ffb40000rockchip,rk3288-efuse :q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   gpinctrlrockchip,rk3288-pinctrl>defaultsleepgpio@ff750000rockchip,gpio-banku Q:@     PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LHUB_USB1_nFALUTPHY_PMEBPHY_INTRECOVERY_SW_LOTP_OUTUSB_OTG_POWER_ENAP_WARM_RESET_HUSB_OTG_nFALUTI2C0_SDA_PMICI2C0_SCL_PMICDEVMODE_LUSB_INTg-gpio@ff780000rockchip,gpio-bankx R:A    gpio@ff790000rockchip,gpio-banky S:B    i CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPg(gpio@ff7a0000rockchip,gpio-bankz T:C     FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7VCC5V_GOOD_HFLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOPHY_TXD2PHY_TXD3MAC_RXD2MAC_RXD3PHY_TXD0PHY_TXD1MAC_RXD0MAC_RXD1gpio@ff7b0000rockchip,gpio-bank{ U:D     MAC_MDCMAC_RXDVMAC_RXERMAC_CLKPHY_TXENMAC_MDIOMAC_RXCLKPHY_RSTPHY_TXCLKUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEggpio@ff7c0000rockchip,gpio-bank| V:E     USB_OTG_CTL1HUB_USB2_CTL1HUB_USB2_PWR_ENHUB_USB_ILIM_SELUSB_OTG_STATUS_LHUB_USB1_CTL1HUB_USB1_PWR_ENVCC50_HDMI_ENggpio@ff7d0000rockchip,gpio-bank} W:F     I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETHUB_USB2_nFALUTUSB_OTG_ILIM_SELgPgpio@ff7e0000rockchip,gpio-bank~ X:G     LCD_BL_PWMPWM_LOGBL_ENPWR_LED1TPM_INT_HSPK_ONAP_FLASH_WP_LCPU_NMIDVSOKEDP_HPDDVS1LCD_ENDVS2HDMI_CECI2C4_SDAI2C4_SCLI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDgMgpio@ff7f0000rockchip,gpio-bank Y:H    ^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc g~hdmi-ddc-unwedge gvcc50-hdmi-en gpcfg-output-low gpcfg-pull-up gpcfg-pull-down gpcfg-pull-none )gpcfg-pull-none-12ma ) 6 gsuspendglobal-pwroff gddrio-pwroff gddr0-retention gddr1-retention edpedp-hpd  gzi2c0i2c0-xfer gIi2c1i2c1-xfer g&i2c2i2c2-xfer   gOi2c3i2c3-xfer g'i2c4i2c4-xfer g,i2c5i2c5-xfer g/i2s0i2s0-bus` ghlcdclcdc-ctl@ gvsdmmcsdmmc-clk sdmmc-cmd sdmmc-cd sdmmc-bus1 sdmmc-bus4@ sdio0sdio0-bus1 sdio0-bus4@ gsdio0-cmd gsdio0-clk gsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h gbt-enable-l bt-host-wake bt-host-wake-l gbt-dev-wake-sleep gbt-dev-wake-awake gbt-dev-wake sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk gemmc-cmd gemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 gemmc-reset  gspi0spi0-clk  gspi0-cs0  gspi0-tx gspi0-rx gspi0-cs1 spi1spi1-clk  gspi1-cs0  g!spi1-rx g spi1-tx gspi2spi2-cs1 spi2-clk g"spi2-cs0 g%spi2-rx g$spi2-tx  g#uart0uart0-xfer g0uart0-cts g1uart0-rts g2uart1uart1-xfer  g3uart1-cts  uart1-rts  uart2uart2-xfer g4uart3uart3-xfer g5uart3-cts  uart3-rts  uart4uart4-xfer g6uart4-cts  uart4-rts  tsadcotp-pin g<otp-out g=pwm0pwm0-pin gRpwm1pwm1-pin gSpwm2pwm2-pin gTpwm3pwm3-pin gUgmacrgmii-pins  gBrmii-pins phy-rst gCphy-pmeb gDphy-int gEspdifspdif-tx  ggpcfg-pull-none-drv-8ma ) 6gpcfg-pull-up-drv-8ma  6pcfg-output-high Egbuttonspwr-key-l gpmicpmic-int-l gJdvs-1  gKdvs-2 gLrebootap-warm-reset-h grecovery-switchrec-mode-l tpmtpm-int-h write-protectfw-wp-ap codechp-det gint-codec gQmic-det  gheadsetts3a227e-int-l g.buck-5vdrv-5v gledspwr-led1-on gpwr-led1-blink gusb-bc12usb-otg-ilim-sel gusb-usb-ilim-sel gusb-hosthub_usb1_pwr_en ghub_usb2_pwr_en gusb_otg_pwr_en gbacklightbl_pwr_en  gbl-en glcdlcd-en gtouchscreentouch-int g)touch-rst g*chosen Qserial2:115200n8memorymemorypower-button gpio-keysdefaultkey-power ]Power - ct nd gpio-restart gpio-restart - default emmc-pwrseqmmc-pwrseq-emmcdefault ( gsdio-pwrseqmmc-pwrseq-simple: ext_clockdefault g vcc-5vregulator-fixedFvcc_5vUi{LK@LK@  MdefaultgNvcc33-sysregulator-fixed Fvcc33_sysUi{2Z2Zgvcc50-hdmiregulator-fixed Fvcc50_hdmiUi N  defaultvdd-logicpwm-regulator Fvdd_logic   { Ui{~psound!rockchip,rockchip-audio-max98090default VEYRON-I2S   P 0P  G ^vccsysregulator-fixedFvccsysiUgvcc33-ioregulator-fixedUi Fvcc33_iog+vcc5-host1-regulatorregulator-fixed  default Fvcc5_host1Uivcc5-host2-regulatorregulator-fixed  default Fvcc5_host2Uivcc5v-otg-regulatorregulator-fixed  - default Fvcc5_otgUiexternal-gmac-clock fixed-clocksY@ ext_gmacg?backlight-regulatorregulator-fixed  ( defaultFbacklight_regulator  r:gpanel-regulatorregulator-fixed  MdefaultFpanel_regulator gbacklightpwm-backlight    Mdefault B@   gpanelauo,b101ean018okay  panel-timing@   $ 0  :  B O [portsportendpoint g} #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymarvell,wakeup-pincap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreset-gpiosvcc33-supplyvccio-supplywakeup-sourceti,micbiasreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplyrx_delaytx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityenable-active-highvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenvactivevfront-porchvback-porchvsync-len