8 ( google,veyron-jaq-rev5google,veyron-jaq-rev4google,veyron-jaq-rev3google,veyron-jaq-rev2google,veyron-jaq-rev1google,veyron-jaqgoogle,veyronrockchip,rk3288& 7Google Jaqaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000/mmc@ff0c0000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12  (7@ELrf rcpu@501cpuarm,cortex-a12  (7@ELrrcpu@502cpuarm,cortex-a12  (7@ELrrcpu@503cpuarm,cortex-a12  (7@ELrropp-table-0operating-points-v2zropp-126000000 opp-216000000  opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJopp-1608000000_" opp-1704000000epopp-1800000000kI\reserved-memorydma-unusable@fe000000 oscillator fixed-clockn6xin24mr timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H Ea   pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр EDrv biuciuciu-driveciu-sample,  @ 7resetCokayJTfw  Z defaultmmc@ff0d0000rockchip,rk3288-dw-mshcр EEsw biuciuciu-driveciu-sample, ! @ 7resetCokayJf!.DO default btmrvl@2marvell,sd8897-bt &]  defaultmmc@ff0e0000rockchip,rk3288-dw-mshcр EFtx biuciuciu-driveciu-sample, " @ 7reset Cdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcр EGuy biuciuciu-driveciu-sample, # @ 7resetCokayJTpDO default  saradc@ff100000rockchip,saradc  $EI[ saradcapb_pclk W 7saradc-apb Cdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiEAR spiclkapb_pclk! ! txrx , default"#$% Cokayec@0google,cros-ec-spi &  default&-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb  -DG;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiEBS spiclkapb_pclk! !txrx - default'()*  Cdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiECT spiclkapb_pclk!!txrx . default+,-. CokayT flash@0jedec,spi-nor i2c@ff140000rockchip,rk3288-i2c  > i2cEM default/Cokayg2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c  ? i2cEO default0 Cdisabledi2c@ff160000rockchip,rk3288-i2c  @ i2cEP default1Cokayg2,ts3a227e@3b ti,ts3a227e ;&2 default3rtrackpad@15elan,ekth3000 &  default45i2c@ff170000rockchip,rk3288-i2c  A i2cEQ default6 Cdisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart  7EMU baudclkapb_pclk!!txrx default 789Cokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart  8ENV baudclkapb_pclk!!txrx default:Cokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart i 9EOW baudclkapb_pclk default;Cokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart  :EPX baudclkapb_pclk!!txrx default< Cdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart  ;EQY baudclkapb_pclk! ! txrx default= Cdisableddma-controller@ff250000arm,pl330arm,primecell %@E  apb_pclkr!thermal-zonesreserve-thermal&<J>cpu-thermal&d<J>tripscpu_alert0Zpfpassiver?cpu_alert1Z$fpassiver@cpu_critZf criticalcooling-mapsmap0q?0vmap1q@0vgpu-thermal&d<J>tripsgpu_alert0Z4fpassiverAgpu_critZf criticalcooling-mapsmap0qA vBtsadc@ff280000rockchip,rk3288-tsadc ( %EHZ tsadcapb_pclk  7tsadc-apb initdefaultsleepCDCEHCokayr>ethernet@ff290000rockchip,rk3288-gmac )macirqeth_wake_irqE8Efgc]M stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B 7stmmaceth Cdisabledusb@ff500000 generic-ehci P EFusbCokay$usb@ff520000 generic-ohci R )EFusb Cdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 T E otg:hostG usb2-phyBCokayYusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 X E otg:hostp@@ H usb2-phyCokayzHYusb@ff5c0000 generic-ehci \ E Cdisableddma-controller@ff600000arm,pl330arm,primecell `@E  apb_pclk Cdisabledi2c@ff650000rockchip,rk3288-i2c e < i2cEL defaultICokayg2dpmic@1brockchip,rk808 xin32kwifibt_32kin&2 default JKL M$0<I5VcMoM| rregulatorsDCDC_REG1vdd_arm q qr regulator-state-memDCDC_REG2vdd_gpu 5qrregulator-state-memDCDC_REG3 vcc135_ddrregulator-state-memDCDC_REG4vcc_18w@w@rregulator-state-mem1w@LDO_REG1 vcc33_io2Z2Zr5regulator-state-mem12ZLDO_REG3vdd_10B@B@regulator-state-mem1B@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-memSWITCH_REG1 vcc33_lcdrcregulator-state-memLDO_REG6 vcc18_codecw@w@rdregulator-state-memLDO_REG4 vccio_sdw@2Zrregulator-state-memLDO_REG5 vcc33_sd2Z2Zrregulator-state-memLDO_REG8 vcc33_ccd2Z2Zregulator-state-memLDO_REG2mic_vccw@w@regulator-state-memi2c@ff660000rockchip,rk3288-i2c f = i2cEN defaultNCokayg2 max98090@10maxim,max98090 &O mclkEq defaultPrpwm@ff680000rockchip,rk3288-pwm hM defaultQE_Cokayrpwm@ff680010rockchip,rk3288-pwm hM defaultRE_Cokayrpwm@ff680020rockchip,rk3288-pwm h M defaultSE_ Cdisabledpwm@ff680030rockchip,rk3288-pwm h0M defaultTE_ Cdisabledsram@ff700000 mmio-sram ppsmp-sram@0rockchip,rk3066-smp-sram sram@ff720000#rockchip,rk3288-pmu-srammmio-sram rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd srpower-controller!rockchip,rk3288-power-controllerXh rhpower-domain@9 Echgfdehilkj$lUVWXYZ[\]Xpower-domain@11 Eopl^_Xpower-domain@12 El`Xpower-domain@13 ElabXreboot-modesyscon-reboot-modeszRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon tclock-controller@ff760000rockchip,rk3288-cru vE  xin24mEHjk$#gׄeрxhрxhrsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd wrEedp-phyrockchip,rk3288-dp-phyEh 24mCokayrxio-domains"rockchip,rk3288-io-voltage-domainCokay5 5 5 c * 6d Cusbphyrockchip,rk3288-usb-phyCokayusb-phy@320  E] phyclk  7phy-resetrHusb-phy@334 4E^ phyclk  7phy-resetrFusb-phy@348 HE_ phyclk  7phy-resetrGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt Ep OCokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  QET  mclkhclketx 6 defaultfE Cdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  Q 5ER i2s_clki2s_hclkeetxrx defaultg b }Cokayrcrypto@ff8a0000rockchip,rk3288-crypto @ 0 E} aclkhclksclkapb_pclk  7crypto-rstiommu@ff900800rockchip,iommu @ E  aclkiface  Cdisablediommu@ff914000rockchip,iommu  @P E  aclkiface   Cdisabledrga@ff920000rockchip,rk3288-rga  Ej aclkhclksclk h  ilm 7coreaxiahbvop@ff930000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop h  def 7axiahbdclk iCokayportr endpoint@0  jrendpoint@1  krzendpoint@2  lrsendpoint@3  mrviommu@ff930300rockchip,iommu  E  aclkiface h  Cokayrivop@ff940000rockchip,rk3288-vop   E aclk_vopdclk_vophclk_vop h   7axiahbdclk nCokayportr endpoint@0  orendpoint@1  pr{endpoint@2  qrtendpoint@3  rrwiommu@ff940300rockchip,iommu  E  aclkiface h  Cokayrndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi @ E~d  refpclk h E Cdisabledportsport@0 endpoint@0  srlendpoint@1  trqport@1 lvds@ff96c000rockchip,rk3288-lvds @Eg  pclk_lvds lcdcu h E Cdisabledportsport@0 endpoint@0  vrmendpoint@1  wrrport@1 dp@ff970000rockchip,rk3288-dp @ bEic dppclkxdp h  o7dpECokay defaultyportsport@0 endpoint@0  zrkendpoint@1  {rpport@1 endpoint@0  |rhdmi@ff980000rockchip,rk3288-dw-hdmi  QE gEhmn iahbisfrcec h Cokay defaultunwedge}~rportsportendpoint@0  rjendpoint@1  rovideo-codec@ff9a0000rockchip,rk3288-vpu    vepuvdpuE  aclkhclk  h iommu@ff9a0800rockchip,iommu  E  aclkiface  h riommu@ff9c0440rockchip,iommu  @@@ oE  aclkiface  Cdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760 $ jobmmugpuE( h Cokay rBopp-table-1operating-points-v2ropp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon raqos@ffaa0080rockchip,rk3288-qossyscon rbqos@ffad0000rockchip,rk3288-qossyscon rVqos@ffad0100rockchip,rk3288-qossyscon  rWqos@ffad0180rockchip,rk3288-qossyscon  rXqos@ffad0400rockchip,rk3288-qossyscon  rYqos@ffad0480rockchip,rk3288-qossyscon  rZqos@ffad0500rockchip,rk3288-qossyscon  rUqos@ffad0800rockchip,rk3288-qossyscon  r[qos@ffad0880rockchip,rk3288-qossyscon  r\qos@ffad0900rockchip,rk3288-qossyscon r]qos@ffae0000rockchip,rk3288-qossyscon r`qos@ffaf0000rockchip,rk3288-qossyscon r^qos@ffaf0080rockchip,rk3288-qossyscon r_dma-controller@ffb20000arm,pl330arm,primecell @E  apb_pclkreefuse@ffb40000rockchip,rk3288-efuse Eq  pclk_efusecpu-id@7 cpu_leakage@17 interrupt-controller@ffc01000 arm,gic-400  @  @ `   rpinctrlrockchip,rk3288-pinctrlE defaultsleepgpio@ff750000rockchip,gpio-bank u QE@  &   2PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTr2gpio@ff780000rockchip,gpio-bank x REA  &  gpio@ff790000rockchip,gpio-bank y SEB  &  M 2CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENrgpio@ff7a0000rockchip,gpio-bank z TEC  &   2FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank { UED  &   2UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKErgpio@ff7c0000rockchip,gpio-bank | VEE  &  A 2SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENrgpio@ff7d0000rockchip,gpio-bank } WEF  &   2I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDrOgpio@ff7e0000rockchip,gpio-bank ~ XEG  &   2LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDr gpio@ff7f0000rockchip,gpio-bank  YEH  &  ^ 2RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 Bhdmi-cec-c7 Bhdmi-ddc Br}hdmi-ddc-unwedge Br~vcc50-hdmi-en Brpcfg-output-low Prpcfg-pull-up [rpcfg-pull-down hrpcfg-pull-none wrpcfg-pull-none-12ma w rsuspendglobal-pwroff Brddrio-pwroff Brddr0-retention Brddr1-retention Bsuspend-l-wake Brsuspend-l-sleep Bredpedp-hpd B ryi2c0i2c0-xfer BrIi2c1i2c1-xfer Br/i2c2i2c2-xfer B  rNi2c3i2c3-xfer Br0i2c4i2c4-xfer Br1i2c5i2c5-xfer Br6i2s0i2s0-bus` Brglcdclcdc-ctl@ Brusdmmcsdmmc-clk Brsdmmc-cmd Brsdmmc-cd Bsdmmc-bus1 Bsdmmc-bus4@ Brsdmmc-cd-disabled Brsdmmc-cd-pin Brsdio0sdio0-bus1 Bsdio0-bus4@ Brsdio0-cmd Brsdio0-clk Brsdio0-cd Bsdio0-wp Bsdio0-pwr Bsdio0-bkpwr Bsdio0-int Bwifienable-h Brbt-enable-l Bbt-host-wake Bbt-host-wake-l Brbt-dev-wake-sleep Brbt-dev-wake-awake Brbt-dev-wake Bsdio1sdio1-bus1 Bsdio1-bus4@ Bsdio1-cd Bsdio1-wp Bsdio1-bkpwr Bsdio1-int Bsdio1-cmd Bsdio1-clk Bsdio1-pwr B emmcemmc-clk Bremmc-cmd Bremmc-pwr B emmc-bus1 Bemmc-bus4@ Bemmc-bus8 Br emmc-reset B rspi0spi0-clk B r"spi0-cs0 B r%spi0-tx Br#spi0-rx Br$spi0-cs1 Bspi1spi1-clk B r'spi1-cs0 B r*spi1-rx Br)spi1-tx Br(spi2spi2-cs1 Bspi2-clk Br+spi2-cs0 Br.spi2-rx Br-spi2-tx B r,uart0uart0-xfer Br7uart0-cts Br8uart0-rts Br9uart1uart1-xfer B r:uart1-cts B uart1-rts B uart2uart2-xfer Br;uart3uart3-xfer Br<uart3-cts B uart3-rts B uart4uart4-xfer Br=uart4-cts B uart4-rts B tsadcotp-pin B rCotp-out B rDpwm0pwm0-pin BrQpwm1pwm1-pin BrRpwm2pwm2-pin BrSpwm3pwm3-pin BrTgmacrgmii-pins B rmii-pins Bspdifspdif-tx B rfpcfg-pull-none-drv-8ma w rpcfg-pull-up-drv-8ma [ pcfg-output-high rbuttonspwr-key-l Brap-lid-int-l Brpmicpmic-int-l BrJdvs-1 B rKdvs-2 BrLrebootap-warm-reset-h B rrecovery-switchrec-mode-l B tpmtpm-int-h Bwrite-protectfw-wp-ap Bcodechp-det Brint-codec BrPmic-det B rheadsetts3a227e-int-l Br3backlightbl_pwr_en B rbl-en Brlcdlcd-en Bravdd-1v8-disp-en B rchargerac-present-ap Brcros-ecec-int Br&trackpadtrackpad-int Br4usb-hosthost1-pwr-en B rusbotg-pwren-h B rbuck-5vdrv-5v Brchosen serial2:115200n8memorymemory power-button gpio-keys defaultkey-power Power 2 t dgpio-restart gpio-restart 2  default emmc-pwrseqmmc-pwrseq-emmc default rsdio-pwrseqmmc-pwrseq-simpleE  ext_clock default rvcc-5vregulator-fixedvcc_5vLK@LK@     defaultrMvcc33-sysregulator-fixed vcc33_sys2Z2Z rvcc50-hdmiregulator-fixed vcc50_hdmi M   defaultvdd-logicpwm-regulator vdd_logic   { *~psound!rockchip,rockchip-audio-max98090 default =VEYRON-I2S L d yO O   backlight-regulatorregulator-fixed    defaultbacklight_regulator  :rpanel-regulatorregulator-fixed    defaultpanel_regulator rvcc18-lcdregulator-fixed    default vcc18_lcd backlightpwm-backlight    $  default B@ 1  F  Wrpanelinnolux,n116bgeCokay W dpanel-timingl nV v <       portsportendpoint r|gpio-charger gpio-charger mains 2 defaultlid-switch gpio-keys defaultswitch-lid Lid 2   vccsysregulator-fixedvccsysrvcc5-host1-regulatorregulator-fixed  2  default vcc5_host1vcc5v-otg-regulatorregulator-fixed  2  default vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,wakeup-pinmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type