84( #asus,rk3288-tinkerrockchip,rk3288&"7Rockchip RK3288 Asus Tinker Boardaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbopp-table-0operating-points-v2jbopp-126000000u| opp-216000000u | opp-312000000u| opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ| opp-1608000000u_"|popp-1704000000ue|popp-1800000000ukI|\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample  @'reset3okay:DVgq|default mmc@ff0d0000rockchip,rk3288-dw-mshc 5Eswbiuciuciu-driveciu-sample ! @'reset3okay:V|defaultmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample "@'reset 3disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample #@'reset 3disabledsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW 'saradc-apb3okay"spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk.  3txrx ,|default 3disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk. 3txrx -|default !"# 3disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclk.3txrx .|default$%&' 3disabledi2c@ff140000rockchip,rk3288-i2c >i2c5M|default( 3disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5O|default) 3disabledi2c@ff160000rockchip,rk3288-i2c @i2c5P|default* 3disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Q|default+3okaybpserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7=G5MUbaudclkapb_pclk.3txrx|default,3okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8=G5NVbaudclkapb_pclk.3txrx|default-3okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9=G5OWbaudclkapb_pclk|default.3okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :=G5PXbaudclkapb_pclk.3txrx|default/3okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;=G5QYbaudclkapb_pclk.  3txrx|default03okaydma-controller@ff250000arm,pl330arm,primecell%@T_z5 apb_pclkbthermal-zonesreserve-thermal1cpu-thermald1tripscpu_alert0ppassiveb2cpu_alert1$passiveb3cpu_crit_ criticalcooling-mapsmap020map130gpu-thermald1tripsgpu_alert0ppassiveb4gpu_crit_ criticalcooling-mapsmap04 5tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 'tsadc-apb|initdefaultsleep6768's3okay>Ub1ethernet@ff290000rockchip,rk3288-gmac)pmacirqeth_wake_irq885fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmaceth3okay9inputrgmii:|default; < 'B@0 usb@ff500000 generic-ehciP 5=usb3okayusb@ff520000 generic-ohciR )5=usb 3disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otg$host> usb2-phy,3okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg$otgCUd@@ ? usb2-phy3okayusb@ff5c0000 generic-ehci\ 5 3disableddma-controller@ff600000arm,pl330arm,primecell`@T_z5 apb_pclk 3disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5L|default@3okaypmic@1brockchip,rk808&Axin32krk808-clkout2sA A |defaultBCDE}FFFFFF F&3bregulatorsDCDC_REG1@Tf q~\vdd_armpb regulator-state-memDCDC_REG2@Tf P~vdd_gpupburegulator-state-memB@DCDC_REG3@Tvcc_ddrregulator-state-memDCDC_REG4@Tf2Z~2Zvcc_iobregulator-state-mem2ZLDO_REG1@Tfw@~w@ vcc18_ldo1bregulator-state-memw@LDO_REG2@Tf2Z~2Z vcc33_mipiregulator-state-memLDO_REG3@TfB@~B@vdd_10regulator-state-memB@LDO_REG4@Tfw@~w@ vcc18_codecregulator-state-memw@LDO_REG5@Tfw@~2Z vccio_sdbregulator-state-mem2ZLDO_REG6@TfB@~B@ vdd10_lcdregulator-state-memB@LDO_REG7@Tfw@~w@vcc_18bregulator-state-memw@LDO_REG8@Tfw@~w@ vcc18_lcdregulator-state-memw@SWITCH_REG1@T vcc33_sdbregulator-state-memSWITCH_REG2@T vcc33_lanb:regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c5N|defaultG3okaypwm@ff680000rockchip,rk3288-pwmh|defaultH5_3okaypwm@ff680010rockchip,rk3288-pwmh|defaultI5_ 3disabledpwm@ff680020rockchip,rk3288-pwmh |defaultJ5_ 3disabledpwm@ff680030rockchip,rk3288-pwmh0|defaultK5_ 3disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh b]power-domain@9 5chgfdehilkj$&LMNOPQRSTpower-domain@11 5op&UVpower-domain@12 5&Wpower-domain@13 5&XYreboot-modesyscon-reboot-mode-4RB@RBNRB ^RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5 xin24m8jHjk$w#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb8edp-phyrockchip,rk3288-dp-phy5h24m 3disabledbmio-domains"rockchip,rk3288-io-voltage-domain3okayusbphyrockchip,rk3288-usb-phy3okayusb-phy@320 5]phyclk 'phy-resetb?usb-phy@33445^phyclk 'phy-resetb=usb-phy@348H5_phyclk 'phy-resetb>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O3okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif5T mclkhclk.Z3tx 6|default[8 3disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 55Ri2s_clki2s_hclk.ZZ3txrx|default\3okaybcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 'crypto-rstiommu@ff900800rockchip,iommu@ 5 aclkiface 3disablediommu@ff914000rockchip,iommu @P 5 aclkiface 3disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk] ilm 'coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop] def 'axiahbdclk-^3okayportb endpoint@04_bqendpoint@14`bnendpoint@24abhendpoint@34bbkiommu@ff930300rockchip,iommu 5 aclkiface] 3okayb^vop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop]  'axiahbdclk-c3okayportb endpoint@04dbrendpoint@14eboendpoint@24fbiendpoint@34gbliommu@ff940300rockchip,iommu 5 aclkiface] 3okaybcdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk] 8 3disabledportsport@0endpoint@04hbaendpoint@14ibfport@1lvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvds|lcdcj] 8 3disabledportsport@0endpoint@04kbbendpoint@14lbgport@1dp@ff970000rockchip,rk3288-dp@ b5icdppclkmdp] o'dp8 3disabledportsport@0endpoint@04nb`endpoint@14obeport@1hdmi@ff980000rockchip,rk3288-dw-hdmiG8 g5hmniahbisfrcec] 3okayDpbportsportendpoint@04qb_endpoint@14rbdvideo-codec@ff9a0000rockchip,rk3288-vpu   pvepuvdpu5 aclkhclk-s] iommu@ff9a0800rockchip,iommu 5 aclkiface] bsiommu@ff9c0440rockchip,iommu @@@ o5 aclkiface 3disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ pjobmmugpu5t] 3okayPub5opp-table-1operating-points-v2btopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000rockchip,rk3288-qossyscon bXqos@ffaa0080rockchip,rk3288-qossyscon bYqos@ffad0000rockchip,rk3288-qossyscon bMqos@ffad0100rockchip,rk3288-qossyscon bNqos@ffad0180rockchip,rk3288-qossyscon bOqos@ffad0400rockchip,rk3288-qossyscon bPqos@ffad0480rockchip,rk3288-qossyscon bQqos@ffad0500rockchip,rk3288-qossyscon bLqos@ffad0800rockchip,rk3288-qossyscon bRqos@ffad0880rockchip,rk3288-qossyscon bSqos@ffad0900rockchip,rk3288-qossyscon bTqos@ffae0000rockchip,rk3288-qossyscon bWqos@ffaf0000rockchip,rk3288-qossyscon bUqos@ffaf0080rockchip,rk3288-qossyscon bVdma-controller@ffb20000arm,pl330arm,primecell@T_z5 apb_pclkbZefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400\q@ @ `   bpinctrlrockchip,rk3288-pinctrl8gpio@ff750000rockchip,gpio-banku Q5@\qbAgpio@ff780000rockchip,gpio-bankx R5A\qb~gpio@ff790000rockchip,gpio-banky S5B\qgpio@ff7a0000rockchip,gpio-bankz T5C\qgpio@ff7b0000rockchip,gpio-bank{ U5D\qb<gpio@ff7c0000rockchip,gpio-bank| V5E\qgpio@ff7d0000rockchip,gpio-bank} W5F\qgpio@ff7e0000rockchip,gpio-bank~ X5G\qbgpio@ff7f0000rockchip,gpio-bank Y5H\qhdmihdmi-cec-c0vhdmi-cec-c7vhdmi-ddc vvhdmi-ddc-unwedge wvpcfg-output-lowbwpcfg-pull-upbxpcfg-pull-downbypcfg-pull-nonebvpcfg-pull-none-12ma b|suspendglobal-pwroffvbCddrio-pwroffvddr0-retentionxddr1-retentionxedpedp-hpd yi2c0i2c0-xfer vvb@i2c1i2c1-xfer vvb(i2c2i2c2-xfer  v vbGi2c3i2c3-xfer vvb)i2c4i2c4-xfer vvb*i2c5i2c5-xfer vvb+i2s0i2s0-bus`vvvvvvb\lcdclcdc-ctl@vvvvbjsdmmcsdmmc-clkzb sdmmc-cmd{bsdmmc-cdxbsdmmc-bus1xsdmmc-bus4@{{{{bsdmmc-pwr vbsdio0sdio0-bus1xsdio0-bus4@xxxxbsdio0-cmdxbsdio0-clkvbsdio0-cdxsdio0-wpxsdio0-pwrxsdio0-bkpwrxsdio0-intxbsdio1sdio1-bus1xsdio1-bus4@xxxxsdio1-cdxsdio1-wpxsdio1-bkpwrxsdio1-intxsdio1-cmdxsdio1-clkvsdio1-pwr xemmcemmc-clkvemmc-cmdxemmc-pwr xemmc-bus1xemmc-bus4@xxxxemmc-bus8xxxxxxxxspi0spi0-clk xbspi0-cs0 xbspi0-txxbspi0-rxxbspi0-cs1xspi1spi1-clk xb spi1-cs0 xb#spi1-rxxb"spi1-txxb!spi2spi2-cs1xspi2-clkxb$spi2-cs0xb'spi2-rxxb&spi2-tx xb%uart0uart0-xfer xvb,uart0-ctsxuart0-rtsvuart1uart1-xfer x vb-uart1-cts xuart1-rts vuart2uart2-xfer xvb.uart3uart3-xfer xvb/uart3-cts xuart3-rts vuart4uart4-xfer xvb0uart4-cts xuart4-rts vtsadcotp-pin vb6otp-out vb7pwm0pwm0-pinvbHpwm1pwm1-pinvbIpwm2pwm2-pinvbJpwm3pwm3-pinvbKgmacrgmii-pinsvvvv||||vvv ||vvb;rmii-pinsvvvvvvvvvvspdifspdif-tx vb[pcfg-pull-none-drv-8mabzpcfg-pull-up-drv-8mab{backlightbl-envbuttonspwrbtnxb}eth_phyeth-phy-pwrvpmicpmic-intxbBdvs-1 ybDdvs-2 ybEusbhost-vbus-drvvpwr-3gvsdiowifi-enable vvbchosenserial2:115200n8memorymemoryexternal-gmac-clock fixed-clocksY@ ext_gmacb9gpio-keys gpio-keys|default}button wA t GPIO Key Power  (dgpio-leds gpio-ledsled-0 w~ :mmc0led-1 w~ :heartbeatled-2 wA :default-onsdio-pwrseqmmc-pwrseq-simple5 ext_clock|default P<<bsoundsimple-audio-card \i2s urockchip,tinker-codec simple-audio-card,codec simple-audio-card,cpu vsys-regulatorregulator-fixedvcc_sysfLK@~LK@@TbFsdmmc-regulatorregulator-fixed  |defaultvcc_sdf2Z~2Z   #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedbroken-cddisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizedvs-gpiosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellssdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthstdout-pathautorepeatlinux,codelabellinux,input-typedebounce-intervallinux,default-triggerreset-gpiossimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssound-daistartup-delay-usvin-supply