BN8>(Z>$rockchip,rk3128-evbrockchip,rk3128 +!7Rockchip RK3128 Evaluation boardarm-pmuarm,cortex-a7-pmu0=LMNOHcpus+cpu@f00[cpuarm,cortex-a7gk@y sB@cpu@f01[cpuarm,cortex-a7gcpu@f02[cpuarm,cortex-a7gcpu@f03[cpuarm,cortex-a7gtimerarm,armv7-timer0=   n6oscillator fixed-clockn6xin24msyscon@100a0000&rockchip,rk3128-pmusysconsimple-mfdg interrupt-controller@10139000arm,cortex-a7-gic g   = usb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2g = y"otg.otg6 ;usb2-phyEokayLusb@101c0000 generic-ehcig = 6 ;usbEokayusb@101e0000 generic-ohcig = 6 ;usbEokaymmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshcg!@@ = yDrv"biuciuciu-driveciu-sampleX ]rx-txgrрQreset Edisabledmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshcg!@ = yEsw"biuciuciu-driveciu-sampleX ]rx-txgrрRreset Edisabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshcg!@ = yGuy"biuciuciu-driveciu-sampleX ]rx-txgrрSresetEokaydefault  nand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfcgP@ =yC"ahbnfcdefault  Edisabledclock-controller@20000000rockchip,rk3128-crug y"xin24m#gsyscon@20008000&rockchip,rk3128-grfsysconsimple-mfdg +usb2phy@17crockchip,rk3128-usb2phyg| y"phyclk usb480m_phyEokayhost-port =5 linestateEokay otg-port$=#34otg-bvalidotg-idlinestateEokaytimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timerg @  =yaU "pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timerg @  =yaV "pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timerg @@  =;yaW "pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timerg @`  =<yaX "pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timerg @  ==yaY "pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timerg @  =>yaZ "pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdtg  ="y? Edisabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwmg y^default Edisabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwmg y^default Edisabledpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwmg  y^default Edisabledpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwmg 0y^default Edisabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2cg ` ="i2cyMdefault+Eokayrtc@51haoyu,hym8563gQxin32ki2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2cg  ="i2cyNdefault+ Edisabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2cg  ="i2cyOdefault+ Edisabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uartg  =n6yMU"baudclkapb_pclkX  ]txrxdefault  !' Edisabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uartg @ =n6yNV"baudclkapb_pclkX  ]txrxdefault"' Edisabledserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uartg  =n6yOW"baudclkapb_pclkX  ]txrxdefault#' Edisabledsaradc@2006c000rockchip,saradcg  =y[>"saradcapb_pclkW saradc-apb1 Edisabledi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2cg   ="i2cyLdefault$+ Edisabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spig @ =yAR"spiclkapb_pclkX  ]txrxdefault%&'()+ Edisableddma-controller@20078000arm,pl330arm,primecellg @=C^y "apb_pclku pinctrlrockchip,rk3128-pinctrl+gpio@2007c000rockchip,gpio-bankg  =$y@,gpio@20080000rockchip,gpio-bankg  =%yAgpio@20084000rockchip,gpio-bankg @ =&yB.gpio@20088000rockchip,gpio-bankg  ='yCpcfg-pull-default+pcfg-pull-none*emmcemmc-clk* emmc-cmd+ emmc-cmd1+emmc-pwr+emmc-bus1+emmc-bus4@++++emmc-bus8++++++++ gmacrgmii-pins+ + + + +++++++++++rmii-pins+ + ++++++++hdmihdmii2c-xfer **hdmi-hpd*hdmi-cec*i2c0i2c0-xfer **$i2c1i2c1-xfer **i2c2i2c2-xfer **i2c3i2c3-xfer **i2si2s-bus`* * * * **i2s1-bus`******lcdclcdc-dclk*lcdc-den *lcdc-hsync *lcdc-vsync *lcdc-rgb24 * *************nfcflash-ale*flash-cle*flash-wrn*flash-rdn*flash-rdy*flash-cs0*flash-dqs*flash-bus8********pwm0pwm0-pin*pwm1pwm1-pin*pwm2pwm2-pin*pwm3pwm3-pin*sdiosdio-clk*sdio-cmd+sdio-pwren+sdio-bus4@++++sdmmcsdmmc-clk*sdmmc-cmd+sdmmc-wp+sdmmc-pwren+sdmmc-bus4@++++spdifspdif-tx*spi0spi0-clk+'spi0-cs0 +(spi0-tx +%spi0-rx +&spi0-cs1 +)spi1-clk+spi1-cs0+spi1-tx+spi1-rx+spi1-cs1+spi2-clk +spi2-cs0+spi2-tx +spi2-rx +uart0uart0-xfer +*uart0-cts* uart0-rts*!uart1uart1-xfer  + +"uart1-cts*uart1-rts *uart2uart2-xfer +*#uart2-cts*uart2-rts*usb-hosthost-vbus-drv*/usb-otgotg-vbus-drv*-aliases/pinctrl/gpio@2007c000/pinctrl/gpio@20080000/pinctrl/gpio@20084000/pinctrl/gpio@20088000/i2c@20056000/mmc@1021c000chosen/serial@20068000memory@60000000[memoryg`@vcc5v0-otg-regulatorregulator-fixed ,default- vcc5v0_otgLK@.LK@vcc5v0-host-regulatorregulator-fixed .default/ vcc5v0_hostFLK@.LK@ compatibleinterrupt-parent#address-cells#size-cellsmodelinterruptsinterrupt-affinitydevice_typeregclock-latencyclocksoperating-points#cooling-cellsphandlearm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsinterrupt-controller#interrupt-cellsclock-namesdr_modephysphy-namesstatusvbus-supplydmasdma-namesfifo-depthmax-frequencyresetsreset-namesbus-widthpinctrl-namespinctrl-0rockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesinterrupt-names#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrangesgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsgpio0gpio1gpio2gpio3i2c1mmc0stdout-pathgpioregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on