^8Yp(=Y8(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000/spi@20070000/spi@20074000/mmc@10214000oscillator ,fixed-clockn6xin24mEgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscorex  disabledx5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3,video-codec@10104000,rockchip,rk3066-vpu@   vepuvdpu (aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu,cache-controller@10138000,arm,pl310-cache:H8scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer     disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicTiserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "zbaudclkapb_pclk@L okaytxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #zbaudclkapb_pclkAM okaytxrxdefaultqos@1012d000,rockchip,rk3066-qossyscon !qos@1012e000,rockchip,rk3066-qossyscon  qos@1012f000,rockchip,rk3066-qossyscon qos@1012f080,rockchip,rk3066-qossyscon qos@1012f100,rockchip,rk3066-qossyscon qos@1012f180,rockchip,rk3066-qossyscon qos@1012f200,rockchip,rk3066-qossyscon qos@1012f280,rockchip,rk3066-qossyscon usb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg@@  usb2-phy okayusb@101c0000 ,snps,dwc2 otghost usb2-phy okayethernet@10204000,rockchip,rk3066-emac @<  D hclkmacref drmii okay # default  mdioethernet-phy@0 mmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciurx-tx.Q9reset okayEdefaultSmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciurx-tx.R9reset  disableddefaultmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciurx-tx.S9reset  disablednand-controller@10500000,rockchip,rk2928-nfcP@ ahb  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode_@fRBrRBRB RBpower-controller!,rockchip,rk3066-power-controllerpower-domain@7POpower-domain@6  power-domain@8!grf@20008000&,rockchip,rk3066-grfsysconsimple-mfd  usbphy,rockchip,rk3066a-usb-phy okayusb-phy@17c|Qphyclkusb-phy@188Rphyclkdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk  disabledi2c@2002d000,rockchip,rk3066-i2c  ( i2cP  disableddefault"i2c@2002f000,rockchip,rk3066-i2c  ) Qi2c okaydefault#tps@2d-$% %%#%/&;&G%S% ,ti,tps65910regulatorsregulator@0`vcc_rtcovrtcregulator@1`vcc_ioovio&regulator@2`vdd_arm '`ovdd19regulator@3`vcc_ddr '`ovdd2regulator@5 `vcc18_cifovdig1regulator@6`vdd_11ovdig2regulator@7`vcc_25ovpllregulator@8`vcc_18ovdacregulator@9 `vcc25_hdmio vaux1regulator@10`vcca_33o vaux2regulator@11 `vcc_rmii vaux33 regulator@12 `vcc28_cifo vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm F  disableddefault'pwm@20030010,rockchip,rk2928-pwm F  disableddefault(watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3 okaypwm@20050020,rockchip,rk2928-pwm  G  disableddefault)pwm@20050030,rockchip,rk2928-pwm 0G okaydefault*Hi2c@20056000,rockchip,rk3066-i2c ` * Ri2c  disableddefault+i2c@2005a000,rockchip,rk3066-i2c  + Si2c  disableddefault,i2c@2005e000,rockchip,rk3066-i2c  4 Ti2c  disableddefault-serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $zbaudclkapb_pclkBN okaytxrxdefault.serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %zbaudclkapb_pclkCO okay txrxdefault/saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkW 9saradc-apb  disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &   txrx  disableddefault0123spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @  txrx  disableddefault4567dma-controller@20078000,arm,pl330arm,primecell @ apb_pclkcpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a988"@ Oa* s* 'g83@A9cpu@1cpu,arm,cortex-a98A9display-subsystem,rockchip,display-subsystemL:;sram@10080000 ,mmio-sram Rsmp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop  aclk_vopdclk_vophclk_vop,def 9axiahbdclk  disabledport:endpoint@0Y<@vop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop,ghi 9axiahbdclk  disabledport;endpoint@0Y=Ahdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefault>?,   disabledportsport@0endpoint@0Y@<endpoint@1YA=port@1i2s@10118000,rockchip,rk3066-i2s  defaultBKi2s_clki2s_hclktxrxi  disabledi2s@1011a000,rockchip,rk3066-i2s   defaultCLi2s_clki2s_hclktxrxi  disabledi2s@1011c000,rockchip,rk3066-i2s  defaultDMi2s_clki2s_hclk  txrxi  disabledclock-controller@20000000,rockchip,rk3066a-cru Exin24m @^_ ׄ#gрxhрxhtimer@2000e000,snps,dw-apb-timer  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer  ,TB timerpclktimer@2003a000,snps,dw-apb-timer  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk \ 9saradc-apb  disabledpinctrl,rockchip,rk3066a-pinctrl Rgpio@20034000,rockchip,gpio-bank @ 6UTigpio@2003c000,rockchip,gpio-bank  7VTigpio@2003e000,rockchip,gpio-bank  8WTigpio@20080000,rockchip,gpio-bank  9XTiIgpio@20084000,rockchip,gpio-bank @ :YTigpio@2000a000,rockchip,gpio-bank  <ZTi$pcfg-pull-defaultGpcfg-pull-noneFemacemac-xferFFFFFFFF emac-mdio FF emmcemmc-clkGemmc-cmd Gemmc-rst Ghdmihdmi-hpdG?hdmii2c-xfer FF>i2c0i2c0-xfer FF"i2c1i2c1-xfer FF#i2c2i2c2-xfer FF+i2c3i2c3-xfer FF,i2c4i2c4-xfer FF-pwm0pwm0-outF'pwm1pwm1-outF(pwm2pwm2-outF)pwm3pwm3-outF*spi0spi0-clkG0spi0-cs0G3spi0-txG1spi0-rxG2spi0-cs1Gspi1spi1-clkG4spi1-cs0G7spi1-rxG6spi1-txG5spi1-cs1Guart0uart0-xfer GGuart0-ctsGuart0-rtsGuart1uart1-xfer GGuart1-ctsGuart1-rtsGuart2uart2-xfer G G.uart3uart3-xfer GG/uart3-ctsGuart3-rtsGsd0sd0-clkGsd0-cmd Gsd0-cdGsd0-wpGsd0-bus-width1 Gsd0-bus-width4@ G G G Gsd1sd1-clkGsd1-cmdGsd1-cdGsd1-wpGsd1-bus-width1Gsd1-bus-width4@GGGGi2s0i2s0-busGG G G G G GGGBi2s1i2s1-bus`GGGGGGCi2s2i2s2-bus`GGGGGGDlan8720aphy-intFmemory@60000000memory`@vdd-log,pwm-regulator  H`vdd_logOOoB@dO* okaysdmmc-regulator,regulator-fixed `sdmmc-supply-- I!2&vsys-regulator,regulator-fixed`vsysLK@LK@% #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0clock-frequency#clock-cellsclock-output-namesphandleregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply