n8e`( oe(Cvariscite,var-dvk-om44variscite,var-som-om44ti,omap4460ti,omap4 +7Variscite VAR-DVK-OM44chosenaliases?=/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0?B/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0?G/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0EL/ocp/interconnect@48000000/segment@200000/target-module@150000/i2c@0?Q/ocp/interconnect@48000000/segment@0/target-module@9c000/mmc@0?V/ocp/interconnect@48000000/segment@0/target-module@b4000/mmc@0?[/ocp/interconnect@48000000/segment@0/target-module@ad000/mmc@0?`/ocp/interconnect@48000000/segment@0/target-module@d1000/mmc@0?e/ocp/interconnect@48000000/segment@0/target-module@d5000/mmc@0Bj/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0Br/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0Bz/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0B/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0 /ocp/dsp/ocp/ipu@55020000 /display /connectorcpus+cpu@0arm,cortex-a9cpucpuW0 `O  cpu@1arm,cortex-a9cpusram@40304000 mmio-sram@0@ interrupt-controller@48241000arm,cortex-a9-gic)H$H$  cache-controller@48242000arm,pl310-cacheH$ :H local-timer@48240600arm,cortex-a9-twd-timerH$  T  interrupt-controller@48281000ti,omap4-wugen-mpu)H(  ocpsimple-pm-bus_$ +ml3-noc@44000000ti,omap4-l3-nocDD ET  interconnect@4a300000ti,omap4-l4-wkupsimple-pm-bus_  fckJ0J0J0 taplaia0+$mJ0J1J2segment@0simple-pm-bus+m`` @@PPtarget-module@4000ti,sysc-omap2ti,sysc@@ trevsysc~ 0fck+ m@counter@0ti,omap-counter32k target-module@6000ti,sysc-omap4ti,sysc`trev+ m` prm@0ti,omap4-prmsimple-bus  T + m clocks+sys_clkin_ck@110 ti,mux-clock sys_clkin_ck  abe_dpll_bypass_clk_mux_ck@108 ti,mux-clockabe_dpll_bypass_clk_mux_ck =abe_dpll_refclk_mux_ck@10c ti,mux-clockabe_dpll_refclk_mux_ck  <dbgclk_mux_ckfixed-factor-clockdbgclk_mux_ckl4_wkup_clk_mux_ck@108 ti,mux-clockl4_wkup_clk_mux_ck syc_clk_div_ck@100ti,divider-clocksyc_clk_div_ck usim_ck@1858ti,divider-clockusim_ckX usim_fclk@1858ti,gate-clock usim_fclkXtrace_clk_div_ckti,clkdm-gate-clocktrace_clk_div_ck  div_ts_ck@1888ti,divider-clock div_ts_ck   bandgap_ts_fclk@1888ti,gate-clockbandgap_ts_fclkclockdomainsemu_sys_clkdmti,clockdomainemu_sys_clkdml4_wkup_cm@1800 ti,omap4-cm l4_wkup_cm+ mclk@20 ti,clkctrll4_wkup_clkctrl \ emu_sys_cm@1a00 ti,omap4-cm emu_sys_cm+ mclk@20 ti,clkctrlemu_sys_clkctrl  prm@300#ti,omap4-prm-instti,omap-prm-inst prm@400#ti,omap4-prm-instti,omap-prm-inst hprm@500#ti,omap4-prm-instti,omap-prm-inst prm@600#ti,omap4-prm-instti,omap-prm-instprm@700#ti,omap4-prm-instti,omap-prm-inst 8prm@f00#ti,omap4-prm-instti,omap-prm-inst prm@1000#ti,omap4-prm-instti,omap-prm-inst prm@1100#ti,omap4-prm-instti,omap-prm-inst@ prm@1200#ti,omap4-prm-instti,omap-prm-inst prm@1300#ti,omap4-prm-instti,omap-prm-instprm@1400#ti,omap4-prm-instti,omap-prm-inst prm@1600#ti,omap4-prm-instti,omap-prm-instprm@1700#ti,omap4-prm-instti,omap-prm-inst prm@1900#ti,omap4-prm-instti,omap-prm-inst prm@1b00#ti,omap4-prm-instti,omap-prm-inst@target-module@a000ti,sysc-omap4ti,sysctrev+ mscrm@0ti,omap4-scrm clocks+auxclk0_src_gate_ck@310 ti,composite-no-wait-gate-clockauxclk0_src_gate_ck auxclk0_src_mux_ck@310ti,composite-mux-clockauxclk0_src_mux_ck  auxclk0_src_ckti,composite-clockauxclk0_src_ck auxclk0_ck@310ti,divider-clock auxclk0_ck  0auxclk1_src_gate_ck@314 ti,composite-no-wait-gate-clockauxclk1_src_gate_ck !auxclk1_src_mux_ck@314ti,composite-mux-clockauxclk1_src_mux_ck  "auxclk1_src_ckti,composite-clockauxclk1_src_ck!" #auxclk1_ck@314ti,divider-clock auxclk1_ck# 1auxclk2_src_gate_ck@318 ti,composite-no-wait-gate-clockauxclk2_src_gate_ck $auxclk2_src_mux_ck@318ti,composite-mux-clockauxclk2_src_mux_ck  %auxclk2_src_ckti,composite-clockauxclk2_src_ck$% &auxclk2_ck@318ti,divider-clock auxclk2_ck& 2auxclk3_src_gate_ck@31c ti,composite-no-wait-gate-clockauxclk3_src_gate_ck 'auxclk3_src_mux_ck@31cti,composite-mux-clockauxclk3_src_mux_ck  (auxclk3_src_ckti,composite-clockauxclk3_src_ck'( )auxclk3_ck@31cti,divider-clock auxclk3_ck) 3auxclk4_src_gate_ck@320 ti,composite-no-wait-gate-clockauxclk4_src_gate_ck  *auxclk4_src_mux_ck@320ti,composite-mux-clockauxclk4_src_mux_ck   +auxclk4_src_ckti,composite-clockauxclk4_src_ck*+ ,auxclk4_ck@320ti,divider-clock auxclk4_ck,  4auxclk5_src_gate_ck@324 ti,composite-no-wait-gate-clockauxclk5_src_gate_ck$ -auxclk5_src_mux_ck@324ti,composite-mux-clockauxclk5_src_mux_ck $ .auxclk5_src_ckti,composite-clockauxclk5_src_ck-. /auxclk5_ck@324ti,divider-clock auxclk5_ck/$ 5auxclkreq0_ck@210 ti,mux-clockauxclkreq0_ck012345auxclkreq1_ck@214 ti,mux-clockauxclkreq1_ck012345auxclkreq2_ck@218 ti,mux-clockauxclkreq2_ck012345auxclkreq3_ck@21c ti,mux-clockauxclkreq3_ck012345auxclkreq4_ck@220 ti,mux-clockauxclkreq4_ck012345 auxclkreq5_ck@224 ti,mux-clockauxclkreq5_ck012345$clockdomainstarget-module@c000ti,sysc-omap4ti,sysc trevsysc~+ mscm@c000ti,omap4-scm-wkupsegment@10000simple-pm-bus+xm@@PPtarget-module@0ti,sysc-omap2ti,sysctrevsyscsyss~*   fckdbclk+ mgpio@0ti,omap4-gpio T7IY)target-module@4000ti,sysc-omap2ti,sysc@@@trevsyscsyss"~* fck+ m@wdt@0ti,omap4-wdtti,omap3-wdt TPtarget-module@8000ti,sysc-omap2-timerti,sysctrevsyscsyss' ~* fck+ meytimer@0ti,omap3430-timer fcktimer_sys_ck T%  target-module@c000ti,sysc-omap2ti,sysctrevsyscsyss' ~* Xfck+ mkeypad@0ti,omap4-keypad Txtmpu disabledtarget-module@e000ti,sysc-omap4ti,sysc trevsysc~+ mpinmux@40 ti,omap4-padconfpinctrl-single@8+) default67hsusbb1-phy-clk-pins# hsusbb1-hub-rst-pins# 6lan7500-rst-pins# 7twl6030-wkup-pins# {segment@20000simple-pm-bus+m``  00@@PPpptarget-module@0ti,sysc disabled+ mtarget-module@2000ti,sysc disabled+ m target-module@4000ti,sysc disabled+ m@target-module@6000ti,sysc disabled+0m`p 0interconnect@4a000000ti,omap4-l4-cfgsimple-pm-bus_8 9fckJJJ taplaia0+TmJJJJ J (J(0J0segment@0simple-pm-bus+m 00@@PP``pp@  00 ``pp @@PPtarget-module@2000ti,sysc-omap4ti,sysc   trevsysc~+ m scm@0ti,omap4-scm-coresimple-bus+ mscm_conf@0syscon+ control-phy@300ti,control-phy-usb2tpower kcontrol-phy@33cti,control-phy-otghs<totghs_control jtarget-module@4000ti,sysc-omap4ti,sysc@trev+ m@cm1@0ti,omap4-cm1simple-bus + m clocks+extalt_clkin_ck fixed-clockextalt_clkin_ck7Dpad_clks_src_ck fixed-clockpad_clks_src_ck7 :pad_clks_ck@108ti,gate-clock pad_clks_ck:pad_slimbus_core_clks_ck fixed-clockpad_slimbus_core_clks_ck7secure_32k_clk_src_ck fixed-clocksecure_32k_clk_src_ck7slimbus_src_clk fixed-clockslimbus_src_clk7 ;slimbus_clk@108ti,gate-clock slimbus_clk; sys_32k_ck fixed-clock sys_32k_ck7 virt_12000000_ck fixed-clockvirt_12000000_ck7 virt_13000000_ck fixed-clockvirt_13000000_ck7]@ virt_16800000_ck fixed-clockvirt_16800000_ck7Y virt_19200000_ck fixed-clockvirt_19200000_ck7$ virt_26000000_ck fixed-clockvirt_26000000_ck7 virt_27000000_ck fixed-clockvirt_27000000_ck7 virt_38400000_ck fixed-clockvirt_38400000_ck7I tie_low_clock_ck fixed-clocktie_low_clock_ck7utmi_phy_clkout_ck fixed-clockutmi_phy_clkout_ck7xclk60mhsp1_ck fixed-clockxclk60mhsp1_ck7 dxclk60mhsp2_ck fixed-clockxclk60mhsp2_ck7 exclk60motg_ck fixed-clockxclk60motg_ck7dpll_abe_ck@1e0ti,omap4-dpll-m4xen-clock dpll_abe_ck<= >dpll_abe_x2_ck@1f0ti,omap4-dpll-x2-clockdpll_abe_x2_ck> ?dpll_abe_m2x2_ck@1f0ti,divider-clockdpll_abe_m2x2_ck?GY @abe_24m_fclkfixed-factor-clock abe_24m_fclk@abe_clk@108ti,divider-clockabe_clk@pdpll_abe_m3x2_ck@1f4ti,divider-clockdpll_abe_m3x2_ck?GY Acore_hsd_byp_clk_mux_ck@12c ti,mux-clockcore_hsd_byp_clk_mux_ckA, Bdpll_core_ck@120ti,omap4-dpll-core-clock dpll_core_ckB $,( Cdpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_x2_ckC Ddpll_core_m6x2_ck@140ti,divider-clockdpll_core_m6x2_ckDG@Ydpll_core_m2_ck@130ti,divider-clockdpll_core_m2_ckCG0Y Eddrphy_ckfixed-factor-clock ddrphy_ckEdpll_core_m5x2_ck@13cti,divider-clockdpll_core_m5x2_ckDG<Y Fdiv_core_ck@100ti,divider-clock div_core_ckF Qdiv_iva_hs_clk@1dcti,divider-clockdiv_iva_hs_clkFp Jdiv_mpu_hs_clk@19cti,divider-clockdiv_mpu_hs_clkFp Pdpll_core_m4x2_ck@138ti,divider-clockdpll_core_m4x2_ckDG8Y Gdll_clk_div_ckfixed-factor-clockdll_clk_div_ckGdpll_abe_m2_ck@1f0ti,divider-clockdpll_abe_m2_ck> Tdpll_core_m3x2_gate_ck@134 ti,composite-no-wait-gate-clockdpll_core_m3x2_gate_ckD4 Hdpll_core_m3x2_div_ck@134ti,composite-divider-clockdpll_core_m3x2_div_ckD4 Idpll_core_m3x2_ckti,composite-clockdpll_core_m3x2_ckHI dpll_core_m7x2_ck@144ti,divider-clockdpll_core_m7x2_ckDGDYiva_hsd_byp_clk_mux_ck@1ac ti,mux-clockiva_hsd_byp_clk_mux_ckJ Kdpll_iva_ck@1a0ti,omap4-dpll-clock dpll_iva_ckKL7 Ldpll_iva_x2_ckti,omap4-dpll-x2-clockdpll_iva_x2_ckL Mdpll_iva_m4x2_ck@1b8ti,divider-clockdpll_iva_m4x2_ckMGYN~ Ndpll_iva_m5x2_ck@1bcti,divider-clockdpll_iva_m5x2_ckMGYO]  Odpll_mpu_ck@160ti,omap4-dpll-clock dpll_mpu_ckP`dlh dpll_mpu_m2_ck@170ti,divider-clockdpll_mpu_m2_ckGpYper_hs_clk_div_ckfixed-factor-clockper_hs_clk_div_ckA Uusb_hs_clk_div_ckfixed-factor-clockusb_hs_clk_div_ckA [l3_div_ck@100ti,divider-clock l3_div_ckQ Rl4_div_ck@100ti,divider-clock l4_div_ckRlp_clk_div_ckfixed-factor-clocklp_clk_div_ck@ mpu_periphclkfixed-factor-clockmpu_periphclk ocp_abe_iclk@528ti,divider-clock ocp_abe_iclk S(per_abe_24m_fclkfixed-factor-clockper_abe_24m_fclkTdummy_ck fixed-clock dummy_ck7clockdomainsmpuss_cm@300 ti,omap4-cm mpuss_cm+ mclk@20 ti,clkctrlmpuss_clkctrl  tesla_cm@400 ti,omap4-cm tesla_cm+ mclk@20 ti,clkctrltesla_clkctrl  gabe_cm@500 ti,omap4-cmabe_cm+ mclk@20 ti,clkctrl abe_clkctrl l Starget-module@8000ti,sysc-omap4ti,sysctrev+ m cm2@0ti,omap4-cm2simple-bus + m clocks+per_hsd_byp_clk_mux_ck@14c ti,mux-clockper_hsd_byp_clk_mux_ckUL Vdpll_per_ck@140ti,omap4-dpll-clock dpll_per_ckV@DLH Wdpll_per_m2_ck@150ti,divider-clockdpll_per_m2_ckWP _dpll_per_x2_ck@150ti,omap4-dpll-x2-clockdpll_per_x2_ckWP Xdpll_per_m2x2_ck@150ti,divider-clockdpll_per_m2x2_ckXGPY ^dpll_per_m3x2_gate_ck@154 ti,composite-no-wait-gate-clockdpll_per_m3x2_gate_ckXT Ydpll_per_m3x2_div_ck@154ti,composite-divider-clockdpll_per_m3x2_div_ckXT Zdpll_per_m3x2_ckti,composite-clockdpll_per_m3x2_ckYZ dpll_per_m4x2_ck@158ti,divider-clockdpll_per_m4x2_ckXGXY dpll_per_m5x2_ck@15cti,divider-clockdpll_per_m5x2_ckXG\Ydpll_per_m6x2_ck@160ti,divider-clockdpll_per_m6x2_ckXG`Y ]dpll_per_m7x2_ck@164ti,divider-clockdpll_per_m7x2_ckXGdYdpll_usb_ck@180ti,omap4-dpll-j-type-clock dpll_usb_ck[ \dpll_usb_clkdcoldo_ck@1b4ti,fixed-factor-clockdpll_usb_clkdcoldo_ck\GYdpll_usb_m2_ck@190ti,divider-clockdpll_usb_m2_ck\GY `ducati_clk_mux_ck@100 ti,mux-clockducati_clk_mux_ckQ]func_12m_fclkfixed-factor-clockfunc_12m_fclk^func_24m_clkfixed-factor-clock func_24m_clk_func_24mc_fclkfixed-factor-clockfunc_24mc_fclk^func_48m_fclk@108ti,divider-clockfunc_48m_fclk^func_48mc_fclkfixed-factor-clockfunc_48mc_fclk^func_64m_fclk@108ti,divider-clockfunc_64m_fclkfunc_96m_fclk@108ti,divider-clockfunc_96m_fclk^init_60m_fclk@104ti,divider-clockinit_60m_fclk` cper_abe_nc_fclk@108ti,divider-clockper_abe_nc_fclkTusb_phy_cm_clk32k@640ti,gate-clockusb_phy_cm_clk32k@ lclockdomainsl3_init_clkdmti,clockdomainl3_init_clkdm\l4_ao_cm@600 ti,omap4-cm l4_ao_cm+ mclk@20 ti,clkctrll4_ao_clkctrl  nl3_1_cm@700 ti,omap4-cml3_1_cm+ mclk@20 ti,clkctrl l3_1_clkctrl  l3_2_cm@800 ti,omap4-cml3_2_cm+ mclk@20 ti,clkctrl l3_2_clkctrl  ducati_cm@900 ti,omap4-cm ducati_cm + m clk@20 ti,clkctrlducati_clkctrl  l3_dma_cm@a00 ti,omap4-cm l3_dma_cm + m clk@20 ti,clkctrll3_dma_clkctrl  al3_emif_cm@b00 ti,omap4-cm l3_emif_cm + m clk@20 ti,clkctrll3_emif_clkctrl  d2d_cm@c00 ti,omap4-cmd2d_cm + m clk@20 ti,clkctrl d2d_clkctrl  ml4_cfg_cm@d00 ti,omap4-cm l4_cfg_cm + m clk@20 ti,clkctrll4_cfg_clkctrl  9l3_instr_cm@e00 ti,omap4-cm l3_instr_cm+ mclk@20 ti,clkctrll3_instr_clkctrl $ ivahd_cm@f00 ti,omap4-cm ivahd_cm+ mclk@20 ti,clkctrlivahd_clkctrl  iss_cm@1000 ti,omap4-cmiss_cm+ mclk@20 ti,clkctrl iss_clkctrl  ql3_dss_cm@1100 ti,omap4-cm l3_dss_cm+ mclk@20 ti,clkctrll3_dss_clkctrl  l3_gfx_cm@1200 ti,omap4-cm l3_gfx_cm+ mclk@20 ti,clkctrll3_gfx_clkctrl  l3_init_cm@1300 ti,omap4-cm l3_init_cm+ mclk@20 ti,clkctrll3_init_clkctrl  bclock@1400 ti,omap4-cm l4_per_cm+ mclock@20 ti,clkctrll4_per_clkctrl D rclock@1a0 ti,clkctrll4_secure_clkctrl< target-module@56000ti,sysc-omap2ti,sysc``,`(trevsyscsyss#  ~* afck+ m`dma-controller@0ti,omap4430-sdmati,omap-sdma0T    target-module@58000ti,sysc-omap2ti,sysctrevsyscsyss#~* bfck+ mPhsi@0 ti,omap4-hsi@Ptsysgdd bhsi_fck TGgdd_mpu+ m@hsi-port@2000ti,omap4-hsi-port (ttxrx TChsi-port@3000ti,omap4-hsi-port08ttxrx TDtarget-module@5e000ti,sysc disabled+ m target-module@62000ti,sysc-omap2ti,sysc   trevsyscsyss ~ bHfck+ m usbhstll@0 ti,usbhs-tll TNtarget-module@64000ti,sysc-omap4ti,sysc@@@trevsyscsyss~ b8fck+ m@usbhshost@0ti,usbhs-host+ m cde3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ehci-phyohci@800ti,ohci-omap3 TLehci@c00 ti,ehci-omap  TMftarget-module@66000ti,sysc-omap2ti,sysc```trevsyscsyss ~ gfck_h!h(rstctrl+ m`mmu@0ti,omap4-iommu T4 segment@80000simple-pm-bus+m      @@PP``pp` `p p        target-module@29000ti,sysc disabled+ mtarget-module@2b000ti,sysc-omap2ti,sysctrevsyscsyss ~* b@fck+ musb_otg_hs@0ti,omap4-musbT\]mcdmaAii Iusb2-phyS^f oj{2target-module@2d000ti,sysc-omap2ti,sysctrevsyscsyss ~* bfck+ mocp2scp@0ti,omap-ocp2scp+ musb2phy@80 ti,omap-usb2Xoklwkupclk itarget-module@36000ti,sysc-omap2ti,sysc```trevsyscsyss~* mfck+ m`target-module@4d000ti,sysc-omap2ti,sysctrevsyscsyss~* mfck+ mtarget-module@59000ti,sysc-omap4-srti,sysc8tsysc~ nfck+ msmartreflex@0ti,omap4-smartreflex-mpu Ttarget-module@5b000ti,sysc-omap4-srti,sysc8tsysc~ nfck+ msmartreflex@0ti,omap4-smartreflex-iva Tftarget-module@5d000ti,sysc-omap4-srti,sysc8tsysc~ nfck+ msmartreflex@0ti,omap4-smartreflex-core Ttarget-module@60000ti,sysc disabled+ mtarget-module@74000ti,sysc-omap4ti,sysc@@ trevsysc ~ 9fck+ m@mailbox@0ti,omap4-mailbox T mbox-ipu   mbox-dsp   target-module@76000ti,sysc-omap2ti,sysc```trevsyscsyss ~* 9fck+ m`spinlock@0ti,omap4-hwspinlocksegment@100000simple-pm-bus+`m  00target-module@0ti,sysc-omap4ti,sysc trevsysc~+ mpinmux@40 ti,omap4-padconfpinctrl-single@+) defaultomcpdm-pins(# twl6040-pins#\` }tsc2004-pins#PR uuart3-pins # shsusbb1-pins`#            ohsusbb1-phy-rst-pins#L i2c1-pins# yi2c3-pins# tmmc1-pins0# twl6030-pins#^A zuart2-pins # xwl12xx-ctrl-pins#"$& mmc4-pins0# uart1-pins # wmcspi1-pins # mcsasp-pins#dss-dpi-pins#"$&(*,.0246tvxz|~ dss-hdmi-pins#Z\^ i2c4-pins# mmc5-pins8#   gpio-led-pins#>@ gpio-key-pins#b ks8851-irq-pins#< hdmi-hpd-pins#X  backlight-pins# omap4_padconf_global@5a0sysconsimple-busp+ mp ppbias_regulator@60ti,pbias-omap4ti,pbias-omap`ppbias_mmc_omap4pbias_mmc_omap4w@- target-module@2000ti,sysc disabled+ m target-module@8000ti,sysc disabled+ mtarget-module@a000ti,sysc-omap4ti,sysc trevsysc  ~5 qfck+ msegment@180000simple-pm-bus+segment@200000simple-pm-bus+hm!!  @ @P P` `p p ! 0!0  !!`!`p!p@!@P!P!!""`"`p"p""""!!target-module@4000ti,sysc disabled+ m@target-module@6000ti,sysc disabled+ m`target-module@a000ti,sysc disabled+ mtarget-module@c000ti,sysc disabled+ mtarget-module@10000ti,sysc disabled+ mtarget-module@12000ti,sysc disabled+ m target-module@14000ti,sysc disabled+ m@target-module@16000ti,sysc disabled+ m`target-module@18000ti,sysc disabled+ mtarget-module@1c000ti,sysc disabled+ mtarget-module@1e000ti,sysc disabled+ mtarget-module@20000ti,sysc disabled+ mtarget-module@26000ti,sysc disabled+ m`target-module@28000ti,sysc disabled+ mtarget-module@2a000ti,sysc disabled+ msegment@280000simple-pm-bus+segment@300000simple-pm-bus+m042@@2@ `2`p2p2232 2@11@1 1 target-module@0ti,sysc disabled+m@  @@@ ``pp @interconnect@48000000ti,omap4-l4-persimple-pm-bus_ rfck0HHHHHHtaplaia0ia1ia2ia3+mH H segment@0simple-pm-bus+m  00@@PP``ppPP``pp  00 ` ` p p``pp``pp             @ @ ` ` @     0 0 @ @ P P        P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,syscPTXtrevsyscsyss~* r0fck+ mserial@0ti,omap4-uart TJ7l defaultsokaytarget-module@32000ti,sysc-omap2-timerti,sysc   trevsyscsyss' ~* rfck+ m timer@0ti,omap3430-timerrfcktimer_sys_ck T&target-module@34000ti,sysc-omap4-timerti,sysc@@ trevsysc~ r fck+ m@timer@0ti,omap4430-timerr fcktimer_sys_ck T'target-module@36000ti,sysc-omap4-timerti,sysc`` trevsysc~ r(fck+ m`timer@0ti,omap4430-timerr(fcktimer_sys_ck T(target-module@3e000ti,sysc-omap4-timerti,sysc trevsysc~ r0fck+ mtimer@0ti,omap4430-timerr0fcktimer_sys_ck T-Ftarget-module@40000ti,sysc disabled+ mtarget-module@55000ti,sysc-omap2ti,syscPPQtrevsyscsyss~*r@r@ fckdbclk+ mPgpio@0ti,omap4-gpio TIY) target-module@57000ti,sysc-omap2ti,syscppqtrevsyscsyss~*rHrH fckdbclk+ mpgpio@0ti,omap4-gpio TIY) target-module@59000ti,sysc-omap2ti,sysctrevsyscsyss~*rPrP fckdbclk+ mgpio@0ti,omap4-gpio T IY) vtarget-module@5b000ti,sysc-omap2ti,sysctrevsyscsyss~*rXrX fckdbclk+ mgpio@0ti,omap4-gpio T!IY)target-module@5d000ti,sysc-omap2ti,sysctrevsyscsyss~*r`r` fckdbclk+ mgpio@0ti,omap4-gpio T"IY) ~target-module@60000ti,sysc-omap2ti,sysctrevsyscsyss~* rfck+ mi2c@0 ti,omap4-i2c T=+ defaulttokay7tsc2004@48 ti,tsc2004H defaultu vT disabledtmp105@49 ti,tmp105Ieeprom@50microchip,24c32atmel,24c32Ptarget-module@6a000ti,sysc-omap2ti,syscPTXtrevsyscsyss~* r fck+ mserial@0ti,omap4-uart TH7lokay defaultwtarget-module@6c000ti,sysc-omap2ti,syscPTXtrevsyscsyss~* r(fck+ mserial@0ti,omap4-uart TI7lokay defaultxtarget-module@6e000ti,sysc-omap2ti,syscPTXtrevsyscsyss~* r8fck+ mserial@0ti,omap4-uart TF7l disabledtarget-module@70000ti,sysc-omap2ti,sysctrevsyscsyss~* rfck+ mi2c@0 ti,omap4-i2c T8+ defaultyokay7twl@48H T ti,twl6030) defaultz{rtcti,twl4030-rtcT regulator-vaux1ti,twl6030-vaux1B@-regulator-vaux2ti,twl6030-vaux2O*regulator-vaux3ti,twl6030-vaux3B@-regulator-vmmcti,twl6030-vmmcO- regulator-vppti,twl6030-vppw@&%regulator-vusimti,twl6030-vusim--Sregulator-vdacti,twl6030-vdac regulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxioS regulator-vusbti,twl6030-vusb |regulator-v1v8ti,twl6030-v1v8S regulator-v2v1ti,twl6030-v2v1S usb-comparatorti,twl6030-usbT g|pwmti,twl6030-pwmrpwmledti,twl6030-pwmledrgpadcti,twl6030-gpadcT}twl@4b ti,twl6040K default} Tw ~ target-module@72000ti,sysc-omap2ti,sysc   trevsyscsyss~* rfck+ m i2c@0 ti,omap4-i2c T9+ disabledtarget-module@76000ti,sysc-omap4ti,sysc`` trevsysc~ rfck+ m`target-module@78000ti,sysc-omap2ti,sysctrevsyscsyss ~* r8fck+ melm@0ti,am3352-elm  T disabledtarget-module@86000ti,sysc-omap2-timerti,sysc```trevsyscsyss' ~* rfck+ m`timer@0ti,omap3430-timerrfcktimer_sys_ck T.Ftarget-module@88000ti,sysc-omap4-timerti,sysc trevsysc~ rfck+ mtimer@0ti,omap4430-timerrfcktimer_sys_ck T/Ftarget-module@90000ti,sysc-omap2ti,sysc   trevsysc~ fck+ m rng@0 ti,omap4-rng  T4target-module@96000ti,sysc-omap2ti,sysc `tsysc ~ rfck+ m `mcbsp@0ti,omap4-mcbsptmpu rfck Tcommon txrx disabledtarget-module@98000ti,sysc-omap4ti,sysc   trevsysc~ rfck+ m spi@0ti,omap4-mcspi TA+@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3okay defaulteth@0ks8851 defaultn6 ~T target-module@9a000ti,sysc-omap4ti,sysc   trevsysc~ rfck+ m spi@0ti,omap4-mcspi TB+ +,-.tx0rx0tx1rx1 disabledtarget-module@9c000ti,sysc-omap4ti,sysc   trevsysc~ bfck+ m mmc@0ti,omap4-hsmmc TS=>txrx, default9EOokaytarget-module@9e000ti,sysc disabled+ m target-module@a2000ti,sysc disabled+ m target-module@a4000ti,sysc disabled+m @ Ptarget-module@a5000ti,sysc-omap2ti,sysc P0 P4 P8trevsyscsyss~* fck+ m Pdes@0 ti,omap4-des TRuttxrxtarget-module@a8000ti,sysc disabled+ m @target-module@ad000ti,sysc-omap4ti,sysc   trevsysc~ rfck+ m mmc@0ti,omap4-hsmmc T^MNtxrx disabledtarget-module@b0000ti,sysc disabled+ m target-module@b2000ti,sysc-omap2ti,sysc   trevsyscsyss*e rhfck+ m 1w@0 ti,omap3-1w T:target-module@b4000ti,sysc-omap4ti,sysc @ @ trevsysc~ bfck+ m @mmc@0ti,omap4-hsmmc TV/0txrx disabledtarget-module@b8000ti,sysc-omap4ti,sysc   trevsysc~ rfck+ m spi@0ti,omap4-mcspi T[+tx0rx0 disabledtarget-module@ba000ti,sysc-omap4ti,sysc   trevsysc~ rfck+ m spi@0ti,omap4-mcspi T0+FGtx0rx0 disabledtarget-module@d1000ti,sysc-omap4ti,sysc   trevsysc~ rfck+ m mmc@0ti,omap4-hsmmc T`9:txrxokay default9RE`+wlcore@2 ti,wl1271 T sItarget-module@d5000ti,sysc-omap4ti,sysc P P trevsysc~ r@fck+ m Pmmc@0ti,omap4-hsmmc T;;<txrxokay default9E vsegment@200000simple-pm-bus+m55target-module@150000ti,sysc-omap2ti,sysctrevsyscsyss~* rfck+ mi2c@0 ti,omap4-i2c T>+okay default7target-module@48210000ti,sysc-omap4-simpleti,sysc_ fck+ mH!mpu ti,omap4-mpuinterconnect@40100000ti,omap4-l4-abesimple-pm-bus@@tlaap_+m@IIsegment@0simple-pm-bus+0m  00@@PP``pp  00      IIIII I I0I0I@I@IPIPI`I`IpIpIIIIIIIIIIIIIIIII I I0I0IIIIIIIIIIIIIIIIIIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,sysc tsysc ~ S(fck+m I I mcbsp@0ti,omap4-mcbspI tmpudma S(fck Tcommon!"txrx disabledtarget-module@24000ti,sysc-omap2ti,sysc@tsysc ~ S0fck+m@I@I@mcbsp@0ti,omap4-mcbspI@tmpudma S0fck Tcommontxrx disabledtarget-module@26000ti,sysc-omap2ti,sysc`tsysc ~ S8fck+m`I`I`mcbsp@0ti,omap4-mcbspI`tmpudma S8fck Tcommontxrx disabledtarget-module@28000ti,sysc-mcaspti,sysc trevsysc ~ S fck+0mII IImcasp@0ti,omap4-mcasp-audio Itmpudat Tmtxtx S fck disabledtarget-module@2e000ti,sysc-omap4ti,sysc trevsysc~ Sfck+mIIdmic@0ti,omap4-dmicItmpudma TrCup_link disabledtarget-module@30000ti,sysc-omap2ti,sysctrevsyscsyss"~* Shfck+mIIwdt@0ti,omap4-wdtti,omap3-wdt TPtarget-module@32000ti,sysc-omap4ti,sysc   trevsysc~ Sfck+m I I okay defaultmcpdm@0ti,omap4-mcpdmI tmpudma TpABup_linkdn_linkpdmclk target-module@38000ti,sysc-omap4-timerti,sysc trevsysc~ SHfck+mIItimer@0ti,omap4430-timerISHfcktimer_sys_ck T)target-module@3a000ti,sysc-omap4-timerti,sysc trevsysc~ SPfck+mIItimer@0ti,omap4430-timerISPfcktimer_sys_ck T*target-module@3c000ti,sysc-omap4-timerti,sysc trevsysc~ SXfck+mIItimer@0ti,omap4430-timerISXfcktimer_sys_ck T+target-module@3e000ti,sysc-omap4-timerti,sysc trevsysc~ S`fck+mIItimer@0ti,omap4430-timerIS`fcktimer_sys_ck T,Ftarget-module@80000ti,sysc disabled+mIItarget-module@a0000ti,sysc disabled+m I I target-module@c0000ti,sysc disabled+m I I target-module@f1000ti,sysc-omap4ti,sysc trevsysc ~ Sfck+mIItarget-module@50000000ti,sysc-omap2ti,syscPPPtrevsyscsyss ~* fck+mPP@gpmc@50000000ti,omap4430-gpmcP+ TrxtxRfck)IY disabledtarget-module@52000000ti,sysc-omap4ti,syscRR trevsysc~5_ qfck+ mRtarget-module@54000000ti,sysc-omap4-simpleti,sysc_ fck+ mTpmuarm,cortex-a9-pmuT67target-module@55082000ti,sysc-omap2ti,syscU U U trevsyscsyss ~ fck!8(rstctrl mU +mmu@0ti,omap4-iommu Td4 target-module@4012c000ti,sysc-omap4ti,sysc@@ trevsysc~ S@fck+m@IItarget-module@4e000000ti,sysc-omap2ti,syscNN trevsysc ~ mN+dmm@0 ti,omap4-dmm Tqtarget-module@4c000000ti,sysc-omap4-simpleti,syscLtrev fcky+ mLemif@0 ti,emif-4d Tn1target-module@4d000000ti,sysc-omap4-simpleti,syscMtrev fcky+ mMemif@0 ti,emif-4d To1dsp ti,omap4-dsp DO!h gVomap4-dsp-fw.xe64Td disabledipu@55020000 ti,omap4-ipuUtl2ramO!88 Vomap4-ipu-fw.xem3d disabledtarget-module@4b501000ti,sysc-omap2ti,syscKPKPKPtrevsyscsyss~* fck+ mKPaes@0 ti,omap4-aes TUontxrxtarget-module@4b701000ti,sysc-omap2ti,syscKpKpKptrevsyscsyss~* fck+ mKpaes@0 ti,omap4-aes T@rqtxrxtarget-module@4b100000ti,sysc-omap3-shamti,syscKKKtrevsyscsyss ~* (fck+ mKsham@0ti,omap4-sham T3wrxregulator-abb-mpu ti,abb-v2abb_mpu+k2okayJ0{J0`J"h'tbase-addressint-addressefuse-addressxO1regulator-abb-iva ti,abb-v2abb_iva+k2okayJ0{J0`J"h'tbase-addressint-addressefuse-addressx~e  target-module@56000000ti,sysc-omap4ti,syscVV trevsysc~_ fck+ mVtarget-module@58000000ti,sysc-omap2ti,syscXX trevsyss*_0 fckhdmi_clksys_clktv_clk+ mXdss@0 ti,omap4-dssokay fck+ m defaulttarget-module@1000ti,sysc-omap2ti,sysctrevsyscsyss ~ *  fcksys_clk+ mdispc@0ti,omap4-dispc T fcktarget-module@2000ti,sysc-omap2ti,sysc   trevsyscsyss ~*  fcksys_clk+ m encoder@0 disabledRfckicktarget-module@3000ti,sysc-omap2ti,sysc0trev sys_clk+ m0encoder@0ti,omap4-venc disabled fcktarget-module@4000ti,sysc-omap2ti,sysc@@@trevsyscsyss ~*+ m@encoder@0 ti,omap4-dsi@ tprotophypll T5 disabled  fcksys_clk+target-module@5000ti,sysc-omap2ti,syscPPPtrevsyscsyss ~*+ mPencoder@0 ti,omap4-dsi@ tprotophypll TTokay  fcksys_clk+target-module@6000ti,sysc-omap4ti,sysc`` trevsysc~  fckdss_clk+ m` encoder@0ti,omap4-hdmi twppllphycore Teokay  fcksys_clkL audio_tx defaultportendpoint portendpoint target-module@5a000000ti,sysc-omap4ti,syscZZ trevsysc  ~_!(rstctrl fck+mZZ[[iva ti,ivahdbandgap@4a002260J"`J#,J#xti,omap4460-bandgap T~  thermal-zonescpu_thermal-\۫tripscpu_alert:Fpassive cpu_crit:HF criticalcooling-mapsmap0Q Vmemory@80000000memoryǀ@soundti,abe-twl6040 eVAR-SOM-OM44nI{LHeadset StereophoneHSOLHeadset StereophoneHSORAFMLLine InAFMRLine Inhsusb1_phyusb-nop-xceiv default ~3 main_clk7$ ffixedregulator-vbatregulator-fixedVBAT2Z2ZS wl12xx_vmmc defaultregulator-fixedvwl1271w@w@  p leds gpio-leds defaultled0var:green:led0 ~  heartbeatled1var:green:led1 ~ gpio-keys gpio-keys default+user-key@184user ~ connectorhdmi-connector defaulthdmia portendpoint displayinnolux,at070tn83panel-dpilcdpanel-timing7U ( %  -( :0 D P X  eportendpoint backlightgpio-backlight default v compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3mmc0mmc1mmc2mmc3mmc4serial0serial1serial2serial3rproc0rproc1display0display1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptspower-domainsrangesreg-namesti,sysc-sidle#clock-cellsclock-output-namesti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#power-domain-cells#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsstatus#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesport1-moderemote-wakeup-connectedphysresetsreset-names#iommu-cellsusb-phyphy-namesmultipointnum-epsram-bitsctrl-moduleinterface-typepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usti,timer-pwmregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,buffer-sizedmasdma-namesti,spi-num-csspi-max-frequencyti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablecap-power-off-cardref-clock-frequencycd-gpiossramop-modeserial-dirti,timer-dspti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertti,bootregiommusfirmware-namemboxesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-deviceti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingreset-gpiosvcc-supplyregulator-boot-onstartup-delay-uslabellinux,default-triggerlinux,codewakeup-sourcehpd-gpioshback-porchhactivehfront-porchhsync-lenvback-porchvactivevfront-porchvsync-len