8H( 4openpandora,omap3-pandora-1ghzti,omap3630ti,omap3 +7Pandora Handheld Console 1GHzchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000!{/ocp@68000000/spi@48098000/lcd@1cpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush + l3_mainl4@48000000ti,omap3-l4-coresimple-bus+  Hscm@2000ti,omap3-scmsimple-bus +  pinmux@30 ti,omap3-padconfpinctrl-single08+"3Hfmmc1-pins0mmc2-pinsP(*,.02468:dss-dpi-pins^ uart3-pinsnApleds-pins $&`bbutton-pinspenirq-pinstwl4030-pinsAscm_conf@270sysconsimple-busp0+  p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselhclock-mcbsp5-mux-fckti,composite-mux-clockmcbsp5_mux_fck clock-mcbsp3-mux-fckti,composite-mux-clockmcbsp3_mux_fck clock-mcbsp4-mux-fckti,composite-mux-clockmcbsp4_mux_fck mcbsp5_fckti,composite-clock clock@4 ti,clkselclock-mcbsp1-mux-fckti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fckti,composite-mux-clockmcbsp2_mux_fck mcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clockmcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+"3Hftwl4030-vpins-pins target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `L revsyscsyss !/ick+  H ` aes1@0 ti,omap3-aesP<  Atxrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PL revsyscsyss !/ick+  H P aes2@0 ti,omap3-aesP<ABAtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockKYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clock[pf"sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}!dpll4_x2_ckfixed-factor-clock }corex2_fckfixed-factor-clock!}#wkup_l4_ickfixed-factor-clock"}bcorex2_d3_fckfixed-factor-clock#}corex2_d5_fckfixed-factor-clock#}clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockKomap_32k_fck fixed-clockKHvirt_12m_ck fixed-clockKvirt_13m_ck fixed-clockK]@virt_19200000_ck fixed-clockK$virt_26000000_ck fixed-clockKvirt_38_4m_ck fixed-clockKIdpll4_ck@d00ti,omap3-dpll-per-j-type-clock"" D 0 dpll4_m2_ck@d48ti,divider-clock [? Hf$dpll4_m2x2_mul_ckfixed-factor-clock$}%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock% &omap_96m_alwon_fckfixed-factor-clock&}2dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0clock@1140 ti,clksel@clock-dpll3-m3ti,divider-clock dpll3_m3_ck[f,clock-dpll4-m6ti,divider-clock dpll4_m6_ck [?f>clock-emu-src-mux ti,mux-clockemu_src_mux_ck"'()vclock-pclk-fckti,divider-clock pclk_fck*[fclock-pclkx2-fckti,divider-clock pclkx2_fck*[fclock-atclk-fckti,divider-clock atclk_fck*[fclock-traceclk-src-fck ti,mux-clocktraceclk_src_fck"'()+clock-traceclk-fckti,divider-clock traceclk_fck+ [fdpll3_m3x2_mul_ckfixed-factor-clock,}-dpll3_m3x2_ck@d00ti,hsdiv-gate-clock-  .emu_core_alwon_ckfixed-factor-clock.}'sys_altclk fixed-clockK5mcbsp_clks fixed-clockKcore_ckfixed-factor-clock}/dpll1_fck@940ti,divider-clock/[ @f0dpll1_ck@904ti,omap3-dpll-clock"0  $ @ 4dpll1_x2_ckfixed-factor-clock}1dpll1_x2m2_ck@944ti,divider-clock1[ DfEcm_96m_fckfixed-factor-clock2}3clock@d40 ti,clksel @clock-dpll3-m2ti,divider-clock dpll3_m2_ck[fclock-omap-96m-fck ti,mux-clock omap_96m_fck3"Yclock-omap-54m-fck ti,mux-clock omap_54m_fck45Aclock-omap-48m-fck ti,mux-clock omap_48m_fck659clock@e40 ti,clksel@clock-dpll4-m3ti,divider-clock dpll4_m3_ck [ f7clock-dpll4-m4ti,divider-clock dpll4_m4_ck [f:dpll4_m3x2_mul_ckfixed-factor-clock7}8dpll4_m3x2_ck@d00ti,hsdiv-gate-clock8 4cm_96m_d2_fckfixed-factor-clock3}6omap_12m_fckfixed-factor-clock9}Zdpll4_m4x2_mul_ckti,fixed-factor-clock:;dpll4_m4x2_ck@d00ti,gate-clock; ^dpll4_m5_ck@f40ti,divider-clock [?@f<dpll4_m5x2_mul_ckti,fixed-factor-clock<=dpll4_m5x2_ck@d00ti,hsdiv-gate-clock= zdpll4_m6x2_mul_ckfixed-factor-clock>}?dpll4_m6x2_ck@d00ti,hsdiv-gate-clock? @emu_per_alwon_ckfixed-factor-clock@}(clock@d70 ti,clksel pclock-clkout2-src-gate ti,composite-no-wait-gate-clockclkout2_src_gate_ck/Cclock-clkout2-src-muxti,composite-mux-clockclkout2_src_mux_ck/"3ADclock-sys-clkout2ti,divider-clock sys_clkout2B[@clkout2_src_ckti,composite-clockCDBmpu_ckfixed-factor-clockE}Farm_fck@924ti,divider-clockF $[emu_mpu_alwon_ckfixed-factor-clockF})clock@a40 ti,clksel @clock-l3-ickti,divider-clockl3_ick/[fGclock-l4-ickti,divider-clockl4_ickG[fIclock-gpt10-mux-fckti,composite-mux-clockgpt10_mux_fckH"Vclock-gpt11-mux-fckti,composite-mux-clockgpt11_mux_fckH"Xclock-ssi-ssr-div-fck-3430es2ti,composite-divider-clockssi_ssr_div_fck_3430es2#$clock@c40 ti,clksel @clock-rm-ickti,divider-clockrm_ickI[fclock-gpt1-mux-fckti,composite-mux-clock gpt1_mux_fckH"aclock-usim-mux-fckti,composite-mux-clock usim_mux_fck("JKLMNOPQRfclock@a00 ti,clksel clock-gpt10-gate-fckti,composite-gate-clockgpt10_gate_fck" Uclock-gpt11-gate-fckti,composite-gate-clockgpt11_gate_fck" Wclock-mmchs2-fckti,wait-gate-clock mmchs2_fckclock-mmchs1-fckti,wait-gate-clock mmchs1_fckclock-i2c3-fckti,wait-gate-clock i2c3_fckclock-i2c2-fckti,wait-gate-clock i2c2_fckclock-i2c1-fckti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fckti,composite-gate-clockmcbsp5_gate_fck  clock-mcbsp1-gate-fckti,composite-gate-clockmcbsp1_gate_fck  clock-mcspi4-fckti,wait-gate-clock mcspi4_fckSclock-mcspi3-fckti,wait-gate-clock mcspi3_fckSclock-mcspi2-fckti,wait-gate-clock mcspi2_fckSclock-mcspi1-fckti,wait-gate-clock mcspi1_fckSclock-uart2-fckti,wait-gate-clock uart2_fckSclock-uart1-fckti,wait-gate-clock uart1_fckS clock-hdq-fckti,wait-gate-clockhdq_fckTclock-modem-fckti,omap3-interface-clock modem_fck"clock-mspro-fckti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2#~clock-mmchs3-fckti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockUVgpt11_fckti,composite-clockWXcore_96m_fckfixed-factor-clockY}core_48m_fckfixed-factor-clock9}Score_12m_fckfixed-factor-clockZ}Tcore_l3_ickfixed-factor-clockG}[clock@a10 ti,clksel clock-sdrc-ickti,wait-gate-clock sdrc_ick[clock-mmchs2-ickti,omap3-interface-clock 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sha12_ick\clock-icr-ickti,omap3-interface-clockicr_ick\clock-des2-ickti,omap3-interface-clock des2_ick\clock-mspro-ickti,omap3-interface-clock mspro_ick\clock-mailboxes-ickti,omap3-interface-clockmailboxes_ick\clock-sad2d-ickti,omap3-interface-clock sad2d_ickGclock-hsotgusb-ick-3430es2"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2[clock-ssi-ick-3430es2ti,omap3-ssi-interface-clockssi_ick_3430es2]clock-mmchs3-ickti,omap3-interface-clock mmchs3_ick\gpmc_fckfixed-factor-clock[}core_l4_ickfixed-factor-clockI}\clock@e00 ti,clkselclock-dss-tv-fckti,gate-clock dss_tv_fckAclock-dss-96m-fckti,gate-clock dss_96m_fckYclock-dss2-alwon-fckti,gate-clockdss2_alwon_fck"clock-dss1-alwon-fck-3430es2ti,dss-gate-clockdss1_alwon_fck_3430es2^dummy_ck fixed-clockKclock@c00 ti,clksel clock-gpt1-gate-fckti,composite-gate-clockgpt1_gate_fck"`clock-gpio1-dbckti,gate-clock gpio1_dbck_clock-wdt2-fckti,wait-gate-clock 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gpt2_mux_fckH"fclock-gpt3-mux-fckti,composite-mux-clock gpt3_mux_fckH"hclock-gpt4-mux-fckti,composite-mux-clock gpt4_mux_fckH"jclock-gpt5-mux-fckti,composite-mux-clock gpt5_mux_fckH"lclock-gpt6-mux-fckti,composite-mux-clock gpt6_mux_fckH"nclock-gpt7-mux-fckti,composite-mux-clock gpt7_mux_fckH"pclock-gpt8-mux-fckti,composite-mux-clock gpt8_mux_fckH"rclock-gpt9-mux-fckti,composite-mux-clock gpt9_mux_fckH"tgpt2_fckti,composite-clockefgpt3_fckti,composite-clockghgpt4_fckti,composite-clockijgpt5_fckti,composite-clockklgpt6_fckti,composite-clockmngpt7_fckti,composite-clockopgpt8_fckti,composite-clockqrgpt9_fckti,composite-clockstper_32k_alwon_fckfixed-factor-clockH}dper_l4_ickfixed-factor-clockI}uclock@1010 ti,clkselclock-gpio6-ickti,omap3-interface-clock gpio6_ickuclock-gpio5-ickti,omap3-interface-clock gpio5_ickuclock-gpio4-ickti,omap3-interface-clock gpio4_ickuclock-gpio3-ickti,omap3-interface-clock gpio3_ickuclock-gpio2-ickti,omap3-interface-clock gpio2_icku clock-wdt3-ickti,omap3-interface-clock wdt3_icku clock-uart3-ickti,omap3-interface-clock uart3_icku clock-uart4-ickti,omap3-interface-clock uart4_ickuclock-gpt9-ickti,omap3-interface-clock gpt9_icku clock-gpt8-ickti,omap3-interface-clock gpt8_icku clock-gpt7-ickti,omap3-interface-clock gpt7_ickuclock-gpt6-ickti,omap3-interface-clock gpt6_ickuclock-gpt5-ickti,omap3-interface-clock gpt5_ickuclock-gpt4-ickti,omap3-interface-clock gpt4_ickuclock-gpt3-ickti,omap3-interface-clock gpt3_ickuclock-gpt2-ickti,omap3-interface-clock gpt2_ickuclock-mcbsp2-ickti,omap3-interface-clock mcbsp2_ickuclock-mcbsp3-ickti,omap3-interface-clock mcbsp3_ickuclock-mcbsp4-ickti,omap3-interface-clock mcbsp4_ickuemu_src_ckti,clkdm-gate-clockv*secure_32k_fck fixed-clockKwgpt12_fckfixed-factor-clockw}wdt1_fckfixed-factor-clockw}security_l4_ick2fixed-factor-clockI}xclock@a14 ti,clksel clock-aes1-ickti,omap3-interface-clock aes1_ickxclock-rng-ickti,omap3-interface-clockrng_ickxclock-sha11-ickti,omap3-interface-clock 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffti,ramp_delay_valuebci3v1-supplyio-channelsio-channel-namesti,bb-uvoltti,bb-uampregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencypendown-gpiovcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourcespi-cpolspi-cphalabelreset-gpiosremote-endpointti,dual-voltpbias-supplyvmmc-supplybus-widthcd-gpiosnon-removableti,non-removablecap-power-off-cardti,wl1251-has-eeprom#iommu-cellsti,#tlb-entriesstatusinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,device-widthmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda-supplyti,channelsdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicelinux,default-triggerdefault-statelinux,codelinux,input-typeregulator-boot-onenable-active-highstartup-delay-us