8 t( p <Bgumstix,omap3-overo-tobigumstix,omap3-overoti,omap3430ti,omap3 +7OMAP35xx Gumstix Overo on Tobichosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/connectorcpus+cpu@0arm,cortex-a8|cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+)Gddefaultruart2-pins |<>@Bi2c1-pins|mmc1-pins0|mmc2-pins0|(*,.02w3cbw003c-pins|lhsusb2-pins@|      twl4030-pins|Ai2c3-pins|uart3-pins|npdss-dpi-pins|scm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselhclock-mcbsp5-mux-fckti,composite-mux-clockmcbsp5_mux_fck clock-mcbsp3-mux-fckti,composite-mux-clockmcbsp3_mux_fckclock-mcbsp4-mux-fckti,composite-mux-clockmcbsp4_mux_fckmcbsp5_fckti,composite-clock clock@4 ti,clkselclock-mcbsp1-mux-fckti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fckti,composite-mux-clockmcbsp2_mux_fckmcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clock mcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+)Gtwl4030-vpins-pins |target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss  (ick+ H ` aes1@0 ti,omap3-aesP5  :txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss  (ick+ H P aes2@0 ti,omap3-aesP5AB:txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockDYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clockTp_!sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockvdpll3_m2x2_ckfixed-factor-clockv dpll4_x2_ckfixed-factor-clockvcorex2_fckfixed-factor-clock v"wkup_l4_ickfixed-factor-clock!vacorex2_d3_fckfixed-factor-clock"vcorex2_d5_fckfixed-factor-clock"vclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockDomap_32k_fck fixed-clockDGvirt_12m_ck fixed-clockDvirt_13m_ck fixed-clockD]@virt_19200000_ck fixed-clockD$virt_26000000_ck fixed-clockDvirt_38_4m_ck fixed-clockDIdpll4_ck@d00ti,omap3-dpll-per-clock!! D 0dpll4_m2_ck@d48ti,divider-clockT? H_#dpll4_m2x2_mul_ckfixed-factor-clock#v$dpll4_m2x2_ck@d00ti,gate-clock$ %omap_96m_alwon_fckfixed-factor-clock%v1dpll3_ck@d00ti,omap3-dpll-core-clock!! @ 0clock@1140 ti,clksel@clock-dpll3-m3ti,divider-clock dpll3_m3_ckT_+clock-dpll4-m6ti,divider-clock dpll4_m6_ckT?_=clock-emu-src-mux ti,mux-clockemu_src_mux_ck!&'(uclock-pclk-fckti,divider-clock pclk_fck)T_clock-pclkx2-fckti,divider-clock pclkx2_fck)T_clock-atclk-fckti,divider-clock atclk_fck)T_clock-traceclk-src-fck ti,mux-clocktraceclk_src_fck!&'(*clock-traceclk-fckti,divider-clock traceclk_fck* T_dpll3_m3x2_mul_ckfixed-factor-clock+v,dpll3_m3x2_ck@d00ti,gate-clock,  -emu_core_alwon_ckfixed-factor-clock-v&sys_altclk fixed-clockD4mcbsp_clks fixed-clockDcore_ckfixed-factor-clockv.dpll1_fck@940ti,divider-clock.T @_/dpll1_ck@904ti,omap3-dpll-clock!/  $ @ 4dpll1_x2_ckfixed-factor-clockv0dpll1_x2m2_ck@944ti,divider-clock0T D_Dcm_96m_fckfixed-factor-clock1v2clock@d40 ti,clksel @clock-dpll3-m2ti,divider-clock dpll3_m2_ckT_clock-omap-96m-fck ti,mux-clock omap_96m_fck2!Xclock-omap-54m-fck ti,mux-clock omap_54m_fck34@clock-omap-48m-fck ti,mux-clock omap_48m_fck548clock@e40 ti,clksel@clock-dpll4-m3ti,divider-clock dpll4_m3_ckT _6clock-dpll4-m4ti,divider-clock dpll4_m4_ckT_9dpll4_m3x2_mul_ckfixed-factor-clock6v7dpll4_m3x2_ck@d00ti,gate-clock7 3cm_96m_d2_fckfixed-factor-clock2v5omap_12m_fckfixed-factor-clock8vYdpll4_m4x2_mul_ckti,fixed-factor-clock9:dpll4_m4x2_ck@d00ti,gate-clock: ]dpll4_m5_ck@f40ti,divider-clockT?@_;dpll4_m5x2_mul_ckti,fixed-factor-clock;<dpll4_m5x2_ck@d00ti,gate-clock< ydpll4_m6x2_mul_ckfixed-factor-clock=v>dpll4_m6x2_ck@d00ti,gate-clock> ?emu_per_alwon_ckfixed-factor-clock?v'clock@d70 ti,clksel pclock-clkout2-src-gate ti,composite-no-wait-gate-clockclkout2_src_gate_ck.Bclock-clkout2-src-muxti,composite-mux-clockclkout2_src_mux_ck.!2@Cclock-sys-clkout2ti,divider-clock sys_clkout2AT@clkout2_src_ckti,composite-clockBCAmpu_ckfixed-factor-clockDvEarm_fck@924ti,divider-clockE $Temu_mpu_alwon_ckfixed-factor-clockEv(clock@a40 ti,clksel @clock-l3-ickti,divider-clockl3_ick.T_Fclock-l4-ickti,divider-clockl4_ickFT_Hclock-gpt10-mux-fckti,composite-mux-clockgpt10_mux_fckG!Uclock-gpt11-mux-fckti,composite-mux-clockgpt11_mux_fckG!Wclock-ssi-ssr-div-fck-3430es2ti,composite-divider-clockssi_ssr_div_fck_3430es2"$~clock@c40 ti,clksel @clock-rm-ickti,divider-clockrm_ickHT_clock-gpt1-mux-fckti,composite-mux-clock gpt1_mux_fckG!`clock-usim-mux-fckti,composite-mux-clock usim_mux_fck(!IJKLMNOPQ_clock@a00 ti,clksel clock-gpt10-gate-fckti,composite-gate-clockgpt10_gate_fck! Tclock-gpt11-gate-fckti,composite-gate-clockgpt11_gate_fck! Vclock-mmchs2-fckti,wait-gate-clock mmchs2_fckclock-mmchs1-fckti,wait-gate-clock mmchs1_fckclock-i2c3-fckti,wait-gate-clock i2c3_fckclock-i2c2-fckti,wait-gate-clock i2c2_fckclock-i2c1-fckti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fckti,composite-gate-clockmcbsp5_gate_fck  clock-mcbsp1-gate-fckti,composite-gate-clockmcbsp1_gate_fck  clock-mcspi4-fckti,wait-gate-clock mcspi4_fckRclock-mcspi3-fckti,wait-gate-clock mcspi3_fckRclock-mcspi2-fckti,wait-gate-clock mcspi2_fckRclock-mcspi1-fckti,wait-gate-clock mcspi1_fckRclock-uart2-fckti,wait-gate-clock uart2_fckRclock-uart1-fckti,wait-gate-clock uart1_fckR clock-hdq-fckti,wait-gate-clockhdq_fckSclock-modem-fckti,omap3-interface-clock modem_fck!clock-mspro-fckti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2"}clock-mmchs3-fckti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockTUgpt11_fckti,composite-clockVWcore_96m_fckfixed-factor-clockXvcore_48m_fckfixed-factor-clock8vRcore_12m_fckfixed-factor-clockYvScore_l3_ickfixed-factor-clockFvZclock@a10 ti,clksel clock-sdrc-ickti,wait-gate-clock sdrc_ickZclock-mmchs2-ickti,omap3-interface-clock mmchs2_ick[clock-mmchs1-ickti,omap3-interface-clock mmchs1_ick[clock-hdq-ickti,omap3-interface-clockhdq_ick[clock-mcspi4-ickti,omap3-interface-clock mcspi4_ick[clock-mcspi3-ickti,omap3-interface-clock mcspi3_ick[clock-mcspi2-ickti,omap3-interface-clock mcspi2_ick[clock-mcspi1-ickti,omap3-interface-clock mcspi1_ick[clock-i2c3-ickti,omap3-interface-clock i2c3_ick[clock-i2c2-ickti,omap3-interface-clock i2c2_ick[clock-i2c1-ickti,omap3-interface-clock i2c1_ick[clock-uart2-ickti,omap3-interface-clock uart2_ick[clock-uart1-ickti,omap3-interface-clock uart1_ick[ clock-gpt11-ickti,omap3-interface-clock gpt11_ick[ clock-gpt10-ickti,omap3-interface-clock gpt10_ick[ clock-mcbsp5-ickti,omap3-interface-clock mcbsp5_ick[ clock-mcbsp1-ickti,omap3-interface-clock mcbsp1_ick[ clock-omapctrl-ickti,omap3-interface-clock omapctrl_ick[clock-aes2-ickti,omap3-interface-clock aes2_ick[clock-sha12-ickti,omap3-interface-clock sha12_ick[clock-icr-ickti,omap3-interface-clockicr_ick[clock-des2-ickti,omap3-interface-clock des2_ick[clock-mspro-ickti,omap3-interface-clock mspro_ick[clock-mailboxes-ickti,omap3-interface-clockmailboxes_ick[clock-sad2d-ickti,omap3-interface-clock sad2d_ickFclock-hsotgusb-ick-3430es2"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2Zclock-ssi-ick-3430es2ti,omap3-ssi-interface-clockssi_ick_3430es2\ clock-mmchs3-ickti,omap3-interface-clock mmchs3_ick[gpmc_fckfixed-factor-clockZvcore_l4_ickfixed-factor-clockHv[clock@e00 ti,clkselclock-dss-tv-fckti,gate-clock dss_tv_fck@clock-dss-96m-fckti,gate-clock dss_96m_fckXclock-dss2-alwon-fckti,gate-clockdss2_alwon_fck!clock-dss1-alwon-fck-3430es2ti,dss-gate-clockdss1_alwon_fck_3430es2]dummy_ck fixed-clockDclock@c00 ti,clksel clock-gpt1-gate-fckti,composite-gate-clockgpt1_gate_fck!_clock-gpio1-dbckti,gate-clock gpio1_dbck^clock-wdt2-fckti,wait-gate-clock wdt2_fck^clock-sr1-fckti,wait-gate-clocksr1_fck!clock-sr2-fckti,wait-gate-clocksr2_fck! clock-usim-gate-fckti,composite-gate-clockusim_gate_fckX gpt1_fckti,composite-clock_`wkup_32k_fckfixed-factor-clockGv^clock@c10 ti,clksel clock-wdt2-ickti,omap3-interface-clock wdt2_ickaclock-wdt1-ickti,omap3-interface-clock wdt1_ickaclock-gpio1-ickti,omap3-interface-clock gpio1_ickaclock-omap-32ksync-ickti,omap3-interface-clockomap_32ksync_ickaclock-gpt12-ickti,omap3-interface-clock gpt12_ickaclock-gpt1-ickti,omap3-interface-clock gpt1_ickaclock-usim-ickti,omap3-interface-clock usim_icka per_96m_fckfixed-factor-clock1vper_48m_fckfixed-factor-clock8vbclock@1000 ti,clkselclock-uart3-fckti,wait-gate-clock uart3_fckb clock-gpt2-gate-fckti,composite-gate-clockgpt2_gate_fck!dclock-gpt3-gate-fckti,composite-gate-clockgpt3_gate_fck!fclock-gpt4-gate-fckti,composite-gate-clockgpt4_gate_fck!hclock-gpt5-gate-fckti,composite-gate-clockgpt5_gate_fck!jclock-gpt6-gate-fckti,composite-gate-clockgpt6_gate_fck!lclock-gpt7-gate-fckti,composite-gate-clockgpt7_gate_fck!nclock-gpt8-gate-fckti,composite-gate-clockgpt8_gate_fck! pclock-gpt9-gate-fckti,composite-gate-clockgpt9_gate_fck! rclock-gpio6-dbckti,gate-clock gpio6_dbckcclock-gpio5-dbckti,gate-clock gpio5_dbckcclock-gpio4-dbckti,gate-clock gpio4_dbckcclock-gpio3-dbckti,gate-clock gpio3_dbckcclock-gpio2-dbckti,gate-clock gpio2_dbckc clock-wdt3-fckti,wait-gate-clock wdt3_fckc clock-mcbsp2-gate-fckti,composite-gate-clockmcbsp2_gate_fck clock-mcbsp3-gate-fckti,composite-gate-clockmcbsp3_gate_fckclock-mcbsp4-gate-fckti,composite-gate-clockmcbsp4_gate_fckclock@1040 ti,clksel@clock-gpt2-mux-fckti,composite-mux-clock gpt2_mux_fckG!eclock-gpt3-mux-fckti,composite-mux-clock gpt3_mux_fckG!gclock-gpt4-mux-fckti,composite-mux-clock gpt4_mux_fckG!iclock-gpt5-mux-fckti,composite-mux-clock gpt5_mux_fckG!kclock-gpt6-mux-fckti,composite-mux-clock gpt6_mux_fckG!mclock-gpt7-mux-fckti,composite-mux-clock gpt7_mux_fckG!oclock-gpt8-mux-fckti,composite-mux-clock gpt8_mux_fckG!qclock-gpt9-mux-fckti,composite-mux-clock gpt9_mux_fckG!sgpt2_fckti,composite-clockdegpt3_fckti,composite-clockfggpt4_fckti,composite-clockhigpt5_fckti,composite-clockjkgpt6_fckti,composite-clocklmgpt7_fckti,composite-clocknogpt8_fckti,composite-clockpqgpt9_fckti,composite-clockrsper_32k_alwon_fckfixed-factor-clockGvcper_l4_ickfixed-factor-clockHvtclock@1010 ti,clkselclock-gpio6-ickti,omap3-interface-clock gpio6_icktclock-gpio5-ickti,omap3-interface-clock gpio5_icktclock-gpio4-ickti,omap3-interface-clock gpio4_icktclock-gpio3-ickti,omap3-interface-clock gpio3_icktclock-gpio2-ickti,omap3-interface-clock gpio2_ickt clock-wdt3-ickti,omap3-interface-clock wdt3_ickt clock-uart3-ickti,omap3-interface-clock uart3_ickt clock-uart4-ickti,omap3-interface-clock uart4_icktclock-gpt9-ickti,omap3-interface-clock gpt9_ickt clock-gpt8-ickti,omap3-interface-clock gpt8_ickt clock-gpt7-ickti,omap3-interface-clock gpt7_icktclock-gpt6-ickti,omap3-interface-clock gpt6_icktclock-gpt5-ickti,omap3-interface-clock gpt5_icktclock-gpt4-ickti,omap3-interface-clock gpt4_icktclock-gpt3-ickti,omap3-interface-clock gpt3_icktclock-gpt2-ickti,omap3-interface-clock gpt2_icktclock-mcbsp2-ickti,omap3-interface-clock mcbsp2_icktclock-mcbsp3-ickti,omap3-interface-clock mcbsp3_icktclock-mcbsp4-ickti,omap3-interface-clock mcbsp4_icktemu_src_ckti,clkdm-gate-clocku)secure_32k_fck fixed-clockDvgpt12_fckfixed-factor-clockvvwdt1_fckfixed-factor-clockvvsecurity_l4_ick2fixed-factor-clockHvwclock@a14 ti,clksel clock-aes1-ickti,omap3-interface-clock aes1_ickwclock-rng-ickti,omap3-interface-clockrng_ickwclock-sha11-ickti,omap3-interface-clock sha11_ickwclock-des1-ickti,omap3-interface-clock des1_ickwclock-pka-ickti,omap3-interface-clockpka_ickxclock@f00 ti,clkselclock-cam-mclkti,gate-clock cam_mclkyclock-csi2-96m-fckti,gate-clock csi2_96m_fckcam_ick@f10!ti,omap3-no-wait-interface-clockHsecurity_l3_ickfixed-factor-clockFvxssi_l4_ickfixed-factor-clockHv\sr_l4_ickfixed-factor-clockHvdpll2_fck@40ti,divider-clock.T@_zdpll2_ck@4ti,omap3-dpll-clock!z$@4 {dpll2_m2_ck@44ti,divider-clock{TD_|iva2_ck@0ti,wait-gate-clock|clock@a18 ti,clksel clock-mad2d-ickti,omap3-interface-clock mad2d_ickFclock-usbtll-ickti,omap3-interface-clock usbtll_ick[ssi_ssr_fck_3430es2ti,composite-clock}~ssi_sst_fck_3430es2fixed-factor-clockv sys_d2_ckfixed-factor-clock!vIomap_96m_d2_fckfixed-factor-clockXvJomap_96m_d4_fckfixed-factor-clockXvKomap_96m_d8_fckfixed-factor-clockXvLomap_96m_d10_fckfixed-factor-clockXv Mdpll5_m2_d4_ckfixed-factor-clockvNdpll5_m2_d8_ckfixed-factor-clockvOdpll5_m2_d16_ckfixed-factor-clockvPdpll5_m2_d20_ckfixed-factor-clockvQusim_fckti,composite-clockdpll5_ck@d04ti,omap3-dpll-clock!!  $ L 4dpll5_m2_ck@d50ti,divider-clockT P_sgx_gate_fck@b00ti,composite-gate-clock. core_d3_ckfixed-factor-clock.vcore_d4_ckfixed-factor-clock.vcore_d6_ckfixed-factor-clock.vomap_192m_alwon_fckfixed-factor-clock%vcore_d2_ckfixed-factor-clock.vsgx_mux_fck@b40ti,composite-mux-clock 2 @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockF cpefuse_fck@a08ti,gate-clock! ts_fck@a08ti,gate-clockG usbtll_fck@a08ti,wait-gate-clock dss_ick_3430es2@e10ti,omap3-dss-interface-clockHusbhost_120m_fck@1400ti,gate-clockusbhost_48m_fck@1400ti,dss-gate-clock8usbhost_ick@1410ti,omap3-dss-interface-clockHclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomain)dpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomain{d2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsysc^fckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intcH target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss #  (Zick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma -8 E`gpio@48310000ti,omap3-gpioH1gpio1Rdtgpio@49050000ti,omap3-gpioIgpio2dtgpio@49052000ti,omap3-gpioI gpio3dtgpio@49054000ti,omap3-gpioI@ gpio4dtgpio@49056000ti,omap3-gpioI`!gpio5dtgpio@49058000ti,omap3-gpioI"gpio6dtserial@4806a000ti,omap3-uartH H512:txrxuart1Dlserial@4806c000ti,omap3-uartHI534:txrxuart2Dlddefaultrserial@49020000ti,omap3-uartIJn556:txrxuart3Dlddefaultri2c@48070000 ti,omap3-i2cH8+i2c1ddefaultrD'@twl@48H  ti,twl4030ddefaultraudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpiodttwl4030-usbti,twl4030-usb  pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad(8madcti,twl4030-madcKi2c@48072000 ti,omap3-i2cH 9+i2c2 ]disabledi2c@48060000 ti,omap3-i2cH=+i2c3ddefaultrDeeprom@51 atmel,24c01Qdlis33de@1dst,lis33dest,lis3lv02dmx   ,;JYhxwx&& ]disabledmailbox@48094000ti,omap3-mailboxmailboxH @mbox-dsp  spi@48098000ti,omap2-mcspiH A+mcspi1@5#$%&'()* :tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2 5+,-.:tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 5:tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi45FG:tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc15=>:txrx#ddefaultr0<mmc@480b4000ti,omap3-hsmmcH @Vmmc25/0:txrxddefaultr0F<S`mmc@480ad000ti,omap3-hsmmcH ^mmc35MN:txrx ]disabledmmu@480bd400nti,omap2-iommuH mmu_isp{ mmu@5d000000nti,omap2-iommu]mmu_iva ]disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp15 :txrxfck ]disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyss (ick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone5!":txrxfckick]okaymcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetone5:txrxfckick ]disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp45:txrxfck ]disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp55:txrxfck ]disabledsham@480c3000ti,omap3-shamshamH 0d15E:rxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss ' (fckick+ H1timer@0ti,omap3430-timerfck%Gtarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss ' (fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss ' (fckick+ H0@timer@0ti,omap3430-timer_*usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ :ehci-phyohci@48064400ti,ohci-omap3HDLEehci@48064800 ti,ehci-omapHHM]gpmc@6e000000ti,omap3430-gpmcgpmcn5:rxtxbn+dt00+,nand@0,0ti,omap2-nandmicron,mt29c4g96maz  bch8,,"%,8(G6V@eRvR(+partition@0SPLpartition@80000U-Bootpartition@1c0000 Environment$partition@280000Kernel(partition@780000 Filesystemethernet@gpmcsmsc,lan9221smsc,lan9115*$ % G*8$e<v6V$  !* ; U o     target-module@480ab000ti,sysc-omap2ti,syscH H H revsyscsyss   (fck+ H usb@0ti,omap3-musb\]mcdma     ] usb2-phy  2dss@48050000 ti,omap3-dssH]okay dss_corefck+ddefaultrdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll ]disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH ]disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  ]disabled dss_vencfckportendpoint  ssi-controller@48058000 ti,omap3-ssissi]okayHHsysgddGgdd_mpu+    ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+)Gddefaultr hsusb2-2-pins0|   "  w3cbw003c-2-pins|isp@480bc000 ti,omap3-ispH H |  l ports+bandgap@48002524H%$ti,omap34xx-bandgap !target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $sysc  fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $sysc fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap2ti,syscPrevfckick+ P@opp-tableoperating-points-v2-ti-cpuopp-125000000 7sY@ > Lopp-250000000 7沀 >g8g8g8 L ]opp-500000000 7e >OOO Lopp-550000000 7 U >txtxtx Lopp-600000000 7#F >ppp Lopp-720000000 7*T >ppp L ithermal-zonescpu-thermal t  N  tripscpu_alert 8 passivecpu_crit _  criticalcooling-mapsmap0  memory@0|memoryled-controller pwm-ledsled-1overo:blue:COM w5  mmc0soundti,omap-twl4030 overo hsusb2_power_regregulator-fixed hsusb2_vbusLK@LK@  !p 2hsusb2-phy-pinsusb-nop-xceiv E Qregulator-w3cbw003c-npoweronregulator-fixedregulator-w3cbw003c-npoweron2Z2Z  2regulator-w3cbw003c-wifi-nresetddefaultrregulator-fixed regulator-w3cbw003c-wifi-nreset2Z2Z  !'lis33-3v3-regregulator-fixedlis33-3v3-reg2Z2Zlis33-1v8-regregulator-fixedlis33-1v8-regw@w@encoder ti,tfp410ports+port@0endpoint port@1endpoint connectordvi-connectordvi \ dportendpoint leds gpio-ledsled-heartbeatovero:red:gpio21 K heartbeatregulator-vddvarioregulator-fixed vddvarioregulator-vdd33aregulator-fixedvdd33a compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicepwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplydigitalddc-i2c-bus