&8( x1goldelico,gta04ti,omap3630ti,omap36xxti,omap3 +7Goldelico GTA04A4/Letux 2804chosen=/ocp@68000000/serial@49020000aliasesI/ocp@68000000/i2c@48070000N/ocp@68000000/i2c@48072000S/ocp@68000000/i2c@48060000X/ocp@68000000/mmc@4809c000]/ocp@68000000/mmc@480b4000b/ocp@68000000/serial@4806a000j/ocp@68000000/serial@4806c000r/ocp@68000000/serial@49020000z/ocp@68000000/serial@49042000/spi/td028ttec1@0 /connectorcpus+cpu@0arm,cortex-a8cpucpu%pmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus +  pinmux@30 ti,omap3-padconfpinctrl-single08+#2CXvdefaulthsusb2-pins0      uart1-pinsRLuart2-pinsJHuart3-pinsnpmmc1-pins0backlight-pinmux-pins/dss-dpi-pinsgps-pinsF hdq-pinsbmp085-pinsbma180-pins itg3200-pinshmc5843-pinspenirq-pinsdcamera-pins mcbsp1-pins0\^`bfhmcbsp2-pins   mcbsp3-pins <>@B mcbsp4-pinsTVZtwl4030-pinsAscm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselhclock-mcbsp5-mux-fckti,composite-mux-clockmcbsp5_mux_fck % clock-mcbsp3-mux-fckti,composite-mux-clockmcbsp3_mux_fck clock-mcbsp4-mux-fckti,composite-mux-clockmcbsp4_mux_fck %mcbsp5_fckti,composite-clock clock@4 ti,clkselclock-mcbsp1-mux-fckti,composite-mux-clockmcbsp1_mux_fck %clock-mcbsp2-mux-fckti,composite-mux-clockmcbsp2_mux_fck %mcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clock mcbsp3_fckti,composite-clock mcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+#2CXvgpio1-pinsAAtwl4030-vpins-pins target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `L2revsyscsyss< IWick+ H ` aes1@0 ti,omap3-aesPd  itxrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PL2revsyscsyss< IWick+ H P aes2@0 ti,omap3-aesPdABitxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clocksYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clock%p#sys_clkout1@d70ti,gate-clock p%dpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock "dpll4_x2_ckfixed-factor-clock!corex2_fckfixed-factor-clock"$wkup_l4_ickfixed-factor-clock#ccorex2_d3_fckfixed-factor-clock$corex2_d5_fckfixed-factor-clock$clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clocksomap_32k_fck fixed-clocksIvirt_12m_ck fixed-clocksvirt_13m_ck fixed-clocks]@virt_19200000_ck fixed-clocks$virt_26000000_ck fixed-clocksvirt_38_4m_ck fixed-clocksIdpll4_ck@d00ti,omap3-dpll-per-j-type-clock## D 0!dpll4_m2_ck@d48ti,divider-clock!? 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$emu_mpu_alwon_ckfixed-factor-clockG*clock@a40 ti,clksel @clock-l3-ickti,divider-clockl3_ick0Hclock-l4-ickti,divider-clockl4_ickH%Jclock-gpt10-mux-fckti,composite-mux-clockgpt10_mux_fckI#%Wclock-gpt11-mux-fckti,composite-mux-clockgpt11_mux_fckI#%Yclock-ssi-ssr-div-fck-3430es2ti,composite-divider-clockssi_ssr_div_fck_3430es2$%$clock@c40 ti,clksel @clock-rm-ickti,divider-clockrm_ickJ%clock-gpt1-mux-fckti,composite-mux-clock gpt1_mux_fckI#bclock-usim-mux-fckti,composite-mux-clock usim_mux_fck(#KLMNOPQRS%clock@a00 ti,clksel clock-gpt10-gate-fckti,composite-gate-clockgpt10_gate_fck#% Vclock-gpt11-gate-fckti,composite-gate-clockgpt11_gate_fck#% Xclock-mmchs2-fckti,wait-gate-clock mmchs2_fck%clock-mmchs1-fckti,wait-gate-clock mmchs1_fck%clock-i2c3-fckti,wait-gate-clock i2c3_fck%clock-i2c2-fckti,wait-gate-clock i2c2_fck%clock-i2c1-fckti,wait-gate-clock i2c1_fck%clock-mcbsp5-gate-fckti,composite-gate-clockmcbsp5_gate_fck %  clock-mcbsp1-gate-fckti,composite-gate-clockmcbsp1_gate_fck %  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mcspi4_ick]%clock-mcspi3-ickti,omap3-interface-clock mcspi3_ick]%clock-mcspi2-ickti,omap3-interface-clock mcspi2_ick]%clock-mcspi1-ickti,omap3-interface-clock mcspi1_ick]%clock-i2c3-ickti,omap3-interface-clock i2c3_ick]%clock-i2c2-ickti,omap3-interface-clock i2c2_ick]%clock-i2c1-ickti,omap3-interface-clock i2c1_ick]%clock-uart2-ickti,omap3-interface-clock uart2_ick]%clock-uart1-ickti,omap3-interface-clock uart1_ick]% clock-gpt11-ickti,omap3-interface-clock gpt11_ick]% clock-gpt10-ickti,omap3-interface-clock gpt10_ick]% clock-mcbsp5-ickti,omap3-interface-clock mcbsp5_ick]% clock-mcbsp1-ickti,omap3-interface-clock mcbsp1_ick]% clock-omapctrl-ickti,omap3-interface-clock omapctrl_ick]%clock-aes2-ickti,omap3-interface-clock aes2_ick]%clock-sha12-ickti,omap3-interface-clock sha12_ick]%clock-icr-ickti,omap3-interface-clockicr_ick]%clock-des2-ickti,omap3-interface-clock des2_ick]%clock-mspro-ickti,omap3-interface-clock mspro_ick]%clock-mailboxes-ickti,omap3-interface-clockmailboxes_ick]%clock-sad2d-ickti,omap3-interface-clock sad2d_ickH%clock-hsotgusb-ick-3430es2"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2\%clock-ssi-ick-3430es2ti,omap3-ssi-interface-clockssi_ick_3430es2^%clock-mmchs3-ickti,omap3-interface-clock mmchs3_ick]%gpmc_fckfixed-factor-clock\core_l4_ickfixed-factor-clockJ]clock@e00 ti,clkselclock-dss-tv-fckti,gate-clock dss_tv_fckB%clock-dss-96m-fckti,gate-clock dss_96m_fckZ%clock-dss2-alwon-fckti,gate-clockdss2_alwon_fck#%clock-dss1-alwon-fck-3430es2ti,dss-gate-clockdss1_alwon_fck_3430es2_%dummy_ck fixed-clocksclock@c00 ti,clksel clock-gpt1-gate-fckti,composite-gate-clockgpt1_gate_fck#%aclock-gpio1-dbckti,gate-clock gpio1_dbck`%clock-wdt2-fckti,wait-gate-clock wdt2_fck`%clock-sr1-fckti,wait-gate-clocksr1_fck#%!clock-sr2-fckti,wait-gate-clocksr2_fck#% clock-usim-gate-fckti,composite-gate-clockusim_gate_fckZ% gpt1_fckti,composite-clockabwkup_32k_fckfixed-factor-clockI`clock@c10 ti,clksel clock-wdt2-ickti,omap3-interface-clock wdt2_ickc%clock-wdt1-ickti,omap3-interface-clock wdt1_ickc%clock-gpio1-ickti,omap3-interface-clock gpio1_ickc%clock-omap-32ksync-ickti,omap3-interface-clockomap_32ksync_ickc%clock-gpt12-ickti,omap3-interface-clock gpt12_ickc%clock-gpt1-ickti,omap3-interface-clock gpt1_ickc%clock-usim-ickti,omap3-interface-clock usim_ickc% per_96m_fckfixed-factor-clock3 per_48m_fckfixed-factor-clock:dclock@1000 ti,clkselclock-uart3-fckti,wait-gate-clock uart3_fckd% clock-gpt2-gate-fckti,composite-gate-clockgpt2_gate_fck#%fclock-gpt3-gate-fckti,composite-gate-clockgpt3_gate_fck#%hclock-gpt4-gate-fckti,composite-gate-clockgpt4_gate_fck#%jclock-gpt5-gate-fckti,composite-gate-clockgpt5_gate_fck#%lclock-gpt6-gate-fckti,composite-gate-clockgpt6_gate_fck#%nclock-gpt7-gate-fckti,composite-gate-clockgpt7_gate_fck#%pclock-gpt8-gate-fckti,composite-gate-clockgpt8_gate_fck#% rclock-gpt9-gate-fckti,composite-gate-clockgpt9_gate_fck#% tclock-gpio6-dbckti,gate-clock gpio6_dbcke%clock-gpio5-dbckti,gate-clock gpio5_dbcke%clock-gpio4-dbckti,gate-clock gpio4_dbcke%clock-gpio3-dbckti,gate-clock gpio3_dbcke%clock-gpio2-dbckti,gate-clock gpio2_dbcke% clock-wdt3-fckti,wait-gate-clock wdt3_fcke% clock-mcbsp2-gate-fckti,composite-gate-clockmcbsp2_gate_fck %clock-mcbsp3-gate-fckti,composite-gate-clockmcbsp3_gate_fck %clock-mcbsp4-gate-fckti,composite-gate-clockmcbsp4_gate_fck %clock-uart4-fckti,wait-gate-clock uart4_fckd%clock@1040 ti,clksel@clock-gpt2-mux-fckti,composite-mux-clock gpt2_mux_fckI#gclock-gpt3-mux-fckti,composite-mux-clock gpt3_mux_fckI#%iclock-gpt4-mux-fckti,composite-mux-clock gpt4_mux_fckI#%kclock-gpt5-mux-fckti,composite-mux-clock gpt5_mux_fckI#%mclock-gpt6-mux-fckti,composite-mux-clock gpt6_mux_fckI#%oclock-gpt7-mux-fckti,composite-mux-clock gpt7_mux_fckI#%qclock-gpt8-mux-fckti,composite-mux-clock gpt8_mux_fckI#%sclock-gpt9-mux-fckti,composite-mux-clock gpt9_mux_fckI#%ugpt2_fckti,composite-clockfggpt3_fckti,composite-clockhigpt4_fckti,composite-clockjkgpt5_fckti,composite-clocklmgpt6_fckti,composite-clocknogpt7_fckti,composite-clockpqgpt8_fckti,composite-clockrsgpt9_fckti,composite-clocktuper_32k_alwon_fckfixed-factor-clockIeper_l4_ickfixed-factor-clockJvclock@1010 ti,clkselclock-gpio6-ickti,omap3-interface-clock gpio6_ickv%clock-gpio5-ickti,omap3-interface-clock gpio5_ickv%clock-gpio4-ickti,omap3-interface-clock gpio4_ickv%clock-gpio3-ickti,omap3-interface-clock gpio3_ickv%clock-gpio2-ickti,omap3-interface-clock gpio2_ickv% clock-wdt3-ickti,omap3-interface-clock wdt3_ickv% clock-uart3-ickti,omap3-interface-clock uart3_ickv% clock-uart4-ickti,omap3-interface-clock uart4_ickv%clock-gpt9-ickti,omap3-interface-clock gpt9_ickv% clock-gpt8-ickti,omap3-interface-clock gpt8_ickv% clock-gpt7-ickti,omap3-interface-clock gpt7_ickv%clock-gpt6-ickti,omap3-interface-clock gpt6_ickv%clock-gpt5-ickti,omap3-interface-clock gpt5_ickv%clock-gpt4-ickti,omap3-interface-clock gpt4_ickv%clock-gpt3-ickti,omap3-interface-clock gpt3_ickv%clock-gpt2-ickti,omap3-interface-clock gpt2_ickv%clock-mcbsp2-ickti,omap3-interface-clock mcbsp2_ickv%clock-mcbsp3-ickti,omap3-interface-clock mcbsp3_ickv%clock-mcbsp4-ickti,omap3-interface-clock mcbsp4_ickv%emu_src_ckti,clkdm-gate-clockw+secure_32k_fck fixed-clocksxgpt12_fckfixed-factor-clockxwdt1_fckfixed-factor-clockxsecurity_l4_ick2fixed-factor-clockJyclock@a14 ti,clksel clock-aes1-ickti,omap3-interface-clock aes1_icky%clock-rng-ickti,omap3-interface-clockrng_icky% clock-sha11-ickti,omap3-interface-clock sha11_icky%clock-des1-ickti,omap3-interface-clock des1_icky%clock-pka-ickti,omap3-interface-clockpka_ickz%clock@f00 ti,clkselclock-cam-mclkti,gate-clock cam_mclk{%clock-csi2-96m-fckti,gate-clock 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ti,omap3-i2cH=+i2c3smailbox@48094000ti,omap3-mailboxmailboxH @mbox-dsp & 1spi@48098000ti,omap2-mcspiH A+mcspi1<@d#$%&'()* itx0rx0tx1rx1tx2rx2tx3rx3 disabledspi@4809a000ti,omap2-mcspiH B+mcspi2< d+,-.itx0rx0tx1rx1 disabledspi@480b8000ti,omap2-mcspiH [+mcspi3< ditx0rx0tx1rx1 disabledspi@480ba000ti,omap2-mcspiH 0+mcspi4<dFGitx0rx0 disabled1w@480b2000 ti,omap3-1wH :hdq1wdefaultmmc@4809c000ti,omap3-hsmmcH Smmc1Jd=>itxrxWdefaultdpzmmc@480b4000ti,omap3-hsmmcH @Vmmc2d/0itxrxdpzmmc@480ad000ti,omap3-hsmmcH ^mmc3dMNitxrx disabledmmu@480bd400ti,omap2-iommuH mmu_ispmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@2mpu ;< commontxrxmcbsp1d itxrxfckokaydefaulttarget-module@480a0000ti,sysc-omap2ti,syscH <H @H D2revsyscsyss<IW ick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I 2mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetoned!"itxrx fckickokaydefault 'mcbsp@49024000ti,omap3-mcbspI@I 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gpio-keysaux-button4aux  & antenna-detect gpio-keysgps-antenna-button 4GPS_EXT_ANT      0  soundti,omap-twl4030 Bgta04 K'sound_telephonysimple-audio-card TGTA04 voice k( ( i2s  simple-audio-card,cpu )simple-audio-card,codec *(gsm_codecoption,gtm601*spi spi-gpio+default+ &  & +& 6& ?td028ttec1@0tpo,td028ttec1 O a j s,4lcdportendpoint C-backlightpwm-backlight }. backlight, (2<FPZd default/,pwm-11ti,omap-dmtimer-pwm 0 .hsusb2-phy-pinsusb-nop-xceiv connectorcomposite-video-connector4tvportendpoint C13opa362 ti,opa362 &ports+port@0endpoint C2port@1endpoint C31wifi_pwrseqmmc-pwrseq-simple 4pinmux@48002274pinctrl-singleH"t+ X v#default5mcbsp1-devconf0-pins 5pinmux@480022d8pinctrl-singleH"+ X v#default6tv-acbias-devconf1-pins 6 compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2mmc0mmc1serial0serial1serial2serial3display0display1device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedsirf,onoff-gpioslna-supplyvcc-supplyti,enable-vibrati,ramp_delay_valueti,system-power-controllerbci3v1-supplyio-channelsio-channel-namesti,bb-uvoltti,bb-uampregulator-always-onti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnsstatus#io-channel-cellsvdda-supplyvddd-supplylabellinux,default-triggerti,x-plate-ohmstouchscreen-size-xtouchscreen-size-ytouchscreen-max-pressuretouchscreen-fuzz-xtouchscreen-fuzz-ytouchscreen-fuzz-pressuretouchscreen-inverted-y#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthti,non-removablebroken-cdcap-power-off-cardmmc-pwrseq#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsti,nand-ecc-optrb-gpiosnand-bus-widthgpmc,device-widthgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-off-nsgpmc,we-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,sync-clk-psmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyremote-endpointti,channelsti,invert-polaritydata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typeti,isp-clock-divisorti,strobe-modedata-shifthsync-activevsync-activedata-activepclk-sample#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicelinux,codewakeup-sourcelinux,input-typedebounce-intervalti,modelti,mcbspsimple-audio-card,namesimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersimple-audio-card,formatsimple-audio-card,bitclock-inversionsimple-audio-card,frame-inversionsound-daisck-gpiosmiso-gpiosmosi-gpioscs-gpiosnum-chipselectsspi-max-frequencyspi-cpolspi-cphabacklightpwmspwm-namesbrightness-levelsdefault-brightness-levelti,timersti,clock-sourcereset-gpiosenable-gpiospinctrl-single,bit-per-muxpinctrl-single,bits