\8 ( P )rockchip,rk3588-evb1-v10rockchip,rk3588 +7Rockchip RK3588 EVB1 V10 Boardcpus+cpu-mapcluster0core0=core1=core2=core3=cluster1core0=core1=cluster2core0=core1= cpu@0Acpuarm,cortex-a55MQpsci_r y 0, @@ 1@ Kcpu@100Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@200Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@300Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@400Acpuarm,cortex-a76MQpsci_r y 0, @@1@Kcpu@500Acpuarm,cortex-a76MQpsci_r  @@1@Kcpu@600Acpuarm,cortex-a76MQpsci_r y 0, @@1@Kcpu@700Acpuarm,cortex-a76MQpsci_r  @@1@K idle-statesSpscicpu-sleeparm,idle-state`qdxK l2-cache-l0cache@K l2-cache-l1cache@Kl2-cache-l2cache@Kl2-cache-l3cache@Kl2-cache-b0cache@Kl2-cache-b1cache@Kl2-cache-b2cache@Kl2-cache-b3cache@Kl3-cachecache0@Kfirmwareopteelinaro,optee-tzXsmcscmi arm,scmi-smcԂ+protocol@14MK protocol@16Mpmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0Xsmcclock-0 fixed-clock )׫splltimerarm,armv8-timerP    %-sec-physphysvirthyp-physhyp-virtclock-1 fixed-clock n6xin24mclock-2 fixed-clock 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adisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartMMr{baudclkapb_pclk$ $ txrxdefaultaokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartMNr{baudclkapb_pclk$ $ txrxdefault adisabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartMOr{baudclkapb_pclk txrxdefault adisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartMPr{baudclkapb_pclk txrxdefault adisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartMQr{baudclkapb_pclk txrxdefault adisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartMRr{baudclkapb_pclkYYtxrxdefault adisabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartMSr{baudclkapb_pclkY Y txrxdefault adisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartMTr{baudclkapb_pclkY Y txrxdefault adisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK {pwmpclkdefault adisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK {pwmpclkdefault adisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rLK {pwmpclkdefault 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@Kpcfg-pull-up5Kpcfg-pull-downBKpcfg-pull-noneQKpcfg-pull-none-drv-level-2Q^Kpcfg-pull-up-drv-level-15^Kpcfg-pull-up-drv-level-25^Kpcfg-pull-none-smtQmKauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnoutKhemmc-bus8Kiemmc-clkKjemmc-cmdKkemmc-data-strobeKleth1fspigmac1gpuhdmii2c0i2c0m0-xfer  K#i2c1i2c1m0-xfer   Ki2c2i2c2m0-xfer   Ki2c3i2c3m0-xfer   Ki2c4i2c4m0-xfer   Ki2c5i2c5m0-xfer   Ki2c6i2c6m0-xfer   Ki2c7i2c7m0-xfer   Ki2c8i2c8m0-xfer   Ki2s0i2s0-lrckKmi2s0-sclkKni2s0-sdi0Koi2s0-sdi1Kpi2s0-sdi2Kqi2s0-sdi3Kri2s0-sdo0Ksi2s0-sdo1Kti2s0-sdo2Kui2s0-sdo3Kvi2s1i2s1m0-lrckKwi2s1m0-sclkKxi2s1m0-sdi0Kyi2s1m0-sdi1Kzi2s1m0-sdi2K{i2s1m0-sdi3K|i2s1m0-sdo0 K}i2s1m0-sdo1 K~i2s1m0-sdo2 Ki2s1m0-sdo3 Ki2s2i2s2m1-lrckKi2s2m1-sclk Ki2s2m1-sdi Ki2s2m1-sdo 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Kgmac0-rx-bus20Kgmac0-tx-bus20Kgmac0-rgmii-clk  Kgmac0-rgmii-bus@  Krtl8211frtl8211f-rst Khym8563hym8563-intKusbvcc5v0-host-enKsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsysconM[Ksyscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsysconM\Ki2s@fddc8000rockchip,rk3588-i2s-tdmM܀r{mclk_txmclk_rxhclkyYtxShotx-m% adisabledi2s@fddf4000rockchip,rk3588-i2s-tdmM@r99?{mclk_txmclk_rxhclky6YtxShotx-m% adisabledi2s@fddf8000rockchip,rk3588-i2s-tdmM߀r++'{mclk_txmclk_rxhclky(YrxShorx-m% adisabledi2s@fde00000rockchip,rk3588-i2s-tdmMr&&"{mclk_txmclk_rxhclky#YrxShorx-m% adisabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+60r@E;JOt){aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr@Q`drD Ipcie-phyS"T= @ @0M @@dbiapbconfigh&+ opwrpipe adisabledlegacy-interrupt-controller@ Kpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+60rAF<KPu){aclk_mstaclk_slvaclk_dbipclkauxpipeApciP-syspmcmsglegacyerr@Q`drD Ipcie-phyS"T= @ @@0M @@@dbiapbconfigh', opwrpipe adisabledlegacy-interrupt-controller@ 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vcc5v0_host9LK@LK@ - @default EK!vcc5v0-sys-regulatorregulator-fixed vcc5v0_sys9LK@LK@ EKvcc5v0-usbdcin-regulatorregulator-fixedvcc5v0_usbdcin9LK@LK@ EKvcc5v0-usb-regulatorregulator-fixed vcc5v0_usb9LK@LK@ EK compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesphysphy-namespower-domainsstatusresetsreset-namesclock-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-cs#gpio-cellsgpio-controllerspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-nameregulator-enable-ramp-delayregulator-off-in-suspendregulator-always-onregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-usreset-gpiosrockchip,phy-grfmmc0serial2stdout-pathpower-supplypwmsenable-active-highgpiovin-supply