8(?dUedgeble,neural-compute-module-6a-ioedgeble,neural-compute-module-6arockchip,rk3588 +7Edgeble Neu6A IO Boardcpus+cpu-mapcluster0core0=core1=core2=core3=cluster1core0=core1=cluster2core0=core1= cpu@0Acpuarm,cortex-a55MQpsci_r y 0, @@ 1@cpu@100Acpuarm,cortex-a55MQpsci_r  @@ 1@cpu@200Acpuarm,cortex-a55MQpsci_r  @@1@cpu@300Acpuarm,cortex-a55MQpsci_r  @@1@cpu@400Acpuarm,cortex-a76MQpsci_r y 0, @@1@cpu@500Acpuarm,cortex-a76MQpsci_r  @@1@cpu@600Acpuarm,cortex-a76MQpsci_r y 0, @@1@cpu@700Acpuarm,cortex-a76MQpsci_r  @@1@ idle-statesHpscicpu-sleeparm,idle-stateUf}dx@ l2-cache-l0cache@@ l2-cache-l1cache@@ l2-cache-l2cache@@l2-cache-l3cache@@l2-cache-b0cache@@l2-cache-b1cache@@l2-cache-b2cache@@l2-cache-b3cache@@l3-cachecache0@@firmwareopteelinaro,optee-tzXsmcscmi arm,scmi-smcɂ+protocol@14M@ protocol@16Mpmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0Xsmcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %"sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sramM2+sram@0arm,scmi-shmemM@usb@fc800000"rockchip,rk3588-ehcigeneric-ehciMr9>usbH Vdisabledusb@fc840000"rockchip,rk3588-ohcigeneric-ohciMr9>usbH Vdisabledusb@fc880000"rockchip,rk3588-ehcigeneric-ehciMr9>usbH Vdisabledusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohciMr9>usbH Vdisabledsyscon@fd58c000rockchip,rk3588-sys-grfsysconMX@[syscon@fd5b0000rockchip,rk3588-php-grfsysconM[@syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsysconM[@syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsysconM\@@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdM]@+usb2-phy@8000rockchip,rk3588-usb2phyM]odphyapbrpphyclk usb480m_phy2 Vdisabled@host-port| Vdisabled@syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdM]@+usb2-phy@c000rockchip,rk3588-usb2phyM]p dphyapbrpphyclk usb480m_phy3 Vdisabled@host-port| Vdisabled@syscon@fd5f0000rockchip,rk3588-iocsysconM_@sram@fd600000 mmio-sramM`2`+clock-controller@fd7c0000rockchip,rk3588-cruM|y]q@A.2Fq)׫ׄe/ׄ eZ р @i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2cM=rts pi2cpclkdefault+ Vdisabledserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartMKrpbaudclkapb_pclk  txrx!default Vdisabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMr ppwmpclk"default Vdisabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMr ppwmpclk#default Vdisabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM r ppwmpclk$default Vdisabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0r ppwmpclk%default Vdisabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdMpower-controller!rockchip,rk3588-power-controller+Vokay@power-domain@8M+power-domain@9M  r!#" &'(+power-domain@10M r!#")power-domain@11M r!#"*power-domain@12M r+,-.power-domain@13M +power-domain@14M(r/power-domain@15M r0power-domain@16Mr 123+power-domain@17M r 456power-domain@21Mr 789:;<=>+power-domain@23MrCA?power-domain@14M r/power-domain@15Mr0power-domain@22Mr@power-domain@24Mr[Z]AB+power-domain@25M8rZCpower-domain@26M8rQDEpower-domain@27M0rFGHI+power-domain@28M rJKpower-domain@29M(rLMpower-domain@30Mrz{Npower-domain@31M8rWOPQRpower-domain@33M!rWZ[power-domain@34M"rWZ[power-domain@37M%r2Spower-domain@38M&r45power-domain@40M(Ti2s@fddc0000rockchip,rk3588-i2s-tdmMrpmclk_txmclk_rxhclkyUtxH]dtx-m Vdisabledi2s@fddf0000rockchip,rk3588-i2s-tdmMr445pmclk_txmclk_rxhclky1UtxH]dtx-m Vdisabledi2s@fddfc000rockchip,rk3588-i2s-tdmMr00,pmclk_txmclk_rxhclky-UrxH]drx-m Vdisabledqos@fdf35000rockchip,rk3588-qossysconMP @+qos@fdf35200rockchip,rk3588-qossysconMR @,qos@fdf35400rockchip,rk3588-qossysconMT @-qos@fdf35600rockchip,rk3588-qossysconMV @.qos@fdf36000rockchip,rk3588-qossysconM` @Nqos@fdf39000rockchip,rk3588-qossysconM @Sqos@fdf3d800rockchip,rk3588-qossysconM @Tqos@fdf3e000rockchip,rk3588-qossysconM @Pqos@fdf3e200rockchip,rk3588-qossysconM @Oqos@fdf3e400rockchip,rk3588-qossysconM @Qqos@fdf3e600rockchip,rk3588-qossysconM @Rqos@fdf40000rockchip,rk3588-qossysconM @Lqos@fdf40200rockchip,rk3588-qossysconM @Mqos@fdf40400rockchip,rk3588-qossysconM @Fqos@fdf40500rockchip,rk3588-qossysconM @Gqos@fdf40600rockchip,rk3588-qossysconM @Hqos@fdf40800rockchip,rk3588-qossysconM @Iqos@fdf41000rockchip,rk3588-qossysconM @Jqos@fdf41100rockchip,rk3588-qossysconM @Kqos@fdf60000rockchip,rk3588-qossysconM @1qos@fdf60200rockchip,rk3588-qossysconM @2qos@fdf60400rockchip,rk3588-qossysconM @3qos@fdf61000rockchip,rk3588-qossysconM @4qos@fdf61200rockchip,rk3588-qossysconM @5qos@fdf61400rockchip,rk3588-qossysconM @6qos@fdf62000rockchip,rk3588-qossysconM @/qos@fdf63000rockchip,rk3588-qossysconM0 @0qos@fdf64000rockchip,rk3588-qossysconM@ @?qos@fdf66000rockchip,rk3588-qossysconM` @7qos@fdf66200rockchip,rk3588-qossysconMb @8qos@fdf66400rockchip,rk3588-qossysconMd @9qos@fdf66600rockchip,rk3588-qossysconMf @:qos@fdf66800rockchip,rk3588-qossysconMh @;qos@fdf66a00rockchip,rk3588-qossysconMj @<qos@fdf66c00rockchip,rk3588-qossysconMl @=qos@fdf66e00rockchip,rk3588-qossysconMn @>qos@fdf67000rockchip,rk3588-qossysconMp @@qos@fdf67200rockchip,rk3588-qossysconMr qos@fdf70000rockchip,rk3588-qossysconM @)qos@fdf71000rockchip,rk3588-qossysconM @*qos@fdf72000rockchip,rk3588-qossysconM @&qos@fdf72200rockchip,rk3588-qossysconM" @'qos@fdf72400rockchip,rk3588-qossysconM$ @(qos@fdf80000rockchip,rk3588-qossysconM @Cqos@fdf81000rockchip,rk3588-qossysconM @Dqos@fdf81200rockchip,rk3588-qossysconM @Eqos@fdf82000rockchip,rk3588-qossysconM @Aqos@fdf82200rockchip,rk3588-qossysconM" @Bpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie 0?0rCH>MR)paclk_mstaclk_slvaclk_dbipclkauxpipeApciP"syspmcmsglegacyerr*;`NVVVV\m|0W09X >pcie-phyH"T2 @ @0M @@dbiapbconfig]). dpwrpipe+ Vdisabledlegacy-interrupt-controller* @Vpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie @O0rDI?NSs)paclk_mstaclk_slvaclk_dbipclkauxpipeApciP"syspmcmsglegacyerr*;`NYYYY\m|@W@9Z >pcie-phyH"T2 @ @0M A@dbiapbconfig]*/ dpwrpipe+ Vdisabledlegacy-interrupt-controller* @Yethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM "macirqeth_wake_irq(r67Y^50pstmmacethclk_mac_refpclk_macaclk_macptp_refH!]$ dstmmaceth[\]^ Vdisabledmdiosnps,dwmac-mdio+stmmac-axi-config(@\rx-queues-config8@]queue0queue1tx-queues-configN@^queue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM!(rb_eTopsatapmaliverxoobrefasicd+ Vdisabledsata-port@0Mv@9Z >sata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM#(rdagVqpsatapmaliverxoobrefasicd+ Vdisabledsata-port@0Mv@9X >sata-phy  mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM,@ r  pbiuciuciu-driveciu-sample default_`abH( Vdisabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM-@ rpbiuciuciu-driveciu-sample defaultcH% Vdisabledmmc@fe2e0000rockchip,rk3588-dwcmshcM.y-., n6 (r,*+-.pcorebusaxiblocktimer defghdefault(]dcorebusaxiblocktimerVokayi2s@fe470000rockchip,rk3588-i2s-tdmMGr+/(pmclk_txmclk_rxhclky)- txrxH&]*+ dtx-mrx-m default(ijklmnopqr Vdisabledi2s@fe480000rockchip,rk3588-i2s-tdmMHry}upmclk_txmclk_rxhclk  txrx]^_ dtx-mrx-m default(stuvwxyz{| Vdisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sMIrpi2s_clki2s_hclky}}txrxH& default~ Vdisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sMJr%pi2s_clki2s_hclky"}}txrxH& default Vdisabledinterrupt-controller@fe600000 arm,gic-v3 M`h $a.892*+@msi-controller@fe640000arm,gic-v3-itsMd9H@Wmsi-controller@fe660000arm,gic-v3-itsMf9H@ppi-partitionsinterrupt-partition-0S@interrupt-partition-1S @dma-controller@fea10000arm,pl330arm,primecellM@ VW\rn papb_pclks@ dma-controller@fea30000arm,pl330arm,primecellM@ XY\ro papb_pclks@}i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr{ pi2cpclk>default+ Vdisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr| pi2cpclk?default+ Vdisabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr} pi2cpclk@default+ Vdisabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr~ pi2cpclkAdefault+ Vdisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr pi2cpclkBdefault+ Vdisabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timerM !rTW ppclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdtMrdc ptclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiMFrpspiclkapb_pclk  txrx~ default+ Vdisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiMGrpspiclkapb_pclk  txrx~ default+ Vdisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiMHrpspiclkapb_pclk}}txrx~ default+ Vdisabledspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiMIrpspiclkapb_pclk}}txrx~ default+ Vdisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartMLrpbaudclkapb_pclk  txrxdefault Vdisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartMMrpbaudclkapb_pclk txrxdefaultVokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartMNrpbaudclkapb_pclk txrxdefault Vdisabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartMOrpbaudclkapb_pclk} } txrxdefault Vdisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartMPrpbaudclkapb_pclk} } txrxdefault Vdisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartMQrpbaudclkapb_pclk} }txrxdefault Vdisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartMRrpbaudclkapb_pclkUUtxrxdefault Vdisabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartMSrpbaudclkapb_pclkU U txrxdefault Vdisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartMTrpbaudclkapb_pclkU U txrxdefault Vdisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK ppwmpclkdefault Vdisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK ppwmpclkdefault Vdisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rLK ppwmpclkdefault Vdisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rLK ppwmpclkdefault Vdisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON ppwmpclkdefault Vdisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON ppwmpclkdefault Vdisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rON ppwmpclkdefault Vdisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rON ppwmpclkdefault Vdisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ ppwmpclkdefault Vdisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ ppwmpclkdefault Vdisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rRQ ppwmpclkdefault Vdisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rRQ ppwmpclkdefault Vdisabledtsadc@fec00000rockchip,rk3588-tsadcMrptsadcapb_pclky]VWdtsadc-apbtsadc gpiootpout Vdisabledadc@fec10000rockchip,rk3588-saradcMrpsaradcapb_pclk]U dsaradc-apb Vdisabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cMr pi2cpclkCdefault+ Vdisabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr pi2cpclkDdefault+ Vdisabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr pi2cpclkEdefault+ Vdisabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiMJrpspiclkapb_pclkU Utxrx~ default+ Vdisabledefuse@fecc0000rockchip,rk3588-otpM rpotpapb_pclkphyarb] dotpapbarb+cpu-code@2Mid@7Mcpu-leakage@17Mcpu-leakage@18Mcpu-leakage@19Mlog-leakage@1aMgpu-leakage@1bMcpu-version@1cMnpu-leakage@28M(codec-leakage@29M)dma-controller@fed10000arm,pl330arm,primecellM@ Z[\rp papb_pclks@Uphy@fee00000rockchip,rk3588-naneng-combphyMrvW prefapbpipey|]<Cdphyapb Vdisabled@Zphy@fee20000rockchip,rk3588-naneng-combphyMrxW prefapbpipey|]>Edphyapb Vdisabled@Xsram@ff001000 mmio-sramM2+pinctrlrockchip,rk3588-pinctrl2+@gpio@fd8a0000rockchip,gpio-bankMrqr-= I*gpio@fec20000rockchip,gpio-bankMrst-= I*gpio@fec30000rockchip,gpio-bankMruv-=@ I*gpio@fec40000rockchip,gpio-bankMrwx-=` I*gpio@fec50000rockchip,gpio-bankMryz-= I*pcfg-pull-upU@pcfg-pull-downb@pcfg-pull-noneq@pcfg-pull-none-drv-level-2q~@pcfg-pull-up-drv-level-1U~@pcfg-pull-up-drv-level-2U~@pcfg-pull-none-smtq@auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout@demmc-bus8@eemmc-clk@femmc-cmd@gemmc-data-strobe@heth1fspigmac1gpuhdmii2c0i2c0m0-xfer  @i2c1i2c1m0-xfer   @i2c2i2c2m0-xfer   @i2c3i2c3m0-xfer   @i2c4i2c4m0-xfer   @i2c5i2c5m0-xfer   @i2c6i2c6m0-xfer   @i2c7i2c7m0-xfer   @i2c8i2c8m0-xfer   @i2s0i2s0-lrck@ii2s0-sclk@ji2s0-sdi0@ki2s0-sdi1@li2s0-sdi2@mi2s0-sdi3@ni2s0-sdo0@oi2s0-sdo1@pi2s0-sdo2@qi2s0-sdo3@ri2s1i2s1m0-lrck@si2s1m0-sclk@ti2s1m0-sdi0@ui2s1m0-sdi1@vi2s1m0-sdi2@wi2s1m0-sdi3@xi2s1m0-sdo0 @yi2s1m0-sdo1 @zi2s1m0-sdo2 @{i2s1m0-sdo3 @|i2s2i2s2m1-lrck@~i2s2m1-sclk @i2s2m1-sdi @i2s2m1-sdo @i2s3i2s3-lrck@i2s3-sclk@i2s3-sdi@i2s3-sdo@jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmupwm0pwm0m0-pins@"pwm1pwm1m0-pins@#pwm2pwm2m0-pins@$pwm3pwm3m0-pins@%pwm4pwm4m0-pins @pwm5pwm5m0-pins @pwm6pwm6m0-pins @pwm7pwm7m0-pins @pwm8pwm8m0-pins @pwm9pwm9m0-pins @pwm10pwm10m0-pins @pwm11pwm11m0-pins @pwm12pwm12m0-pins @pwm13pwm13m0-pins @pwm14pwm14m0-pins @pwm15pwm15m0-pins @refclksatasata0sata1sata2sdiosdiom1-pins`@csdmmcsdmmc-bus4@@bsdmmc-clk@_sdmmc-cmd@`sdmmc-det@aspdif0spdif1spi0spi0m0-pins0@spi0m0-cs0@spi0m0-cs1@spi1spi1m1-pins0@spi1m1-cs0@spi1m1-cs1@spi2spi2m2-pins0 @spi2m2-cs0 @spi2m2-cs1@spi3spi3m1-pins0 @spi3m1-cs0@spi3m1-cs1@spi4spi4m0-pins0@spi4m0-cs0@spi4m0-cs1@tsadctsadc-shut@uart0uart0m1-xfer  @!uart1uart1m1-xfer   @uart2uart2m0-xfer  @uart3uart3m1-xfer   @uart4uart4m1-xfer   @uart5uart5m1-xfer   @uart6uart6m1-xfer   @uart7uart7m1-xfer   @uart8uart8m1-xfer   @uart9uart9m1-xfer   @vopbt656gpio-functsadc-gpio-func@eth0gmac0syscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsysconM[@syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsysconM\@i2s@fddc8000rockchip,rk3588-i2s-tdmM܀rpmclk_txmclk_rxhclkyUtxH]dtx-m Vdisabledi2s@fddf4000rockchip,rk3588-i2s-tdmM@r99?pmclk_txmclk_rxhclky6UtxH]dtx-m Vdisabledi2s@fddf8000rockchip,rk3588-i2s-tdmM߀r++'pmclk_txmclk_rxhclky(UrxH]drx-m Vdisabledi2s@fde00000rockchip,rk3588-i2s-tdmMr&&"pmclk_txmclk_rxhclky#UrxH]drx-m Vdisabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+ 0r@E;JOt)paclk_mstaclk_slvaclk_dbipclkauxpipeApciP"syspmcmsglegacyerr*;`N\m|9 >pcie-phyH"T2 @ @0M @@dbiapbconfig]&+ dpwrpipe Vdisabledlegacy-interrupt-controller* @pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+ 0rAF<KPu)paclk_mstaclk_slvaclk_dbipclkauxpipeApciP"syspmcmsglegacyerr*;`N\m|9 >pcie-phyH"T2 @ @@0M @@@dbiapbconfig]', dpwrpipe Vdisabledlegacy-interrupt-controller* @pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0rBG=LQ)paclk_mstaclk_slvaclk_dbipclkauxpipeApciP"syspmcmsglegacyerr*;`N\m| W 9 >pcie-phyH"T2 @ @0M @@dbiapbconfig](- dpwrpipe+ Vdisabledlegacy-interrupt-controller* @ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM "macirqeth_wake_irq(r67X]40pstmmacethclk_mac_refpclk_macaclk_macptp_refH!]# dstmmaceth[ Vdisabledmdiosnps,dwmac-mdio+stmmac-axi-config(@rx-queues-config8@queue0queue1tx-queues-configN@queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciM"(rc`fUppsatapmaliverxoobrefasicd+ Vdisabledsata-port@0Mv@9 >sata-phy  phy@fee10000rockchip,rk3588-naneng-combphyMrwW prefapbpipey|]=Ddphyapb Vdisabled@phy@fee80000rockchip,rk3588-pcie3-phyM|ryppclk]Hdphy Vdisabled@aliases/mmc@fe2e0000/serial@feb50000vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinchosen3serial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesphysphy-namespower-domainsstatusresetsreset-namesclock-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfmmc0serial2regulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltstdout-path