I8x( @ &,firefly,rk3568-roc-pcrockchip,rk35687Firefly Station P2aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe2a0000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 !psci/Ccpu@100cpu,arm,cortex-a55!psci/C cpu@200cpu,arm,cortex-a55!psci/C cpu@300cpu,arm,cortex-a55!psci/C opp-table-0,operating-points-v2KCopp-408000000VQ ] 0k@opp-600000000V#F ] 0opp-816000000V0, ] 0|opp-1104000000VAʹ ] 0opp-1416000000VTfr ] 0opp-1608000000V_" ]0opp-1800000000VkI ]0opp-1992000000Vv ]000display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc protocol@14Copp-table-1,operating-points-v2CBopp-200000000V ] opp-300000000V] opp-400000000Vׄ] opp-600000000V#F] opp-700000000V)'] opp-800000000V/]B@hdmi-sound,simple-audio-cardHDMIi2sokaysimple-audio-card,codecsimple-audio-card,cpupmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0(smctimer,arm,armv8-timer0   %xin24m ,fixed-clock<n6Lxin24mCxin32k ,fixed-clock<Lxin32k_ idefaultsram@10f000 ,mmio-sram wsram@0,arm,scmi-shmemCsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ ~satapmaliverxoob _ sata-phy disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ~satapmaliverxoob ` sata-phyokayusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@  ~ref_clksuspend_clkbus_clkotg utmi_wide okay usb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@  ~ref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide okayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(%Cusb@fd800000 ,generic-ehci  usbokayusb@fd840000 ,generic-ohci  usbokayusb@fd880000 ,generic-ehci  usbokayusb@fd8c0000 ,generic-ohci  usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdCio-domains&,rockchip,rk3568-pmu-io-voltage-domainokay4BP^lzsyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconCsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdCsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconCsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconCsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconCsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀCclock-controller@fdd00000,rockchip,rk3568-pmucruCclock-controller@fdd20000,rockchip,rk3568-cru ~xin24m  G C i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c . - ~i2cpclk_idefault okaypmic@20,rockchip,rk809 idefault_ )!5!A!M!Y!e!q!}!!regulatorsDCDC_REG1 vdd_logic   p8qregulator-state-memMDCDC_REG2vdd_gpu   p8qCCregulator-state-memMDCDC_REG3vcc_ddrregulator-state-memfDCDC_REG4vdd_npu   p8qregulator-state-memMDCDC_REG5vcc_1v8w@ w@Cregulator-state-memMLDO_REG1vdda0v9_image  CYregulator-state-memMLDO_REG2 vdda_0v9  regulator-state-memMLDO_REG3 vdda0v9_pmu  regulator-state-memf~ LDO_REG4 vccio_acodec2Z 2ZCregulator-state-memMLDO_REG5 vccio_sdw@ 2ZCregulator-state-memMLDO_REG6 vcc3v3_pmu2Z 2ZCregulator-state-memf~2ZLDO_REG7 vcca_1v8w@ w@Cregulator-state-memMLDO_REG8 vcca1v8_pmuw@ w@regulator-state-memf~w@LDO_REG9vcca1v8_imagew@ w@CZregulator-state-memMSWITCH_REG1vcc_3v3Cregulator-state-memMSWITCH_REG2 vcc3v3_sdCbregulator-state-memMserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t  ,~baudclkapb_pclk""_#idefault disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 ~pwmpclk_$idefault disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 ~pwmpclk_%idefault disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm   0 ~pwmpclk_&idefault disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0  0 ~pwmpclk_'idefault disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller Cpower-domain@7  (power-domain@8  )*+power-domain@9   ,-.power-domain@10  /01234power-domain@11  5power-domain@13  6power-domain@14  789power-domain@15  :;<=>?@Agpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpu  ~gpubus/BokayCCvideo-codec@fdea0400,rockchip,rk3568-vpu   ~aclkhclkD iommu@fdea0800,rockchip,rk3568-iommu@  ~aclkiface  CDrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga Z ~aclkhclksclk & $ %  coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu @  ~aclkhclkE iommu@fdee0800,rockchip,rk3568-iommu@ ?  ~aclkiface CEmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d   ~biuciuciu-driveciu-sample#р  reset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@     W~stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref   stmmaceth1FARGeHxokay    Iinputidefault_JKLMNOPrgmii Q N O&mdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22CPstmmac-axi-config CFrx-queues-configCGqueue0tx-queues-config/CHqueue0vop@fe040000 0@Evopgamma-lut ( %~aclkhclkdclk_vp0dclk_vp1dclk_vp2R okay,rockchip,rk3568-vop  ports Cport@0 endpoint@2OSC[port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?   ~aclkifaceokayCRdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi D~pclk dphyT  apb  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi E~pclk dphyU  apb  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -( ( ~iahbisfrcecrefidefault _VWX _okaypYZCports port@0endpointO[CSport@1endpointO\Cqos@fe128000,rockchip,rk3568-qossyscon C(qos@fe138080,rockchip,rk3568-qossyscon C7qos@fe138100,rockchip,rk3568-qossyscon C8qos@fe138180,rockchip,rk3568-qossyscon C9qos@fe148000,rockchip,rk3568-qossyscon C)qos@fe148080,rockchip,rk3568-qossyscon C*qos@fe148100,rockchip,rk3568-qossyscon C+qos@fe150000,rockchip,rk3568-qossyscon C5qos@fe158000,rockchip,rk3568-qossyscon C/qos@fe158100,rockchip,rk3568-qossyscon C0qos@fe158180,rockchip,rk3568-qossyscon C1qos@fe158200,rockchip,rk3568-qossyscon C2qos@fe158280,rockchip,rk3568-qossyscon C3qos@fe158300,rockchip,rk3568-qossyscon C4qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon C:qos@fe190280,rockchip,rk3568-qossyscon C>qos@fe190300,rockchip,rk3568-qossyscon C?qos@fe190380,rockchip,rk3568-qossyscon C@qos@fe190400,rockchip,rk3568-qossyscon CAqos@fe198000,rockchip,rk3568-qossyscon C6qos@fe1a8000,rockchip,rk3568-qossyscon C,qos@fe1a8080,rockchip,rk3568-qossyscon C-qos@fe1a8100,rockchip,rk3568-qossyscon C.pcie@fe260000,rockchip,rk3568-pcie0@&Edbiapbconfig<KJIHGsyspmcmsilegacyerr( $~aclk_mstaclk_slvaclk_dbipclkauxpci`]]]] pcie-phyTw @@  pipe  disabledlegacy-interrupt-controller HC]mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b   ~biuciuciu-driveciu-sample#р  resetokay  &/idefault_^_`a:HbTmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c   ~biuciuciu-driveciu-sample#р  reset disabledspi@fe300000 ,rockchip,sfc0@ e x v~clk_sfchclk_sfc_cidefault disabledmmc@fe310000,rockchip,rk3568-dwcmshc1  { } n6( | z y { }~corebusaxiblocktimerokay # aidefault_defgi2s@fe400000,rockchip,rk3568-i2s-tdm@ 4 = AFqFq ? C 9~mclk_txmclk_rxhclkhotx P Q  tx-mrx-m_okayCi2s@fe410000,rockchip,rk3568-i2s-tdmA 5 E IFqFq G K :~mclk_txmclk_rxhclkhhorxtx R S  tx-mrx-midefault0_ijklmnopqrst_ disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB 6 MFq O O ;~mclk_txmclk_rxhclkhhotxrx T midefault_uvwx_ disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7 S W <~mclk_txmclk_rxhclkhhotxrx U V  tx-mrx-m_ disabledpdm@fe440000,rockchip,rk3568-pdmD L Z Y~pdm_clkpdm_hclkh orx_yz{|}~idefault X pdm-m_ disabledspdif@fe460000,rockchip,rk3568-spdifF f ~mclkhclk _ \hotxidefault__ disableddma-controller@fe530000,arm,pl330arm,primecellS@ y   ~apb_pclkC"dma-controller@fe550000,arm,pl330arm,primecellU@y   ~apb_pclkChi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ / H G ~i2cpclk_idefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0 J I ~i2cpclk_idefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1 L K ~i2cpclk_idefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2 N M ~i2cpclk_idefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3 P O ~i2cpclk_idefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`    ~tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia g R Q~spiclkapb_pclk""otxrxidefault _  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib h T S~spiclkapb_pclk""otxrxidefault _  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic i V U~spiclkapb_pclk""otxrxidefault _  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid j X W~spiclkapb_pclk""otxrxidefault _  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte u  ~baudclkapb_pclk""_idefault disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v #  ~baudclkapb_pclk""_idefaultokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w ' $~baudclkapb_pclk""_idefault disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x + (~baudclkapb_pclk"" _idefault disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y / ,~baudclkapb_pclk" " _idefault disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z 3 0~baudclkapb_pclk" " _idefault disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk { 7 4~baudclkapb_pclk""_idefault disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl | ; 8~baudclkapb_pclk""_idefault disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm } ? <~baudclkapb_pclk""_idefault disabledthermal-zonescpu-thermaldtripscpu_alert0ppassiveCcpu_alert1$passivecpu_crits criticalcooling-mapsmap00 gpu-thermaltripsgpu-thresholdppassivegpu-target$passiveCgpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq s  f@ `  ~tsadcapb_pclk   siinitdefaultsleep_   %okayCsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]  ~saradcapb_pclk   saradc-apb ;okay Mpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y ~pwmpclk_idefault disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y ~pwmpclk_idefault disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  Z Y ~pwmpclk_idefault disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 Z Y ~pwmpclk_idefault disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ ~pwmpclk_idefault disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ ~pwmpclk_idefault disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ] \ ~pwmpclk_idefault disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ] \ ~pwmpclk_idefault disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ ~pwmpclk_idefault disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ ~pwmpclk_idefault disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  ` _ ~pwmpclk_idefault disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 ` _ ~pwmpclk_idefault disabledphy@fe830000,rockchip,rk3568-naneng-combphy " }  ~refapbpipe"  Y k okayCphy@fe840000,rockchip,rk3568-naneng-combphy % ~  ~refapbpipe%  Y k okayCphy@fe870000,rockchip,rk3568-csi-dphy y~pclk   apb disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy ~refpclk  z   apb  disabledCTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy ~refpclk  {   apb  disabledCUusb2phy@fe8a0000,rockchip,rk3568-usb2phy ~phyclkLclk_usbphy0_480m  okayhost-port okay Cotg-port okayCusb2phy@fe8b0000,rockchip,rk3568-usb2phy ~phyclkLclk_usbphy1_480m  okayhost-port okay Cotg-port okay Cpinctrl,rockchip,rk3568-pinctrl  wCgpio@fdd60000,rockchip,gpio-bank ! .    Cgpio@fe740000,rockchip,gpio-bankt " c d   Cgpio@fe750000,rockchip,gpio-banku # e f  @  CQgpio@fe760000,rockchip,gpio-bankv $ g h  `  gpio@fe770000,rockchip,gpio-bankw % i j   pcfg-pull-up Cpcfg-pull-none Cpcfg-pull-none-drv-level-1  Cpcfg-pull-none-drv-level-2  Cpcfg-pull-none-drv-level-3  Cpcfg-pull-up-drv-level-1  Cpcfg-pull-up-drv-level-2  Cpcfg-pull-none-smt  Cacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 C cpuebcedpdpemmcemmc-bus8   Cdemmc-clk Ceemmc-cmd Cfemmc-datastrobe Cgeth0eth1flashfspifspi-pins` Ccgmac0gmac0-miim Cgmac0-clkinout Cgmac0-rx-bus20 Cgmac0-tx-bus20    Cgmac0-rgmii-clk Cgmac0-rgmii-bus@ Cgmac1gmac1m1-miim CJgmac1m1-clkinout COgmac1m1-rx-bus20  CLgmac1m1-tx-bus20 CKgmac1m1-rgmii-clk CMgmac1m1-rgmii-bus@ CNgpuhdmitxhdmitxm0-cec CXhdmitx-scl CVhdmitx-sda CWi2c0i2c0-xfer   Ci2c1i2c1-xfer   Ci2c2i2c2m0-xfer  Ci2c3i2c3m0-xfer Ci2c4i2c4m0-xfer   Ci2c5i2c5m0-xfer   Ci2s1i2s1m0-lrckrx Cli2s1m0-lrcktx Cki2s1m0-sclkrx Cji2s1m0-sclktx Cii2s1m0-sdi0  Cmi2s1m0-sdi1  Cni2s1m0-sdi2  Coi2s1m0-sdi3 Cpi2s1m0-sdo0 Cqi2s1m0-sdo1 Cri2s1m0-sdo2  Csi2s1m0-sdo3  Cti2s2i2s2m0-lrcktx Cvi2s2m0-sclktx Cui2s2m0-sdi Cwi2s2m0-sdo Cxi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Cypdmm0-clk1 Czpdmm0-sdi0  C{pdmm0-sdi1  C|pdmm0-sdi2  C}pdmm0-sdi3 C~pmicpmic-int C pmupwm0pwm0m0-pins C$pwm1pwm1m0-pins C%pwm2pwm2m0-pins C&pwm3pwm3-pins C'pwm4pwm4-pins Cpwm5pwm5-pins Cpwm6pwm6-pins Cpwm7pwm7-pins Cpwm8pwm8m0-pins  Cpwm9pwm9m0-pins  Cpwm10pwm10m0-pins  Cpwm11pwm11m0-pins Cpwm12pwm12m0-pins Cpwm13pwm13m0-pins Cpwm14pwm14m0-pins Cpwm15pwm15m0-pins Crefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ C^sdmmc0-clk C_sdmmc0-cmd C`sdmmc0-det Casdmmc1sdmmc2spdifspdifm0-tx Cspi0spi0m0-pins0  Cspi0m0-cs0 Cspi0m0-cs1 Cspi1spi1m0-pins0  Cspi1m0-cs0 Cspi1m0-cs1 Cspi2spi2m0-pins0 Cspi2m0-cs0 Cspi2m0-cs1 Cspi3spi3m0-pins0   Cspi3m0-cs0 Cspi3m0-cs1 Ctsadctsadc-shutorg Ctsadc-pin Cuart0uart0-xfer C#uart1uart1m0-xfer   Cuart2uart2m0-xfer Cuart3uart3m0-xfer Cuart4uart4m0-xfer Cuart5uart5m0-xfer Cuart6uart6m0-xfer Cuart7uart7m0-xfer Cuart8uart8m0-xfer Cuart9uart9m0-xfer Cvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-led-enable-h  Cusbvcc5v0-host-en Cvcc5v0-otg-en Cpciepcie-reset-pin Cvcc3v3-pcie-en-pin Csata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ~satapmaliverxoob ^ sata-phy disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconCqos@fe190080,rockchip,rk3568-qossyscon C;qos@fe190100,rockchip,rk3568-qossyscon C<qos@fe190200,rockchip,rk3568-qossyscon C=syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀCphy@fe8c0000,rockchip,rk3568-pcie3-phy  &' w~refclk_mrefclk_npclk  phy (okayCpcie@fe270000,rockchip,rk3568-pcie ( $~aclk_mstaclk_slvaclk_dbipclkauxpci<syspmcmsglegacyerr` pcie-phy0@@'Tw @@@Edbiapbconfig  pipe disabledlegacy-interrupt-controller Cpcie@fe280000,rockchip,rk3568-pcie ( $~aclk_mstaclk_slvaclk_dbipclkauxpci<syspmcmsglegacyerr`  pcie-phy0@(Tw @@Edbiapbconfig  pipeokayidefault_ 9Q Elegacy-interrupt-controller Cethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*macirqeth_wake_irq@     W~stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref   stmmaceth1ARexokay    inputidefault_rgmii Q N </mdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22Cstmmac-axi-config Crx-queues-configCqueue0tx-queues-config/Cqueue0phy@fe820000,rockchip,rk3568-naneng-combphy  |  ~refapbpipe  Y k okayCchosen Userial2:1500000n8dc-12v-regulator,regulator-fixeddc_12v Cexternal-gmac0-clock ,fixed-clock<sY@ Lgmac0_clkinCexternal-gmac1-clock ,fixed-clock<sY@ Lgmac1_clkinCIleds ,gpio-ledsled-user auser-led gon )  uheartbeatidefault_ hdmi-con,hdmi-connectoraportendpointOC\pcie30-avdd0v9-regulator,regulator-fixedpcie30_avdd0v9   !pcie30-avdd1v8-regulator,regulator-fixedpcie30_avdd1v8w@ w@ !vcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z 2Z C!vcc3v3-pcie-regulator,regulator-fixed vcc3v3_pcie 2Z 2Zidefault_   Cvcc5v0-sys-regulator,regulator-fixed vcc5v0_sysLK@ LK@ Cvcc5v0-usb-regulator,regulator-fixed vcc5v0_usbLK@ LK@ Cvcc5v0-host-regulator,regulator-fixed vcc5v0_host  idefault_ Cvcc5v0-otg-regulator,regulator-fixed vcc5v0_otg  idefault_  interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-init-microvoltregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaysnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplybus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyrockchip,pmugpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfreset-gpiosvpcie3v3-supplystdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedvin-supplyenable-active-highstartup-delay-us