ܽ8( Ҭ$rockchip,rk3399-evbrockchip,rk3399 +!7Rockchip RK3399 Evaluation Boardaliases=/ethernet@fe300000G/i2c@ff3c0000L/i2c@ff110000Q/i2c@ff120000V/i2c@ff130000[/i2c@ff3d0000`/i2c@ff140000e/i2c@ff150000j/i2c@ff160000o/i2c@ff3e0000t/serial@ff180000|/serial@ff190000/serial@ff1a0000/serial@ff1b0000/serial@ff370000/mmc@fe330000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53pscid cpu@1cpuarm,cortex-a53pscid cpu@2cpuarm,cortex-a53pscid cpu@3cpuarm,cortex-a53pscid cpu@100cpuarm,cortex-a72psci  thermal-idle'*cpu@101cpuarm,cortex-a72psci  thermal-idle'*idle-states:pscicpu-sleeparm,idle-stateGXox* cluster-sleeparm,idle-stateGXo* display-subsystemrockchip,display-subsystem memory-controllerrockchip,rk3399-dmc dmc_clk disabledpmu_a53arm,cortex-a53-pmupmu_a72arm,cortex-a72-pmupsci arm,psci-1.0smctimerarm,armv8-timer@   xin24m fixed-clockn6xin24m ypcie@f8000000rockchip,rk3399-pcie axi-baseapb-basepci+"3? Gaclkaclk-perfhclkpm0123IsyslegacyclientY`lz ,pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-388(coremgmtmgmt-stickypipepmpclkaclk disabled  defaultinterrupt-controller"pcie-ep@f8000000rockchip,rk3399-pcie-ep apb-basemem-base Gaclkaclk-perfhclkpm8(coremgmtmgmt-stickypipepmpclkaclk ,pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-3 default disabledethernet@fe300000rockchip,rk3399-gmac0 Imacirq8ighfjfMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac& stmmaceth4AokayL\sinputrgmiidefault  'P(mmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc1@@р Mbiuciuciu-driveciu-sample&yreset disabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc2@AрL  Lbiuciuciu-driveciu-sample&zreset disabledmmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.13 LN Nclk_xinclk_ahbemmc_cardclock  phy_arasan&%okay6@Oi{usb@fe380000 generic-ehci8usbokayusb@fe3a0000 generic-ohci:usbokayusb@fe3c0000 generic-ehci< usbokayusb@fe3e0000 generic-ohci>  usbokaydebug@fe430000&arm,coresight-cpu-debugarm,primecellCM apb_pclkdebug@fe432000&arm,coresight-cpu-debugarm,primecellC M apb_pclkdebug@fe434000&arm,coresight-cpu-debugarm,primecellC@M apb_pclkdebug@fe436000&arm,coresight-cpu-debugarm,primecellC`M apb_pclkdebug@fe610000&arm,coresight-cpu-debugarm,primecellaL apb_pclkdebug@fe710000&arm,coresight-cpu-debugarm,primecellqL apb_pclkusb@fe800000rockchip,rk3399-dwc3+0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% usb3-otg disabledusb@fe800000 snps,dwc3irefbus_earlysuspendwotg!"usb2-phyusb3-phy utmi_wide& disabledusb@fe900000rockchip,rk3399-dwc3+0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& usb3-otg disabledusb@fe900000 snps,dwc3nrefbus_earlysuspendwotg#$usb2-phyusb3-phy utmi_wide& disableddp@fec00000rockchip,rk3399-cdn-dp Lr  ruocore-clkpclkspdifgrf%&& HJspdifdptxapbcore4 disabledportsport+endpoint@0.'endpoint@1.(interrupt-controller@fee00000 arm,gic-v3"+P  msi-controller@fee20000arm,gic-v3-its>Mppi-partitionsinterrupt-partition-0Xinterrupt-partition-1Xsaradc@ff100000rockchip,rk3399-saradc>aPesaradcapb_pclk saradc-apb disabledcrypto@ff8b0000rockchip,rk3399-crypto@hclk_masterhclk_slavesclkmasterslavecrypto-rstcrypto@ff8b8000rockchip,rk3399-crypto@hclk_masterhclk_slavesclkmasterslavecrypto-rsti2c@ff110000rockchip,rk3399-i2cLA AU i2cpclk;default)+ disabledi2c@ff120000rockchip,rk3399-i2cLB BV i2cpclk#default*+ disabledi2c@ff130000rockchip,rk3399-i2cLC CW i2cpclk"default++ disabledi2c@ff140000rockchip,rk3399-i2cLD DX i2cpclk&default,+ disabledi2c@ff150000rockchip,rk3399-i2cLE EY i2cpclk%default-+ disabledi2c@ff160000rockchip,rk3399-i2cLF FZ i2cpclk$default.+ disabledserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartQ`baudclkapb_pclkcs}default/ disabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartRabaudclkapb_pclkbs}default0 disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartSbbaudclkapb_pclkds}default1okayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartTcbaudclkapb_pclkes}default2 disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiG[spiclkapb_pclkD3 3 txrxdefault4567+ disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiH\spiclkapb_pclk53 3 txrxdefault89:;+ disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiI]spiclkapb_pclk433txrxdefault<=>?+ disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiJ^spiclkapb_pclkC33txrxdefault@ABC+ disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi K_spiclkapb_pclkDD txrxdefaultEFGH&+ disabledthermal-zonescpu-thermaldItripscpu_alert0ppassiveJcpu_alert1$passiveKcpu_crits criticalcooling-mapsmap0Jmap1KHgpu-thermaldItripsgpu_alert0$passiveLgpu_crits criticalcooling-mapsmap0L Mtsadc@ff260000rockchip,rk3399-tsadc&aLO qOdtsadcapb_pclk tsadc-apb4sinitdefaultsleepNON# disabledIqos@ffa58000rockchip,rk3399-qossyscon Wqos@ffa5c000rockchip,rk3399-qossyscon Xqos@ffa60080rockchip,rk3399-qossyscon qos@ffa60100rockchip,rk3399-qossyscon qos@ffa60180rockchip,rk3399-qossyscon qos@ffa70000rockchip,rk3399-qossyscon [qos@ffa70080rockchip,rk3399-qossyscon \qos@ffa74000rockchip,rk3399-qossyscon@ Yqos@ffa76000rockchip,rk3399-qossyscon` Zqos@ffa90000rockchip,rk3399-qossyscon ]qos@ffa98000rockchip,rk3399-qossyscon Pqos@ffaa0000rockchip,rk3399-qossyscon ^qos@ffaa0080rockchip,rk3399-qossyscon _qos@ffaa8000rockchip,rk3399-qossyscon `qos@ffaa8080rockchip,rk3399-qossyscon aqos@ffab0000rockchip,rk3399-qossyscon Qqos@ffab0080rockchip,rk3399-qossyscon Rqos@ffab8000rockchip,rk3399-qossyscon Sqos@ffac0000rockchip,rk3399-qossyscon Tqos@ffac0080rockchip,rk3399-qossyscon Uqos@ffac8000rockchip,rk3399-qossyscon bqos@ffac8080rockchip,rk3399-qossyscon cqos@ffad0000rockchip,rk3399-qossyscon dqos@ffad8080rockchip,rk3399-qossyscon qos@ffae0000rockchip,rk3399-qossyscon Vpower-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controller9+power-domain@34"MP9power-domain@33!MQR9power-domain@31MS9power-domain@32  MTU9power-domain@35#MV9power-domain@25l9power-domain@23MW9power-domain@22fMX9power-domain@27LMY9power-domain@28MZ9power-domain@8~}9power-domain@9 9power-domain@24M[\9power-domain@159+power-domain@21rM]9power-domain@19M^_9power-domain@20M`a9power-domain@169+power-domain@17Mbc9power-domain@18Md9syscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2 io-domains&rockchip,rk3399-pmu-io-voltage-domain disabledspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5eespiclkapb_pclk<defaultfghi+ disabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uart7ee"baudclkapb_pclkfs}defaultj disabledi2c@ff3c0000rockchip,rk3399-i2c<Le  e e i2cpclk9defaultk+okaypmic@1brockchip,rk808 ldefaultmTu rk808-clkout1rk808-clkout2nnnnnnnnnnn oregulatorsDCDC_REG1vdd_log& q>pVqkregulator-state-mem DCDC_REG2 vdd_cpu_l& q>pVqkregulator-state-memDCDC_REG3vcc_ddrkregulator-state-memDCDC_REG4vcc_1v8&w@>w@kregulator-state-memw@LDO_REG1 vcc1v8_dvp&w@>w@kregulator-state-memLDO_REG2 vcc3v0_tp&->-kregulator-state-memLDO_REG3 vcc1v8_pmu&w@>w@koregulator-state-memw@LDO_REG4vcc_sd&w@>-kregulator-state-mem-LDO_REG5vcca3v0_codec&->-kregulator-state-memLDO_REG6vcc_1v5&`>`kregulator-state-mem`LDO_REG7vcca1v8_codec&w@>w@kregulator-state-memLDO_REG8vcc_3v0&->-kregulator-state-mem-SWITCH_REG1 vcc3v3_s3kregulator-state-memSWITCH_REG2 vcc3v3_s0kregulator-state-memregulator@40silergy,syr827@ vdd_cpu_b& 4>`Vkpregulator-state-memregulator@41silergy,syr828Avdd_gpu& 4>`Vkpregulator-state-memi2c@ff3d0000rockchip,rk3399-i2c=Le  e e i2cpclk8defaultq+ disabledi2c@ff3e0000rockchip,rk3399-i2c>Le  e e i2cpclk:defaultr+ disabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmBdefaultseokaypwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmBdefaultte disabledpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmB defaultueokaypwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmB0defaultveokaydfi@ff630000c@rockchip,rk3399-dfi y pclk_ddr_mon disabledvideo-codec@ff650000rockchip,rk3399-vpue rq Ivepuvdpu aclkhclkw&iommu@ff650800rockchip,iommue@s aclkiface&wvideo-codec@ff660000rockchip,rk3399-vdecft axiahbcabaccorex& iommu@ff660480rockchip,iommu f@f@u aclkiface& xiommu@ff670800rockchip,iommug@* aclkiface disabledrga@ff680000rockchip,rk3399-rgah7maclkhclksclkjgi coreaxiahb&!efuse@ff690000rockchip,rk3399-efusei+} pclk_efusecpu-id@7cpu-leakage@17gpu-leakage@18center-leakage@19cpu-leakage@1alogic-leakage@1bwafer-info@1cdma-controller@ff6d0000arm,pl330arm,primecellm@ %0 apb_pclkDdma-controller@ff6e0000arm,pl330arm,primecelln@ %0 apb_pclk3clock-controller@ff750000rockchip,rk3399-pmucruuyxin24m4  GLe(Jeclock-controller@ff760000rockchip,rk3399-cruvyxin24m4 GL@BCxD#g/;рxh<4`#Fׄׄ ׄsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdw+io-domains"rockchip,rk3399-io-voltage-domain disabledmipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0wodphy-refdphy-cfggrf&T disabledusb2phy@e450rockchip,rk3399-usb2phyP{phyclk clk_usbphy0_480mokayhost-portT Ilinestateokayzotg-portT0ghjIotg-bvalidotg-idlinestate disabled!usb2phy@e460rockchip,rk3399-usb2phy`|phyclk clk_usbphy1_480mokayhost-portT Ilinestateokayz otg-portT0lmoIotg-bvalidotg-idlinestate disabled#phy@f780rockchip,rk3399-emmc-phy${emmcclk_2Tokaypcie-phyrockchip,rk3399-pcie-phyrefclkTphy disabledphy@ff7c0000rockchip,rk3399-typec-phy|~}tcpdcoretcpdphy-refL~&Luphyuphy-pipeuphy-tcphy4 disableddp-portT%usb3-portT"phy@ff800000rockchip,rk3399-typec-phytcpdcoretcpdphy-refL& Muphyuphy-pipeuphy-tcphy4 disableddp-portT&usb3-portT$watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdt|xrktimer@ff850000rockchip,rk3399-timerQhZ pclktimerspdif@ff870000rockchip,rk3399-spdifBDtx mclkhclkUdefault|& disabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2s4'DDtxrxi2s_clki2s_hclkVbclk_onbclk_off}~& disabledi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2s(DDtxrxi2s_clki2s_hclkWdefault& disabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2s)DDtxrxi2s_clki2s_hclkX& disabledvop@ff8f0000rockchip,rk3399-vop-lit wLׄaclk_vopdclk_vophclk_vop& axiahbdclk disabledport+ endpoint@0.endpoint@1.endpoint@2.endpoint@3.endpoint@4.(iommu@ff8f3f00rockchip,iommu?w aclkiface& disabledvop@ff900000rockchip,rk3399-vop-big vLׄaclk_vopdclk_vophclk_vop& axiahbdclkokayport+ endpoint@0.endpoint@1.endpoint@2.endpoint@3.endpoint@4.'iommu@ff903f00rockchip,iommu?v aclkiface&okayisp0@ff910000rockchip,rk3399-cif-isp@+nispaclkhclkdphy& disabledports+port@0+iommu@ff914000rockchip,iommu @P+ aclkiface&sisp1@ff920000rockchip,rk3399-cif-isp@,oispaclkhclkdphy& disabledports+port@0+iommu@ff924000rockchip,iommu @P, aclkiface&shdmi-soundsimple-audio-cardi2s hdmi-sound disabledsimple-audio-card,cpusimple-audio-card,codechdmi@ff940000rockchip,rk3399-dw-hdmi(tqpoiahbisfrcecgrfref&}4 disabledportsport+endpoint@0.endpoint@1.dsi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi- porefpclkphy_cfggrf&apb4+ disabledports+port@0+endpoint@0.endpoint@1.port@1dsi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi. qorefpclkphy_cfggrf&apb4+T disabledports+port@0+endpoint@0.endpoint@1.port@1dp@ff970000rockchip,rk3399-edp jlo dppclkgrfdefault&dp4okayports+port@0+endpoint@0.endpoint@1.port@1+endpoint@0.gpu@ff9a0000#rockchip,rk3399-maliarm,mali-t8600 Ijobmmugpu&# disabledMpinctrlrockchip,rk3399-pinctrl4 +gpio@ff720000rockchip,gpio-bankre"gpio@ff730000rockchip,gpio-bankse"lgpio@ff780000rockchip,gpio-bankxP"gpio@ff788000rockchip,gpio-bankxQ"gpio@ff790000rockchip,gpio-bankyR"pcfg-pull-up pcfg-pull-down pcfg-pull-none $pcfg-pull-none-12ma $ 1 pcfg-pull-none-13ma $ 1 pcfg-pull-none-18ma $ 1pcfg-pull-none-20ma $ 1pcfg-pull-up-2ma  1pcfg-pull-up-8ma  1pcfg-pull-up-18ma  1pcfg-pull-up-20ma  1pcfg-pull-down-4ma  1pcfg-pull-down-8ma  1pcfg-pull-down-12ma  1 pcfg-pull-down-18ma  1pcfg-pull-down-20ma  1pcfg-output-high @pcfg-output-low Lpcfg-input-enable Wpcfg-input-pull-up W pcfg-input-pull-down W clockclk-32k dcifcif-clkin d cif-clkouta d edpedp-hpd dgmacrgmii-pins d    rmii-pins d     i2c0i2c0-xfer dki2c1i2c1-xfer d)i2c2i2c2-xfer d*i2c3i2c3-xfer d+i2c4i2c4-xfer d  qi2c5i2c5-xfer d  ,i2c6i2c6-xfer d  -i2c7i2c7-xfer d.i2c8i2c8-xfer dri2s0i2s0-2ch-bus` di2s0-2ch-bus-bclk-off` di2s0-8ch-bus d}i2s0-8ch-bus-bclk-off d~i2s1i2s1-2ch-busP di2s1-2ch-bus-bclk-offP dsdio0sdio0-bus1 dsdio0-bus4@ dsdio0-cmd dsdio0-clk dsdio0-cd dsdio0-pwr dsdio0-bkpwr dsdio0-wp dsdio0-int dsdmmcsdmmc-bus1 dsdmmc-bus4@ d   sdmmc-clk d sdmmc-cmd d sdmmc-cd dsdmmc-wp dsuspendap-pwroff dddrio-pwroff dspdifspdif-bus d|spdif-bus-1 dspi0spi0-clk d4spi0-cs0 d7spi0-cs1 dspi0-tx d5spi0-rx d6spi1spi1-clk d 8spi1-cs0 d ;spi1-rx d:spi1-tx d9spi2spi2-clk d <spi2-cs0 d ?spi2-rx d >spi2-tx d =spi3spi3-clk dfspi3-cs0 dispi3-rx dhspi3-tx dgspi4spi4-clk d@spi4-cs0 dCspi4-rx dBspi4-tx dAspi5spi5-clk dEspi5-cs0 dHspi5-rx dGspi5-tx dFtestclktest-clkout0 dtest-clkout1 dtest-clkout2 dtsadcotp-pin dNotp-out dOuart0uart0-xfer d/uart0-cts duart0-rts duart1uart1-xfer d  0uart2auart2a-xfer d uart2buart2b-xfer duart2cuart2c-xfer d1uart3uart3-xfer d2uart3-cts duart3-rts duart4uart4-xfer djuarthdcpuarthdcp-xfer dpwm0pwm0-pin dspwm0-pin-pull-down dvop0-pwm-pin dvop1-pwm-pin dpwm1pwm1-pin dtpwm1-pin-pull-down dpwm2pwm2-pin dupwm2-pin-pull-down dpwm3apwm3a-pin dvpwm3bpwm3b-pin dhdmihdmi-i2c-xfer dhdmi-cec dpciepci-clkreqn-cpm dpci-clkreqnb-cpm dpmicpmic-int-l dmusb2vcc5v0-host-en dbacklightpwm-backlight r  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  aedp-panellg,lp079qx1-sp0v  l  portendpoint.external-gmac-clock fixed-clocksY@ clkin_gmac vdd-centerpwm-regulator a vdd_center& 5>\kokayvcc3v3-sysregulator-fixed vcc3v3_sysk&2Z>2Znvcc5v0-sysregulator-fixed vcc5v0_sysk&LK@>LK@pvcc5v0-host-regulatorregulator-fixed  default vcc5v0_hostpzvcc-phy-regulatorregulator-fixedvcc_phyk compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesep-gpiosnum-lanespinctrl-namespinctrl-0interrupt-controllermax-functionsrockchip,max-outbound-regionspower-domainsrockchip,grfsnps,txpblassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaymax-frequencyfifo-depthassigned-clock-ratesarasan,soc-ctl-syscondisable-cqe-dcmdbus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsreg-shiftreg-io-widthdmasdma-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#power-domain-cellspm_qosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendfcs,suspend-voltage-selectorvin-supply#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cells#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiforce-hpdgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsbrightness-levelsdefault-brightness-levelpwmsbacklightenable-gpiospower-supplyenable-active-high