mZ8f(vf)tronsmart,orion-r68-metarockchip,rk3368 +7Rockchip Orion R68aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6 xin24m Fmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @- ;  D r vBbiuciuciu-driveciu-sampleN Y `resetlokays}default mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  E s wBbiuciuciu-driveciu-sampleN !Y `reset ldisabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@-р ;  G u yBbiuciuciu-driveciu-sampleN #Y `resetlokays default saradc@ff100000rockchip,saradc $; I [Bsaradcapb_pclkY W `saradc-apblokay,spi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi; A RBspiclkapb_pclk ,default+ ldisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi; B SBspiclkapb_pclk -default+ ldisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi; C TBspiclkapb_pclk )default !+ ldisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Bi2c; Ndefault" ldisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Bi2c; Odefault# ldisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Bi2c; Pdefault$ ldisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Bi2c; Qdefault% ldisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6; M UBbaudclkapb_pclk 78B ldisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6; N VBbaudclkapb_pclk 88B ldisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; P XBbaudclkapb_pclk :8B ldisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; Q YBbaudclkapb_pclk ;8Blokaydefault&dma-controller@ff250000arm,pl330arm,primecell%@OZu;  Bapb_pclkthermal-zonescpu-thermald'tripscpu_alert0$passive(cpu_alert18passive)cpu_crits criticalcooling-mapsmap0(0map1)0 gpu-thermald'tripsgpu_alert08passive*gpu_crit8 criticalcooling-mapsmap0*0tsadc@ff280000rockchip,rk3368-tsadc( %; H ZBtsadcapb_pclkY  `tsadc-apbinitdefaultsleep+,+s ldisabled'ethernet@ff290000rockchip,rk3368-gmac) ,macirq<-8;  f g c ]MBstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maclokayI Y.pinput}/rgmiidefault0 1  'B@0usb@ff500000 generic-ehciP ; lokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X ; Botgotg@@ lokaydma-controller@ff600000arm,pl330arm,primecell`@OZu;  Bapb_pclkGi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce; LBi2c <default2+lokaysyr827@40silergy,syr827@3vdd_cpuB,^ 4v`@3rtc@51haoyu,hym8563Q  xin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Bi2c; Mdefault4 ldisabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault5; _ ldisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault6; _ ldisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh ; _ ldisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default7; _ ldisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti; O WBbaudclkapb_pclk 9default88Blokaymbox@ff6b0000rockchip,rk3368-mailboxk0; E Bpclk_mailbox ldisabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller+Jpower-domain@12 ;       c h g n o r s f d d h i l k j n m$9:;<=>?@Apower-domain@14 ;  o p BCDpower-domain@16; @Esyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsKio-domains&rockchip,rk3368-pmu-io-voltage-domain ldisabledreboot-modesyscon-reboot-mode RBRB'RB 7RBclock-controller@ff760000rockchip,rk3368-cruv;FBxin24m<- C syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain ldisabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt; p Olokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  B; a U Bpclktimerspdif@ff880000rockchip,rk3368-spdif 6; S  BmclkhclkPGUtxdefaultH ldisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Bi2s_clki2s_hclk; T PGGUtxrx ldisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Bi2s_clki2s_hclk; R PGGUtxrxdefaultI ldisablediommu@ff900800rockchip,iommu ;  Baclkiface_J m ldisablediommu@ff914000rockchip,iommu @P ;  Baclkifacem_J z ldisablediommu@ff930300rockchip,iommu ;  Baclkiface_J m ldisablediommu@ff9a0440rockchip,iommu @@@ ;  Baclkifacem ldisablediommu@ff9a0800rockchip,iommu  ;  Baclkifacem ldisabledqos@ffad0000rockchip,rk3368-qossyscon 9qos@ffad0080rockchip,rk3368-qossyscon :qos@ffad0100rockchip,rk3368-qossyscon ;qos@ffad0180rockchip,rk3368-qossyscon <qos@ffad0200rockchip,rk3368-qossyscon =qos@ffad0280rockchip,rk3368-qossyscon >qos@ffad0300rockchip,rk3368-qossyscon ?qos@ffad0380rockchip,rk3368-qossyscon @qos@ffad0400rockchip,rk3368-qossyscon Aqos@ffae0000rockchip,rk3368-qossyscon Bqos@ffae0100rockchip,rk3368-qossyscon Cqos@ffae0180rockchip,rk3368-qossyscon Dqos@ffaf0000rockchip,rk3368-qossyscon Eefuse@ffb00000rockchip,rk3368-efuse +; q Bpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl<-K+gpio@ff750000rockchip,gpio-banku; @ QUgpio@ff780000rockchip,gpio-bankx; A Rgpio@ff790000rockchip,gpio-banky; B SSgpio@ff7a0000rockchip,gpio-bankz; C T1pcfg-pull-upNpcfg-pull-downQpcfg-pull-noneOpcfg-pull-none-12ma Pemmcemmc-clk#Lemmc-cmd#Memmc-pwr#Nemmc-bus1#Nemmc-bus4@#NNNNemmc-bus8#MMMMMMMMemmc-reset#ORgmacrgmii-pins#OOOP P PPP POOOOOO0rmii-pins#OOOP P POOOOi2c0i2c0-xfer #OO2i2c1i2c1-xfer #OO4i2c2i2c2-xfer # OO"i2c3i2c3-xfer #OO#i2c4i2c4-xfer #OO$i2c5i2c5-xfer #OO%i2si2s-8ch-bus# O OOOOOOOOIpwm0pwm0-pin#O5pwm1pwm1-pin#O6pwm3pwm3-pin#O7sdio0sdio0-bus1#Nsdio0-bus4@#NNNNsdio0-cmd#Nsdio0-clk#Osdio0-cd#Nsdio0-wp#Nsdio0-pwr#Nsdio0-bkpwr#Nsdio0-int#Nsdmmcsdmmc-clk# L sdmmc-cmd# M sdmmc-cd# M sdmmc-bus1#Msdmmc-bus4@#MMMMspdifspdif-tx#OHspi0spi0-clk#Nspi0-cs0#Nspi0-cs1#Nspi0-tx#Nspi0-rx#Nspi1spi1-clk#Nspi1-cs0#Nspi1-cs1#Nspi1-rx#Nspi1-tx#Nspi2spi2-clk# Nspi2-cs0# N!spi2-rx# N spi2-tx# Ntsadcotp-pin#O+otp-out#O,uart0uart0-xfer #NOuart0-cts#Ouart0-rts#Ouart1uart1-xfer #NOuart1-cts#Ouart1-rts#Ouart2uart2-xfer #NO8uart3uart3-xfer #NOuart3-cts#Ouart3-rts#Ouart4uart4-xfer #NO&uart4-cts#Ouart4-rts#Opcfg-pull-none-drv-8maLpcfg-pull-up-drv-8maMkeyspwr-key#QTledsstby-pwren# OWled-ctl#OVusbhost-vbus-drv#OXchosen1serial2:115200n8memorymemoryemmc-pwrseqmmc-pwrseq-emmcRdefault =Sexternal-gmac-clock fixed-clock sY@  ext_gmac.gpio-keys gpio-keysdefaultTkey-powerI CU WGPIO Power]tgpio-leds gpio-ledsled-0 C1Worion:red:leddefaultVhonled-1 CU Worion:blue:leddefaultWhoffvcc18-regulatorregulator-fixed3vcc_18^w@vw@3vcc-host-regulatorregulator-fixed UdefaultX 3vcc_host3vcc-io-regulatorregulator-fixed3vcc_io^2Zv2Z3Yvcc-lan-regulatorregulator-fixed3vcc_lan^2Zv2ZY/vcc-sd-regulatorregulator-fixed3vcc_sd 1 ^w@v2ZYvcc-sys-regulatorregulator-fixed3vcc_sys^LK@vLK@3vcc-io-sd-regulatorregulator-fixed 3vccio_sd^w@v2ZYvccio-wl-regulatorregulator-fixed 3vccio_wl^2Zv2ZYvdd-10-regulatorregulator-fixed3vdd_10^B@vB@3 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state