8( -xunlong,orangepi-r1-plus-ltsrockchip,rk3328 +7Xunlong Orange Pi R1 Plus LTSaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/usb@ff600000/device@2}/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci cpu@1cpuarm,cortex-a53xpsci cpu@2cpuarm,cortex-a53xpsci cpu@3cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state%6Mx^nl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2s Analog  disabledsimple-audio-card,cpu'simple-audio-card,codec'arm-pmuarm,cortex-a53-pmu01defg< display-subsystemrockchip,display-subsystemO   disabledhdmi-soundsimple-audio-cardi2s HDMI  disabledsimple-audio-card,cpu'simple-audio-card,codec'psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer01   xin24m fixed-clockUbn6rxin24mCi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s 1)7i2s_clki2s_hclk  txrx  disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s 1*8i2s_clki2s_hclktxrx  disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s 1+9i2s_clki2s_hclktxrx  disabledspdif@ff030000rockchip,rk3328-spdif 1.: mclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd8io-domains"rockchip,rk3328-io-voltage-domain okay &gpiorockchip,rk3328-grf-gpio4Dpower-controller!rockchip,rk3328-power-controllerP+:power-domain@6Ppower-domain@5 BABPpower-domain@8FPreboot-modesyscon-reboot-modedkRBwRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 17&baudclkapb_pclktxrxdefault    disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 18'baudclkapb_pclktxrxdefault !"#  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 19(baudclkapb_pclktxrxdefault$ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c 1$+7 i2cpclkdefault%  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c 1%+8 i2cpclkdefault& okaypmic@18rockchip,rk805 '1Urxin32krk805-clkout24D(default))) )#)regulatorsDCDC_REG1/vdd_log>Rd 4| 0regulator-state-memB@DCDC_REG2/vdd_arm>Rd 4| 0regulator-state-mem~DCDC_REG3/vcc_ddr>Rregulator-state-memDCDC_REG4/vcc_io>Rd2Z|2Zregulator-state-mem2ZLDO_REG1/vcc_18>Rdw@|w@regulator-state-memw@LDO_REG2 /vcc18_emmc>Rdw@|w@regulator-state-memw@LDO_REG3/vdd_10>RdB@|B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c 1&+9 i2cpclkdefault*  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c 1'+: i2cpclkdefault+  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 11+ spiclkapb_pclk txrxdefault,-./ okayflash@0jedec,spi-norwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt 1(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault0  disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault1  disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault2 okaypwm@ff1b0030rockchip,rk3328-pwm0 12< pwmpclkdefault3  disableddma-controller@ff1f0000arm,pl330arm,primecell@1 apb_pclkthermal-zonessoc-thermal2@R4tripstrip-point0bpnpassivetrip-point1bLnpassive5soc-critbsn criticalcooling-mapsmap0y50~ tsadc@ff250000rockchip,rk3328-tsadc% 1:$P$tsadcapb_pclkinitdefaultsleep676B tsadc-apb8 okay-4efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuseH id@7cpu-leakage@17logic-leakage@19cpu-version@1a\Dadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( 1Pa%saradcapb_pclkV saradc-apb  disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500T1ZW]XY[\"sgpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 1` aclkiface  disablediommu@ff340800rockchip,iommu4@ 1bF aclkiface  disabledvideo-codec@ff350000rockchip,rk3328-vpu5 1 svdpuF aclkhclk9:iommu@ff350800rockchip,iommu5@ 1 F aclkiface:9video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 1 BABaxiahbcabaccoreAB ׄׄ;:iommu@ff360480rockchip,iommu 6@6@ 1JB aclkiface:;vop@ff370000rockchip,rk3328-vop7> 1 x;aclk_vopdclk_vophclk_vop axiahbdclk<  disabledport+ endpoint@0=Biommu@ff373f00rockchip,iommu7? 1 ; aclkiface  disabled<hdmi@ff3c0000rockchip,rk3328-dw-hdmi<1#GFiahbisfrcec>hdmidefault ?@A8  disabledportsportendpointB=codec@ff410000rockchip,rk3328-codecA* pclkmclk8  disabledphy@ff430000rockchip,rk3328-hdmi-phyC 1SCysysclkrefoclkrefpclk rhdmi_phyUD cpu-version  disabled>clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD8Ux=&'(ABDC"\5H4$zCCC|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyCphyclk rusb480m_phyU{E okayEotg-port$1;<=sotg-bvalidotg-idlinestate okayRhost-port 1> slinestate okaySmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ 1  =!JNbiuciuciu-driveciu-sampleр okay%6FGHIdefaultAJmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ 1  >"KObiuciuciu-driveciu-sampleр  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ 1 ?#LPbiuciuciu-driveciu-sampleр  disabledethernet@ff540000rockchip,rk3328-gmacT 1smacirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth8M okaydfKKXinputeLprgmiiyMdefaultmdiosnps,dwmac-mdio+ethernet-phy@0ethernet-phy-ieee802.3-c22sY@Ndefault:P 'Lethernet@ff550000rockchip,rk3328-gmacU8 1smacirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethprmiieOMXoutput  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultPQ%Ousb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X 1Motg7host?Q`@ R usb2-phy okayusb@ff5c0000 generic-ehci\ 1 NESusb okayusb@ff5d0000 generic-ohci] 1 NESusb okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` 1C`aref_clksuspend_clkbus_clk7host outmi_widex  okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400 & 7@ @ `  1 crypto@ff060000rockchip,rk3328-crypto@ 1PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl8+ Lgpio@ff210000rockchip,gpio-bank! 134D 7 &dgpio@ff220000rockchip,gpio-bank" 144D 7 &'gpio@ff230000rockchip,gpio-bank# 154D 7 &bgpio@ff240000rockchip,gpio-bank$ 164D 7 &cpcfg-pull-up SVpcfg-pull-down `^pcfg-pull-none oTpcfg-pull-none-2ma o |]pcfg-pull-up-2ma S |pcfg-pull-up-4ma S |Wpcfg-pull-none-4ma o |Zpcfg-pull-down-4ma ` |pcfg-pull-none-8ma o |Xpcfg-pull-up-8ma S |Ypcfg-pull-none-12ma o | [pcfg-pull-up-12ma S | \pcfg-output-high pcfg-output-low pcfg-input-high S Upcfg-input i2c0i2c0-xfer TT%i2c1i2c1-xfer TT&i2c2i2c2-xfer  TT*i2c3i2c3-xfer TT+i2c3-pins TThdmi_i2chdmii2c-xfer TT@pdm-0pdmm0-clk Tpdmm0-fsync Tpdmm0-sdi0 Tpdmm0-sdi1 Tpdmm0-sdi2 Tpdmm0-sdi3 Tpdmm0-clk-sleep Updmm0-sdi0-sleep Updmm0-sdi1-sleep Updmm0-sdi2-sleep Updmm0-sdi3-sleep Updmm0-fsync-sleep Utsadcotp-pin  T6otp-out  T7uart0uart0-xfer  TVuart0-cts  Tuart0-rts  T uart0-rts-pin  Tuart1uart1-xfer TV!uart1-cts T"uart1-rts T#uart1-rts-pin Tuart2-0uart2m0-xfer TVuart2-1uart2m1-xfer TV$spi0-0spi0m0-clk Vspi0m0-cs0  Vspi0m0-tx  Vspi0m0-rx  Vspi0m0-cs1  Vspi0-1spi0m1-clk Vspi0m1-cs0 Vspi0m1-tx Vspi0m1-rx Vspi0m1-cs1 Vspi0-2spi0m2-clk V,spi0m2-cs0 V/spi0m2-tx V-spi0m2-rx V.i2s1i2s1-mclk Ti2s1-sclk Ti2s1-lrckrx Ti2s1-lrcktx Ti2s1-sdi Ti2s1-sdo Ti2s1-sdio1 Ti2s1-sdio2 Ti2s1-sdio3 Ti2s1-sleep UUUUUUUUUi2s2-0i2s2m0-mclk Ti2s2m0-sclk Ti2s2m0-lrckrx Ti2s2m0-lrcktx Ti2s2m0-sdi Ti2s2m0-sdo Ti2s2m0-sleep` UUUUUUi2s2-1i2s2m1-mclk Ti2s2m1-sclk Ti2sm1-lrckrx Ti2s2m1-lrcktx Ti2s2m1-sdi Ti2s2m1-sdo Ti2s2m1-sleepP UUUUUspdif-0spdifm0-tx Tspdif-1spdifm1-tx Tspdif-2spdifm2-tx Tsdmmc0-0sdmmc0m0-pwren Wsdmmc0m0-pin Wsdmmc0-1sdmmc0m1-pwren Wsdmmc0m1-pin Wesdmmc0sdmmc0-clk XFsdmmc0-cmd YGsdmmc0-dectn WHsdmmc0-wrprt Wsdmmc0-bus1 Ysdmmc0-bus4@ YYYYIsdmmc0-pins WWWWWWWWsdmmc0extsdmmc0ext-clk Zsdmmc0ext-cmd Wsdmmc0ext-wrprt Wsdmmc0ext-dectn Wsdmmc0ext-bus1 Wsdmmc0ext-bus4@ WWWWsdmmc0ext-pins WWWWWWWWsdmmc1sdmmc1-clk  Xsdmmc1-cmd  Ysdmmc1-pwren Ysdmmc1-wrprt Ysdmmc1-dectn Ysdmmc1-bus1 Ysdmmc1-bus4@ YYYYsdmmc1-pins  W WWWWWWWWemmcemmc-clk [emmc-cmd \emmc-pwren Temmc-rstnout Temmc-bus1 \emmc-bus4@ \\\\emmc-bus8 \\\\\\\\pwm0pwm0-pin T0pwm1pwm1-pin T1pwm2pwm2-pin T2pwmirpwmir-pin T3gmac-1rgmiim1-pins`  X ZZXZZZ Z ZX XZZXXX XZXXXXMrmiim1-pins ][]]]] ] ][ [ T TTTTTgmac2phyfephyled-speed10 Tfephyled-duplex Tfephyled-rxm1 TPfephyled-txm1 Tfephyled-linkm1 TQtsadc_pintsadc-int  Ttsadc-pin  Thdmi_pinhdmi-cec T?hdmi-hpd ^Acif-0dvp-d2d9-m0 TTTTT T T TTTTTcif-1dvp-d2d9-m1 TTTTTTTTTTTTgmac2ioeth-phy-reset-pin ^Nledslan-led-pin T_sys-led-pin T`wan-led-pin Talanlan-vdd-pin Tfpmicpmic-int-l V(chosen serial2:1500000n8gmac-clock fixed-clockbsY@ rgmac_clkinUKleds gpio-leds _`adefaultled-0 lan  bled-1 status  c heartbeatled-2 wan  bsdmmc-regulatorregulator-fixed dedefault/vcc_sdR Jvcc-sys-regulatorregulator-fixed/vcc_sys>RdLK@|LK@)vdd-5v-lan-regulatorregulator-fixed  bfdefault /vdd_5v_lan>R ) compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-sd-highspeeddisable-wpvmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalrx_delaytx_delaymotorcomm,clk-out-frequency-hzmotorcomm,keep-pll-enabledmotorcomm,auto-sleep-disabledreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathfunctioncolorlinux,default-triggergpiovin-supplyenable-active-high