*8( >'friendlyarm,nanopi-r2srockchip,rk3328 +7FriendlyElec NanoPi R2Saliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/usb@ff600000/device@2}/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci cpu@1cpuarm,cortex-a53xpsci cpu@2cpuarm,cortex-a53xpsci cpu@3cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state%6Mx^nl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2s Analog  disabledsimple-audio-card,cpu'simple-audio-card,codec'arm-pmuarm,cortex-a53-pmu01defg< display-subsystemrockchip,display-subsystemO   disabledhdmi-soundsimple-audio-cardi2s HDMI  disabledsimple-audio-card,cpu'simple-audio-card,codec'psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer01   xin24m fixed-clockUbn6rxin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s 1)7i2s_clki2s_hclk  txrx  disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s 1*8i2s_clki2s_hclktxrx  disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s 1+9i2s_clki2s_hclktxrx  disabledspdif@ff030000rockchip,rk3328-spdif 1.: mclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd:io-domains"rockchip,rk3328-io-voltage-domain okay &gpiorockchip,rk3328-grf-gpio4Dpower-controller!rockchip,rk3328-power-controllerP+<power-domain@6Ppower-domain@5 BABPpower-domain@8FPreboot-modesyscon-reboot-modedkRBwRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 17&baudclkapb_pclktxrxdefault  !"  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 18'baudclkapb_pclktxrxdefault #$%  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 19(baudclkapb_pclktxrxdefault& okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c 1$+7 i2cpclkdefault'  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c 1%+8 i2cpclkdefault( okaypmic@18rockchip,rk805 )1Urxin32krk805-clkout24D*default+++ +#+regulatorsDCDC_REG1/vdd_log>Rd 4| 0regulator-state-memB@DCDC_REG2/vdd_arm>Rd 4| 0regulator-state-mem~DCDC_REG3/vcc_ddr>Rregulator-state-memDCDC_REG4 /vcc_io_33>Rd2Z|2Zregulator-state-mem2ZLDO_REG1/vcc_18>Rdw@|w@regulator-state-memw@LDO_REG2 /vcc18_emmc>Rdw@|w@regulator-state-memw@LDO_REG3/vdd_10>RdB@|B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c 1&+9 i2cpclkdefault,  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c 1'+: i2cpclkdefault-  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 11+ spiclkapb_pclk txrxdefault./01  disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt 1(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault2  disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault3  disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault4 okaypwm@ff1b0030rockchip,rk3328-pwm0 12< pwmpclkdefault5  disableddma-controller@ff1f0000arm,pl330arm,primecell@1 apb_pclkthermal-zonessoc-thermal  .@6tripstrip-point0Pp\passivetrip-point1PL\passive7soc-critPs\ criticalcooling-mapsmap0g70l {tsadc@ff250000rockchip,rk3328-tsadc% 1:$P$tsadcapb_pclkinitdefaultsleep898B tsadc-apb: okay6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse6 id@7cpu-leakage@17logic-leakage@19cpu-version@1aJFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( 1PO%saradcapb_pclkV saradc-apb  disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500T1ZW]XY[\"agpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 1` aclkifaceq  disablediommu@ff340800rockchip,iommu4@ 1bF aclkifaceq  disabledvideo-codec@ff350000rockchip,rk3328-vpu5 1 avdpuF aclkhclk~;<iommu@ff350800rockchip,iommu5@ 1 F aclkifaceq<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 1 BABaxiahbcabaccoreAB ׄׄ~=<iommu@ff360480rockchip,iommu 6@6@ 1JB aclkifaceq<=vop@ff370000rockchip,rk3328-vop7> 1 x;aclk_vopdclk_vophclk_vop axiahbdclk~>  disabledport+ endpoint@0?Diommu@ff373f00rockchip,iommu7? 1 ; aclkifaceq  disabled>hdmi@ff3c0000rockchip,rk3328-dw-hdmi<1#GFiahbisfrcec@hdmidefault ABC:  disabledportsportendpointD?codec@ff410000rockchip,rk3328-codecA* pclkmclk:  disabledphy@ff430000rockchip,rk3328-hdmi-phyC 1SEysysclkrefoclkrefpclk rhdmi_phyUF cpu-version  disabled@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD:Ux=&'(ABDC"\5H4$zEEE|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk rusb480m_phyU{G okayGotg-port$1;<=aotg-bvalidotg-idlinestate okayThost-port 1> alinestate okayUmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ 1  =!JNbiuciuciu-driveciu-sample р okay!2HIJKdefault=JWdrL~mmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ 1  >"KObiuciuciu-driveciu-sample р  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ 1 ?#LPbiuciuciu-driveciu-sample р  disabledethernet@ff540000rockchip,rk3328-gmacT 1amacirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth: okaydfMMinputNrgmiiOdefault$mdiosnps,dwmac-mdio+ethernet-phy@1Pdefault'P )Nethernet@ff550000rockchip,rk3328-gmacU: 1amacirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmiiQoutput  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultRS Qusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X 1Motghost%7F@ T usb2-phy okayusb@ff5c0000 generic-ehci\ 1 NGUusb okayusb@ff5d0000 generic-ohci] 1 NGUusb okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` 1C`aref_clksuspend_clkbus_clkhost Uutmi_wide^ okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `  1 crypto@ff060000rockchip,rk3328-crypto@ 1PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl:+ 2gpio@ff210000rockchip,gpio-bank! 134D  bgpio@ff220000rockchip,gpio-bank" 144D  )gpio@ff230000rockchip,gpio-bank# 154D  fgpio@ff240000rockchip,gpio-bank$ 164D  pcfg-pull-up 9Xpcfg-pull-down F`pcfg-pull-none UVpcfg-pull-none-2ma U b_pcfg-pull-up-2ma 9 bpcfg-pull-up-4ma 9 bYpcfg-pull-none-4ma U b\pcfg-pull-down-4ma F bpcfg-pull-none-8ma U bZpcfg-pull-up-8ma 9 b[pcfg-pull-none-12ma U b ]pcfg-pull-up-12ma 9 b ^pcfg-output-high qpcfg-output-low }pcfg-input-high 9 Wpcfg-input i2c0i2c0-xfer VV'i2c1i2c1-xfer VV(i2c2i2c2-xfer  VV,i2c3i2c3-xfer VV-i2c3-pins VVhdmi_i2chdmii2c-xfer VVBpdm-0pdmm0-clk Vpdmm0-fsync Vpdmm0-sdi0 Vpdmm0-sdi1 Vpdmm0-sdi2 Vpdmm0-sdi3 Vpdmm0-clk-sleep Wpdmm0-sdi0-sleep Wpdmm0-sdi1-sleep Wpdmm0-sdi2-sleep Wpdmm0-sdi3-sleep Wpdmm0-fsync-sleep Wtsadcotp-pin  V8otp-out  V9uart0uart0-xfer  VX uart0-cts  V!uart0-rts  V"uart0-rts-pin  Vuart1uart1-xfer VX#uart1-cts V$uart1-rts V%uart1-rts-pin Vuart2-0uart2m0-xfer VXuart2-1uart2m1-xfer VX&spi0-0spi0m0-clk Xspi0m0-cs0  Xspi0m0-tx  Xspi0m0-rx  Xspi0m0-cs1  Xspi0-1spi0m1-clk Xspi0m1-cs0 Xspi0m1-tx Xspi0m1-rx Xspi0m1-cs1 Xspi0-2spi0m2-clk X.spi0m2-cs0 X1spi0m2-tx X/spi0m2-rx X0i2s1i2s1-mclk Vi2s1-sclk Vi2s1-lrckrx Vi2s1-lrcktx Vi2s1-sdi Vi2s1-sdo Vi2s1-sdio1 Vi2s1-sdio2 Vi2s1-sdio3 Vi2s1-sleep WWWWWWWWWi2s2-0i2s2m0-mclk Vi2s2m0-sclk Vi2s2m0-lrckrx Vi2s2m0-lrcktx Vi2s2m0-sdi Vi2s2m0-sdo Vi2s2m0-sleep` WWWWWWi2s2-1i2s2m1-mclk Vi2s2m1-sclk Vi2sm1-lrckrx Vi2s2m1-lrcktx Vi2s2m1-sdi Vi2s2m1-sdo Vi2s2m1-sleepP WWWWWspdif-0spdifm0-tx Vspdif-1spdifm1-tx Vspdif-2spdifm2-tx Vsdmmc0-0sdmmc0m0-pwren Ysdmmc0m0-pin Ysdmmc0-1sdmmc0m1-pwren Ysdmmc0m1-pin Yhsdmmc0sdmmc0-clk ZHsdmmc0-cmd [Isdmmc0-dectn YJsdmmc0-wrprt Ysdmmc0-bus1 [sdmmc0-bus4@ [[[[Ksdmmc0-pins YYYYYYYYsdmmc0extsdmmc0ext-clk \sdmmc0ext-cmd Ysdmmc0ext-wrprt Ysdmmc0ext-dectn Ysdmmc0ext-bus1 Ysdmmc0ext-bus4@ YYYYsdmmc0ext-pins YYYYYYYYsdmmc1sdmmc1-clk  Zsdmmc1-cmd  [sdmmc1-pwren [sdmmc1-wrprt [sdmmc1-dectn [sdmmc1-bus1 [sdmmc1-bus4@ [[[[sdmmc1-pins  Y YYYYYYYYemmcemmc-clk ]emmc-cmd ^emmc-pwren Vemmc-rstnout Vemmc-bus1 ^emmc-bus4@ ^^^^emmc-bus8 ^^^^^^^^pwm0pwm0-pin V2pwm1pwm1-pin V3pwm2pwm2-pin V4pwmirpwmir-pin V5gmac-1rgmiim1-pins`  Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZOrmiim1-pins _]____ _ _] ] V VVVVVgmac2phyfephyled-speed10 Vfephyled-duplex Vfephyled-rxm1 VRfephyled-txm1 Vfephyled-linkm1 VStsadc_pintsadc-int  Vtsadc-pin  Vhdmi_pinhdmi-cec VAhdmi-hpd `Ccif-0dvp-d2d9-m0 VVVVV V V VVVVVcif-1dvp-d2d9-m1 VVVVVVVVVVVVbuttonreset-button-pin Vagmac2ioeth-phy-reset-pin `Pledslan-led-pin Vcsys-led-pin Vdwan-led-pin Velanlan-vdd-pin Vipmicpmic-int-l X*sdsdio-vcc-pin Xgchosen serial2:1500000n8gmac-clock fixed-clockbsY@ rgmac_clkinUMkeys gpio-keysadefaultkey-reset reset b  2leds gpio-leds cdedefaultled-0 f nanopi-r2s:green:lanled-1 b nanopi-r2s:red:sys onled-2 f nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio  )gdefault /vcc_io_sdio>dw@|2Z  voltage w@2Z .sdmmc-regulatorregulator-fixed 9bhdefault/vcc_sdRd2Z|2Z .Lvdd-5vregulator-fixed/vdd_5v>RdLK@|LK@+vdd-5v-lanregulator-fixed  9fidefault /vdd_5v_lan>R .+ compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio