8(  rockchip,px30-evbrockchip,px30 +7Rockchip PX30 EVBaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff370000/mmc@ff380000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ!cpu@1cpuarm,cortex-a35psciZ!cpu@2cpuarm,cortex-a35psciZ! cpu@3cpuarm,cortex-a35psciZ! idle-states)pscicpu-sleeparm,idle-state6G^xo!cluster-sleeparm,idle-state6G^o!opp-table-0operating-points-v2!opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal(>L^ tripstrip-point-0npzpassivetrip-point-1nLzpassive!soc-critn8z criticalcooling-mapsmap0 gpu-thermal(d>^ tripsgpu-thresholdnpzpassivegpu-targetnLzpassive!gpu-critn8z criticalcooling-mapsmap0 xin24m fixed-clockn6xin24m!upower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+!wpower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+!io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&(baudclkapb_pclk4''9txrxCMZdefault h()* disabledi2s@ff060000rockchip,px30-i2s-tdm  (mclk_txmclk_rxhclk4''9txrxr+ tx-mrx-mZdefault0h,-./01234567 disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  (i2s_clki2s_hclk4''9txrxZdefaulth89:;okayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s (i2s_clki2s_hclk4''9txrxZdefaulth<=>? disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+!+io-domains rockchip,px30-io-voltage-domainokay@AB%B@lvdsrockchip,px30-lvdsC"dphyr+,lvds disabledports+port@0+endpoint@0<D!endpoint@1<E!port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I(baudclkapb_pclk4''9txrxCMZdefaulthFGokayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J(baudclkapb_pclk4''9txrxCMZdefaulthH disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K(baudclkapb_pclk4''9txrxCMZdefault hIJK disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L(baudclkapb_pclk4'' 9txrxCMZdefault hLMN disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M(baudclkapb_pclk4' ' 9txrxCMZdefault hOPQokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN (i2cpclk ZdefaulthR+okaypmic@20rockchip,rk809  SZdefaulthTLmxin32k{UUUUVVVVUregulatorsDCDC_REG1vdd_log~p&q;O!regulator-state-memay~DCDC_REG2vdd_arm~p&q;O!regulator-state-memy~DCDC_REG3vcc_ddr;Oregulator-state-memaDCDC_REG4vcc_3v0--;O!Bregulator-state-memay-DCDC_REG5 vcc3v3_sys2Z2Z;O!Vregulator-state-memay2ZLDO_REG1vcc_1v0B@B@;Oregulator-state-memayB@LDO_REG2vcc_1v8w@w@;O!@regulator-state-memayw@LDO_REG3vdd_1v0B@B@;Oregulator-state-memayB@LDO_REG4 vcc3v0_pmu--;O!%regulator-state-memay-LDO_REG5 vccio_sdw@2Z;O!Aregulator-state-memay2ZLDO_REG6vcc_sd2Z2ZO!regulator-state-memay2ZLDO_REG7 vcc2v8_dvp**O!Zregulator-state-memy*LDO_REG8 vcc1v8_dvpw@w@O!\regulator-state-memayw@LDO_REG9 vcc1v5_dvp``O![regulator-state-memy`SWITCH_REG1 vcc3v3_lcdO!XSWITCH_REG2 vcc5v0_host;Oi2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO (i2cpclk ZdefaulthW+okaysensor@dasahi-kasei,ak8963  S%100010001touchscreen@14goodix,gt1151 S S S Xsensor@4c fsl,mma7660L Si2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP (i2cpclk  ZdefaulthY+okay2,ov5695@36 ovti,ov56956Z4(xvclk*[6\Zdefaulth]^ _portendpoint<`C!i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q (i2cpclk  Zdefaultha+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U(spiclkapb_pclk4' ' 9txrxZdefaulthbcde+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V(spiclkapb_pclk4''9txrxZdefaulthfghij+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthkN disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthlNokay!pwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthmN disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S (pwmpclkZdefaulthnN disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthoN disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthpN disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthqN disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T (pwmpclkZdefaulthrN disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& (pclktimerdma-controller@ff240000arm,pl330arm,primecell$@Y (apb_pclkp!'tsadc@ff280000rockchip,px30-tsadc( ${,P,X(tsadcapb_pclk tsadc-apbr+Zinitdefaultsleephstsokay! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-W(saradcapb_pclk saradc-apbokay%@!nvmem@ff290000rockchip,px30-otp)@/Za(otpapb_pclkphyphy+id@7cpu-leakage@17performance@1e1clock-controller@ff2b0000rockchip,px30-cru+ u& (xin24mgpllr+68{@IFq рр !clock-controller@ff2bc000rockchip,px30-pmucru+u(xin24mr+6{&&& G!&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & (phyclk{Cv usb480m_phyokay!vhost-portZ D elinestateokay!yotg-portZ$BA@eotg-bvalidotg-idlinestateokay!xphy@ff2e0000rockchip,px30-dsi-dphy.& E (refpclk>apbZuw okay!Cphy@ff2f0000rockchip,px30-csi-dphy/@F(pclkZuw /apbr+okay!usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >(otgotg@ x "usb2-phyuwokayusb@ff340000 generic-ehci4 <y"usbuwokayusb@ff350000 generic-ohci5 =y"usbuwokayethernet@ff360000rockchip,px30-gmac6 +emacirq@>??@ACL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedr+rmiiZdefaulthz{uw ^ stmmacethokayoutputB _  PPmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD(biuciuciu-driveciu-sample!,рZdefaulth|}~uwokay:L] o|Ammc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF(biuciuciu-driveciu-sample!,рZdefault huw okayLmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH(biuciuciu-driveciu-sample!,рZdefault huw okay:B@spi@ff3a0000 rockchip,sfc:@ 8:(clk_sfchclk_sfc hZdefaultuw  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97(ahbnfc{7рZdefault huw  disabledopp-table-1operating-points-v2!opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- ejobmmugpuIuwokay!video-codec@ff442000rockchip,px30-vpuD PO evepuvdpu (aclkhclk uw iommu@ff442800rockchip,iommuD( Q (aclkiface uw !dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD(pclkC"dphyuw =apbr++okayports+port@0+endpoint@0<!endpoint@1<!port@1endpoint<!panel@0xinpeng,xpp055c272  %@ 2Xportendpoint<!vop@ff460000rockchip,px30-vop-bigF M(aclk_vopdclk_vophclk_vop345 axiahbdclk uw okayport+! endpoint@0<!endpoint@1<!Diommu@ff460f00rockchip,iommuF M (aclkifaceuw  okay!vop@ff470000rockchip,px30-vop-litG N(aclk_vopdclk_vophclk_vop789 axiahbdclk uw okayport+! endpoint@0<!endpoint@1<!Eiommu@ff470f00rockchip,iommuG N (aclkifaceuw  okay!isp@ff4a0000rockchip,px30-cif-ispJ$FIJ eispmimipi 3_(ispaclkhclkpclk "dphyuw okayports+port@0+endpoint@0C<!`iommu@ff4a8000rockchip,iommuJ F (aclkifaceuw  = okay!qos@ff518000rockchip,px30-qossysconQ !qos@ff520000rockchip,px30-qossysconR !$qos@ff52c000rockchip,px30-qossysconR !qos@ff538000rockchip,px30-qossysconS !qos@ff538080rockchip,px30-qossysconS !qos@ff538100rockchip,px30-qossysconS !qos@ff538180rockchip,px30-qossysconS !qos@ff540000rockchip,px30-qossysconT !qos@ff540080rockchip,px30-qossysconT !qos@ff548000rockchip,px30-qossysconT !qos@ff548080rockchip,px30-qossysconT ! qos@ff548100rockchip,px30-qossysconT !!qos@ff548180rockchip,px30-qossysconT !"qos@ff548200rockchip,px30-qossysconT !#qos@ff550000rockchip,px30-qossysconU !qos@ff550080rockchip,px30-qossysconU !qos@ff550100rockchip,px30-qossysconU !qos@ff550180rockchip,px30-qossysconU !qos@ff558000rockchip,px30-qossysconU !qos@ff558080rockchip,px30-qossysconU !pinctrlrockchip,px30-pinctrlr+ X+ egpio@ff040000rockchip,gpio-bank & l |!Sgpio@ff250000rockchip,gpio-bank% \ l |!gpio@ff260000rockchip,gpio-bank& ] l |!_gpio@ff270000rockchip,gpio-bank' ^ l |pcfg-pull-up !pcfg-pull-down !pcfg-pull-none !pcfg-pull-none-2ma  pcfg-pull-up-2ma  pcfg-pull-up-4ma  !pcfg-pull-none-4ma  pcfg-pull-down-4ma  pcfg-pull-none-8ma  !pcfg-pull-up-8ma  !pcfg-pull-none-12ma  !pcfg-pull-up-12ma  !pcfg-pull-none-smt  !pcfg-output-high pcfg-output-low !pcfg-input-high  !pcfg-input i2c0i2c0-xfer  !Ri2c1i2c1-xfer !Wi2c2i2c2-xfer !Yi2c3i2c3-xfer   !atsadctsadc-otp-pin !stsadc-otp-out !tuart0uart0-xfer  !(uart0-cts !)uart0-rts !*uart1uart1-xfer !Fuart1-cts !Guart1-rts uart2-m0uart2m0-xfer !Huart2-m1uart2m1-xfer  uart3-m0uart3m0-xfer uart3m0-cts uart3m0-rts uart3-m1uart3m1-xfer !Iuart3m1-cts  !Juart3m1-rts  !Kuart4uart4-xfer !Luart4-cts !Muart4-rts !Nuart5uart5-xfer !Ouart5-cts !Puart5-rts !Qspi0spi0-clk !bspi0-csn !cspi0-miso  !dspi0-mosi  !espi0-clk-hs spi0-miso-hs  spi0-mosi-hs  spi1spi1-clk !fspi1-csn0  !gspi1-csn1  !hspi1-miso !ispi1-mosi  !jspi1-clk-hs spi1-miso-hs spi1-mosi-hs  pdmpdm-clk0m0 pdm-clk0m1 pdm-clk1 pdm-sdi0m0 pdm-sdi0m1 pdm-sdi1 pdm-sdi2 pdm-sdi3 pdm-clk0m0-sleep pdm-clk0m1-sleep pdm-clk1-sleep pdm-sdi0m0-sleep pdm-sdi0m1-sleep pdm-sdi1-sleep pdm-sdi2-sleep pdm-sdi3-sleep i2s0i2s0-8ch-mclk i2s0-8ch-sclktx !,i2s0-8ch-sclkrx  !-i2s0-8ch-lrcktx !.i2s0-8ch-lrckrx  !/i2s0-8ch-sdo0 !0i2s0-8ch-sdo1 !2i2s0-8ch-sdo2 !4i2s0-8ch-sdo3 !6i2s0-8ch-sdi0 !1i2s0-8ch-sdi1  !3i2s0-8ch-sdi2  !5i2s0-8ch-sdi3 !7i2s1i2s1-2ch-mclk i2s1-2ch-sclk !8i2s1-2ch-lrck !9i2s1-2ch-sdi !:i2s1-2ch-sdo !;i2s2i2s2-2ch-mclk i2s2-2ch-sclk !<i2s2-2ch-lrck !=i2s2-2ch-sdi !>i2s2-2ch-sdo !?sdmmcsdmmc-clk !|sdmmc-cmd !}sdmmc-det !~sdmmc-bus1 sdmmc-bus4@ !sdiosdio-clk !sdio-cmd !sdio-bus4@ !emmcemmc-clk  !emmc-cmd  !emmc-rstnout  emmc-bus1 emmc-bus4@ emmc-bus8 !emmc-reset  !flashflash-cs0 !flash-rdy  !flash-dqs  !flash-ale  !flash-cle  !flash-wrn  !flash-csl flash-rdn !flash-bus8 !sfcsfc-bus4@ !sfc-bus2 sfc-cs0 !sfc-clk  !lcdclcdc-rgb-dclk-pin lcdc-rgb-m0-hsync-pin lcdc-rgb-m0-vsync-pin lcdc-rgb-m0-den-pin lcdc-rgb888-m0-data-pins      lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins      lcdc-rgb888-m1-data-pins    lcdc-rgb666-m1-data-pins    lcdc-rgb565-m1-data-pins    pwm0pwm0-pin !kpwm1pwm1-pin !lpwm2pwm2-pin  !mpwm3pwm3-pin !npwm4pwm4-pin !opwm5pwm5-pin !ppwm6pwm6-pin !qpwm7pwm7-pin !rgmacrmii-pins  !zmac-refclk-12ma  !{mac-refclk  cif-m0cif-clkout-m0  !]dvp-d2d9-m0    dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1 dvp-d2d9-m1   dvp-d0d1-m1 d10-d11-m1 ispisp-prelight headphonehp-det pmicpmic_int !Tsoc_slppin_gpio soc_slppin_slp soc_slppin_rst sdio-pwrseqwifi-enable-h !mipimipi-pdn !^chosen serial5:115200n8adc-keys adc-keys  buttons 0w@ Jdbutton-esc Xesc ^ i0button-home Xhome ^f i button-menu Xmenu ^ ixbutton-down Xvolume down ^r ibutton-up Xvolume up ^s iBhbacklightpwm-backlight a X!emmc-pwrseqmmc-pwrseq-emmchZdefault  !sdio-pwrseqmmc-pwrseq-simpleZdefaulth S!vccsysregulator-fixed vcc5v0_sys;OLK@LK@!U compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendgpiosvdd-supplymount-matrixirq-gpiosreset-gpiosVDDIO-supplyi2c-scl-falling-time-nsi2c-scl-rising-time-nsavdd-supplydvdd-supplydovdd-supplydata-lanes#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8vmali-supplyiommus#iommu-cellsbacklightiovcc-supplyvci-supplyrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpwmspower-supply