8h( m0:engicam,px30-core-ctouch2engicam,px30-corerockchip,px30 +7Engicam PX30.Core C.TOUCH 2.0aliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff370000/mmc@ff380000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ!cpu@1cpuarm,cortex-a35psciZ!cpu@2cpuarm,cortex-a35psciZ! cpu@3cpuarm,cortex-a35psciZ! idle-states)pscicpu-sleeparm,idle-state6G^xo!cluster-sleeparm,idle-state6G^o!opp-table-0operating-points-v2!opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal(>L^ tripstrip-point-0npzpassivetrip-point-1nLzpassive!soc-critn8z criticalcooling-mapsmap0 gpu-thermal(d>^ tripsgpu-thresholdnpzpassivegpu-targetnLzpassive!gpu-critn8z criticalcooling-mapsmap0 xin24m fixed-clockn6xin24m!lpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+!npower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+!io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&(baudclkapb_pclk4''9txrxCMZdefault h()* disabledi2s@ff060000rockchip,px30-i2s-tdm  (mclk_txmclk_rxhclk4''9txrxr+ tx-mrx-mZdefault0h,-./01234567 disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  (i2s_clki2s_hclk4''9txrxZdefaulth89:; disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s (i2s_clki2s_hclk4''9txrxZdefaulth<=>? disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+!+io-domains rockchip,px30-io-voltage-domainokay%%%%%@lvdsrockchip,px30-lvdsA"dphyr+,lvds disabledports+port@0+endpoint@0<B!endpoint@1<C!port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I(baudclkapb_pclk4''9txrxCMZdefault hDEF disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J(baudclkapb_pclk4''9txrxCMZdefaulthGokayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K(baudclkapb_pclk4''9txrxCMZdefault hHIJ disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L(baudclkapb_pclk4'' 9txrxCMZdefault hKLM disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M(baudclkapb_pclk4' ' 9txrxCMZdefault hNOP disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN (i2cpclk ZdefaulthQ+okaypmic@20rockchip,rk809  RZdefaulthSLmrk808-clkout1rk808-clkout2{TTTTUUUUTregulatorsDCDC_REG1vdd_log ~4pLqregulator-state-memay~DCDC_REG2vdd_arm ~4pLq!regulator-state-memy~DCDC_REG3vcc_ddr regulator-state-memaDCDC_REG4vcc_3v3 2Z42Z!%regulator-state-memay2ZDCDC_REG5 vcc3v3_sys 2Z42Z!Uregulator-state-memay2ZLDO_REG1vcc_1v0 B@4B@regulator-state-memayB@LDO_REG2vcc_1v8 w@4w@!@regulator-state-memayw@LDO_REG3vdd_1v0 B@4B@regulator-state-memayB@LDO_REG4 vcc3v0_pmu 2Z42Zregulator-state-memay2ZLDO_REG5 vccio_sd w@42Zregulator-state-memay2ZSWITCH_REG1  vcc3v3_lcdSWITCH_REG2 vcc5v0_host i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO (i2cpclk ZdefaulthV+ disabledi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP (i2cpclk  ZdefaulthW+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q (i2cpclk  ZdefaulthX+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U(spiclkapb_pclk4' ' 9txrxZdefaulthYZ[\+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V(spiclkapb_pclk4''9txrxZdefaulth]^_`a+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthbokaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthc disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthd disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S (pwmpclkZdefaulthe disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthf disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthg disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthh disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T (pwmpclkZdefaulthi disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& (pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ (apb_pclk!'tsadc@ff280000rockchip,px30-tsadc( $,P,X(tsadcapb_pclk tsadc-apbr+Zinitdefaultsleephjk!j+okayAX! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( Ts-W(saradcapb_pclk saradc-apb disablednvmem@ff290000rockchip,px30-otp)@/Za(otpapb_pclkphyphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ l& (xin24mgpllr+8@IFq рр !clock-controller@ff2bc000rockchip,px30-pmucru+l(xin24mr+&&& G!&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & (phyclkm usb480m_phyokay!mhost-port D linestateokay!potg-port$BA@otg-bvalidotg-idlinestateokay!ophy@ff2e0000rockchip,px30-dsi-dphy.& E (refpclk>apbn  disabled!Aphy@ff2f0000rockchip,px30-csi-dphy/@F(pclkn /apbr+ disabled!usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >(otgotg@ o "usb2-phynokayusb@ff340000 generic-ehci4 <p"usbnokayusb@ff350000 generic-ohci5 =p"usbnokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedr+rmiiZdefaulthqrn ^ stmmacethokayoutput%%0 FPP [s mmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD(biuciuciu-driveciu-samplekuрZdefaulthtuvwnokay %%mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF(biuciuciu-driveciu-samplekuрZdefault hxyzn okay+{wifi@1brcm,bcm4329-fmacmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH(biuciuciu-driveciu-samplekuрZdefault h|}~n okay&spi@ff3a0000 rockchip,sfc:@ 8:(clk_sfchclk_sfc hZdefaultn  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97(ahbnfc7рZdefault hn  disabledopp-table-1operating-points-v2!opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIn disabled!video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu (aclkhclk5n iommu@ff442800rockchip,iommuD( Q (aclkiface<n !dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD(pclkA"dphyn =apbr++ disabledports+port@0+endpoint@0<!endpoint@1<!port@1vop@ff460000rockchip,px30-vop-bigF M(aclk_vopdclk_vophclk_vop345 axiahbdclk5n  disabledport+! endpoint@0<!endpoint@1<!Biommu@ff460f00rockchip,iommuF M (aclkifacen < disabled!vop@ff470000rockchip,px30-vop-litG N(aclk_vopdclk_vophclk_vop789 axiahbdclk5n  disabledport+! endpoint@0<!endpoint@1<!Ciommu@ff470f00rockchip,iommuG N (aclkifacen < disabled!isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_(ispaclkhclkpclk5"dphyn  disabledports+port@0+iommu@ff4a8000rockchip,iommuJ F (aclkifacen I<!qos@ff518000rockchip,px30-qossysconQ !qos@ff520000rockchip,px30-qossysconR !$qos@ff52c000rockchip,px30-qossysconR !qos@ff538000rockchip,px30-qossysconS !qos@ff538080rockchip,px30-qossysconS !qos@ff538100rockchip,px30-qossysconS !qos@ff538180rockchip,px30-qossysconS !qos@ff540000rockchip,px30-qossysconT !qos@ff540080rockchip,px30-qossysconT !qos@ff548000rockchip,px30-qossysconT !qos@ff548080rockchip,px30-qossysconT ! qos@ff548100rockchip,px30-qossysconT !!qos@ff548180rockchip,px30-qossysconT !"qos@ff548200rockchip,px30-qossysconT !#qos@ff550000rockchip,px30-qossysconU !qos@ff550080rockchip,px30-qossysconU !qos@ff550100rockchip,px30-qossysconU !qos@ff550180rockchip,px30-qossysconU !qos@ff558000rockchip,px30-qossysconU !qos@ff558080rockchip,px30-qossysconU !pinctrlrockchip,px30-pinctrlr+d+qgpio@ff040000rockchip,gpio-bank &x!Rgpio@ff250000rockchip,gpio-bank% \x!gpio@ff260000rockchip,gpio-bank& ]x!sgpio@ff270000rockchip,gpio-bank' ^xpcfg-pull-up!pcfg-pull-downpcfg-pull-none!pcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4ma!pcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8ma!pcfg-pull-up-8ma!pcfg-pull-none-12ma !pcfg-pull-up-12ma !pcfg-pull-none-smt!pcfg-output-highpcfg-output-lowpcfg-input-high!pcfg-inputi2c0i2c0-xfer  !Qi2c1i2c1-xfer !Vi2c2i2c2-xfer !Wi2c3i2c3-xfer   !Xtsadctsadc-otp-pin !jtsadc-otp-out !kuart0uart0-xfer   !(uart0-cts  !)uart0-rts  !*uart1uart1-xfer !Duart1-cts !Euart1-rts !Fuart2-m0uart2m0-xfer uart2-m1uart2m1-xfer  !Guart3-m0uart3m0-xfer uart3m0-cts uart3m0-rts uart3-m1uart3m1-xfer !Huart3m1-cts  !Iuart3m1-rts  !Juart4uart4-xfer !Kuart4-cts !Luart4-rts !Muart5uart5-xfer !Nuart5-cts !Ouart5-rts !Pspi0spi0-clk !Yspi0-csn !Zspi0-miso  ![spi0-mosi  !\spi0-clk-hs spi0-miso-hs  spi0-mosi-hs  spi1spi1-clk !]spi1-csn0  !^spi1-csn1  !_spi1-miso !`spi1-mosi  !aspi1-clk-hs spi1-miso-hs spi1-mosi-hs  pdmpdm-clk0m0 pdm-clk0m1 pdm-clk1 pdm-sdi0m0 pdm-sdi0m1 pdm-sdi1 pdm-sdi2 pdm-sdi3 pdm-clk0m0-sleep pdm-clk0m1-sleep pdm-clk1-sleep pdm-sdi0m0-sleep pdm-sdi0m1-sleep pdm-sdi1-sleep pdm-sdi2-sleep pdm-sdi3-sleep i2s0i2s0-8ch-mclk i2s0-8ch-sclktx !,i2s0-8ch-sclkrx  !-i2s0-8ch-lrcktx !.i2s0-8ch-lrckrx  !/i2s0-8ch-sdo0 !0i2s0-8ch-sdo1 !2i2s0-8ch-sdo2 !4i2s0-8ch-sdo3 !6i2s0-8ch-sdi0 !1i2s0-8ch-sdi1  !3i2s0-8ch-sdi2  !5i2s0-8ch-sdi3 !7i2s1i2s1-2ch-mclk i2s1-2ch-sclk !8i2s1-2ch-lrck !9i2s1-2ch-sdi !:i2s1-2ch-sdo !;i2s2i2s2-2ch-mclk i2s2-2ch-sclk !<i2s2-2ch-lrck !=i2s2-2ch-sdi !>i2s2-2ch-sdo !?sdmmcsdmmc-clk !tsdmmc-cmd !usdmmc-det !vsdmmc-bus1 sdmmc-bus4@ !wsdiosdio-clk !zsdio-cmd !ysdio-bus4@ !xemmcemmc-clk  !|emmc-cmd  !}emmc-rstnout  emmc-bus1 emmc-bus4@ emmc-bus8 !~flashflash-cs0 !flash-rdy  !flash-dqs  !flash-ale  !flash-cle  !flash-wrn  !flash-csl flash-rdn !flash-bus8 !sfcsfc-bus4@ !sfc-bus2 sfc-cs0 !sfc-clk  !lcdclcdc-rgb-dclk-pin lcdc-rgb-m0-hsync-pin lcdc-rgb-m0-vsync-pin lcdc-rgb-m0-den-pin lcdc-rgb888-m0-data-pins      lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins      lcdc-rgb888-m1-data-pins    lcdc-rgb666-m1-data-pins    lcdc-rgb565-m1-data-pins    pwm0pwm0-pin !bpwm1pwm1-pin !cpwm2pwm2-pin  !dpwm3pwm3-pin !epwm4pwm4-pin !fpwm5pwm5-pin !gpwm6pwm6-pin !hpwm7pwm7-pin !igmacrmii-pins  !qmac-refclk-12ma  !rmac-refclk  cif-m0cif-clkout-m0  dvp-d2d9-m0    dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1 dvp-d2d9-m1   dvp-d0d1-m1 d10-d11-m1 ispisp-prelight btbt-enable-h !sdio-pwrseqwifi-enable-h !pmicpmic_int !Svcc5v0-sysregulator-fixed vcc5v0_sys LK@4LK@!Tsdio-pwrseqmmc-pwrseq-simple (ext_clock PZdefaulth *!{vcc3v3-btregregulator-gpio 6Zdefaulthbtreg-gpio-supply2Z42Z2Z Ivcc3v3-rf-aux-modregulator-fixedvcc3v3_rf_aux_mod2Z42Z  VTxin32k fixed-clockxin32k!chosen aserial2:115200n8 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc1mmc2mmc0device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspend#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsbits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiobus-widthfifo-depthmax-frequencycap-sd-highspeedcard-detect-delayvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104cap-mmc-highspeedmmc-hs200-1_8viommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinspost-power-on-delay-msreset-gpiosenable-active-highenable-gpiosvin-supplystdout-path