}}8vD(9v  (,Qualcomm Technologies, Inc. QRU1000 IDP2qcom,qru1000-idpqcom,qru1000 =embeddedchosenJserial0:115200n8cpus cpu@0Vcpu2arm,cortex-a55bfmpsci{psci l2-cache2cachel3-cache2cachecpu@100Vcpu2arm,cortex-a55bfmpsci{psci l2-cache2cachecpu@200Vcpu2arm,cortex-a55bfmpsci{psci l2-cache2cache cpu@300Vcpu2arm,cortex-a55bfmpsci{ psci l2-cache2cache cpu-mapcluster0core0 core1 core2core3idle-statespscicpu-sleep-02arm,idle-state^$@;domain-idle-statescluster-sleep-02domain-idle-stateH $ADcluster-sleep-12domain-idle-state M'$A3Dfirmwarescm2qcom,scm-qdu1000qcom,scminterconnect-02qcom,qdu1000-mc-virtL\Hinterconnect-12qcom,qdu1000-clk-virtL\memory@80000000Vmemorybpmu2arm,armv8-pmuv3 ppsci 2arm,psci-1.0tsmcpower-domain-cpu0{{power-domain-cpu1{{power-domain-cpu2{{power-domain-cpu3{{ power-domain-cluster{reserved-memory hyp@80000000b`xbl-dt-log@80600000b`xbl-ramdump@80640000bdaop-image@80800000baop-cmd-db@80860000 2qcom,cmd-dbbaop-config@80880000btme-crash-dump@808a0000btme-log@808e0000b@uefi-log@808e4000b@smem@80900000 2qcom,smemb cpucp-fw@80b00000bmemory@80c00000btz-stat@81d00000btags@81e00000bPqtee@82300000b0Pta@82800000bfs1@83200000b @fs2@83600000b`@fs3@83a00000b@ipa-fw@8be00000bipa-gsi@8be10000b@mpss@8c000000bq6-mpss-dtb@9ec00000bipa-buffer@c3200000b oem-tenx@a0000000b@mpss-diag-buffer@aea00000b@tenx-q6-buffer@b4e00000b ecc-meta-data@f0000000btenx-sp-buffer@800000000bsoc@0 2simple-bus clock-controller@800002qcom,qdu1000-gccbBf{dma-controller@900000)2qcom,qdu1000-gpi-dmaqcom,sm6350-gpi-dmabp ? geniqup@9c00002qcom,geni-se-qupb fZ[  m-ahbs-ahb  'qup-core :okayserial@9800002qcom,geni-uartb@f8 seAKdefault pY :disabledi2c@9840002qcom,geni-i2cb@@f: se pZAKdefault  :disabledspi@9840002qcom,geni-spib@@  pZf: seAKdefault :disabledi2c@9880002qcom,geni-i2cb@f< se p[AKdefault  :disabledspi@9880002qcom,geni-spib@  p[f< seA !Kdefault :disabledi2c@98c0002qcom,geni-i2cb@f> se p\A"Kdefault  :disabledspi@98c0002qcom,geni-spib@  p\f> seA#$Kdefault :disabledi2c@9900002qcom,geni-i2cb@f@ se p]A%Kdefault  :disabledspi@9900002qcom,geni-spib@  p]f@ seA&'Kdefault :disabledi2c@9940002qcom,geni-i2cb@@fB se p^A(Kdefault  :disabledspi@9940002qcom,geni-spib@@  p^fB seA)*Kdefault :disabledi2c@9980002qcom,geni-i2cb@fD se p_A+Kdefault  :disabledspi@9980002qcom,geni-spib@  p_fD seA,-Kdefault :disabledserial@99c0002qcom,geni-debug-uartb@fF seA./Kdefault p`:okaydma-controller@a00000)2qcom,qdu1000-gpi-dmaqcom,sm6350-gpi-dmabp%&'()* ? geniqup@ac00002qcom,geni-se-qupb f\]  m-ahbs-ahb   :disabledserial@a800002qcom,geni-uartb@fJ seA0Kdefault pa  :disabledi2c@a840002qcom,geni-i2cb@@fL se pbA1Kdefault  :disabledspi@a840002qcom,geni-spib@@  pbfL seA23Kdefault :disabledi2c@a880002qcom,geni-i2cb@fN se pcA4Kdefault  :disabledspi@a880002qcom,geni-spib@  pcfN seA56Kdefault :disabledi2c@a8c0002qcom,geni-i2cb@fP se pdA7Kdefault  :disabledspi@a8c0002qcom,geni-spib@  pdfP seA89Kdefault :disabledi2c@a900002qcom,geni-i2cb@fR se peA:Kdefault  :disabledspi@a900002qcom,geni-spib@  pefR seA;<Kdefault :disabledi2c@a940002qcom,geni-i2cb@@fT se pfA=Kdefault  :disabledserial@a940002qcom,geni-uartb@@fT seA>Kdefault pf  :disabledspi@a940002qcom,geni-spib@@  pffT seA?@Kdefault :disabledi2c@a980002qcom,geni-i2cb@fV se pkAAKdefault  :disabledspi@a980002qcom,geni-spib@  pkfV seABCKdefault :disabledi2c@a9c0002qcom,geni-i2cb@fX se pmADKdefault  :disabledspi@a9c0002qcom,geni-spib@  pmfX seAEFKdefault :disabledinterconnect@16400002qcom,qdu1000-system-nocbdPL\Ghwlock@1f400002qcom,tcsr-mutexbYmmc@8804000%2qcom,qdu1000-sdhciqcom,sdhci-msm-v5 b@P ghccqhcipqhc_irqpwr_irqf^_ ifacecorexo0GHIG,'sdhc-ddrcpu-sdhc{JK d,Àh :disabledopp-table2operating-points-v2Kopp-384000000`Lc8@interrupt-controller@b2200002qcom,qdu1000-pdcqcom,pdc b "@d< (6^a}?$Mspmi@c4000002qcom,spmi-pmic-arbPb @0 P@ D L B@gcorechnlsobsrvrintrcnfg 9M qperiph_irqMU $pmic@02qcom,pm8150qcom,spmi-pmicb pon@8002qcom,pm8998-ponbbrpwrkey2qcom,pm8941-pwrkeyp= t :disabledresin2qcom,pm8941-resinp=  :disabledtemp-alarm@24002qcom,spmi-temp-alarmb$p$NthermalWadc@31002qcom,spmi-adc5b1 p1Nchannel@0bref_gndchannel@1b vref_1p25channel@6b die_tempadc-tm@35002qcom,spmi-adc-tm5b5p5  :disabledrtc@60002qcom,pm8941-rtcb`a grtcalarmpagpio@c000 2qcom,pm8150-gpioqcom,spmi-gpiob O $Opmic@12qcom,pm8150qcom,spmi-pmicb pinctrl@f0000002qcom,qdu1000-tlmmb p$ P%M3Pqup-uart0-default-stateHgpio6gpio7gpio8gpio9Mqup00qup-i2c1-data-clk-stateHgpio10gpio11Mqup01Vqup-spi1-data-clk-stateHgpio10gpio11gpio12Mqup01Vequp-spi1-cs-stateHgpio13MgpioVequp-i2c2-data-clk-stateHgpio12gpio13Mqup02Vqup-spi2-data-clk-stateHgpio12gpio13gpio10Mqup02Ve qup-spi2-cs-stateHgpio11MgpioVe!qup-i2c3-data-clk-stateHgpio14gpio15Mqup03V"qup-spi3-data-clk-stateHgpio14gpio15gpio16Mqup03Ve#qup-spi3-cs-stateHgpio17MgpioVe$qup-i2c4-data-clk-stateHgpio16gpio17Mqup04V%qup-spi4-data-clk-stateHgpio16gpio17gpio14Mqup04Ve&qup-spi4-cs-stateHgpio15MgpioVe'qup-i2c5-data-clk-stateHgpio130gpio131Mqup05V(qup-spi5-data-clk-stateHgpio130gpio131gpio132Mqup05Ve)qup-spi5-cs-stateHgpio133MgpioVe*qup-i2c6-data-clk-stateHgpio132gpio133Mqup06V+qup-spi6-data-clk-stateHgpio132gpio133gpio130Mqup06Ve,qup-spi6-cs-stateHgpio131MgpioVe-qup-uart7-rx-stateHgpio135Mqup07Ve/qup-uart7-tx-stateHgpio134Mqup07Ve.qup-uart8-default-stateHgpio18gpio19gpio20gpio21Mqup100qup-i2c9-data-clk-stateHgpio22gpio23Mqup11V1qup-spi9-data-clk-stateHgpio22gpio23gpio24Mqup11Ve2qup-spi9-cs-stateHgpio25MgpioVe3qup-i2c10-data-clk-stateHgpio24gpio25Mqup12V4qup-spi10-data-clk-stateHgpio24gpio25gpio22Mqup12Ve5qup-spi10-cs-stateHgpio23MgpioVe6qup-i2c11-data-clk-stateHgpio26gpio27Mqup13V7qup-spi11-data-clk-stateHgpio26gpio27gpio28Mqup13Ve8qup-spi11-cs-stateHgpio29MgpioVe9qup-i2c12-data-clk-stateHgpio28gpio29Mqup14V:qup-spi12-data-clk-stateHgpio28gpio29gpio26Mqup14Ve;qup-spi12-cs-stateHgpio27MgpioVe<qup-i2c13-data-clk-stateHgpio30gpio31Mqup15V=qup-spi13-data-clk-stateHgpio30gpio31gpio32Mqup15Ve?qup-spi13-cs-stateHgpio33MgpioVe@qup-uart13-default-stateHgpio30gpio31gpio32gpio33Mqup15>qup-i2c14-data-clk-stateHgpio34gpio35Mqup16VAqup-spi14-data-clk-stateHgpio34gpio35gpio36Mqup16VeBqup-spi14-cs-stateHgpio37gpio38MgpioVeCqup-i2c15-data-clk-stateHgpio40gpio41Mqup17VDqup-spi15-data-clk-stateHgpio40gpio41gpio30Mqup17VeEqup-spi15-cs-stateHgpio31MgpioVeFsdc-on-stateclk-pins Hsdc1_clkVecmd-pins Hsdc1_cmdV data-pins Hsdc1_dataV rclk-pins Hsdc1_rclkrsdc-off-stateclk-pins Hsdc1_clkVecmd-pins Hsdc1_cmdVdata-pins Hsdc1_dataVrclk-pins Hsdc1_rclkrsram@14680000$2qcom,qdu1000-imemsysconsimple-mfdbhh pil-reloc@94c2qcom,pil-reloc-infob Liommu@1500000002qcom,qdu1000-smmu-500qcom,smmu-500arm,mmu-500bLpAI^_`abcdefghijklmnopqrstuv;<=>?@Ainterrupt-controller@17200000 2arm,gic-v3 b & p $timer@174200002arm,armv7-timer-membB  frame@17421000bBB pframe@17423000bB0 p  :disabledframe@17425000bBPB` p  :disabledframe@17427000bBp p  :disabledframe@17429000bB p  :disabledframe@1742b000bB p  :disabledframe@1742d000bB p :disabledrsc@17a000002qcom,rpmh-rsc0bgdrv-0drv-1drv-2$p   apps_rsc{bcm-voter2qcom,bcm-voterclock-controller2qcom,qdu1000-rpmh-clkfQ xopower-controller2qcom,qdu1000-rpmhpd{RJopp-table2operating-points-v2Ropp1opp20opp3@opp4opp5opp6Lopp7@opp8Popp9opp10regulators2qcom,pm8150-rpmh-regulatorsaS+S9SGSUScSqSSSSTSUTVSsmps2 +vreg_s2a_0p5:Rsmps3+vreg_s3a_1p05:~RPsmps4 +vreg_s4a_1p8:w@Rw@Vsmps5 +vreg_s5a_2p0: RUsmps6 +vreg_s6a_0p9: R6@Tsmps7 +vreg_s7a_1p2:OROsmps8 +vreg_s8a_1p3:@R@ldo1+vreg_l1a_0p91:Rjldo2 +vreg_l2a_2p3:-QR2Zjldo3 +vreg_l3a_1p2: R9jldo5 +vreg_l5a_0p8:Rjldo6+vreg_l6a_0p91: mR~jldo7 +vreg_l7a_1p8:-PRjldo8+vreg_l8a_0p91: RHjldo9+vreg_l9a_0p91:Rjldo10+vreg_l10a_2p95:)2R6jldo11+vreg_l11a_0p91: 5RB@jldo12+vreg_l12a_1p8:Rjldo14+vreg_l14a_1p8:-PR0jldo15+vreg_l15a_1p8:Rjldo16+vreg_l16a_1p8:Rjldo17+vreg_l17a_3p3:-R6jldo18+vreg_l18a_1p2:Rjcpufreq@17d90000,2qcom,qdu1000-cpufreq-epssqcom,cpufreq-epss bgfreq-domain0freq-domain1f  xoalternateinterconnect@191000002qcom,qdu1000-gem-nocb L\Isystem-cache-controller@192000002qcom,qdu1000-llcc0b  "(5gllcc_basellcc_broadcast_basemulti_channel_register p timer2arm,armv8-timer<p    thermal-zonespm8150-thermaldWtripstrip0sEpassivetrip18Ehottrip26h Ecriticalaliases$/soc@0/geniqup@9c0000/serial@99c000clocksxo-board-clk 2fixed-clock$Qsleep-clk 2fixed-clock}ppvar-sys-regulator2regulator-fixed +ppvar_sys:@@R@@Xvph-pwr-regulator2regulator-fixed+vph_pwr:8u R8u .XS interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typestdout-pathdevice_typeregclocksenable-methodpower-domainspower-domain-namesqcom,freq-domainsnext-level-cachephandlecache-levelcache-unifiedcpuentry-methodentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramlocal-timer-stopqcom,bcm-voters#interconnect-cellsinterrupts#power-domain-cellsdomain-idle-statesrangesno-maphwlocksdma-ranges#clock-cells#reset-cellsdma-channelsdma-channel-maskiommus#dma-cellsclock-namesinterconnectsinterconnect-namesstatuspinctrl-0pinctrl-names#hwlock-cellsreg-namesinterrupt-namesresetsoperating-points-v2dma-coherentbus-widthqcom,dll-configqcom,ddr-configopp-hzrequired-oppsopp-peak-kBpsopp-avg-kBpsqcom,pdc-ranges#interrupt-cellsinterrupt-controllerinterrupts-extendedqcom,eeqcom,channelmode-bootloadermode-recoverydebouncebias-pull-uplinux,codeio-channelsio-channel-names#thermal-sensor-cells#io-channel-cellsqcom,pre-scalinglabelgpio-controllergpio-ranges#gpio-cellswakeup-parentgpio-reserved-rangespinsfunctiondrive-strengthbias-disablebias-pull-down#iommu-cells#global-interrupts#redistributor-regionsredistributor-strideframe-numberqcom,tcs-offsetqcom,drv-idqcom,tcs-configopp-levelqcom,pmic-idvdd-s1-supplyvdd-s2-supplyvdd-s3-supplyvdd-s4-supplyvdd-s5-supplyvdd-s6-supplyvdd-s7-supplyvdd-s8-supplyvdd-s9-supplyvdd-s10-supplyvdd-l1-l8-l11-supplyvdd-l2-l10-supplyvdd-l3-l4-l5-l18-supplyvdd-l6-l9-supplyvdd-l7-l12-l14-l15-supplyvdd-l13-l16-l17-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-mode#freq-domain-cellsmulti-ch-bit-offpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisserial0clock-frequencyregulator-always-onregulator-boot-onvin-supply