#g8 D(#  +,Qualcomm Technologies, Inc. IPQ5332 MI01.3$2qcom,ipq5332-ap-mi01.3qcom,ipq5332clockssleep-clk 2fixed-clock=J}Z xo-board-clk 2fixed-clock=Jn6Z cpus cpu@0bcpu2arm,cortex-a53nrpscicpu@1bcpu2arm,cortex-a53nrpscicpu@2bcpu2arm,cortex-a53nrpscicpu@3bcpu2arm,cortex-a53nrpscil2-cache2cacheZfirmwarescm2qcom,scm-ipq5332qcom,scmamemory@40000000bmemoryn@opp-table-cpu2operating-points-v2Zopp-1488000000X @pmu2arm,cortex-a53-pmu psci 2arm,psci-1.0ysmcreserved-memory bootloader@4a100000nJ@ sbl@4a500000nJP tz@4a600000nJ`  smem@4a800000 2qcom,smemnJ soc@0 2simple-bus efuse@a4000 2qcom,ipq5332-qfpromqcom,qfpromn @! rng@e3000 2qcom,prng-een0Ycorepinctrl@10000002qcom,ipq5332-tlmmn0 &6B5NcZserial0-statetgpio18gpio19 yblsp0_uart0Z gpio-keys-default-statetgpio35ygpioZgpio-leds-default-statetgpio36ygpioZi2c-1-statetgpio29gpio30 yblsp1_i2c0Zsdc-default-stateZ clk-pinstgpio13ysdc_clkcmd-pinstgpio12ysdc_cmddata-pinstgpio8gpio9gpio10gpio11 ysdc_dataspi-0-data-clk-statetgpio14gpio15gpio16 yblsp0_spiZspi-0-cs-statetgpio17 yblsp0_spiZclock-controller@18000002qcom,ipq5332-gccn= Zhwlock@19050002qcom,tcsr-mutexnPZsyscon@19370002qcom,tcsr-ipq5332sysconnpZmmc@7804000%2qcom,ipq5332-sdhciqcom,sdhci-msm-v5n@P9<hc_irqpwr_irqqr ifacecorexookay q%4B Ldefaultdma-controller@78840002qcom,bam-v1.7.0n@ ! bam_clkZeZ serial@78af000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmn "  coreifaceokayB Ldefaultserial@78b0000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmn #  coreifacem  rtxrx disabledspi@78b50002qcom,spi-qup-v2.2.1nP  $   coreifacem  rtxrxokayBLdefaultflash@0 2micron,n25q128a11jedec,spi-norn |i2c@78b60002qcom,i2c-qup-v2.2.1n`  %  coreifacem  rtxrxokayJBLdefaultspi@78b70002qcom,spi-qup-v2.2.1np  &  coreifacem  rtxrx disabledinterrupt-controller@b0000002qcom,msm-qgic2 n    @  Nc   0Zv2m@02arm,gic-v2m-framenv2m@10002arm,gic-v2m-framenv2m@20002arm,gic-v2m-framen watchdog@b017000$2qcom,apss-wdt-ipq5332qcom,kpss-wdtn p  mailbox@b111000<2qcom,ipq5332-apcs-apps-globalqcom,ipq6018-apcs-apps-globaln = pllxoZclock@b1160002qcom,ipq5332-a53plln `@= xoZtimer@b1200002arm,armv7-timer-memn  frame@b120000n   frame@b123000n 0  disabledframe@b124000n @  disabledframe@b125000n P  disabledframe@b126000n `  disabledframe@b127000n p  disabledframe@b128000n   disabledtimer2arm,armv8-timer0aliases/soc@0/serial@78af000chosenserial0gpio-keys 2gpio-keysBLdefaultbutton-wpswps #<leds 2gpio-ledsBLdefaultled-0 $phy0txoff interrupt-parent#address-cells#size-cellsmodelcompatible#clock-cellsclock-frequencyphandledevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cache-levelcache-unifiedqcom,dload-modeopp-sharedopp-hzclock-latency-nsinterruptsrangesno-maphwlocksclock-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-upbias-pull-downbias-disable#reset-cells#power-domain-cells#hwlock-cellsinterrupt-namesstatusbus-widthmax-frequencymmc-ddr-1_8vmmc-hs200-1_8vnon-removablepinctrl-0pinctrl-names#dma-cellsqcom,eedmasdma-namesspi-max-frequencymsi-controllertimeout-sec#mbox-cellsframe-numberserial0stdout-pathlabellinux,codegpiosdebounce-intervallinux,default-triggerdefault-state