.8+8(+"amd,seattle-overdriveamd,seattle +37AMD Seattle (Rev.B0) Development Board (Overdrive)interrupt-controller@e1101000arm,gic-400arm,cortex-a15-gic=R+@c    g ryv2m@e0080000arm,gic-v2m-framecytimerarm,armv8-timer0g   smb simple-bus+rclk100mhz_0 fixed-clockadl3clk_100mhzclk375mhz fixed-clockZ ccpclk_375mhzclk333mhz fixed-clock-@sataclk_333mhzyclk500mhz_0 fixed-clockepcieclk_500mhzclk500mhz_1 fixed-clockedmaclk_500mhzclk250mhz_4 fixed-clock沀miscclk_250mhzyclk100mhz_1 fixed-clockuartspiclk_100mhzysata@e0300000snps,dwc-ahcic0 gc sata@e0d00000 disabledsnps,dwc-ahcic gbiommu@e0200000 arm,mmu-401c gLLyiommu@e0c00000 arm,mmu-401cgKKyi2c@e1000000okaysnps,designware-i2cc gei2c@e0050000okaysnps,designware-i2cc gTserial@e1010000arm,pl011arm,primecellc gH uartclkapb_pclkspi@e1020000okayarm,pl022arm,primecellc gJ  apb_pclkspi@e1030000okayarm,pl022arm,primecellc gI  apb_pclk(+sdcard@0 mmc-spi-slotc/1-A HP`pgpio@e1040000 disabledarm,pl061arm,primecellc gg=R  apb_pclkgpio@e1050000okayarm,pl061arm,primecellc=R gf  apb_pclkgpio@e0020000 disabledarm,pl061arm,primecellc=R gn  apb_pclkgpio@e0030000 disabledarm,pl061arm,primecellc=R gm  apb_pclkgpio@e0080000okayarm,pl061arm,primecellc=R gi  apb_pclkccp@e0100000okayamd,ccp-seattle-v1ac g @Bpcie@f0000000pci-host-ecam-generic+Rpcic !"#$%&'()*+CTr@@okayiommu@e0a00000 arm,mmu-401cgMMyccn@e8000000 arm,ccn-504c g|kcs@e0010000 disabled ipmi-kcsipmic g )clk250mhz_0 fixed-clock沀xgmacclk0_dma_250mhzy clk250mhz_1 fixed-clock沀xgmacclk0_ptp_250mhzy clk250mhz_2 fixed-clock沀xgmacclk1_dma_250mhzy clk250mhz_3 fixed-clock沀xgmacclk1_ptp_250mhzy xgmac@e0700000amd,xgbe-seattle-v1aPcpx$%`%HgEZ[\]C5O ] m       dma_clkptp_clkxgmii xgmac@e0900000amd,xgbe-seattle-v1aPc$ %`%HgDUVWXB5O ] m       dma_clkptp_clkxgmii iommu@e0600000 arm,mmu-401c`gPPy iommu@e0800000 arm,mmu-401cgOOycpus+cpu-mapcluster0core0core1cluster1core0core1cluster2core0core1cluster3core0core1cpu@0cpuarm,cortex-a57cpsci@ -:@LYycpu@1cpuarm,cortex-a57cpsci@ -:@LYycpu@100cpuarm,cortex-a57cpsci@ -:@LYycpu@101cpuarm,cortex-a57cpsci@ -:@LYycpu@200cpuarm,cortex-a57cpsci@ -:@LYycpu@201cpuarm,cortex-a57cpsci@ -:@LYycpu@300cpuarm,cortex-a57cpsci@ -:@LYycpu@301cpuarm,cortex-a57cpsci@ -:@LYyl2-cache0@"bpyl2-cache1@"bpyl2-cache2@"bpyl2-cache3@"bpyl3-cache@" bypmuarm,cortex-a57-pmu`g      chosen/smb/serial@e1010000psci arm,psci-0.2smc compatibleinterrupt-parent#address-cells#size-cellsmodelinterrupt-controller#interrupt-cellsreginterruptsrangesphandlemsi-controllerdma-ranges#clock-cellsclock-frequencyclock-output-namesclocksiommusdma-coherentstatus#global-interrupts#iommu-cellsclock-namesspi-controllernum-csspi-max-frequencyvoltage-rangespl022,hierarchypl022,interfacepl022,com-modepl022,rx-level-trigpl022,tx-level-trig#gpio-cellsgpio-controlleramd,zlib-supportdevice_typebus-rangemsi-parentinterrupt-map-maskinterrupt-mapiommu-mapreg-sizereg-spacingamd,per-channel-interruptamd,speed-setamd,serdes-blwcamd,serdes-cdr-rateamd,serdes-pq-skewamd,serdes-tx-ampamd,serdes-dfe-tap-configamd,serdes-dfe-tap-enablemac-addressphy-modecpuenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsl2-cachecache-unifiednext-level-cachecache-levelinterrupt-affinitystdout-path