bc8[([.rockchip,px5-evbrockchip,px5rockchip,rk3368 +7Rockchip PX5 EVBaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53pscibus simple-bus+dma-controller@ff250000arm,pl330arm,primecell%@ $  +apb_pclkdma-controller@ff600000arm,pl330arm,primecell`@ $  +apb_pclk9arm-pmuarm,armv8-pmuv3`pqrstuvw 7 psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockJn6Zxin24mmmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @zр $  D r v+biuciuciu-driveciu-sample  resetokaydefault &ZDPmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @zр $  E s w+biuciuciu-driveciu-sample ! reset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@zр $  G u y+biuciuciu-driveciu-sample # resetokayJр]lrdefault DPsaradc@ff100000rockchip,saradc $$ I [+saradcapb_pclk W saradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi$ A R+spiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi$ B S+spiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi$ C T+spiclkapb_pclk )default !+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >++i2c$ Ndefault"okaytouchscreen@40silead,gsl1680@ # # i2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?++i2c$ Odefault$ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @++i2c$ Pdefault% disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A++i2c$ Qdefault& disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ M U+baudclkapb_pclk 7 disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ N V+baudclkapb_pclk 8 disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ P X+baudclkapb_pclk : disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ Q Y+baudclkapb_pclk ;okaythermal-zonescpud'tripscpu_alert0"$.passive(cpu_alert1"8.passive)cpu_crit"s. criticalcooling-mapsmap09(0>map19)0> gpud'tripsgpu_alert0"8.passive*gpu_crit"8. criticalcooling-mapsmap09*0>tsadc@ff280000rockchip,rk3368-tsadc( %$ H Z+tsadcapb_pclk  tsadc-apbinitdefaultsleep+M,W+awsokay'ethernet@ff290000rockchip,rk3368-gmac) macirq-8$  f g c ]M+stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac disabledusb@ff500000 generic-ehciP $ okayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X $ +otgotg@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce$ L+i2c <default.+okaypmic@1brockchip,rk808 /default0162B2N2Z2f2r2~222Zxin32krk808-clkout2mregulatorsDCDC_REG1 ``vdd_cpuDCDC_REG2 ``vdd_logDCDC_REG3vcc_ddrDCDC_REG42Z2Zvcc_ioLDO_REG1w@w@ vcc18_flashLDO_REG22Z2Zvcca_33LDO_REG3B@B@vdd_10LDO_REG42Z2Zavdd_33LDO_REG5w@2Z vccio_sdLDO_REG6B@B@ vdd10_lcdLDO_REG7w@w@vcc_18LDO_REG8w@w@ vcc18_lcdSWITCH_REG1vcc_sdSWITCH_REG2 vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =++i2c$ Mdefault3okayaccelerometer@18 bosch,bma250 4pwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmh"default5$ _+pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmh"default6$ _+pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh "$ _+pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0"default7$ _+pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti$ O W+baudclkapb_pclk 9default8 disabledmbox@ff6b0000rockchip,rk3368-mailboxk0$ E +pclk_mailbox- disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfds<io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-mode9@RBLRBZRB jRBclock-controller@ff760000rockchip,rk3368-cruv-mv syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt$ p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  Bspdif@ff880000rockchip,rk3368-spdif 6$ S  +mclkhclk9txdefault: disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (+i2s_clki2s_hclk$ T 99txrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5+i2s_clki2s_hclk$ R 99txrxdefault; disablediommu@ff900800rockchip,iommu iep_mmu$  +aclkiface disablediommu@ff914000rockchip,iommu @P isp_mmu$  +aclkiface disablediommu@ff930300rockchip,iommu vop_mmu$  +aclkiface disablediommu@ff9a0440rockchip,iommu @@@  hevc_mmu$  +aclkiface disablediommu@ff9a0800rockchip,iommu  vepu_mmuvdpu_mmu$  +aclkiface disabledefuse@ffb00000rockchip,rk3368-efuse +$ q +pclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl-<+gpio0@ff750000rockchip,gpio-banku$ @ Q/gpio1@ff780000rockchip,gpio-bankx$ A Rgpio2@ff790000rockchip,gpio-banky$ B S4gpio3@ff7a0000rockchip,gpio-bankz$ C T#pcfg-pull-up>pcfg-pull-down'pcfg-pull-none6=pcfg-pull-none-12ma6C ?emmcemmc-clkR=emmc-cmdR>emmc-pwrR>emmc-bus1R>emmc-bus4@R>>>>emmc-bus8R>>>>>>>>gmacrgmii-pinsR===? ? ??? ?======rmii-pinsR===? ? ?====i2c0i2c0-xfer R==.i2c1i2c1-xfer R==3i2c2i2c2-xfer R =="i2c3i2c3-xfer R==$i2c4i2c4-xfer R==%i2c5i2c5-xfer R==&i2si2s-8ch-busR = ========;pwm0pwm0-pinR=5pwm1pwm1-pinR=6pwm3pwm3-pinR=7sdio0sdio0-bus1R>sdio0-bus4@R>>>>sdio0-cmdR>sdio0-clkR=sdio0-cdR>sdio0-wpR>sdio0-pwrR>sdio0-bkpwrR>sdio0-intR>sdmmcsdmmc-clkR = sdmmc-cmdR > sdmmc-cdR >sdmmc-bus1R>sdmmc-bus4@R>>>> spdifspdif-txR=:spi0spi0-clkR>spi0-cs0R>spi0-cs1R>spi0-txR>spi0-rxR>spi1spi1-clkR>spi1-cs0R>spi1-cs1R>spi1-rxR>spi1-txR>spi2spi2-clkR >spi2-cs0R >!spi2-rxR > spi2-txR >tsadcotp-pinR=+otp-outR=,uart0uart0-xfer R>=uart0-ctsR=uart0-rtsR=uart1uart1-xfer R>=uart1-ctsR=uart1-rtsR=uart2uart2-xfer R>=8uart3uart3-xfer R>=uart3-ctsR=uart3-rtsR=uart4uart4-xfer R>=uart4-ctsR=uart4-rtsR=keyspwr-keyR=@pmicpmic-sleepR=1pmic-intR>0chosen`serial4:115200n8memory@0@memorygpio-keys gpio-keysdefault@power / lGPIO Powerrt}vcc-sys-regulatorregulator-fixedvcc_sysLK@LK@2 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellsphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-sdiosd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplymmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cells#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source