1#![allow(improper_ctypes)]
9
10#[cfg(test)]
11use stdarch_test::assert_instr;
12
13use super::*;
14
15#[doc = "CRC32 single round checksum for bytes (8 bits)."]
16#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
17#[inline]
18#[target_feature(enable = "crc")]
19#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20#[cfg_attr(test, assert_instr(crc32b))]
21#[cfg_attr(
22 target_arch = "arm",
23 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
24)]
25#[cfg_attr(
26 not(target_arch = "arm"),
27 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
28)]
29pub fn __crc32b(crc: u32, data: u8) -> u32 {
30 unsafe extern "unadjusted" {
31 #[cfg_attr(
32 any(target_arch = "aarch64", target_arch = "arm64ec"),
33 link_name = "llvm.aarch64.crc32b"
34 )]
35 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
36 fn ___crc32b(crc: u32, data: u32) -> u32;
37 }
38 unsafe { ___crc32b(crc, data as u32) }
39}
40#[doc = "CRC32-C single round checksum for bytes (8 bits)."]
41#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
42#[inline]
43#[target_feature(enable = "crc")]
44#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
45#[cfg_attr(test, assert_instr(crc32cb))]
46#[cfg_attr(
47 target_arch = "arm",
48 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
49)]
50#[cfg_attr(
51 not(target_arch = "arm"),
52 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
53)]
54pub fn __crc32cb(crc: u32, data: u8) -> u32 {
55 unsafe extern "unadjusted" {
56 #[cfg_attr(
57 any(target_arch = "aarch64", target_arch = "arm64ec"),
58 link_name = "llvm.aarch64.crc32cb"
59 )]
60 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
61 fn ___crc32cb(crc: u32, data: u32) -> u32;
62 }
63 unsafe { ___crc32cb(crc, data as u32) }
64}
65#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
66#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
67#[inline]
68#[target_feature(enable = "crc")]
69#[cfg(target_arch = "arm")]
70#[cfg_attr(test, assert_instr(crc32cw))]
71#[cfg_attr(
72 target_arch = "arm",
73 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
74)]
75pub fn __crc32cd(crc: u32, data: u64) -> u32 {
76 let b: u32 = (data & 0xFFFFFFFF) as u32;
77 let c: u32 = (data >> 32) as u32;
78 unsafe extern "unadjusted" {
79 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
80 fn ___crc32cw(crc: u32, data: u32) -> u32;
81 }
82 unsafe { ___crc32cw(___crc32cw(crc, b), c) }
83}
84#[doc = "CRC32-C single round checksum for bytes (16 bits)."]
85#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
86#[inline]
87#[target_feature(enable = "crc")]
88#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
89#[cfg_attr(test, assert_instr(crc32ch))]
90#[cfg_attr(
91 target_arch = "arm",
92 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
93)]
94#[cfg_attr(
95 not(target_arch = "arm"),
96 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
97)]
98pub fn __crc32ch(crc: u32, data: u16) -> u32 {
99 unsafe extern "unadjusted" {
100 #[cfg_attr(
101 any(target_arch = "aarch64", target_arch = "arm64ec"),
102 link_name = "llvm.aarch64.crc32ch"
103 )]
104 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
105 fn ___crc32ch(crc: u32, data: u32) -> u32;
106 }
107 unsafe { ___crc32ch(crc, data as u32) }
108}
109#[doc = "CRC32-C single round checksum for bytes (32 bits)."]
110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
111#[inline]
112#[target_feature(enable = "crc")]
113#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
114#[cfg_attr(test, assert_instr(crc32cw))]
115#[cfg_attr(
116 target_arch = "arm",
117 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
118)]
119#[cfg_attr(
120 not(target_arch = "arm"),
121 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
122)]
123pub fn __crc32cw(crc: u32, data: u32) -> u32 {
124 unsafe extern "unadjusted" {
125 #[cfg_attr(
126 any(target_arch = "aarch64", target_arch = "arm64ec"),
127 link_name = "llvm.aarch64.crc32cw"
128 )]
129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
130 fn ___crc32cw(crc: u32, data: u32) -> u32;
131 }
132 unsafe { ___crc32cw(crc, data) }
133}
134#[doc = "CRC32 single round checksum for quad words (64 bits)."]
135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
136#[inline]
137#[target_feature(enable = "crc")]
138#[cfg(target_arch = "arm")]
139#[cfg_attr(test, assert_instr(crc32w))]
140#[cfg_attr(
141 target_arch = "arm",
142 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
143)]
144pub fn __crc32d(crc: u32, data: u64) -> u32 {
145 let b: u32 = (data & 0xFFFFFFFF) as u32;
146 let c: u32 = (data >> 32) as u32;
147 unsafe extern "unadjusted" {
148 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
149 fn ___crc32w(crc: u32, data: u32) -> u32;
150 }
151 unsafe { ___crc32w(___crc32w(crc, b), c) }
152}
153#[doc = "CRC32 single round checksum for bytes (16 bits)."]
154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
155#[inline]
156#[target_feature(enable = "crc")]
157#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
158#[cfg_attr(test, assert_instr(crc32h))]
159#[cfg_attr(
160 target_arch = "arm",
161 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
162)]
163#[cfg_attr(
164 not(target_arch = "arm"),
165 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
166)]
167pub fn __crc32h(crc: u32, data: u16) -> u32 {
168 unsafe extern "unadjusted" {
169 #[cfg_attr(
170 any(target_arch = "aarch64", target_arch = "arm64ec"),
171 link_name = "llvm.aarch64.crc32h"
172 )]
173 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
174 fn ___crc32h(crc: u32, data: u32) -> u32;
175 }
176 unsafe { ___crc32h(crc, data as u32) }
177}
178#[doc = "CRC32 single round checksum for bytes (32 bits)."]
179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
180#[inline]
181#[target_feature(enable = "crc")]
182#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183#[cfg_attr(test, assert_instr(crc32w))]
184#[cfg_attr(
185 target_arch = "arm",
186 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
187)]
188#[cfg_attr(
189 not(target_arch = "arm"),
190 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
191)]
192pub fn __crc32w(crc: u32, data: u32) -> u32 {
193 unsafe extern "unadjusted" {
194 #[cfg_attr(
195 any(target_arch = "aarch64", target_arch = "arm64ec"),
196 link_name = "llvm.aarch64.crc32w"
197 )]
198 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
199 fn ___crc32w(crc: u32, data: u32) -> u32;
200 }
201 unsafe { ___crc32w(crc, data) }
202}
203#[doc = "Signed Add and Accumulate Long Pairwise."]
204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
205#[inline]
206#[target_feature(enable = "neon")]
207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
208#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
209#[cfg_attr(
210 target_arch = "arm",
211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
212)]
213fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
214 unsafe extern "unadjusted" {
215 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")]
216 fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t;
217 }
218 unsafe { _priv_vpadal_s8(a, b) }
219}
220#[doc = "Signed Add and Accumulate Long Pairwise."]
221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
222#[inline]
223#[target_feature(enable = "neon")]
224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
225#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
226#[cfg_attr(
227 target_arch = "arm",
228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
229)]
230fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
231 unsafe extern "unadjusted" {
232 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")]
233 fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t;
234 }
235 unsafe { _priv_vpadalq_s8(a, b) }
236}
237#[doc = "Signed Add and Accumulate Long Pairwise."]
238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
239#[inline]
240#[target_feature(enable = "neon")]
241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
243#[cfg_attr(
244 target_arch = "arm",
245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
246)]
247fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
248 unsafe extern "unadjusted" {
249 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")]
250 fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t;
251 }
252 unsafe { _priv_vpadal_s16(a, b) }
253}
254#[doc = "Signed Add and Accumulate Long Pairwise."]
255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
256#[inline]
257#[target_feature(enable = "neon")]
258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
259#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
260#[cfg_attr(
261 target_arch = "arm",
262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
263)]
264fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
265 unsafe extern "unadjusted" {
266 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")]
267 fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t;
268 }
269 unsafe { _priv_vpadalq_s16(a, b) }
270}
271#[doc = "Signed Add and Accumulate Long Pairwise."]
272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
273#[inline]
274#[target_feature(enable = "neon")]
275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
276#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
277#[cfg_attr(
278 target_arch = "arm",
279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
280)]
281fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
282 unsafe extern "unadjusted" {
283 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")]
284 fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t;
285 }
286 unsafe { _priv_vpadal_s32(a, b) }
287}
288#[doc = "Signed Add and Accumulate Long Pairwise."]
289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
290#[inline]
291#[target_feature(enable = "neon")]
292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
293#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
294#[cfg_attr(
295 target_arch = "arm",
296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
297)]
298fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
299 unsafe extern "unadjusted" {
300 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")]
301 fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t;
302 }
303 unsafe { _priv_vpadalq_s32(a, b) }
304}
305#[doc = "Signed Add and Accumulate Long Pairwise."]
306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
307#[inline]
308#[target_feature(enable = "neon")]
309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
311#[cfg_attr(
312 target_arch = "arm",
313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
314)]
315fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
316 unsafe extern "unadjusted" {
317 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")]
318 fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
319 }
320 unsafe { _priv_vpadal_u8(a, b) }
321}
322#[doc = "Signed Add and Accumulate Long Pairwise."]
323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
324#[inline]
325#[target_feature(enable = "neon")]
326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
327#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
328#[cfg_attr(
329 target_arch = "arm",
330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
331)]
332fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
333 unsafe extern "unadjusted" {
334 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")]
335 fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
336 }
337 unsafe { _priv_vpadalq_u8(a, b) }
338}
339#[doc = "Signed Add and Accumulate Long Pairwise."]
340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
341#[inline]
342#[target_feature(enable = "neon")]
343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
345#[cfg_attr(
346 target_arch = "arm",
347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
348)]
349fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
350 unsafe extern "unadjusted" {
351 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")]
352 fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
353 }
354 unsafe { _priv_vpadal_u16(a, b) }
355}
356#[doc = "Signed Add and Accumulate Long Pairwise."]
357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
358#[inline]
359#[target_feature(enable = "neon")]
360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
362#[cfg_attr(
363 target_arch = "arm",
364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
365)]
366fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
367 unsafe extern "unadjusted" {
368 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")]
369 fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
370 }
371 unsafe { _priv_vpadalq_u16(a, b) }
372}
373#[doc = "Signed Add and Accumulate Long Pairwise."]
374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
375#[inline]
376#[target_feature(enable = "neon")]
377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
379#[cfg_attr(
380 target_arch = "arm",
381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
382)]
383fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
384 unsafe extern "unadjusted" {
385 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")]
386 fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
387 }
388 unsafe { _priv_vpadal_u32(a, b) }
389}
390#[doc = "Signed Add and Accumulate Long Pairwise."]
391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
392#[inline]
393#[target_feature(enable = "neon")]
394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
395#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
396#[cfg_attr(
397 target_arch = "arm",
398 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
399)]
400fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
401 unsafe extern "unadjusted" {
402 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")]
403 fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
404 }
405 unsafe { _priv_vpadalq_u32(a, b) }
406}
407#[doc = "Signed Absolute difference and Accumulate Long"]
408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
409#[inline]
410#[target_feature(enable = "neon")]
411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
412#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
413#[cfg_attr(
414 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
415 assert_instr(sabal)
416)]
417#[cfg_attr(
418 not(target_arch = "arm"),
419 stable(feature = "neon_intrinsics", since = "1.59.0")
420)]
421#[cfg_attr(
422 target_arch = "arm",
423 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
424)]
425pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
426 let d: int8x8_t = vabd_s8(b, c);
427 unsafe {
428 let e: uint8x8_t = simd_cast(d);
429 simd_add(a, simd_cast(e))
430 }
431}
432#[doc = "Signed Absolute difference and Accumulate Long"]
433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
434#[inline]
435#[target_feature(enable = "neon")]
436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
437#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
438#[cfg_attr(
439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
440 assert_instr(sabal)
441)]
442#[cfg_attr(
443 not(target_arch = "arm"),
444 stable(feature = "neon_intrinsics", since = "1.59.0")
445)]
446#[cfg_attr(
447 target_arch = "arm",
448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
449)]
450pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
451 let d: int16x4_t = vabd_s16(b, c);
452 unsafe {
453 let e: uint16x4_t = simd_cast(d);
454 simd_add(a, simd_cast(e))
455 }
456}
457#[doc = "Signed Absolute difference and Accumulate Long"]
458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
459#[inline]
460#[target_feature(enable = "neon")]
461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
462#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
463#[cfg_attr(
464 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
465 assert_instr(sabal)
466)]
467#[cfg_attr(
468 not(target_arch = "arm"),
469 stable(feature = "neon_intrinsics", since = "1.59.0")
470)]
471#[cfg_attr(
472 target_arch = "arm",
473 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
474)]
475pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
476 let d: int32x2_t = vabd_s32(b, c);
477 unsafe {
478 let e: uint32x2_t = simd_cast(d);
479 simd_add(a, simd_cast(e))
480 }
481}
482#[doc = "Unsigned Absolute difference and Accumulate Long"]
483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
484#[inline]
485#[target_feature(enable = "neon")]
486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
487#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
488#[cfg_attr(
489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
490 assert_instr(uabal)
491)]
492#[cfg_attr(
493 not(target_arch = "arm"),
494 stable(feature = "neon_intrinsics", since = "1.59.0")
495)]
496#[cfg_attr(
497 target_arch = "arm",
498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
499)]
500pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
501 let d: uint8x8_t = vabd_u8(b, c);
502 unsafe { simd_add(a, simd_cast(d)) }
503}
504#[doc = "Unsigned Absolute difference and Accumulate Long"]
505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
506#[inline]
507#[target_feature(enable = "neon")]
508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
509#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
510#[cfg_attr(
511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
512 assert_instr(uabal)
513)]
514#[cfg_attr(
515 not(target_arch = "arm"),
516 stable(feature = "neon_intrinsics", since = "1.59.0")
517)]
518#[cfg_attr(
519 target_arch = "arm",
520 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
521)]
522pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
523 let d: uint16x4_t = vabd_u16(b, c);
524 unsafe { simd_add(a, simd_cast(d)) }
525}
526#[doc = "Unsigned Absolute difference and Accumulate Long"]
527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
528#[inline]
529#[target_feature(enable = "neon")]
530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
531#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
532#[cfg_attr(
533 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
534 assert_instr(uabal)
535)]
536#[cfg_attr(
537 not(target_arch = "arm"),
538 stable(feature = "neon_intrinsics", since = "1.59.0")
539)]
540#[cfg_attr(
541 target_arch = "arm",
542 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
543)]
544pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
545 let d: uint32x2_t = vabd_u32(b, c);
546 unsafe { simd_add(a, simd_cast(d)) }
547}
548#[doc = "Absolute difference between the arguments of Floating"]
549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
550#[inline]
551#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
552#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
553#[cfg_attr(
554 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
555 assert_instr(fabd)
556)]
557#[target_feature(enable = "neon,fp16")]
558#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
559pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
560 unsafe extern "unadjusted" {
561 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f16")]
562 #[cfg_attr(
563 any(target_arch = "aarch64", target_arch = "arm64ec"),
564 link_name = "llvm.aarch64.neon.fabd.v4f16"
565 )]
566 fn _vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
567 }
568 unsafe { _vabd_f16(a, b) }
569}
570#[doc = "Absolute difference between the arguments of Floating"]
571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
572#[inline]
573#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
574#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
575#[cfg_attr(
576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
577 assert_instr(fabd)
578)]
579#[target_feature(enable = "neon,fp16")]
580#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
581pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
582 unsafe extern "unadjusted" {
583 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8f16")]
584 #[cfg_attr(
585 any(target_arch = "aarch64", target_arch = "arm64ec"),
586 link_name = "llvm.aarch64.neon.fabd.v8f16"
587 )]
588 fn _vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
589 }
590 unsafe { _vabdq_f16(a, b) }
591}
592#[doc = "Absolute difference between the arguments of Floating"]
593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
594#[inline]
595#[target_feature(enable = "neon")]
596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
597#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
598#[cfg_attr(
599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
600 assert_instr(fabd)
601)]
602#[cfg_attr(
603 not(target_arch = "arm"),
604 stable(feature = "neon_intrinsics", since = "1.59.0")
605)]
606#[cfg_attr(
607 target_arch = "arm",
608 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
609)]
610pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
611 unsafe extern "unadjusted" {
612 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")]
613 #[cfg_attr(
614 any(target_arch = "aarch64", target_arch = "arm64ec"),
615 link_name = "llvm.aarch64.neon.fabd.v2f32"
616 )]
617 fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
618 }
619 unsafe { _vabd_f32(a, b) }
620}
621#[doc = "Absolute difference between the arguments of Floating"]
622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
623#[inline]
624#[target_feature(enable = "neon")]
625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
626#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
627#[cfg_attr(
628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
629 assert_instr(fabd)
630)]
631#[cfg_attr(
632 not(target_arch = "arm"),
633 stable(feature = "neon_intrinsics", since = "1.59.0")
634)]
635#[cfg_attr(
636 target_arch = "arm",
637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
638)]
639pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
640 unsafe extern "unadjusted" {
641 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")]
642 #[cfg_attr(
643 any(target_arch = "aarch64", target_arch = "arm64ec"),
644 link_name = "llvm.aarch64.neon.fabd.v4f32"
645 )]
646 fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
647 }
648 unsafe { _vabdq_f32(a, b) }
649}
650#[doc = "Absolute difference between the arguments"]
651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
652#[inline]
653#[target_feature(enable = "neon")]
654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
656#[cfg_attr(
657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
658 assert_instr(sabd)
659)]
660#[cfg_attr(
661 not(target_arch = "arm"),
662 stable(feature = "neon_intrinsics", since = "1.59.0")
663)]
664#[cfg_attr(
665 target_arch = "arm",
666 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
667)]
668pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
669 unsafe extern "unadjusted" {
670 #[cfg_attr(
671 any(target_arch = "aarch64", target_arch = "arm64ec"),
672 link_name = "llvm.aarch64.neon.sabd.v8i8"
673 )]
674 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")]
675 fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
676 }
677 unsafe { _vabd_s8(a, b) }
678}
679#[doc = "Absolute difference between the arguments"]
680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
681#[inline]
682#[target_feature(enable = "neon")]
683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
684#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
685#[cfg_attr(
686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
687 assert_instr(sabd)
688)]
689#[cfg_attr(
690 not(target_arch = "arm"),
691 stable(feature = "neon_intrinsics", since = "1.59.0")
692)]
693#[cfg_attr(
694 target_arch = "arm",
695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
696)]
697pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
698 unsafe extern "unadjusted" {
699 #[cfg_attr(
700 any(target_arch = "aarch64", target_arch = "arm64ec"),
701 link_name = "llvm.aarch64.neon.sabd.v16i8"
702 )]
703 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")]
704 fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
705 }
706 unsafe { _vabdq_s8(a, b) }
707}
708#[doc = "Absolute difference between the arguments"]
709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
710#[inline]
711#[target_feature(enable = "neon")]
712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
713#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
714#[cfg_attr(
715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
716 assert_instr(sabd)
717)]
718#[cfg_attr(
719 not(target_arch = "arm"),
720 stable(feature = "neon_intrinsics", since = "1.59.0")
721)]
722#[cfg_attr(
723 target_arch = "arm",
724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
725)]
726pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
727 unsafe extern "unadjusted" {
728 #[cfg_attr(
729 any(target_arch = "aarch64", target_arch = "arm64ec"),
730 link_name = "llvm.aarch64.neon.sabd.v4i16"
731 )]
732 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")]
733 fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
734 }
735 unsafe { _vabd_s16(a, b) }
736}
737#[doc = "Absolute difference between the arguments"]
738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
739#[inline]
740#[target_feature(enable = "neon")]
741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
743#[cfg_attr(
744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
745 assert_instr(sabd)
746)]
747#[cfg_attr(
748 not(target_arch = "arm"),
749 stable(feature = "neon_intrinsics", since = "1.59.0")
750)]
751#[cfg_attr(
752 target_arch = "arm",
753 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
754)]
755pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
756 unsafe extern "unadjusted" {
757 #[cfg_attr(
758 any(target_arch = "aarch64", target_arch = "arm64ec"),
759 link_name = "llvm.aarch64.neon.sabd.v8i16"
760 )]
761 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")]
762 fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
763 }
764 unsafe { _vabdq_s16(a, b) }
765}
766#[doc = "Absolute difference between the arguments"]
767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
768#[inline]
769#[target_feature(enable = "neon")]
770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
771#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
772#[cfg_attr(
773 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
774 assert_instr(sabd)
775)]
776#[cfg_attr(
777 not(target_arch = "arm"),
778 stable(feature = "neon_intrinsics", since = "1.59.0")
779)]
780#[cfg_attr(
781 target_arch = "arm",
782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
783)]
784pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
785 unsafe extern "unadjusted" {
786 #[cfg_attr(
787 any(target_arch = "aarch64", target_arch = "arm64ec"),
788 link_name = "llvm.aarch64.neon.sabd.v2i32"
789 )]
790 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")]
791 fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
792 }
793 unsafe { _vabd_s32(a, b) }
794}
795#[doc = "Absolute difference between the arguments"]
796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
797#[inline]
798#[target_feature(enable = "neon")]
799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
800#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
801#[cfg_attr(
802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
803 assert_instr(sabd)
804)]
805#[cfg_attr(
806 not(target_arch = "arm"),
807 stable(feature = "neon_intrinsics", since = "1.59.0")
808)]
809#[cfg_attr(
810 target_arch = "arm",
811 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
812)]
813pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
814 unsafe extern "unadjusted" {
815 #[cfg_attr(
816 any(target_arch = "aarch64", target_arch = "arm64ec"),
817 link_name = "llvm.aarch64.neon.sabd.v4i32"
818 )]
819 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")]
820 fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
821 }
822 unsafe { _vabdq_s32(a, b) }
823}
824#[doc = "Absolute difference between the arguments"]
825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
826#[inline]
827#[target_feature(enable = "neon")]
828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
829#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
830#[cfg_attr(
831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
832 assert_instr(uabd)
833)]
834#[cfg_attr(
835 not(target_arch = "arm"),
836 stable(feature = "neon_intrinsics", since = "1.59.0")
837)]
838#[cfg_attr(
839 target_arch = "arm",
840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
841)]
842pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
843 unsafe extern "unadjusted" {
844 #[cfg_attr(
845 any(target_arch = "aarch64", target_arch = "arm64ec"),
846 link_name = "llvm.aarch64.neon.uabd.v8i8"
847 )]
848 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")]
849 fn _vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
850 }
851 unsafe { _vabd_u8(a, b) }
852}
853#[doc = "Absolute difference between the arguments"]
854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
855#[inline]
856#[target_feature(enable = "neon")]
857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
858#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
859#[cfg_attr(
860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
861 assert_instr(uabd)
862)]
863#[cfg_attr(
864 not(target_arch = "arm"),
865 stable(feature = "neon_intrinsics", since = "1.59.0")
866)]
867#[cfg_attr(
868 target_arch = "arm",
869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
870)]
871pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
872 unsafe extern "unadjusted" {
873 #[cfg_attr(
874 any(target_arch = "aarch64", target_arch = "arm64ec"),
875 link_name = "llvm.aarch64.neon.uabd.v16i8"
876 )]
877 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")]
878 fn _vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
879 }
880 unsafe { _vabdq_u8(a, b) }
881}
882#[doc = "Absolute difference between the arguments"]
883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
884#[inline]
885#[target_feature(enable = "neon")]
886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
887#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
888#[cfg_attr(
889 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
890 assert_instr(uabd)
891)]
892#[cfg_attr(
893 not(target_arch = "arm"),
894 stable(feature = "neon_intrinsics", since = "1.59.0")
895)]
896#[cfg_attr(
897 target_arch = "arm",
898 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
899)]
900pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
901 unsafe extern "unadjusted" {
902 #[cfg_attr(
903 any(target_arch = "aarch64", target_arch = "arm64ec"),
904 link_name = "llvm.aarch64.neon.uabd.v4i16"
905 )]
906 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")]
907 fn _vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
908 }
909 unsafe { _vabd_u16(a, b) }
910}
911#[doc = "Absolute difference between the arguments"]
912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
913#[inline]
914#[target_feature(enable = "neon")]
915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
916#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
917#[cfg_attr(
918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
919 assert_instr(uabd)
920)]
921#[cfg_attr(
922 not(target_arch = "arm"),
923 stable(feature = "neon_intrinsics", since = "1.59.0")
924)]
925#[cfg_attr(
926 target_arch = "arm",
927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
928)]
929pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
930 unsafe extern "unadjusted" {
931 #[cfg_attr(
932 any(target_arch = "aarch64", target_arch = "arm64ec"),
933 link_name = "llvm.aarch64.neon.uabd.v8i16"
934 )]
935 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")]
936 fn _vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
937 }
938 unsafe { _vabdq_u16(a, b) }
939}
940#[doc = "Absolute difference between the arguments"]
941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
942#[inline]
943#[target_feature(enable = "neon")]
944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
945#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
946#[cfg_attr(
947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
948 assert_instr(uabd)
949)]
950#[cfg_attr(
951 not(target_arch = "arm"),
952 stable(feature = "neon_intrinsics", since = "1.59.0")
953)]
954#[cfg_attr(
955 target_arch = "arm",
956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
957)]
958pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
959 unsafe extern "unadjusted" {
960 #[cfg_attr(
961 any(target_arch = "aarch64", target_arch = "arm64ec"),
962 link_name = "llvm.aarch64.neon.uabd.v2i32"
963 )]
964 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")]
965 fn _vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
966 }
967 unsafe { _vabd_u32(a, b) }
968}
969#[doc = "Absolute difference between the arguments"]
970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
971#[inline]
972#[target_feature(enable = "neon")]
973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
974#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
975#[cfg_attr(
976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
977 assert_instr(uabd)
978)]
979#[cfg_attr(
980 not(target_arch = "arm"),
981 stable(feature = "neon_intrinsics", since = "1.59.0")
982)]
983#[cfg_attr(
984 target_arch = "arm",
985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
986)]
987pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
988 unsafe extern "unadjusted" {
989 #[cfg_attr(
990 any(target_arch = "aarch64", target_arch = "arm64ec"),
991 link_name = "llvm.aarch64.neon.uabd.v4i32"
992 )]
993 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")]
994 fn _vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
995 }
996 unsafe { _vabdq_u32(a, b) }
997}
998#[doc = "Signed Absolute difference Long"]
999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
1000#[inline]
1001#[target_feature(enable = "neon")]
1002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
1004#[cfg_attr(
1005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1006 assert_instr(sabdl)
1007)]
1008#[cfg_attr(
1009 not(target_arch = "arm"),
1010 stable(feature = "neon_intrinsics", since = "1.59.0")
1011)]
1012#[cfg_attr(
1013 target_arch = "arm",
1014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1015)]
1016pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
1017 unsafe {
1018 let c: uint8x8_t = simd_cast(vabd_s8(a, b));
1019 simd_cast(c)
1020 }
1021}
1022#[doc = "Signed Absolute difference Long"]
1023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
1024#[inline]
1025#[target_feature(enable = "neon")]
1026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1027#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
1028#[cfg_attr(
1029 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1030 assert_instr(sabdl)
1031)]
1032#[cfg_attr(
1033 not(target_arch = "arm"),
1034 stable(feature = "neon_intrinsics", since = "1.59.0")
1035)]
1036#[cfg_attr(
1037 target_arch = "arm",
1038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1039)]
1040pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
1041 unsafe {
1042 let c: uint16x4_t = simd_cast(vabd_s16(a, b));
1043 simd_cast(c)
1044 }
1045}
1046#[doc = "Signed Absolute difference Long"]
1047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
1048#[inline]
1049#[target_feature(enable = "neon")]
1050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1051#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
1052#[cfg_attr(
1053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1054 assert_instr(sabdl)
1055)]
1056#[cfg_attr(
1057 not(target_arch = "arm"),
1058 stable(feature = "neon_intrinsics", since = "1.59.0")
1059)]
1060#[cfg_attr(
1061 target_arch = "arm",
1062 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1063)]
1064pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
1065 unsafe {
1066 let c: uint32x2_t = simd_cast(vabd_s32(a, b));
1067 simd_cast(c)
1068 }
1069}
1070#[doc = "Unsigned Absolute difference Long"]
1071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
1072#[inline]
1073#[target_feature(enable = "neon")]
1074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1075#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
1076#[cfg_attr(
1077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1078 assert_instr(uabdl)
1079)]
1080#[cfg_attr(
1081 not(target_arch = "arm"),
1082 stable(feature = "neon_intrinsics", since = "1.59.0")
1083)]
1084#[cfg_attr(
1085 target_arch = "arm",
1086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1087)]
1088pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
1089 unsafe { simd_cast(vabd_u8(a, b)) }
1090}
1091#[doc = "Unsigned Absolute difference Long"]
1092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
1093#[inline]
1094#[target_feature(enable = "neon")]
1095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1096#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
1097#[cfg_attr(
1098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1099 assert_instr(uabdl)
1100)]
1101#[cfg_attr(
1102 not(target_arch = "arm"),
1103 stable(feature = "neon_intrinsics", since = "1.59.0")
1104)]
1105#[cfg_attr(
1106 target_arch = "arm",
1107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1108)]
1109pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
1110 unsafe { simd_cast(vabd_u16(a, b)) }
1111}
1112#[doc = "Unsigned Absolute difference Long"]
1113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
1114#[inline]
1115#[target_feature(enable = "neon")]
1116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1117#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
1118#[cfg_attr(
1119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1120 assert_instr(uabdl)
1121)]
1122#[cfg_attr(
1123 not(target_arch = "arm"),
1124 stable(feature = "neon_intrinsics", since = "1.59.0")
1125)]
1126#[cfg_attr(
1127 target_arch = "arm",
1128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1129)]
1130pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
1131 unsafe { simd_cast(vabd_u32(a, b)) }
1132}
1133#[doc = "Floating-point absolute value"]
1134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
1135#[inline]
1136#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1138#[cfg_attr(
1139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1140 assert_instr(fabs)
1141)]
1142#[target_feature(enable = "neon,fp16")]
1143#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1144pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
1145 unsafe { simd_fabs(a) }
1146}
1147#[doc = "Floating-point absolute value"]
1148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
1149#[inline]
1150#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1151#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1152#[cfg_attr(
1153 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1154 assert_instr(fabs)
1155)]
1156#[target_feature(enable = "neon,fp16")]
1157#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1158pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
1159 unsafe { simd_fabs(a) }
1160}
1161#[doc = "Floating-point absolute value"]
1162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
1163#[inline]
1164#[target_feature(enable = "neon")]
1165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1167#[cfg_attr(
1168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1169 assert_instr(fabs)
1170)]
1171#[cfg_attr(
1172 not(target_arch = "arm"),
1173 stable(feature = "neon_intrinsics", since = "1.59.0")
1174)]
1175#[cfg_attr(
1176 target_arch = "arm",
1177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1178)]
1179pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
1180 unsafe { simd_fabs(a) }
1181}
1182#[doc = "Floating-point absolute value"]
1183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
1184#[inline]
1185#[target_feature(enable = "neon")]
1186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1188#[cfg_attr(
1189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1190 assert_instr(fabs)
1191)]
1192#[cfg_attr(
1193 not(target_arch = "arm"),
1194 stable(feature = "neon_intrinsics", since = "1.59.0")
1195)]
1196#[cfg_attr(
1197 target_arch = "arm",
1198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1199)]
1200pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
1201 unsafe { simd_fabs(a) }
1202}
1203#[doc = "Absolute value (wrapping)."]
1204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
1205#[inline]
1206#[target_feature(enable = "neon")]
1207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1209#[cfg_attr(
1210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1211 assert_instr(abs)
1212)]
1213#[cfg_attr(
1214 not(target_arch = "arm"),
1215 stable(feature = "neon_intrinsics", since = "1.59.0")
1216)]
1217#[cfg_attr(
1218 target_arch = "arm",
1219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1220)]
1221pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
1222 unsafe extern "unadjusted" {
1223 #[cfg_attr(
1224 any(target_arch = "aarch64", target_arch = "arm64ec"),
1225 link_name = "llvm.aarch64.neon.abs.v8i8"
1226 )]
1227 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")]
1228 fn _vabs_s8(a: int8x8_t) -> int8x8_t;
1229 }
1230 unsafe { _vabs_s8(a) }
1231}
1232#[doc = "Absolute value (wrapping)."]
1233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
1234#[inline]
1235#[target_feature(enable = "neon")]
1236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1238#[cfg_attr(
1239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1240 assert_instr(abs)
1241)]
1242#[cfg_attr(
1243 not(target_arch = "arm"),
1244 stable(feature = "neon_intrinsics", since = "1.59.0")
1245)]
1246#[cfg_attr(
1247 target_arch = "arm",
1248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1249)]
1250pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
1251 unsafe extern "unadjusted" {
1252 #[cfg_attr(
1253 any(target_arch = "aarch64", target_arch = "arm64ec"),
1254 link_name = "llvm.aarch64.neon.abs.v16i8"
1255 )]
1256 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")]
1257 fn _vabsq_s8(a: int8x16_t) -> int8x16_t;
1258 }
1259 unsafe { _vabsq_s8(a) }
1260}
1261#[doc = "Absolute value (wrapping)."]
1262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
1263#[inline]
1264#[target_feature(enable = "neon")]
1265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1267#[cfg_attr(
1268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1269 assert_instr(abs)
1270)]
1271#[cfg_attr(
1272 not(target_arch = "arm"),
1273 stable(feature = "neon_intrinsics", since = "1.59.0")
1274)]
1275#[cfg_attr(
1276 target_arch = "arm",
1277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1278)]
1279pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
1280 unsafe extern "unadjusted" {
1281 #[cfg_attr(
1282 any(target_arch = "aarch64", target_arch = "arm64ec"),
1283 link_name = "llvm.aarch64.neon.abs.v4i16"
1284 )]
1285 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")]
1286 fn _vabs_s16(a: int16x4_t) -> int16x4_t;
1287 }
1288 unsafe { _vabs_s16(a) }
1289}
1290#[doc = "Absolute value (wrapping)."]
1291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
1292#[inline]
1293#[target_feature(enable = "neon")]
1294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1296#[cfg_attr(
1297 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1298 assert_instr(abs)
1299)]
1300#[cfg_attr(
1301 not(target_arch = "arm"),
1302 stable(feature = "neon_intrinsics", since = "1.59.0")
1303)]
1304#[cfg_attr(
1305 target_arch = "arm",
1306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1307)]
1308pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
1309 unsafe extern "unadjusted" {
1310 #[cfg_attr(
1311 any(target_arch = "aarch64", target_arch = "arm64ec"),
1312 link_name = "llvm.aarch64.neon.abs.v8i16"
1313 )]
1314 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")]
1315 fn _vabsq_s16(a: int16x8_t) -> int16x8_t;
1316 }
1317 unsafe { _vabsq_s16(a) }
1318}
1319#[doc = "Absolute value (wrapping)."]
1320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
1321#[inline]
1322#[target_feature(enable = "neon")]
1323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1325#[cfg_attr(
1326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1327 assert_instr(abs)
1328)]
1329#[cfg_attr(
1330 not(target_arch = "arm"),
1331 stable(feature = "neon_intrinsics", since = "1.59.0")
1332)]
1333#[cfg_attr(
1334 target_arch = "arm",
1335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1336)]
1337pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
1338 unsafe extern "unadjusted" {
1339 #[cfg_attr(
1340 any(target_arch = "aarch64", target_arch = "arm64ec"),
1341 link_name = "llvm.aarch64.neon.abs.v2i32"
1342 )]
1343 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")]
1344 fn _vabs_s32(a: int32x2_t) -> int32x2_t;
1345 }
1346 unsafe { _vabs_s32(a) }
1347}
1348#[doc = "Absolute value (wrapping)."]
1349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
1350#[inline]
1351#[target_feature(enable = "neon")]
1352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1353#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1354#[cfg_attr(
1355 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1356 assert_instr(abs)
1357)]
1358#[cfg_attr(
1359 not(target_arch = "arm"),
1360 stable(feature = "neon_intrinsics", since = "1.59.0")
1361)]
1362#[cfg_attr(
1363 target_arch = "arm",
1364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1365)]
1366pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
1367 unsafe extern "unadjusted" {
1368 #[cfg_attr(
1369 any(target_arch = "aarch64", target_arch = "arm64ec"),
1370 link_name = "llvm.aarch64.neon.abs.v4i32"
1371 )]
1372 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")]
1373 fn _vabsq_s32(a: int32x4_t) -> int32x4_t;
1374 }
1375 unsafe { _vabsq_s32(a) }
1376}
1377#[doc = "Floating-point absolute value"]
1378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
1379#[inline]
1380#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1382#[cfg_attr(
1383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1384 assert_instr(fabs)
1385)]
1386#[target_feature(enable = "neon,fp16")]
1387#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1388pub fn vabsh_f16(a: f16) -> f16 {
1389 unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) }
1390}
1391#[doc = "Floating-point Add (vector)."]
1392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
1393#[inline]
1394#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1395#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1396#[cfg_attr(
1397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1398 assert_instr(fadd)
1399)]
1400#[target_feature(enable = "neon,fp16")]
1401#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1402pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1403 unsafe { simd_add(a, b) }
1404}
1405#[doc = "Floating-point Add (vector)."]
1406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
1407#[inline]
1408#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1409#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1410#[cfg_attr(
1411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1412 assert_instr(fadd)
1413)]
1414#[target_feature(enable = "neon,fp16")]
1415#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1416pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1417 unsafe { simd_add(a, b) }
1418}
1419#[doc = "Bitwise exclusive OR"]
1420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
1421#[inline]
1422#[target_feature(enable = "neon")]
1423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1425#[cfg_attr(
1426 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1427 assert_instr(nop)
1428)]
1429#[cfg_attr(
1430 not(target_arch = "arm"),
1431 stable(feature = "neon_intrinsics", since = "1.59.0")
1432)]
1433#[cfg_attr(
1434 target_arch = "arm",
1435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1436)]
1437pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
1438 unsafe { simd_xor(a, b) }
1439}
1440#[doc = "Bitwise exclusive OR"]
1441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
1442#[inline]
1443#[target_feature(enable = "neon")]
1444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1446#[cfg_attr(
1447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1448 assert_instr(nop)
1449)]
1450#[cfg_attr(
1451 not(target_arch = "arm"),
1452 stable(feature = "neon_intrinsics", since = "1.59.0")
1453)]
1454#[cfg_attr(
1455 target_arch = "arm",
1456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1457)]
1458pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
1459 unsafe { simd_xor(a, b) }
1460}
1461#[doc = "Bitwise exclusive OR"]
1462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
1463#[inline]
1464#[target_feature(enable = "neon")]
1465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1467#[cfg_attr(
1468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1469 assert_instr(nop)
1470)]
1471#[cfg_attr(
1472 not(target_arch = "arm"),
1473 stable(feature = "neon_intrinsics", since = "1.59.0")
1474)]
1475#[cfg_attr(
1476 target_arch = "arm",
1477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1478)]
1479pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
1480 unsafe { simd_xor(a, b) }
1481}
1482#[doc = "Bitwise exclusive OR"]
1483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
1484#[inline]
1485#[target_feature(enable = "neon")]
1486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1488#[cfg_attr(
1489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1490 assert_instr(nop)
1491)]
1492#[cfg_attr(
1493 not(target_arch = "arm"),
1494 stable(feature = "neon_intrinsics", since = "1.59.0")
1495)]
1496#[cfg_attr(
1497 target_arch = "arm",
1498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1499)]
1500pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
1501 unsafe { simd_xor(a, b) }
1502}
1503#[doc = "Bitwise exclusive OR"]
1504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
1505#[inline]
1506#[target_feature(enable = "neon")]
1507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1509#[cfg_attr(
1510 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1511 assert_instr(nop)
1512)]
1513#[cfg_attr(
1514 not(target_arch = "arm"),
1515 stable(feature = "neon_intrinsics", since = "1.59.0")
1516)]
1517#[cfg_attr(
1518 target_arch = "arm",
1519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1520)]
1521pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
1522 unsafe { simd_xor(a, b) }
1523}
1524#[doc = "Bitwise exclusive OR"]
1525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
1526#[inline]
1527#[target_feature(enable = "neon")]
1528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1530#[cfg_attr(
1531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1532 assert_instr(nop)
1533)]
1534#[cfg_attr(
1535 not(target_arch = "arm"),
1536 stable(feature = "neon_intrinsics", since = "1.59.0")
1537)]
1538#[cfg_attr(
1539 target_arch = "arm",
1540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1541)]
1542pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
1543 unsafe { simd_xor(a, b) }
1544}
1545#[doc = "Add"]
1546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
1547#[inline]
1548#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1549#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1550#[cfg_attr(
1551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1552 assert_instr(fadd)
1553)]
1554#[target_feature(enable = "neon,fp16")]
1555#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1556pub fn vaddh_f16(a: f16, b: f16) -> f16 {
1557 a + b
1558}
1559#[doc = "Bitwise exclusive OR"]
1560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
1561#[inline]
1562#[target_feature(enable = "neon")]
1563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
1565#[cfg_attr(
1566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1567 assert_instr(nop)
1568)]
1569#[cfg_attr(
1570 not(target_arch = "arm"),
1571 stable(feature = "neon_intrinsics", since = "1.59.0")
1572)]
1573#[cfg_attr(
1574 target_arch = "arm",
1575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1576)]
1577pub fn vaddq_p128(a: p128, b: p128) -> p128 {
1578 a ^ b
1579}
1580#[doc = "AES single round encryption."]
1581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
1582#[inline]
1583#[target_feature(enable = "aes")]
1584#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1585#[cfg_attr(test, assert_instr(aesd))]
1586#[cfg_attr(
1587 target_arch = "arm",
1588 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1589)]
1590#[cfg_attr(
1591 not(target_arch = "arm"),
1592 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
1593)]
1594pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
1595 unsafe extern "unadjusted" {
1596 #[cfg_attr(
1597 any(target_arch = "aarch64", target_arch = "arm64ec"),
1598 link_name = "llvm.aarch64.crypto.aesd"
1599 )]
1600 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
1601 fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
1602 }
1603 unsafe { _vaesdq_u8(data, key) }
1604}
1605#[doc = "AES single round encryption."]
1606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
1607#[inline]
1608#[target_feature(enable = "aes")]
1609#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1610#[cfg_attr(test, assert_instr(aese))]
1611#[cfg_attr(
1612 target_arch = "arm",
1613 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1614)]
1615#[cfg_attr(
1616 not(target_arch = "arm"),
1617 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
1618)]
1619pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
1620 unsafe extern "unadjusted" {
1621 #[cfg_attr(
1622 any(target_arch = "aarch64", target_arch = "arm64ec"),
1623 link_name = "llvm.aarch64.crypto.aese"
1624 )]
1625 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
1626 fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
1627 }
1628 unsafe { _vaeseq_u8(data, key) }
1629}
1630#[doc = "AES inverse mix columns."]
1631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
1632#[inline]
1633#[target_feature(enable = "aes")]
1634#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1635#[cfg_attr(test, assert_instr(aesimc))]
1636#[cfg_attr(
1637 target_arch = "arm",
1638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1639)]
1640#[cfg_attr(
1641 not(target_arch = "arm"),
1642 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
1643)]
1644pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
1645 unsafe extern "unadjusted" {
1646 #[cfg_attr(
1647 any(target_arch = "aarch64", target_arch = "arm64ec"),
1648 link_name = "llvm.aarch64.crypto.aesimc"
1649 )]
1650 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
1651 fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t;
1652 }
1653 unsafe { _vaesimcq_u8(data) }
1654}
1655#[doc = "AES mix columns."]
1656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
1657#[inline]
1658#[target_feature(enable = "aes")]
1659#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1660#[cfg_attr(test, assert_instr(aesmc))]
1661#[cfg_attr(
1662 target_arch = "arm",
1663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1664)]
1665#[cfg_attr(
1666 not(target_arch = "arm"),
1667 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
1668)]
1669pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
1670 unsafe extern "unadjusted" {
1671 #[cfg_attr(
1672 any(target_arch = "aarch64", target_arch = "arm64ec"),
1673 link_name = "llvm.aarch64.crypto.aesmc"
1674 )]
1675 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
1676 fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t;
1677 }
1678 unsafe { _vaesmcq_u8(data) }
1679}
1680#[doc = "Vector bitwise and"]
1681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
1682#[inline]
1683#[target_feature(enable = "neon")]
1684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1686#[cfg_attr(
1687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1688 assert_instr(and)
1689)]
1690#[cfg_attr(
1691 not(target_arch = "arm"),
1692 stable(feature = "neon_intrinsics", since = "1.59.0")
1693)]
1694#[cfg_attr(
1695 target_arch = "arm",
1696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1697)]
1698pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
1699 unsafe { simd_and(a, b) }
1700}
1701#[doc = "Vector bitwise and"]
1702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
1703#[inline]
1704#[target_feature(enable = "neon")]
1705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1707#[cfg_attr(
1708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1709 assert_instr(and)
1710)]
1711#[cfg_attr(
1712 not(target_arch = "arm"),
1713 stable(feature = "neon_intrinsics", since = "1.59.0")
1714)]
1715#[cfg_attr(
1716 target_arch = "arm",
1717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1718)]
1719pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
1720 unsafe { simd_and(a, b) }
1721}
1722#[doc = "Vector bitwise and"]
1723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
1724#[inline]
1725#[target_feature(enable = "neon")]
1726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1728#[cfg_attr(
1729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1730 assert_instr(and)
1731)]
1732#[cfg_attr(
1733 not(target_arch = "arm"),
1734 stable(feature = "neon_intrinsics", since = "1.59.0")
1735)]
1736#[cfg_attr(
1737 target_arch = "arm",
1738 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1739)]
1740pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
1741 unsafe { simd_and(a, b) }
1742}
1743#[doc = "Vector bitwise and"]
1744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
1745#[inline]
1746#[target_feature(enable = "neon")]
1747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1749#[cfg_attr(
1750 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1751 assert_instr(and)
1752)]
1753#[cfg_attr(
1754 not(target_arch = "arm"),
1755 stable(feature = "neon_intrinsics", since = "1.59.0")
1756)]
1757#[cfg_attr(
1758 target_arch = "arm",
1759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1760)]
1761pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1762 unsafe { simd_and(a, b) }
1763}
1764#[doc = "Vector bitwise and"]
1765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
1766#[inline]
1767#[target_feature(enable = "neon")]
1768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1770#[cfg_attr(
1771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1772 assert_instr(and)
1773)]
1774#[cfg_attr(
1775 not(target_arch = "arm"),
1776 stable(feature = "neon_intrinsics", since = "1.59.0")
1777)]
1778#[cfg_attr(
1779 target_arch = "arm",
1780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1781)]
1782pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1783 unsafe { simd_and(a, b) }
1784}
1785#[doc = "Vector bitwise and"]
1786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
1787#[inline]
1788#[target_feature(enable = "neon")]
1789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1791#[cfg_attr(
1792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1793 assert_instr(and)
1794)]
1795#[cfg_attr(
1796 not(target_arch = "arm"),
1797 stable(feature = "neon_intrinsics", since = "1.59.0")
1798)]
1799#[cfg_attr(
1800 target_arch = "arm",
1801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1802)]
1803pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1804 unsafe { simd_and(a, b) }
1805}
1806#[doc = "Vector bitwise and"]
1807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
1808#[inline]
1809#[target_feature(enable = "neon")]
1810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1812#[cfg_attr(
1813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1814 assert_instr(and)
1815)]
1816#[cfg_attr(
1817 not(target_arch = "arm"),
1818 stable(feature = "neon_intrinsics", since = "1.59.0")
1819)]
1820#[cfg_attr(
1821 target_arch = "arm",
1822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1823)]
1824pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
1825 unsafe { simd_and(a, b) }
1826}
1827#[doc = "Vector bitwise and"]
1828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
1829#[inline]
1830#[target_feature(enable = "neon")]
1831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1833#[cfg_attr(
1834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1835 assert_instr(and)
1836)]
1837#[cfg_attr(
1838 not(target_arch = "arm"),
1839 stable(feature = "neon_intrinsics", since = "1.59.0")
1840)]
1841#[cfg_attr(
1842 target_arch = "arm",
1843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1844)]
1845pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
1846 unsafe { simd_and(a, b) }
1847}
1848#[doc = "Vector bitwise and"]
1849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
1850#[inline]
1851#[target_feature(enable = "neon")]
1852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1854#[cfg_attr(
1855 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1856 assert_instr(and)
1857)]
1858#[cfg_attr(
1859 not(target_arch = "arm"),
1860 stable(feature = "neon_intrinsics", since = "1.59.0")
1861)]
1862#[cfg_attr(
1863 target_arch = "arm",
1864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1865)]
1866pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1867 unsafe { simd_and(a, b) }
1868}
1869#[doc = "Vector bitwise and"]
1870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
1871#[inline]
1872#[target_feature(enable = "neon")]
1873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1875#[cfg_attr(
1876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1877 assert_instr(and)
1878)]
1879#[cfg_attr(
1880 not(target_arch = "arm"),
1881 stable(feature = "neon_intrinsics", since = "1.59.0")
1882)]
1883#[cfg_attr(
1884 target_arch = "arm",
1885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1886)]
1887pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
1888 unsafe { simd_and(a, b) }
1889}
1890#[doc = "Vector bitwise and"]
1891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
1892#[inline]
1893#[target_feature(enable = "neon")]
1894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1896#[cfg_attr(
1897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1898 assert_instr(and)
1899)]
1900#[cfg_attr(
1901 not(target_arch = "arm"),
1902 stable(feature = "neon_intrinsics", since = "1.59.0")
1903)]
1904#[cfg_attr(
1905 target_arch = "arm",
1906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1907)]
1908pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1909 unsafe { simd_and(a, b) }
1910}
1911#[doc = "Vector bitwise and"]
1912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
1913#[inline]
1914#[target_feature(enable = "neon")]
1915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1917#[cfg_attr(
1918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1919 assert_instr(and)
1920)]
1921#[cfg_attr(
1922 not(target_arch = "arm"),
1923 stable(feature = "neon_intrinsics", since = "1.59.0")
1924)]
1925#[cfg_attr(
1926 target_arch = "arm",
1927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1928)]
1929pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1930 unsafe { simd_and(a, b) }
1931}
1932#[doc = "Vector bitwise and"]
1933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
1934#[inline]
1935#[target_feature(enable = "neon")]
1936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1938#[cfg_attr(
1939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1940 assert_instr(and)
1941)]
1942#[cfg_attr(
1943 not(target_arch = "arm"),
1944 stable(feature = "neon_intrinsics", since = "1.59.0")
1945)]
1946#[cfg_attr(
1947 target_arch = "arm",
1948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1949)]
1950pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1951 unsafe { simd_and(a, b) }
1952}
1953#[doc = "Vector bitwise and"]
1954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
1955#[inline]
1956#[target_feature(enable = "neon")]
1957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1959#[cfg_attr(
1960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1961 assert_instr(and)
1962)]
1963#[cfg_attr(
1964 not(target_arch = "arm"),
1965 stable(feature = "neon_intrinsics", since = "1.59.0")
1966)]
1967#[cfg_attr(
1968 target_arch = "arm",
1969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1970)]
1971pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1972 unsafe { simd_and(a, b) }
1973}
1974#[doc = "Vector bitwise and"]
1975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
1976#[inline]
1977#[target_feature(enable = "neon")]
1978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1979#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
1980#[cfg_attr(
1981 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1982 assert_instr(and)
1983)]
1984#[cfg_attr(
1985 not(target_arch = "arm"),
1986 stable(feature = "neon_intrinsics", since = "1.59.0")
1987)]
1988#[cfg_attr(
1989 target_arch = "arm",
1990 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1991)]
1992pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
1993 unsafe { simd_and(a, b) }
1994}
1995#[doc = "Vector bitwise and"]
1996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
1997#[inline]
1998#[target_feature(enable = "neon")]
1999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
2001#[cfg_attr(
2002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2003 assert_instr(and)
2004)]
2005#[cfg_attr(
2006 not(target_arch = "arm"),
2007 stable(feature = "neon_intrinsics", since = "1.59.0")
2008)]
2009#[cfg_attr(
2010 target_arch = "arm",
2011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2012)]
2013pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2014 unsafe { simd_and(a, b) }
2015}
2016#[doc = "Floating-point absolute compare greater than or equal"]
2017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
2018#[inline]
2019#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2020#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
2021#[cfg_attr(
2022 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2023 assert_instr(facge)
2024)]
2025#[target_feature(enable = "neon,fp16")]
2026#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2027pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
2028 unsafe extern "unadjusted" {
2029 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i16.v4f16")]
2030 #[cfg_attr(
2031 any(target_arch = "aarch64", target_arch = "arm64ec"),
2032 link_name = "llvm.aarch64.neon.facge.v4i16.v4f16"
2033 )]
2034 fn _vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
2035 }
2036 unsafe { _vcage_f16(a, b) }
2037}
2038#[doc = "Floating-point absolute compare greater than or equal"]
2039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
2040#[inline]
2041#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2042#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
2043#[cfg_attr(
2044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2045 assert_instr(facge)
2046)]
2047#[target_feature(enable = "neon,fp16")]
2048#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2049pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
2050 unsafe extern "unadjusted" {
2051 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v8i16.v8f16")]
2052 #[cfg_attr(
2053 any(target_arch = "aarch64", target_arch = "arm64ec"),
2054 link_name = "llvm.aarch64.neon.facge.v8i16.v8f16"
2055 )]
2056 fn _vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
2057 }
2058 unsafe { _vcageq_f16(a, b) }
2059}
2060#[doc = "Floating-point absolute compare greater than or equal"]
2061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
2062#[inline]
2063#[target_feature(enable = "neon")]
2064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
2066#[cfg_attr(
2067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2068 assert_instr(facge)
2069)]
2070#[cfg_attr(
2071 not(target_arch = "arm"),
2072 stable(feature = "neon_intrinsics", since = "1.59.0")
2073)]
2074#[cfg_attr(
2075 target_arch = "arm",
2076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2077)]
2078pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
2079 unsafe extern "unadjusted" {
2080 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")]
2081 #[cfg_attr(
2082 any(target_arch = "aarch64", target_arch = "arm64ec"),
2083 link_name = "llvm.aarch64.neon.facge.v2i32.v2f32"
2084 )]
2085 fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
2086 }
2087 unsafe { _vcage_f32(a, b) }
2088}
2089#[doc = "Floating-point absolute compare greater than or equal"]
2090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
2091#[inline]
2092#[target_feature(enable = "neon")]
2093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
2095#[cfg_attr(
2096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2097 assert_instr(facge)
2098)]
2099#[cfg_attr(
2100 not(target_arch = "arm"),
2101 stable(feature = "neon_intrinsics", since = "1.59.0")
2102)]
2103#[cfg_attr(
2104 target_arch = "arm",
2105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2106)]
2107pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
2108 unsafe extern "unadjusted" {
2109 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")]
2110 #[cfg_attr(
2111 any(target_arch = "aarch64", target_arch = "arm64ec"),
2112 link_name = "llvm.aarch64.neon.facge.v4i32.v4f32"
2113 )]
2114 fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
2115 }
2116 unsafe { _vcageq_f32(a, b) }
2117}
2118#[doc = "Floating-point absolute compare greater than"]
2119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
2120#[inline]
2121#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
2123#[cfg_attr(
2124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2125 assert_instr(facgt)
2126)]
2127#[target_feature(enable = "neon,fp16")]
2128#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2129pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
2130 unsafe extern "unadjusted" {
2131 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i16.v4f16")]
2132 #[cfg_attr(
2133 any(target_arch = "aarch64", target_arch = "arm64ec"),
2134 link_name = "llvm.aarch64.neon.facgt.v4i16.v4f16"
2135 )]
2136 fn _vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
2137 }
2138 unsafe { _vcagt_f16(a, b) }
2139}
2140#[doc = "Floating-point absolute compare greater than"]
2141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
2142#[inline]
2143#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2144#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
2145#[cfg_attr(
2146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2147 assert_instr(facgt)
2148)]
2149#[target_feature(enable = "neon,fp16")]
2150#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2151pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
2152 unsafe extern "unadjusted" {
2153 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v8i16.v8f16")]
2154 #[cfg_attr(
2155 any(target_arch = "aarch64", target_arch = "arm64ec"),
2156 link_name = "llvm.aarch64.neon.facgt.v8i16.v8f16"
2157 )]
2158 fn _vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
2159 }
2160 unsafe { _vcagtq_f16(a, b) }
2161}
2162#[doc = "Floating-point absolute compare greater than"]
2163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
2164#[inline]
2165#[target_feature(enable = "neon")]
2166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2167#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
2168#[cfg_attr(
2169 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2170 assert_instr(facgt)
2171)]
2172#[cfg_attr(
2173 not(target_arch = "arm"),
2174 stable(feature = "neon_intrinsics", since = "1.59.0")
2175)]
2176#[cfg_attr(
2177 target_arch = "arm",
2178 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2179)]
2180pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
2181 unsafe extern "unadjusted" {
2182 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")]
2183 #[cfg_attr(
2184 any(target_arch = "aarch64", target_arch = "arm64ec"),
2185 link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32"
2186 )]
2187 fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
2188 }
2189 unsafe { _vcagt_f32(a, b) }
2190}
2191#[doc = "Floating-point absolute compare greater than"]
2192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
2193#[inline]
2194#[target_feature(enable = "neon")]
2195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2196#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
2197#[cfg_attr(
2198 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2199 assert_instr(facgt)
2200)]
2201#[cfg_attr(
2202 not(target_arch = "arm"),
2203 stable(feature = "neon_intrinsics", since = "1.59.0")
2204)]
2205#[cfg_attr(
2206 target_arch = "arm",
2207 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2208)]
2209pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
2210 unsafe extern "unadjusted" {
2211 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")]
2212 #[cfg_attr(
2213 any(target_arch = "aarch64", target_arch = "arm64ec"),
2214 link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32"
2215 )]
2216 fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
2217 }
2218 unsafe { _vcagtq_f32(a, b) }
2219}
2220#[doc = "Floating-point absolute compare less than or equal"]
2221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
2222#[inline]
2223#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
2225#[cfg_attr(
2226 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2227 assert_instr(facge)
2228)]
2229#[target_feature(enable = "neon,fp16")]
2230#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2231pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
2232 vcage_f16(b, a)
2233}
2234#[doc = "Floating-point absolute compare less than or equal"]
2235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
2236#[inline]
2237#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
2239#[cfg_attr(
2240 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2241 assert_instr(facge)
2242)]
2243#[target_feature(enable = "neon,fp16")]
2244#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2245pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
2246 vcageq_f16(b, a)
2247}
2248#[doc = "Floating-point absolute compare less than or equal"]
2249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
2250#[inline]
2251#[target_feature(enable = "neon")]
2252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2253#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
2254#[cfg_attr(
2255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2256 assert_instr(facge)
2257)]
2258#[cfg_attr(
2259 not(target_arch = "arm"),
2260 stable(feature = "neon_intrinsics", since = "1.59.0")
2261)]
2262#[cfg_attr(
2263 target_arch = "arm",
2264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2265)]
2266pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
2267 vcage_f32(b, a)
2268}
2269#[doc = "Floating-point absolute compare less than or equal"]
2270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
2271#[inline]
2272#[target_feature(enable = "neon")]
2273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2274#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
2275#[cfg_attr(
2276 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2277 assert_instr(facge)
2278)]
2279#[cfg_attr(
2280 not(target_arch = "arm"),
2281 stable(feature = "neon_intrinsics", since = "1.59.0")
2282)]
2283#[cfg_attr(
2284 target_arch = "arm",
2285 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2286)]
2287pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
2288 vcageq_f32(b, a)
2289}
2290#[doc = "Floating-point absolute compare less than"]
2291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
2292#[inline]
2293#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2294#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
2295#[cfg_attr(
2296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2297 assert_instr(facgt)
2298)]
2299#[target_feature(enable = "neon,fp16")]
2300#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2301pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
2302 vcagt_f16(b, a)
2303}
2304#[doc = "Floating-point absolute compare less than"]
2305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
2306#[inline]
2307#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2308#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
2309#[cfg_attr(
2310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2311 assert_instr(facgt)
2312)]
2313#[target_feature(enable = "neon,fp16")]
2314#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2315pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
2316 vcagtq_f16(b, a)
2317}
2318#[doc = "Floating-point absolute compare less than"]
2319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
2320#[inline]
2321#[target_feature(enable = "neon")]
2322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2323#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
2324#[cfg_attr(
2325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2326 assert_instr(facgt)
2327)]
2328#[cfg_attr(
2329 not(target_arch = "arm"),
2330 stable(feature = "neon_intrinsics", since = "1.59.0")
2331)]
2332#[cfg_attr(
2333 target_arch = "arm",
2334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2335)]
2336pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
2337 vcagt_f32(b, a)
2338}
2339#[doc = "Floating-point absolute compare less than"]
2340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
2341#[inline]
2342#[target_feature(enable = "neon")]
2343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
2345#[cfg_attr(
2346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2347 assert_instr(facgt)
2348)]
2349#[cfg_attr(
2350 not(target_arch = "arm"),
2351 stable(feature = "neon_intrinsics", since = "1.59.0")
2352)]
2353#[cfg_attr(
2354 target_arch = "arm",
2355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2356)]
2357pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
2358 vcagtq_f32(b, a)
2359}
2360#[doc = "Floating-point compare equal"]
2361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
2362#[inline]
2363#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2364#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
2365#[cfg_attr(
2366 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2367 assert_instr(fcmeq)
2368)]
2369#[target_feature(enable = "neon,fp16")]
2370#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2371pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
2372 unsafe { simd_eq(a, b) }
2373}
2374#[doc = "Floating-point compare equal"]
2375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
2376#[inline]
2377#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
2379#[cfg_attr(
2380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2381 assert_instr(fcmeq)
2382)]
2383#[target_feature(enable = "neon,fp16")]
2384#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2385pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
2386 unsafe { simd_eq(a, b) }
2387}
2388#[doc = "Floating-point compare equal"]
2389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
2390#[inline]
2391#[target_feature(enable = "neon")]
2392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2393#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
2394#[cfg_attr(
2395 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2396 assert_instr(fcmeq)
2397)]
2398#[cfg_attr(
2399 not(target_arch = "arm"),
2400 stable(feature = "neon_intrinsics", since = "1.59.0")
2401)]
2402#[cfg_attr(
2403 target_arch = "arm",
2404 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2405)]
2406pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
2407 unsafe { simd_eq(a, b) }
2408}
2409#[doc = "Floating-point compare equal"]
2410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
2411#[inline]
2412#[target_feature(enable = "neon")]
2413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2414#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
2415#[cfg_attr(
2416 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2417 assert_instr(fcmeq)
2418)]
2419#[cfg_attr(
2420 not(target_arch = "arm"),
2421 stable(feature = "neon_intrinsics", since = "1.59.0")
2422)]
2423#[cfg_attr(
2424 target_arch = "arm",
2425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2426)]
2427pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
2428 unsafe { simd_eq(a, b) }
2429}
2430#[doc = "Compare bitwise Equal (vector)"]
2431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
2432#[inline]
2433#[target_feature(enable = "neon")]
2434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2435#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
2436#[cfg_attr(
2437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2438 assert_instr(cmeq)
2439)]
2440#[cfg_attr(
2441 not(target_arch = "arm"),
2442 stable(feature = "neon_intrinsics", since = "1.59.0")
2443)]
2444#[cfg_attr(
2445 target_arch = "arm",
2446 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2447)]
2448pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
2449 unsafe { simd_eq(a, b) }
2450}
2451#[doc = "Compare bitwise Equal (vector)"]
2452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
2453#[inline]
2454#[target_feature(enable = "neon")]
2455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2456#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
2457#[cfg_attr(
2458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2459 assert_instr(cmeq)
2460)]
2461#[cfg_attr(
2462 not(target_arch = "arm"),
2463 stable(feature = "neon_intrinsics", since = "1.59.0")
2464)]
2465#[cfg_attr(
2466 target_arch = "arm",
2467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2468)]
2469pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
2470 unsafe { simd_eq(a, b) }
2471}
2472#[doc = "Compare bitwise Equal (vector)"]
2473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
2474#[inline]
2475#[target_feature(enable = "neon")]
2476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2477#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
2478#[cfg_attr(
2479 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2480 assert_instr(cmeq)
2481)]
2482#[cfg_attr(
2483 not(target_arch = "arm"),
2484 stable(feature = "neon_intrinsics", since = "1.59.0")
2485)]
2486#[cfg_attr(
2487 target_arch = "arm",
2488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2489)]
2490pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
2491 unsafe { simd_eq(a, b) }
2492}
2493#[doc = "Compare bitwise Equal (vector)"]
2494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
2495#[inline]
2496#[target_feature(enable = "neon")]
2497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2498#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
2499#[cfg_attr(
2500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2501 assert_instr(cmeq)
2502)]
2503#[cfg_attr(
2504 not(target_arch = "arm"),
2505 stable(feature = "neon_intrinsics", since = "1.59.0")
2506)]
2507#[cfg_attr(
2508 target_arch = "arm",
2509 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2510)]
2511pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
2512 unsafe { simd_eq(a, b) }
2513}
2514#[doc = "Compare bitwise Equal (vector)"]
2515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
2516#[inline]
2517#[target_feature(enable = "neon")]
2518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2519#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
2520#[cfg_attr(
2521 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2522 assert_instr(cmeq)
2523)]
2524#[cfg_attr(
2525 not(target_arch = "arm"),
2526 stable(feature = "neon_intrinsics", since = "1.59.0")
2527)]
2528#[cfg_attr(
2529 target_arch = "arm",
2530 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2531)]
2532pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
2533 unsafe { simd_eq(a, b) }
2534}
2535#[doc = "Compare bitwise Equal (vector)"]
2536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
2537#[inline]
2538#[target_feature(enable = "neon")]
2539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
2541#[cfg_attr(
2542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2543 assert_instr(cmeq)
2544)]
2545#[cfg_attr(
2546 not(target_arch = "arm"),
2547 stable(feature = "neon_intrinsics", since = "1.59.0")
2548)]
2549#[cfg_attr(
2550 target_arch = "arm",
2551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2552)]
2553pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
2554 unsafe { simd_eq(a, b) }
2555}
2556#[doc = "Compare bitwise Equal (vector)"]
2557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
2558#[inline]
2559#[target_feature(enable = "neon")]
2560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2561#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
2562#[cfg_attr(
2563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2564 assert_instr(cmeq)
2565)]
2566#[cfg_attr(
2567 not(target_arch = "arm"),
2568 stable(feature = "neon_intrinsics", since = "1.59.0")
2569)]
2570#[cfg_attr(
2571 target_arch = "arm",
2572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2573)]
2574pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
2575 unsafe { simd_eq(a, b) }
2576}
2577#[doc = "Compare bitwise Equal (vector)"]
2578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
2579#[inline]
2580#[target_feature(enable = "neon")]
2581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
2583#[cfg_attr(
2584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2585 assert_instr(cmeq)
2586)]
2587#[cfg_attr(
2588 not(target_arch = "arm"),
2589 stable(feature = "neon_intrinsics", since = "1.59.0")
2590)]
2591#[cfg_attr(
2592 target_arch = "arm",
2593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2594)]
2595pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
2596 unsafe { simd_eq(a, b) }
2597}
2598#[doc = "Compare bitwise Equal (vector)"]
2599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
2600#[inline]
2601#[target_feature(enable = "neon")]
2602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2603#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
2604#[cfg_attr(
2605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2606 assert_instr(cmeq)
2607)]
2608#[cfg_attr(
2609 not(target_arch = "arm"),
2610 stable(feature = "neon_intrinsics", since = "1.59.0")
2611)]
2612#[cfg_attr(
2613 target_arch = "arm",
2614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2615)]
2616pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
2617 unsafe { simd_eq(a, b) }
2618}
2619#[doc = "Compare bitwise Equal (vector)"]
2620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
2621#[inline]
2622#[target_feature(enable = "neon")]
2623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2624#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
2625#[cfg_attr(
2626 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2627 assert_instr(cmeq)
2628)]
2629#[cfg_attr(
2630 not(target_arch = "arm"),
2631 stable(feature = "neon_intrinsics", since = "1.59.0")
2632)]
2633#[cfg_attr(
2634 target_arch = "arm",
2635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2636)]
2637pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
2638 unsafe { simd_eq(a, b) }
2639}
2640#[doc = "Compare bitwise Equal (vector)"]
2641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
2642#[inline]
2643#[target_feature(enable = "neon")]
2644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2645#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
2646#[cfg_attr(
2647 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2648 assert_instr(cmeq)
2649)]
2650#[cfg_attr(
2651 not(target_arch = "arm"),
2652 stable(feature = "neon_intrinsics", since = "1.59.0")
2653)]
2654#[cfg_attr(
2655 target_arch = "arm",
2656 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2657)]
2658pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
2659 unsafe { simd_eq(a, b) }
2660}
2661#[doc = "Compare bitwise Equal (vector)"]
2662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
2663#[inline]
2664#[target_feature(enable = "neon")]
2665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2666#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
2667#[cfg_attr(
2668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2669 assert_instr(cmeq)
2670)]
2671#[cfg_attr(
2672 not(target_arch = "arm"),
2673 stable(feature = "neon_intrinsics", since = "1.59.0")
2674)]
2675#[cfg_attr(
2676 target_arch = "arm",
2677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2678)]
2679pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
2680 unsafe { simd_eq(a, b) }
2681}
2682#[doc = "Compare bitwise Equal (vector)"]
2683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
2684#[inline]
2685#[target_feature(enable = "neon")]
2686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2687#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
2688#[cfg_attr(
2689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2690 assert_instr(cmeq)
2691)]
2692#[cfg_attr(
2693 not(target_arch = "arm"),
2694 stable(feature = "neon_intrinsics", since = "1.59.0")
2695)]
2696#[cfg_attr(
2697 target_arch = "arm",
2698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2699)]
2700pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
2701 unsafe { simd_eq(a, b) }
2702}
2703#[doc = "Compare bitwise Equal (vector)"]
2704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
2705#[inline]
2706#[target_feature(enable = "neon")]
2707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2708#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
2709#[cfg_attr(
2710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2711 assert_instr(cmeq)
2712)]
2713#[cfg_attr(
2714 not(target_arch = "arm"),
2715 stable(feature = "neon_intrinsics", since = "1.59.0")
2716)]
2717#[cfg_attr(
2718 target_arch = "arm",
2719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2720)]
2721pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
2722 unsafe { simd_eq(a, b) }
2723}
2724#[doc = "Floating-point compare greater than or equal"]
2725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
2726#[inline]
2727#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2728#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
2729#[cfg_attr(
2730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2731 assert_instr(fcmge)
2732)]
2733#[target_feature(enable = "neon,fp16")]
2734#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2735pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
2736 unsafe { simd_ge(a, b) }
2737}
2738#[doc = "Floating-point compare greater than or equal"]
2739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
2740#[inline]
2741#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
2743#[cfg_attr(
2744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2745 assert_instr(fcmge)
2746)]
2747#[target_feature(enable = "neon,fp16")]
2748#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2749pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
2750 unsafe { simd_ge(a, b) }
2751}
2752#[doc = "Floating-point compare greater than or equal"]
2753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
2754#[inline]
2755#[target_feature(enable = "neon")]
2756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2757#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
2758#[cfg_attr(
2759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2760 assert_instr(fcmge)
2761)]
2762#[cfg_attr(
2763 not(target_arch = "arm"),
2764 stable(feature = "neon_intrinsics", since = "1.59.0")
2765)]
2766#[cfg_attr(
2767 target_arch = "arm",
2768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2769)]
2770pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
2771 unsafe { simd_ge(a, b) }
2772}
2773#[doc = "Floating-point compare greater than or equal"]
2774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
2775#[inline]
2776#[target_feature(enable = "neon")]
2777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
2779#[cfg_attr(
2780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2781 assert_instr(fcmge)
2782)]
2783#[cfg_attr(
2784 not(target_arch = "arm"),
2785 stable(feature = "neon_intrinsics", since = "1.59.0")
2786)]
2787#[cfg_attr(
2788 target_arch = "arm",
2789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2790)]
2791pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
2792 unsafe { simd_ge(a, b) }
2793}
2794#[doc = "Compare signed greater than or equal"]
2795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
2796#[inline]
2797#[target_feature(enable = "neon")]
2798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2799#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
2800#[cfg_attr(
2801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2802 assert_instr(cmge)
2803)]
2804#[cfg_attr(
2805 not(target_arch = "arm"),
2806 stable(feature = "neon_intrinsics", since = "1.59.0")
2807)]
2808#[cfg_attr(
2809 target_arch = "arm",
2810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2811)]
2812pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
2813 unsafe { simd_ge(a, b) }
2814}
2815#[doc = "Compare signed greater than or equal"]
2816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
2817#[inline]
2818#[target_feature(enable = "neon")]
2819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2820#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
2821#[cfg_attr(
2822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2823 assert_instr(cmge)
2824)]
2825#[cfg_attr(
2826 not(target_arch = "arm"),
2827 stable(feature = "neon_intrinsics", since = "1.59.0")
2828)]
2829#[cfg_attr(
2830 target_arch = "arm",
2831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2832)]
2833pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
2834 unsafe { simd_ge(a, b) }
2835}
2836#[doc = "Compare signed greater than or equal"]
2837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
2838#[inline]
2839#[target_feature(enable = "neon")]
2840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2841#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
2842#[cfg_attr(
2843 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2844 assert_instr(cmge)
2845)]
2846#[cfg_attr(
2847 not(target_arch = "arm"),
2848 stable(feature = "neon_intrinsics", since = "1.59.0")
2849)]
2850#[cfg_attr(
2851 target_arch = "arm",
2852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2853)]
2854pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
2855 unsafe { simd_ge(a, b) }
2856}
2857#[doc = "Compare signed greater than or equal"]
2858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
2859#[inline]
2860#[target_feature(enable = "neon")]
2861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2862#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
2863#[cfg_attr(
2864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2865 assert_instr(cmge)
2866)]
2867#[cfg_attr(
2868 not(target_arch = "arm"),
2869 stable(feature = "neon_intrinsics", since = "1.59.0")
2870)]
2871#[cfg_attr(
2872 target_arch = "arm",
2873 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2874)]
2875pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
2876 unsafe { simd_ge(a, b) }
2877}
2878#[doc = "Compare signed greater than or equal"]
2879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
2880#[inline]
2881#[target_feature(enable = "neon")]
2882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2883#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
2884#[cfg_attr(
2885 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2886 assert_instr(cmge)
2887)]
2888#[cfg_attr(
2889 not(target_arch = "arm"),
2890 stable(feature = "neon_intrinsics", since = "1.59.0")
2891)]
2892#[cfg_attr(
2893 target_arch = "arm",
2894 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2895)]
2896pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
2897 unsafe { simd_ge(a, b) }
2898}
2899#[doc = "Compare signed greater than or equal"]
2900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
2901#[inline]
2902#[target_feature(enable = "neon")]
2903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2904#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
2905#[cfg_attr(
2906 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2907 assert_instr(cmge)
2908)]
2909#[cfg_attr(
2910 not(target_arch = "arm"),
2911 stable(feature = "neon_intrinsics", since = "1.59.0")
2912)]
2913#[cfg_attr(
2914 target_arch = "arm",
2915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2916)]
2917pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
2918 unsafe { simd_ge(a, b) }
2919}
2920#[doc = "Compare unsigned greater than or equal"]
2921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
2922#[inline]
2923#[target_feature(enable = "neon")]
2924#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2925#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
2926#[cfg_attr(
2927 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2928 assert_instr(cmhs)
2929)]
2930#[cfg_attr(
2931 not(target_arch = "arm"),
2932 stable(feature = "neon_intrinsics", since = "1.59.0")
2933)]
2934#[cfg_attr(
2935 target_arch = "arm",
2936 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2937)]
2938pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
2939 unsafe { simd_ge(a, b) }
2940}
2941#[doc = "Compare unsigned greater than or equal"]
2942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
2943#[inline]
2944#[target_feature(enable = "neon")]
2945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2946#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
2947#[cfg_attr(
2948 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2949 assert_instr(cmhs)
2950)]
2951#[cfg_attr(
2952 not(target_arch = "arm"),
2953 stable(feature = "neon_intrinsics", since = "1.59.0")
2954)]
2955#[cfg_attr(
2956 target_arch = "arm",
2957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2958)]
2959pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
2960 unsafe { simd_ge(a, b) }
2961}
2962#[doc = "Compare unsigned greater than or equal"]
2963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
2964#[inline]
2965#[target_feature(enable = "neon")]
2966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2967#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
2968#[cfg_attr(
2969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2970 assert_instr(cmhs)
2971)]
2972#[cfg_attr(
2973 not(target_arch = "arm"),
2974 stable(feature = "neon_intrinsics", since = "1.59.0")
2975)]
2976#[cfg_attr(
2977 target_arch = "arm",
2978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2979)]
2980pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
2981 unsafe { simd_ge(a, b) }
2982}
2983#[doc = "Compare unsigned greater than or equal"]
2984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
2985#[inline]
2986#[target_feature(enable = "neon")]
2987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
2989#[cfg_attr(
2990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2991 assert_instr(cmhs)
2992)]
2993#[cfg_attr(
2994 not(target_arch = "arm"),
2995 stable(feature = "neon_intrinsics", since = "1.59.0")
2996)]
2997#[cfg_attr(
2998 target_arch = "arm",
2999 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3000)]
3001pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3002 unsafe { simd_ge(a, b) }
3003}
3004#[doc = "Compare unsigned greater than or equal"]
3005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
3006#[inline]
3007#[target_feature(enable = "neon")]
3008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
3010#[cfg_attr(
3011 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3012 assert_instr(cmhs)
3013)]
3014#[cfg_attr(
3015 not(target_arch = "arm"),
3016 stable(feature = "neon_intrinsics", since = "1.59.0")
3017)]
3018#[cfg_attr(
3019 target_arch = "arm",
3020 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3021)]
3022pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3023 unsafe { simd_ge(a, b) }
3024}
3025#[doc = "Compare unsigned greater than or equal"]
3026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
3027#[inline]
3028#[target_feature(enable = "neon")]
3029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3030#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
3031#[cfg_attr(
3032 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3033 assert_instr(cmhs)
3034)]
3035#[cfg_attr(
3036 not(target_arch = "arm"),
3037 stable(feature = "neon_intrinsics", since = "1.59.0")
3038)]
3039#[cfg_attr(
3040 target_arch = "arm",
3041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3042)]
3043pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3044 unsafe { simd_ge(a, b) }
3045}
3046#[doc = "Floating-point compare greater than or equal to zero"]
3047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
3048#[inline]
3049#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3050#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
3051#[cfg_attr(
3052 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3053 assert_instr(fcmge)
3054)]
3055#[target_feature(enable = "neon,fp16")]
3056#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3057pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
3058 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
3059 unsafe { simd_ge(a, transmute(b)) }
3060}
3061#[doc = "Floating-point compare greater than or equal to zero"]
3062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
3063#[inline]
3064#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
3066#[cfg_attr(
3067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3068 assert_instr(fcmge)
3069)]
3070#[target_feature(enable = "neon,fp16")]
3071#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3072pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
3073 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
3074 unsafe { simd_ge(a, transmute(b)) }
3075}
3076#[doc = "Floating-point compare greater than"]
3077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
3078#[inline]
3079#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3080#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
3081#[cfg_attr(
3082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3083 assert_instr(fcmgt)
3084)]
3085#[target_feature(enable = "neon,fp16")]
3086#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3087pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
3088 unsafe { simd_gt(a, b) }
3089}
3090#[doc = "Floating-point compare greater than"]
3091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
3092#[inline]
3093#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
3095#[cfg_attr(
3096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3097 assert_instr(fcmgt)
3098)]
3099#[target_feature(enable = "neon,fp16")]
3100#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3101pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
3102 unsafe { simd_gt(a, b) }
3103}
3104#[doc = "Floating-point compare greater than"]
3105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
3106#[inline]
3107#[target_feature(enable = "neon")]
3108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3109#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
3110#[cfg_attr(
3111 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3112 assert_instr(fcmgt)
3113)]
3114#[cfg_attr(
3115 not(target_arch = "arm"),
3116 stable(feature = "neon_intrinsics", since = "1.59.0")
3117)]
3118#[cfg_attr(
3119 target_arch = "arm",
3120 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3121)]
3122pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
3123 unsafe { simd_gt(a, b) }
3124}
3125#[doc = "Floating-point compare greater than"]
3126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
3127#[inline]
3128#[target_feature(enable = "neon")]
3129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3130#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
3131#[cfg_attr(
3132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3133 assert_instr(fcmgt)
3134)]
3135#[cfg_attr(
3136 not(target_arch = "arm"),
3137 stable(feature = "neon_intrinsics", since = "1.59.0")
3138)]
3139#[cfg_attr(
3140 target_arch = "arm",
3141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3142)]
3143pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
3144 unsafe { simd_gt(a, b) }
3145}
3146#[doc = "Compare signed greater than"]
3147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
3148#[inline]
3149#[target_feature(enable = "neon")]
3150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
3152#[cfg_attr(
3153 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3154 assert_instr(cmgt)
3155)]
3156#[cfg_attr(
3157 not(target_arch = "arm"),
3158 stable(feature = "neon_intrinsics", since = "1.59.0")
3159)]
3160#[cfg_attr(
3161 target_arch = "arm",
3162 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3163)]
3164pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
3165 unsafe { simd_gt(a, b) }
3166}
3167#[doc = "Compare signed greater than"]
3168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
3169#[inline]
3170#[target_feature(enable = "neon")]
3171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3172#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
3173#[cfg_attr(
3174 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3175 assert_instr(cmgt)
3176)]
3177#[cfg_attr(
3178 not(target_arch = "arm"),
3179 stable(feature = "neon_intrinsics", since = "1.59.0")
3180)]
3181#[cfg_attr(
3182 target_arch = "arm",
3183 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3184)]
3185pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
3186 unsafe { simd_gt(a, b) }
3187}
3188#[doc = "Compare signed greater than"]
3189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
3190#[inline]
3191#[target_feature(enable = "neon")]
3192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3193#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
3194#[cfg_attr(
3195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3196 assert_instr(cmgt)
3197)]
3198#[cfg_attr(
3199 not(target_arch = "arm"),
3200 stable(feature = "neon_intrinsics", since = "1.59.0")
3201)]
3202#[cfg_attr(
3203 target_arch = "arm",
3204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3205)]
3206pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
3207 unsafe { simd_gt(a, b) }
3208}
3209#[doc = "Compare signed greater than"]
3210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
3211#[inline]
3212#[target_feature(enable = "neon")]
3213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3214#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
3215#[cfg_attr(
3216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3217 assert_instr(cmgt)
3218)]
3219#[cfg_attr(
3220 not(target_arch = "arm"),
3221 stable(feature = "neon_intrinsics", since = "1.59.0")
3222)]
3223#[cfg_attr(
3224 target_arch = "arm",
3225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3226)]
3227pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
3228 unsafe { simd_gt(a, b) }
3229}
3230#[doc = "Compare signed greater than"]
3231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
3232#[inline]
3233#[target_feature(enable = "neon")]
3234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3235#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
3236#[cfg_attr(
3237 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3238 assert_instr(cmgt)
3239)]
3240#[cfg_attr(
3241 not(target_arch = "arm"),
3242 stable(feature = "neon_intrinsics", since = "1.59.0")
3243)]
3244#[cfg_attr(
3245 target_arch = "arm",
3246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3247)]
3248pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
3249 unsafe { simd_gt(a, b) }
3250}
3251#[doc = "Compare signed greater than"]
3252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
3253#[inline]
3254#[target_feature(enable = "neon")]
3255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
3257#[cfg_attr(
3258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3259 assert_instr(cmgt)
3260)]
3261#[cfg_attr(
3262 not(target_arch = "arm"),
3263 stable(feature = "neon_intrinsics", since = "1.59.0")
3264)]
3265#[cfg_attr(
3266 target_arch = "arm",
3267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3268)]
3269pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
3270 unsafe { simd_gt(a, b) }
3271}
3272#[doc = "Compare unsigned greater than"]
3273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
3274#[inline]
3275#[target_feature(enable = "neon")]
3276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3277#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
3278#[cfg_attr(
3279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3280 assert_instr(cmhi)
3281)]
3282#[cfg_attr(
3283 not(target_arch = "arm"),
3284 stable(feature = "neon_intrinsics", since = "1.59.0")
3285)]
3286#[cfg_attr(
3287 target_arch = "arm",
3288 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3289)]
3290pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3291 unsafe { simd_gt(a, b) }
3292}
3293#[doc = "Compare unsigned greater than"]
3294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
3295#[inline]
3296#[target_feature(enable = "neon")]
3297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3298#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
3299#[cfg_attr(
3300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3301 assert_instr(cmhi)
3302)]
3303#[cfg_attr(
3304 not(target_arch = "arm"),
3305 stable(feature = "neon_intrinsics", since = "1.59.0")
3306)]
3307#[cfg_attr(
3308 target_arch = "arm",
3309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3310)]
3311pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3312 unsafe { simd_gt(a, b) }
3313}
3314#[doc = "Compare unsigned greater than"]
3315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
3316#[inline]
3317#[target_feature(enable = "neon")]
3318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3319#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
3320#[cfg_attr(
3321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3322 assert_instr(cmhi)
3323)]
3324#[cfg_attr(
3325 not(target_arch = "arm"),
3326 stable(feature = "neon_intrinsics", since = "1.59.0")
3327)]
3328#[cfg_attr(
3329 target_arch = "arm",
3330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3331)]
3332pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3333 unsafe { simd_gt(a, b) }
3334}
3335#[doc = "Compare unsigned greater than"]
3336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
3337#[inline]
3338#[target_feature(enable = "neon")]
3339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
3341#[cfg_attr(
3342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3343 assert_instr(cmhi)
3344)]
3345#[cfg_attr(
3346 not(target_arch = "arm"),
3347 stable(feature = "neon_intrinsics", since = "1.59.0")
3348)]
3349#[cfg_attr(
3350 target_arch = "arm",
3351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3352)]
3353pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3354 unsafe { simd_gt(a, b) }
3355}
3356#[doc = "Compare unsigned greater than"]
3357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
3358#[inline]
3359#[target_feature(enable = "neon")]
3360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
3362#[cfg_attr(
3363 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3364 assert_instr(cmhi)
3365)]
3366#[cfg_attr(
3367 not(target_arch = "arm"),
3368 stable(feature = "neon_intrinsics", since = "1.59.0")
3369)]
3370#[cfg_attr(
3371 target_arch = "arm",
3372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3373)]
3374pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3375 unsafe { simd_gt(a, b) }
3376}
3377#[doc = "Compare unsigned greater than"]
3378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
3379#[inline]
3380#[target_feature(enable = "neon")]
3381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3382#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
3383#[cfg_attr(
3384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3385 assert_instr(cmhi)
3386)]
3387#[cfg_attr(
3388 not(target_arch = "arm"),
3389 stable(feature = "neon_intrinsics", since = "1.59.0")
3390)]
3391#[cfg_attr(
3392 target_arch = "arm",
3393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3394)]
3395pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3396 unsafe { simd_gt(a, b) }
3397}
3398#[doc = "Floating-point compare greater than zero"]
3399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
3400#[inline]
3401#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
3403#[cfg_attr(
3404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3405 assert_instr(fcmgt)
3406)]
3407#[target_feature(enable = "neon,fp16")]
3408#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3409pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
3410 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
3411 unsafe { simd_gt(a, transmute(b)) }
3412}
3413#[doc = "Floating-point compare greater than zero"]
3414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
3415#[inline]
3416#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3417#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
3418#[cfg_attr(
3419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3420 assert_instr(fcmgt)
3421)]
3422#[target_feature(enable = "neon,fp16")]
3423#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3424pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
3425 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
3426 unsafe { simd_gt(a, transmute(b)) }
3427}
3428#[doc = "Floating-point compare less than or equal"]
3429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
3430#[inline]
3431#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3432#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
3433#[cfg_attr(
3434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3435 assert_instr(fcmge)
3436)]
3437#[target_feature(enable = "neon,fp16")]
3438#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3439pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
3440 unsafe { simd_le(a, b) }
3441}
3442#[doc = "Floating-point compare less than or equal"]
3443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
3444#[inline]
3445#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3446#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
3447#[cfg_attr(
3448 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3449 assert_instr(fcmge)
3450)]
3451#[target_feature(enable = "neon,fp16")]
3452#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3453pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
3454 unsafe { simd_le(a, b) }
3455}
3456#[doc = "Floating-point compare less than or equal"]
3457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
3458#[inline]
3459#[target_feature(enable = "neon")]
3460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3461#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
3462#[cfg_attr(
3463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3464 assert_instr(fcmge)
3465)]
3466#[cfg_attr(
3467 not(target_arch = "arm"),
3468 stable(feature = "neon_intrinsics", since = "1.59.0")
3469)]
3470#[cfg_attr(
3471 target_arch = "arm",
3472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3473)]
3474pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
3475 unsafe { simd_le(a, b) }
3476}
3477#[doc = "Floating-point compare less than or equal"]
3478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
3479#[inline]
3480#[target_feature(enable = "neon")]
3481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3482#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
3483#[cfg_attr(
3484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3485 assert_instr(fcmge)
3486)]
3487#[cfg_attr(
3488 not(target_arch = "arm"),
3489 stable(feature = "neon_intrinsics", since = "1.59.0")
3490)]
3491#[cfg_attr(
3492 target_arch = "arm",
3493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3494)]
3495pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
3496 unsafe { simd_le(a, b) }
3497}
3498#[doc = "Compare signed less than or equal"]
3499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
3500#[inline]
3501#[target_feature(enable = "neon")]
3502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
3504#[cfg_attr(
3505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3506 assert_instr(cmge)
3507)]
3508#[cfg_attr(
3509 not(target_arch = "arm"),
3510 stable(feature = "neon_intrinsics", since = "1.59.0")
3511)]
3512#[cfg_attr(
3513 target_arch = "arm",
3514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3515)]
3516pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
3517 unsafe { simd_le(a, b) }
3518}
3519#[doc = "Compare signed less than or equal"]
3520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
3521#[inline]
3522#[target_feature(enable = "neon")]
3523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3524#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
3525#[cfg_attr(
3526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3527 assert_instr(cmge)
3528)]
3529#[cfg_attr(
3530 not(target_arch = "arm"),
3531 stable(feature = "neon_intrinsics", since = "1.59.0")
3532)]
3533#[cfg_attr(
3534 target_arch = "arm",
3535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3536)]
3537pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
3538 unsafe { simd_le(a, b) }
3539}
3540#[doc = "Compare signed less than or equal"]
3541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
3542#[inline]
3543#[target_feature(enable = "neon")]
3544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3545#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
3546#[cfg_attr(
3547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3548 assert_instr(cmge)
3549)]
3550#[cfg_attr(
3551 not(target_arch = "arm"),
3552 stable(feature = "neon_intrinsics", since = "1.59.0")
3553)]
3554#[cfg_attr(
3555 target_arch = "arm",
3556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3557)]
3558pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
3559 unsafe { simd_le(a, b) }
3560}
3561#[doc = "Compare signed less than or equal"]
3562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
3563#[inline]
3564#[target_feature(enable = "neon")]
3565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3566#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
3567#[cfg_attr(
3568 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3569 assert_instr(cmge)
3570)]
3571#[cfg_attr(
3572 not(target_arch = "arm"),
3573 stable(feature = "neon_intrinsics", since = "1.59.0")
3574)]
3575#[cfg_attr(
3576 target_arch = "arm",
3577 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3578)]
3579pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
3580 unsafe { simd_le(a, b) }
3581}
3582#[doc = "Compare signed less than or equal"]
3583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
3584#[inline]
3585#[target_feature(enable = "neon")]
3586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3587#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
3588#[cfg_attr(
3589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3590 assert_instr(cmge)
3591)]
3592#[cfg_attr(
3593 not(target_arch = "arm"),
3594 stable(feature = "neon_intrinsics", since = "1.59.0")
3595)]
3596#[cfg_attr(
3597 target_arch = "arm",
3598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3599)]
3600pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
3601 unsafe { simd_le(a, b) }
3602}
3603#[doc = "Compare signed less than or equal"]
3604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
3605#[inline]
3606#[target_feature(enable = "neon")]
3607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3608#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
3609#[cfg_attr(
3610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3611 assert_instr(cmge)
3612)]
3613#[cfg_attr(
3614 not(target_arch = "arm"),
3615 stable(feature = "neon_intrinsics", since = "1.59.0")
3616)]
3617#[cfg_attr(
3618 target_arch = "arm",
3619 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3620)]
3621pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
3622 unsafe { simd_le(a, b) }
3623}
3624#[doc = "Compare unsigned less than or equal"]
3625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
3626#[inline]
3627#[target_feature(enable = "neon")]
3628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3629#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
3630#[cfg_attr(
3631 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3632 assert_instr(cmhs)
3633)]
3634#[cfg_attr(
3635 not(target_arch = "arm"),
3636 stable(feature = "neon_intrinsics", since = "1.59.0")
3637)]
3638#[cfg_attr(
3639 target_arch = "arm",
3640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3641)]
3642pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3643 unsafe { simd_le(a, b) }
3644}
3645#[doc = "Compare unsigned less than or equal"]
3646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
3647#[inline]
3648#[target_feature(enable = "neon")]
3649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3650#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
3651#[cfg_attr(
3652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3653 assert_instr(cmhs)
3654)]
3655#[cfg_attr(
3656 not(target_arch = "arm"),
3657 stable(feature = "neon_intrinsics", since = "1.59.0")
3658)]
3659#[cfg_attr(
3660 target_arch = "arm",
3661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3662)]
3663pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3664 unsafe { simd_le(a, b) }
3665}
3666#[doc = "Compare unsigned less than or equal"]
3667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
3668#[inline]
3669#[target_feature(enable = "neon")]
3670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
3672#[cfg_attr(
3673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3674 assert_instr(cmhs)
3675)]
3676#[cfg_attr(
3677 not(target_arch = "arm"),
3678 stable(feature = "neon_intrinsics", since = "1.59.0")
3679)]
3680#[cfg_attr(
3681 target_arch = "arm",
3682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3683)]
3684pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3685 unsafe { simd_le(a, b) }
3686}
3687#[doc = "Compare unsigned less than or equal"]
3688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
3689#[inline]
3690#[target_feature(enable = "neon")]
3691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3692#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
3693#[cfg_attr(
3694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3695 assert_instr(cmhs)
3696)]
3697#[cfg_attr(
3698 not(target_arch = "arm"),
3699 stable(feature = "neon_intrinsics", since = "1.59.0")
3700)]
3701#[cfg_attr(
3702 target_arch = "arm",
3703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3704)]
3705pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3706 unsafe { simd_le(a, b) }
3707}
3708#[doc = "Compare unsigned less than or equal"]
3709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
3710#[inline]
3711#[target_feature(enable = "neon")]
3712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3713#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
3714#[cfg_attr(
3715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3716 assert_instr(cmhs)
3717)]
3718#[cfg_attr(
3719 not(target_arch = "arm"),
3720 stable(feature = "neon_intrinsics", since = "1.59.0")
3721)]
3722#[cfg_attr(
3723 target_arch = "arm",
3724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3725)]
3726pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3727 unsafe { simd_le(a, b) }
3728}
3729#[doc = "Compare unsigned less than or equal"]
3730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
3731#[inline]
3732#[target_feature(enable = "neon")]
3733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3734#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
3735#[cfg_attr(
3736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3737 assert_instr(cmhs)
3738)]
3739#[cfg_attr(
3740 not(target_arch = "arm"),
3741 stable(feature = "neon_intrinsics", since = "1.59.0")
3742)]
3743#[cfg_attr(
3744 target_arch = "arm",
3745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3746)]
3747pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3748 unsafe { simd_le(a, b) }
3749}
3750#[doc = "Floating-point compare less than or equal to zero"]
3751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
3752#[inline]
3753#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3754#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
3755#[cfg_attr(
3756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3757 assert_instr(fcmle)
3758)]
3759#[target_feature(enable = "neon,fp16")]
3760#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3761pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
3762 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
3763 unsafe { simd_le(a, transmute(b)) }
3764}
3765#[doc = "Floating-point compare less than or equal to zero"]
3766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
3767#[inline]
3768#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3769#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
3770#[cfg_attr(
3771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3772 assert_instr(fcmle)
3773)]
3774#[target_feature(enable = "neon,fp16")]
3775#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3776pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
3777 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
3778 unsafe { simd_le(a, transmute(b)) }
3779}
3780#[doc = "Count leading sign bits"]
3781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
3782#[inline]
3783#[target_feature(enable = "neon")]
3784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3785#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
3786#[cfg_attr(
3787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3788 assert_instr(cls)
3789)]
3790#[cfg_attr(
3791 not(target_arch = "arm"),
3792 stable(feature = "neon_intrinsics", since = "1.59.0")
3793)]
3794#[cfg_attr(
3795 target_arch = "arm",
3796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3797)]
3798pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
3799 unsafe extern "unadjusted" {
3800 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")]
3801 #[cfg_attr(
3802 any(target_arch = "aarch64", target_arch = "arm64ec"),
3803 link_name = "llvm.aarch64.neon.cls.v8i8"
3804 )]
3805 fn _vcls_s8(a: int8x8_t) -> int8x8_t;
3806 }
3807 unsafe { _vcls_s8(a) }
3808}
3809#[doc = "Count leading sign bits"]
3810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
3811#[inline]
3812#[target_feature(enable = "neon")]
3813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3814#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
3815#[cfg_attr(
3816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3817 assert_instr(cls)
3818)]
3819#[cfg_attr(
3820 not(target_arch = "arm"),
3821 stable(feature = "neon_intrinsics", since = "1.59.0")
3822)]
3823#[cfg_attr(
3824 target_arch = "arm",
3825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3826)]
3827pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
3828 unsafe extern "unadjusted" {
3829 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")]
3830 #[cfg_attr(
3831 any(target_arch = "aarch64", target_arch = "arm64ec"),
3832 link_name = "llvm.aarch64.neon.cls.v16i8"
3833 )]
3834 fn _vclsq_s8(a: int8x16_t) -> int8x16_t;
3835 }
3836 unsafe { _vclsq_s8(a) }
3837}
3838#[doc = "Count leading sign bits"]
3839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
3840#[inline]
3841#[target_feature(enable = "neon")]
3842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3843#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
3844#[cfg_attr(
3845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3846 assert_instr(cls)
3847)]
3848#[cfg_attr(
3849 not(target_arch = "arm"),
3850 stable(feature = "neon_intrinsics", since = "1.59.0")
3851)]
3852#[cfg_attr(
3853 target_arch = "arm",
3854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3855)]
3856pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
3857 unsafe extern "unadjusted" {
3858 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")]
3859 #[cfg_attr(
3860 any(target_arch = "aarch64", target_arch = "arm64ec"),
3861 link_name = "llvm.aarch64.neon.cls.v4i16"
3862 )]
3863 fn _vcls_s16(a: int16x4_t) -> int16x4_t;
3864 }
3865 unsafe { _vcls_s16(a) }
3866}
3867#[doc = "Count leading sign bits"]
3868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
3869#[inline]
3870#[target_feature(enable = "neon")]
3871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3872#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
3873#[cfg_attr(
3874 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3875 assert_instr(cls)
3876)]
3877#[cfg_attr(
3878 not(target_arch = "arm"),
3879 stable(feature = "neon_intrinsics", since = "1.59.0")
3880)]
3881#[cfg_attr(
3882 target_arch = "arm",
3883 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3884)]
3885pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
3886 unsafe extern "unadjusted" {
3887 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")]
3888 #[cfg_attr(
3889 any(target_arch = "aarch64", target_arch = "arm64ec"),
3890 link_name = "llvm.aarch64.neon.cls.v8i16"
3891 )]
3892 fn _vclsq_s16(a: int16x8_t) -> int16x8_t;
3893 }
3894 unsafe { _vclsq_s16(a) }
3895}
3896#[doc = "Count leading sign bits"]
3897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
3898#[inline]
3899#[target_feature(enable = "neon")]
3900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3901#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
3902#[cfg_attr(
3903 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3904 assert_instr(cls)
3905)]
3906#[cfg_attr(
3907 not(target_arch = "arm"),
3908 stable(feature = "neon_intrinsics", since = "1.59.0")
3909)]
3910#[cfg_attr(
3911 target_arch = "arm",
3912 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3913)]
3914pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
3915 unsafe extern "unadjusted" {
3916 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")]
3917 #[cfg_attr(
3918 any(target_arch = "aarch64", target_arch = "arm64ec"),
3919 link_name = "llvm.aarch64.neon.cls.v2i32"
3920 )]
3921 fn _vcls_s32(a: int32x2_t) -> int32x2_t;
3922 }
3923 unsafe { _vcls_s32(a) }
3924}
3925#[doc = "Count leading sign bits"]
3926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
3927#[inline]
3928#[target_feature(enable = "neon")]
3929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3930#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
3931#[cfg_attr(
3932 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3933 assert_instr(cls)
3934)]
3935#[cfg_attr(
3936 not(target_arch = "arm"),
3937 stable(feature = "neon_intrinsics", since = "1.59.0")
3938)]
3939#[cfg_attr(
3940 target_arch = "arm",
3941 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3942)]
3943pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
3944 unsafe extern "unadjusted" {
3945 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")]
3946 #[cfg_attr(
3947 any(target_arch = "aarch64", target_arch = "arm64ec"),
3948 link_name = "llvm.aarch64.neon.cls.v4i32"
3949 )]
3950 fn _vclsq_s32(a: int32x4_t) -> int32x4_t;
3951 }
3952 unsafe { _vclsq_s32(a) }
3953}
3954#[doc = "Count leading sign bits"]
3955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
3956#[inline]
3957#[target_feature(enable = "neon")]
3958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
3960#[cfg_attr(
3961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3962 assert_instr(cls)
3963)]
3964#[cfg_attr(
3965 not(target_arch = "arm"),
3966 stable(feature = "neon_intrinsics", since = "1.59.0")
3967)]
3968#[cfg_attr(
3969 target_arch = "arm",
3970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3971)]
3972pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
3973 unsafe { vcls_s8(transmute(a)) }
3974}
3975#[doc = "Count leading sign bits"]
3976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
3977#[inline]
3978#[target_feature(enable = "neon")]
3979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
3981#[cfg_attr(
3982 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3983 assert_instr(cls)
3984)]
3985#[cfg_attr(
3986 not(target_arch = "arm"),
3987 stable(feature = "neon_intrinsics", since = "1.59.0")
3988)]
3989#[cfg_attr(
3990 target_arch = "arm",
3991 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3992)]
3993pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
3994 unsafe { vclsq_s8(transmute(a)) }
3995}
3996#[doc = "Count leading sign bits"]
3997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
3998#[inline]
3999#[target_feature(enable = "neon")]
4000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
4002#[cfg_attr(
4003 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4004 assert_instr(cls)
4005)]
4006#[cfg_attr(
4007 not(target_arch = "arm"),
4008 stable(feature = "neon_intrinsics", since = "1.59.0")
4009)]
4010#[cfg_attr(
4011 target_arch = "arm",
4012 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4013)]
4014pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
4015 unsafe { vcls_s16(transmute(a)) }
4016}
4017#[doc = "Count leading sign bits"]
4018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
4019#[inline]
4020#[target_feature(enable = "neon")]
4021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
4023#[cfg_attr(
4024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4025 assert_instr(cls)
4026)]
4027#[cfg_attr(
4028 not(target_arch = "arm"),
4029 stable(feature = "neon_intrinsics", since = "1.59.0")
4030)]
4031#[cfg_attr(
4032 target_arch = "arm",
4033 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4034)]
4035pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
4036 unsafe { vclsq_s16(transmute(a)) }
4037}
4038#[doc = "Count leading sign bits"]
4039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
4040#[inline]
4041#[target_feature(enable = "neon")]
4042#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4043#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
4044#[cfg_attr(
4045 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4046 assert_instr(cls)
4047)]
4048#[cfg_attr(
4049 not(target_arch = "arm"),
4050 stable(feature = "neon_intrinsics", since = "1.59.0")
4051)]
4052#[cfg_attr(
4053 target_arch = "arm",
4054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4055)]
4056pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
4057 unsafe { vcls_s32(transmute(a)) }
4058}
4059#[doc = "Count leading sign bits"]
4060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
4061#[inline]
4062#[target_feature(enable = "neon")]
4063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
4065#[cfg_attr(
4066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4067 assert_instr(cls)
4068)]
4069#[cfg_attr(
4070 not(target_arch = "arm"),
4071 stable(feature = "neon_intrinsics", since = "1.59.0")
4072)]
4073#[cfg_attr(
4074 target_arch = "arm",
4075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4076)]
4077pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
4078 unsafe { vclsq_s32(transmute(a)) }
4079}
4080#[doc = "Floating-point compare less than"]
4081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
4082#[inline]
4083#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4084#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
4085#[cfg_attr(
4086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4087 assert_instr(fcmgt)
4088)]
4089#[target_feature(enable = "neon,fp16")]
4090#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4091pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4092 unsafe { simd_lt(a, b) }
4093}
4094#[doc = "Floating-point compare less than"]
4095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
4096#[inline]
4097#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
4099#[cfg_attr(
4100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4101 assert_instr(fcmgt)
4102)]
4103#[target_feature(enable = "neon,fp16")]
4104#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4105pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4106 unsafe { simd_lt(a, b) }
4107}
4108#[doc = "Floating-point compare less than"]
4109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
4110#[inline]
4111#[target_feature(enable = "neon")]
4112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4113#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
4114#[cfg_attr(
4115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4116 assert_instr(fcmgt)
4117)]
4118#[cfg_attr(
4119 not(target_arch = "arm"),
4120 stable(feature = "neon_intrinsics", since = "1.59.0")
4121)]
4122#[cfg_attr(
4123 target_arch = "arm",
4124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4125)]
4126pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4127 unsafe { simd_lt(a, b) }
4128}
4129#[doc = "Floating-point compare less than"]
4130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
4131#[inline]
4132#[target_feature(enable = "neon")]
4133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4134#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
4135#[cfg_attr(
4136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4137 assert_instr(fcmgt)
4138)]
4139#[cfg_attr(
4140 not(target_arch = "arm"),
4141 stable(feature = "neon_intrinsics", since = "1.59.0")
4142)]
4143#[cfg_attr(
4144 target_arch = "arm",
4145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4146)]
4147pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4148 unsafe { simd_lt(a, b) }
4149}
4150#[doc = "Compare signed less than"]
4151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
4152#[inline]
4153#[target_feature(enable = "neon")]
4154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4155#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
4156#[cfg_attr(
4157 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4158 assert_instr(cmgt)
4159)]
4160#[cfg_attr(
4161 not(target_arch = "arm"),
4162 stable(feature = "neon_intrinsics", since = "1.59.0")
4163)]
4164#[cfg_attr(
4165 target_arch = "arm",
4166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4167)]
4168pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
4169 unsafe { simd_lt(a, b) }
4170}
4171#[doc = "Compare signed less than"]
4172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
4173#[inline]
4174#[target_feature(enable = "neon")]
4175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4176#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
4177#[cfg_attr(
4178 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4179 assert_instr(cmgt)
4180)]
4181#[cfg_attr(
4182 not(target_arch = "arm"),
4183 stable(feature = "neon_intrinsics", since = "1.59.0")
4184)]
4185#[cfg_attr(
4186 target_arch = "arm",
4187 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4188)]
4189pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
4190 unsafe { simd_lt(a, b) }
4191}
4192#[doc = "Compare signed less than"]
4193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
4194#[inline]
4195#[target_feature(enable = "neon")]
4196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4197#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
4198#[cfg_attr(
4199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4200 assert_instr(cmgt)
4201)]
4202#[cfg_attr(
4203 not(target_arch = "arm"),
4204 stable(feature = "neon_intrinsics", since = "1.59.0")
4205)]
4206#[cfg_attr(
4207 target_arch = "arm",
4208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4209)]
4210pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
4211 unsafe { simd_lt(a, b) }
4212}
4213#[doc = "Compare signed less than"]
4214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
4215#[inline]
4216#[target_feature(enable = "neon")]
4217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4218#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
4219#[cfg_attr(
4220 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4221 assert_instr(cmgt)
4222)]
4223#[cfg_attr(
4224 not(target_arch = "arm"),
4225 stable(feature = "neon_intrinsics", since = "1.59.0")
4226)]
4227#[cfg_attr(
4228 target_arch = "arm",
4229 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4230)]
4231pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
4232 unsafe { simd_lt(a, b) }
4233}
4234#[doc = "Compare signed less than"]
4235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
4236#[inline]
4237#[target_feature(enable = "neon")]
4238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
4240#[cfg_attr(
4241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4242 assert_instr(cmgt)
4243)]
4244#[cfg_attr(
4245 not(target_arch = "arm"),
4246 stable(feature = "neon_intrinsics", since = "1.59.0")
4247)]
4248#[cfg_attr(
4249 target_arch = "arm",
4250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4251)]
4252pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
4253 unsafe { simd_lt(a, b) }
4254}
4255#[doc = "Compare signed less than"]
4256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
4257#[inline]
4258#[target_feature(enable = "neon")]
4259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4260#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
4261#[cfg_attr(
4262 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4263 assert_instr(cmgt)
4264)]
4265#[cfg_attr(
4266 not(target_arch = "arm"),
4267 stable(feature = "neon_intrinsics", since = "1.59.0")
4268)]
4269#[cfg_attr(
4270 target_arch = "arm",
4271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4272)]
4273pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
4274 unsafe { simd_lt(a, b) }
4275}
4276#[doc = "Compare unsigned less than"]
4277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
4278#[inline]
4279#[target_feature(enable = "neon")]
4280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4281#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
4282#[cfg_attr(
4283 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4284 assert_instr(cmhi)
4285)]
4286#[cfg_attr(
4287 not(target_arch = "arm"),
4288 stable(feature = "neon_intrinsics", since = "1.59.0")
4289)]
4290#[cfg_attr(
4291 target_arch = "arm",
4292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4293)]
4294pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
4295 unsafe { simd_lt(a, b) }
4296}
4297#[doc = "Compare unsigned less than"]
4298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
4299#[inline]
4300#[target_feature(enable = "neon")]
4301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4302#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
4303#[cfg_attr(
4304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4305 assert_instr(cmhi)
4306)]
4307#[cfg_attr(
4308 not(target_arch = "arm"),
4309 stable(feature = "neon_intrinsics", since = "1.59.0")
4310)]
4311#[cfg_attr(
4312 target_arch = "arm",
4313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4314)]
4315pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
4316 unsafe { simd_lt(a, b) }
4317}
4318#[doc = "Compare unsigned less than"]
4319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
4320#[inline]
4321#[target_feature(enable = "neon")]
4322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4323#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
4324#[cfg_attr(
4325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4326 assert_instr(cmhi)
4327)]
4328#[cfg_attr(
4329 not(target_arch = "arm"),
4330 stable(feature = "neon_intrinsics", since = "1.59.0")
4331)]
4332#[cfg_attr(
4333 target_arch = "arm",
4334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4335)]
4336pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
4337 unsafe { simd_lt(a, b) }
4338}
4339#[doc = "Compare unsigned less than"]
4340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
4341#[inline]
4342#[target_feature(enable = "neon")]
4343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
4345#[cfg_attr(
4346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4347 assert_instr(cmhi)
4348)]
4349#[cfg_attr(
4350 not(target_arch = "arm"),
4351 stable(feature = "neon_intrinsics", since = "1.59.0")
4352)]
4353#[cfg_attr(
4354 target_arch = "arm",
4355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4356)]
4357pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
4358 unsafe { simd_lt(a, b) }
4359}
4360#[doc = "Compare unsigned less than"]
4361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
4362#[inline]
4363#[target_feature(enable = "neon")]
4364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4365#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
4366#[cfg_attr(
4367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4368 assert_instr(cmhi)
4369)]
4370#[cfg_attr(
4371 not(target_arch = "arm"),
4372 stable(feature = "neon_intrinsics", since = "1.59.0")
4373)]
4374#[cfg_attr(
4375 target_arch = "arm",
4376 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4377)]
4378pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
4379 unsafe { simd_lt(a, b) }
4380}
4381#[doc = "Compare unsigned less than"]
4382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
4383#[inline]
4384#[target_feature(enable = "neon")]
4385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4386#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
4387#[cfg_attr(
4388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4389 assert_instr(cmhi)
4390)]
4391#[cfg_attr(
4392 not(target_arch = "arm"),
4393 stable(feature = "neon_intrinsics", since = "1.59.0")
4394)]
4395#[cfg_attr(
4396 target_arch = "arm",
4397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4398)]
4399pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
4400 unsafe { simd_lt(a, b) }
4401}
4402#[doc = "Floating-point compare less than"]
4403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
4404#[inline]
4405#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4406#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
4407#[cfg_attr(
4408 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4409 assert_instr(fcmlt)
4410)]
4411#[target_feature(enable = "neon,fp16")]
4412#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4413pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
4414 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
4415 unsafe { simd_lt(a, transmute(b)) }
4416}
4417#[doc = "Floating-point compare less than"]
4418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
4419#[inline]
4420#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4421#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
4422#[cfg_attr(
4423 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4424 assert_instr(fcmlt)
4425)]
4426#[target_feature(enable = "neon,fp16")]
4427#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4428pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
4429 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
4430 unsafe { simd_lt(a, transmute(b)) }
4431}
4432#[doc = "Count leading zero bits"]
4433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
4434#[inline]
4435#[target_feature(enable = "neon")]
4436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4437#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
4438#[cfg_attr(
4439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4440 assert_instr(clz)
4441)]
4442#[cfg_attr(
4443 not(target_arch = "arm"),
4444 stable(feature = "neon_intrinsics", since = "1.59.0")
4445)]
4446#[cfg_attr(
4447 target_arch = "arm",
4448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4449)]
4450pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
4451 unsafe extern "unadjusted" {
4452 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i8")]
4453 #[cfg_attr(
4454 any(target_arch = "aarch64", target_arch = "arm64ec"),
4455 link_name = "llvm.ctlz.v8i8"
4456 )]
4457 fn _vclz_s8(a: int8x8_t) -> int8x8_t;
4458 }
4459 unsafe { _vclz_s8(a) }
4460}
4461#[doc = "Count leading zero bits"]
4462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
4463#[inline]
4464#[target_feature(enable = "neon")]
4465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4466#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
4467#[cfg_attr(
4468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4469 assert_instr(clz)
4470)]
4471#[cfg_attr(
4472 not(target_arch = "arm"),
4473 stable(feature = "neon_intrinsics", since = "1.59.0")
4474)]
4475#[cfg_attr(
4476 target_arch = "arm",
4477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4478)]
4479pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
4480 unsafe extern "unadjusted" {
4481 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v16i8")]
4482 #[cfg_attr(
4483 any(target_arch = "aarch64", target_arch = "arm64ec"),
4484 link_name = "llvm.ctlz.v16i8"
4485 )]
4486 fn _vclzq_s8(a: int8x16_t) -> int8x16_t;
4487 }
4488 unsafe { _vclzq_s8(a) }
4489}
4490#[doc = "Count leading zero bits"]
4491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
4492#[inline]
4493#[target_feature(enable = "neon")]
4494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4495#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
4496#[cfg_attr(
4497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4498 assert_instr(clz)
4499)]
4500#[cfg_attr(
4501 not(target_arch = "arm"),
4502 stable(feature = "neon_intrinsics", since = "1.59.0")
4503)]
4504#[cfg_attr(
4505 target_arch = "arm",
4506 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4507)]
4508pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
4509 unsafe extern "unadjusted" {
4510 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i16")]
4511 #[cfg_attr(
4512 any(target_arch = "aarch64", target_arch = "arm64ec"),
4513 link_name = "llvm.ctlz.v4i16"
4514 )]
4515 fn _vclz_s16(a: int16x4_t) -> int16x4_t;
4516 }
4517 unsafe { _vclz_s16(a) }
4518}
4519#[doc = "Count leading zero bits"]
4520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
4521#[inline]
4522#[target_feature(enable = "neon")]
4523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4524#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
4525#[cfg_attr(
4526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4527 assert_instr(clz)
4528)]
4529#[cfg_attr(
4530 not(target_arch = "arm"),
4531 stable(feature = "neon_intrinsics", since = "1.59.0")
4532)]
4533#[cfg_attr(
4534 target_arch = "arm",
4535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4536)]
4537pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
4538 unsafe extern "unadjusted" {
4539 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i16")]
4540 #[cfg_attr(
4541 any(target_arch = "aarch64", target_arch = "arm64ec"),
4542 link_name = "llvm.ctlz.v8i16"
4543 )]
4544 fn _vclzq_s16(a: int16x8_t) -> int16x8_t;
4545 }
4546 unsafe { _vclzq_s16(a) }
4547}
4548#[doc = "Count leading zero bits"]
4549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
4550#[inline]
4551#[target_feature(enable = "neon")]
4552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4553#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
4554#[cfg_attr(
4555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4556 assert_instr(clz)
4557)]
4558#[cfg_attr(
4559 not(target_arch = "arm"),
4560 stable(feature = "neon_intrinsics", since = "1.59.0")
4561)]
4562#[cfg_attr(
4563 target_arch = "arm",
4564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4565)]
4566pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
4567 unsafe extern "unadjusted" {
4568 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v2i32")]
4569 #[cfg_attr(
4570 any(target_arch = "aarch64", target_arch = "arm64ec"),
4571 link_name = "llvm.ctlz.v2i32"
4572 )]
4573 fn _vclz_s32(a: int32x2_t) -> int32x2_t;
4574 }
4575 unsafe { _vclz_s32(a) }
4576}
4577#[doc = "Count leading zero bits"]
4578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
4579#[inline]
4580#[target_feature(enable = "neon")]
4581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
4583#[cfg_attr(
4584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4585 assert_instr(clz)
4586)]
4587#[cfg_attr(
4588 not(target_arch = "arm"),
4589 stable(feature = "neon_intrinsics", since = "1.59.0")
4590)]
4591#[cfg_attr(
4592 target_arch = "arm",
4593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4594)]
4595pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
4596 unsafe extern "unadjusted" {
4597 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i32")]
4598 #[cfg_attr(
4599 any(target_arch = "aarch64", target_arch = "arm64ec"),
4600 link_name = "llvm.ctlz.v4i32"
4601 )]
4602 fn _vclzq_s32(a: int32x4_t) -> int32x4_t;
4603 }
4604 unsafe { _vclzq_s32(a) }
4605}
4606#[doc = "Count leading zero bits"]
4607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
4608#[inline]
4609#[cfg(target_endian = "little")]
4610#[target_feature(enable = "neon")]
4611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
4613#[cfg_attr(
4614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4615 assert_instr(clz)
4616)]
4617#[cfg_attr(
4618 not(target_arch = "arm"),
4619 stable(feature = "neon_intrinsics", since = "1.59.0")
4620)]
4621#[cfg_attr(
4622 target_arch = "arm",
4623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4624)]
4625pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
4626 unsafe { transmute(vclz_s16(transmute(a))) }
4627}
4628#[doc = "Count leading zero bits"]
4629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
4630#[inline]
4631#[cfg(target_endian = "big")]
4632#[target_feature(enable = "neon")]
4633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
4635#[cfg_attr(
4636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4637 assert_instr(clz)
4638)]
4639#[cfg_attr(
4640 not(target_arch = "arm"),
4641 stable(feature = "neon_intrinsics", since = "1.59.0")
4642)]
4643#[cfg_attr(
4644 target_arch = "arm",
4645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4646)]
4647pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
4648 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
4649 unsafe {
4650 let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
4651 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
4652 }
4653}
4654#[doc = "Count leading zero bits"]
4655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
4656#[inline]
4657#[cfg(target_endian = "little")]
4658#[target_feature(enable = "neon")]
4659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4660#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
4661#[cfg_attr(
4662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4663 assert_instr(clz)
4664)]
4665#[cfg_attr(
4666 not(target_arch = "arm"),
4667 stable(feature = "neon_intrinsics", since = "1.59.0")
4668)]
4669#[cfg_attr(
4670 target_arch = "arm",
4671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4672)]
4673pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
4674 unsafe { transmute(vclzq_s16(transmute(a))) }
4675}
4676#[doc = "Count leading zero bits"]
4677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
4678#[inline]
4679#[cfg(target_endian = "big")]
4680#[target_feature(enable = "neon")]
4681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
4683#[cfg_attr(
4684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4685 assert_instr(clz)
4686)]
4687#[cfg_attr(
4688 not(target_arch = "arm"),
4689 stable(feature = "neon_intrinsics", since = "1.59.0")
4690)]
4691#[cfg_attr(
4692 target_arch = "arm",
4693 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4694)]
4695pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
4696 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
4697 unsafe {
4698 let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
4699 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
4700 }
4701}
4702#[doc = "Count leading zero bits"]
4703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
4704#[inline]
4705#[cfg(target_endian = "little")]
4706#[target_feature(enable = "neon")]
4707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4708#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
4709#[cfg_attr(
4710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4711 assert_instr(clz)
4712)]
4713#[cfg_attr(
4714 not(target_arch = "arm"),
4715 stable(feature = "neon_intrinsics", since = "1.59.0")
4716)]
4717#[cfg_attr(
4718 target_arch = "arm",
4719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4720)]
4721pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
4722 unsafe { transmute(vclz_s32(transmute(a))) }
4723}
4724#[doc = "Count leading zero bits"]
4725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
4726#[inline]
4727#[cfg(target_endian = "big")]
4728#[target_feature(enable = "neon")]
4729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4730#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
4731#[cfg_attr(
4732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4733 assert_instr(clz)
4734)]
4735#[cfg_attr(
4736 not(target_arch = "arm"),
4737 stable(feature = "neon_intrinsics", since = "1.59.0")
4738)]
4739#[cfg_attr(
4740 target_arch = "arm",
4741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4742)]
4743pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
4744 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
4745 unsafe {
4746 let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
4747 simd_shuffle!(ret_val, ret_val, [1, 0])
4748 }
4749}
4750#[doc = "Count leading zero bits"]
4751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
4752#[inline]
4753#[cfg(target_endian = "little")]
4754#[target_feature(enable = "neon")]
4755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4756#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
4757#[cfg_attr(
4758 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4759 assert_instr(clz)
4760)]
4761#[cfg_attr(
4762 not(target_arch = "arm"),
4763 stable(feature = "neon_intrinsics", since = "1.59.0")
4764)]
4765#[cfg_attr(
4766 target_arch = "arm",
4767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4768)]
4769pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
4770 unsafe { transmute(vclzq_s32(transmute(a))) }
4771}
4772#[doc = "Count leading zero bits"]
4773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
4774#[inline]
4775#[cfg(target_endian = "big")]
4776#[target_feature(enable = "neon")]
4777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
4779#[cfg_attr(
4780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4781 assert_instr(clz)
4782)]
4783#[cfg_attr(
4784 not(target_arch = "arm"),
4785 stable(feature = "neon_intrinsics", since = "1.59.0")
4786)]
4787#[cfg_attr(
4788 target_arch = "arm",
4789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4790)]
4791pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
4792 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
4793 unsafe {
4794 let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
4795 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
4796 }
4797}
4798#[doc = "Count leading zero bits"]
4799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
4800#[inline]
4801#[cfg(target_endian = "little")]
4802#[target_feature(enable = "neon")]
4803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
4805#[cfg_attr(
4806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4807 assert_instr(clz)
4808)]
4809#[cfg_attr(
4810 not(target_arch = "arm"),
4811 stable(feature = "neon_intrinsics", since = "1.59.0")
4812)]
4813#[cfg_attr(
4814 target_arch = "arm",
4815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4816)]
4817pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
4818 unsafe { transmute(vclz_s8(transmute(a))) }
4819}
4820#[doc = "Count leading zero bits"]
4821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
4822#[inline]
4823#[cfg(target_endian = "big")]
4824#[target_feature(enable = "neon")]
4825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
4827#[cfg_attr(
4828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4829 assert_instr(clz)
4830)]
4831#[cfg_attr(
4832 not(target_arch = "arm"),
4833 stable(feature = "neon_intrinsics", since = "1.59.0")
4834)]
4835#[cfg_attr(
4836 target_arch = "arm",
4837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4838)]
4839pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
4840 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
4841 unsafe {
4842 let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
4843 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
4844 }
4845}
4846#[doc = "Count leading zero bits"]
4847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
4848#[inline]
4849#[cfg(target_endian = "little")]
4850#[target_feature(enable = "neon")]
4851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
4853#[cfg_attr(
4854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4855 assert_instr(clz)
4856)]
4857#[cfg_attr(
4858 not(target_arch = "arm"),
4859 stable(feature = "neon_intrinsics", since = "1.59.0")
4860)]
4861#[cfg_attr(
4862 target_arch = "arm",
4863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4864)]
4865pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
4866 unsafe { transmute(vclzq_s8(transmute(a))) }
4867}
4868#[doc = "Count leading zero bits"]
4869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
4870#[inline]
4871#[cfg(target_endian = "big")]
4872#[target_feature(enable = "neon")]
4873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4874#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
4875#[cfg_attr(
4876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4877 assert_instr(clz)
4878)]
4879#[cfg_attr(
4880 not(target_arch = "arm"),
4881 stable(feature = "neon_intrinsics", since = "1.59.0")
4882)]
4883#[cfg_attr(
4884 target_arch = "arm",
4885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4886)]
4887pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
4888 let a: uint8x16_t =
4889 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
4890 unsafe {
4891 let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
4892 simd_shuffle!(
4893 ret_val,
4894 ret_val,
4895 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
4896 )
4897 }
4898}
4899#[doc = "Population count per byte."]
4900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
4901#[inline]
4902#[target_feature(enable = "neon")]
4903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
4905#[cfg_attr(
4906 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4907 assert_instr(cnt)
4908)]
4909#[cfg_attr(
4910 not(target_arch = "arm"),
4911 stable(feature = "neon_intrinsics", since = "1.59.0")
4912)]
4913#[cfg_attr(
4914 target_arch = "arm",
4915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4916)]
4917pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
4918 unsafe extern "unadjusted" {
4919 #[cfg_attr(
4920 any(target_arch = "aarch64", target_arch = "arm64ec"),
4921 link_name = "llvm.ctpop.v8i8"
4922 )]
4923 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v8i8")]
4924 fn _vcnt_s8(a: int8x8_t) -> int8x8_t;
4925 }
4926 unsafe { _vcnt_s8(a) }
4927}
4928#[doc = "Population count per byte."]
4929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
4930#[inline]
4931#[target_feature(enable = "neon")]
4932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
4934#[cfg_attr(
4935 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4936 assert_instr(cnt)
4937)]
4938#[cfg_attr(
4939 not(target_arch = "arm"),
4940 stable(feature = "neon_intrinsics", since = "1.59.0")
4941)]
4942#[cfg_attr(
4943 target_arch = "arm",
4944 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4945)]
4946pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
4947 unsafe extern "unadjusted" {
4948 #[cfg_attr(
4949 any(target_arch = "aarch64", target_arch = "arm64ec"),
4950 link_name = "llvm.ctpop.v16i8"
4951 )]
4952 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v16i8")]
4953 fn _vcntq_s8(a: int8x16_t) -> int8x16_t;
4954 }
4955 unsafe { _vcntq_s8(a) }
4956}
4957#[doc = "Population count per byte."]
4958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
4959#[inline]
4960#[cfg(target_endian = "little")]
4961#[target_feature(enable = "neon")]
4962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4963#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
4964#[cfg_attr(
4965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4966 assert_instr(cnt)
4967)]
4968#[cfg_attr(
4969 not(target_arch = "arm"),
4970 stable(feature = "neon_intrinsics", since = "1.59.0")
4971)]
4972#[cfg_attr(
4973 target_arch = "arm",
4974 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4975)]
4976pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
4977 unsafe { transmute(vcnt_s8(transmute(a))) }
4978}
4979#[doc = "Population count per byte."]
4980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
4981#[inline]
4982#[cfg(target_endian = "big")]
4983#[target_feature(enable = "neon")]
4984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
4986#[cfg_attr(
4987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4988 assert_instr(cnt)
4989)]
4990#[cfg_attr(
4991 not(target_arch = "arm"),
4992 stable(feature = "neon_intrinsics", since = "1.59.0")
4993)]
4994#[cfg_attr(
4995 target_arch = "arm",
4996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4997)]
4998pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
4999 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
5000 unsafe {
5001 let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
5002 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5003 }
5004}
5005#[doc = "Population count per byte."]
5006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
5007#[inline]
5008#[cfg(target_endian = "little")]
5009#[target_feature(enable = "neon")]
5010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
5012#[cfg_attr(
5013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5014 assert_instr(cnt)
5015)]
5016#[cfg_attr(
5017 not(target_arch = "arm"),
5018 stable(feature = "neon_intrinsics", since = "1.59.0")
5019)]
5020#[cfg_attr(
5021 target_arch = "arm",
5022 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5023)]
5024pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
5025 unsafe { transmute(vcntq_s8(transmute(a))) }
5026}
5027#[doc = "Population count per byte."]
5028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
5029#[inline]
5030#[cfg(target_endian = "big")]
5031#[target_feature(enable = "neon")]
5032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
5034#[cfg_attr(
5035 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5036 assert_instr(cnt)
5037)]
5038#[cfg_attr(
5039 not(target_arch = "arm"),
5040 stable(feature = "neon_intrinsics", since = "1.59.0")
5041)]
5042#[cfg_attr(
5043 target_arch = "arm",
5044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5045)]
5046pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
5047 let a: uint8x16_t =
5048 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
5049 unsafe {
5050 let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
5051 simd_shuffle!(
5052 ret_val,
5053 ret_val,
5054 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
5055 )
5056 }
5057}
5058#[doc = "Population count per byte."]
5059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
5060#[inline]
5061#[cfg(target_endian = "little")]
5062#[target_feature(enable = "neon")]
5063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
5065#[cfg_attr(
5066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5067 assert_instr(cnt)
5068)]
5069#[cfg_attr(
5070 not(target_arch = "arm"),
5071 stable(feature = "neon_intrinsics", since = "1.59.0")
5072)]
5073#[cfg_attr(
5074 target_arch = "arm",
5075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5076)]
5077pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
5078 unsafe { transmute(vcnt_s8(transmute(a))) }
5079}
5080#[doc = "Population count per byte."]
5081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
5082#[inline]
5083#[cfg(target_endian = "big")]
5084#[target_feature(enable = "neon")]
5085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
5087#[cfg_attr(
5088 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5089 assert_instr(cnt)
5090)]
5091#[cfg_attr(
5092 not(target_arch = "arm"),
5093 stable(feature = "neon_intrinsics", since = "1.59.0")
5094)]
5095#[cfg_attr(
5096 target_arch = "arm",
5097 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5098)]
5099pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
5100 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
5101 unsafe {
5102 let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
5103 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5104 }
5105}
5106#[doc = "Population count per byte."]
5107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
5108#[inline]
5109#[cfg(target_endian = "little")]
5110#[target_feature(enable = "neon")]
5111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
5113#[cfg_attr(
5114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5115 assert_instr(cnt)
5116)]
5117#[cfg_attr(
5118 not(target_arch = "arm"),
5119 stable(feature = "neon_intrinsics", since = "1.59.0")
5120)]
5121#[cfg_attr(
5122 target_arch = "arm",
5123 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5124)]
5125pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
5126 unsafe { transmute(vcntq_s8(transmute(a))) }
5127}
5128#[doc = "Population count per byte."]
5129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
5130#[inline]
5131#[cfg(target_endian = "big")]
5132#[target_feature(enable = "neon")]
5133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
5135#[cfg_attr(
5136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5137 assert_instr(cnt)
5138)]
5139#[cfg_attr(
5140 not(target_arch = "arm"),
5141 stable(feature = "neon_intrinsics", since = "1.59.0")
5142)]
5143#[cfg_attr(
5144 target_arch = "arm",
5145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5146)]
5147pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
5148 let a: poly8x16_t =
5149 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
5150 unsafe {
5151 let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
5152 simd_shuffle!(
5153 ret_val,
5154 ret_val,
5155 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
5156 )
5157 }
5158}
5159#[doc = "Join two smaller vectors into a single larger vector"]
5160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
5161#[inline]
5162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5163#[target_feature(enable = "neon,fp16")]
5164#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5165#[cfg_attr(test, assert_instr(nop))]
5166pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
5167 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
5168}
5169#[doc = "Join two smaller vectors into a single larger vector"]
5170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
5171#[inline]
5172#[target_feature(enable = "neon")]
5173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5175#[cfg_attr(
5176 not(target_arch = "arm"),
5177 stable(feature = "neon_intrinsics", since = "1.59.0")
5178)]
5179#[cfg_attr(
5180 target_arch = "arm",
5181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5182)]
5183pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
5184 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
5185}
5186#[doc = "Join two smaller vectors into a single larger vector"]
5187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
5188#[inline]
5189#[target_feature(enable = "neon")]
5190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5192#[cfg_attr(
5193 not(target_arch = "arm"),
5194 stable(feature = "neon_intrinsics", since = "1.59.0")
5195)]
5196#[cfg_attr(
5197 target_arch = "arm",
5198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5199)]
5200pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
5201 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
5202}
5203#[doc = "Join two smaller vectors into a single larger vector"]
5204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
5205#[inline]
5206#[target_feature(enable = "neon")]
5207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5209#[cfg_attr(
5210 not(target_arch = "arm"),
5211 stable(feature = "neon_intrinsics", since = "1.59.0")
5212)]
5213#[cfg_attr(
5214 target_arch = "arm",
5215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5216)]
5217pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
5218 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
5219}
5220#[doc = "Join two smaller vectors into a single larger vector"]
5221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
5222#[inline]
5223#[target_feature(enable = "neon")]
5224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5226#[cfg_attr(
5227 not(target_arch = "arm"),
5228 stable(feature = "neon_intrinsics", since = "1.59.0")
5229)]
5230#[cfg_attr(
5231 target_arch = "arm",
5232 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5233)]
5234pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
5235 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
5236}
5237#[doc = "Join two smaller vectors into a single larger vector"]
5238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
5239#[inline]
5240#[target_feature(enable = "neon")]
5241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5243#[cfg_attr(
5244 not(target_arch = "arm"),
5245 stable(feature = "neon_intrinsics", since = "1.59.0")
5246)]
5247#[cfg_attr(
5248 target_arch = "arm",
5249 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5250)]
5251pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
5252 unsafe { simd_shuffle!(a, b, [0, 1]) }
5253}
5254#[doc = "Join two smaller vectors into a single larger vector"]
5255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
5256#[inline]
5257#[target_feature(enable = "neon")]
5258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5260#[cfg_attr(
5261 not(target_arch = "arm"),
5262 stable(feature = "neon_intrinsics", since = "1.59.0")
5263)]
5264#[cfg_attr(
5265 target_arch = "arm",
5266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5267)]
5268pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
5269 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
5270}
5271#[doc = "Join two smaller vectors into a single larger vector"]
5272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
5273#[inline]
5274#[target_feature(enable = "neon")]
5275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5277#[cfg_attr(
5278 not(target_arch = "arm"),
5279 stable(feature = "neon_intrinsics", since = "1.59.0")
5280)]
5281#[cfg_attr(
5282 target_arch = "arm",
5283 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5284)]
5285pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
5286 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
5287}
5288#[doc = "Join two smaller vectors into a single larger vector"]
5289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
5290#[inline]
5291#[target_feature(enable = "neon")]
5292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5294#[cfg_attr(
5295 not(target_arch = "arm"),
5296 stable(feature = "neon_intrinsics", since = "1.59.0")
5297)]
5298#[cfg_attr(
5299 target_arch = "arm",
5300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5301)]
5302pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
5303 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
5304}
5305#[doc = "Join two smaller vectors into a single larger vector"]
5306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
5307#[inline]
5308#[target_feature(enable = "neon")]
5309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5311#[cfg_attr(
5312 not(target_arch = "arm"),
5313 stable(feature = "neon_intrinsics", since = "1.59.0")
5314)]
5315#[cfg_attr(
5316 target_arch = "arm",
5317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5318)]
5319pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
5320 unsafe { simd_shuffle!(a, b, [0, 1]) }
5321}
5322#[doc = "Join two smaller vectors into a single larger vector"]
5323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
5324#[inline]
5325#[target_feature(enable = "neon")]
5326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5328#[cfg_attr(
5329 not(target_arch = "arm"),
5330 stable(feature = "neon_intrinsics", since = "1.59.0")
5331)]
5332#[cfg_attr(
5333 target_arch = "arm",
5334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5335)]
5336pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
5337 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
5338}
5339#[doc = "Join two smaller vectors into a single larger vector"]
5340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
5341#[inline]
5342#[target_feature(enable = "neon")]
5343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5345#[cfg_attr(
5346 not(target_arch = "arm"),
5347 stable(feature = "neon_intrinsics", since = "1.59.0")
5348)]
5349#[cfg_attr(
5350 target_arch = "arm",
5351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5352)]
5353pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
5354 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
5355}
5356#[doc = "Join two smaller vectors into a single larger vector"]
5357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
5358#[inline]
5359#[target_feature(enable = "neon")]
5360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5362#[cfg_attr(
5363 not(target_arch = "arm"),
5364 stable(feature = "neon_intrinsics", since = "1.59.0")
5365)]
5366#[cfg_attr(
5367 target_arch = "arm",
5368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5369)]
5370pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
5371 unsafe { simd_shuffle!(a, b, [0, 1]) }
5372}
5373#[doc = "Insert vector element from another vector element"]
5374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
5375#[inline]
5376#[cfg(target_endian = "little")]
5377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5379#[cfg_attr(
5380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5381 assert_instr(nop)
5382)]
5383#[target_feature(enable = "neon,fp16")]
5384#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5385pub fn vcreate_f16(a: u64) -> float16x4_t {
5386 unsafe { transmute(a) }
5387}
5388#[doc = "Insert vector element from another vector element"]
5389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
5390#[inline]
5391#[cfg(target_endian = "big")]
5392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5394#[cfg_attr(
5395 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5396 assert_instr(nop)
5397)]
5398#[target_feature(enable = "neon,fp16")]
5399#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5400pub fn vcreate_f16(a: u64) -> float16x4_t {
5401 unsafe {
5402 let ret_val: float16x4_t = transmute(a);
5403 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
5404 }
5405}
5406#[doc = "Insert vector element from another vector element"]
5407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
5408#[inline]
5409#[cfg(target_endian = "little")]
5410#[target_feature(enable = "neon")]
5411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5413#[cfg_attr(
5414 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5415 assert_instr(nop)
5416)]
5417#[cfg_attr(
5418 not(target_arch = "arm"),
5419 stable(feature = "neon_intrinsics", since = "1.59.0")
5420)]
5421#[cfg_attr(
5422 target_arch = "arm",
5423 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5424)]
5425pub fn vcreate_f32(a: u64) -> float32x2_t {
5426 unsafe { transmute(a) }
5427}
5428#[doc = "Insert vector element from another vector element"]
5429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
5430#[inline]
5431#[cfg(target_endian = "big")]
5432#[target_feature(enable = "neon")]
5433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5435#[cfg_attr(
5436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5437 assert_instr(nop)
5438)]
5439#[cfg_attr(
5440 not(target_arch = "arm"),
5441 stable(feature = "neon_intrinsics", since = "1.59.0")
5442)]
5443#[cfg_attr(
5444 target_arch = "arm",
5445 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5446)]
5447pub fn vcreate_f32(a: u64) -> float32x2_t {
5448 unsafe {
5449 let ret_val: float32x2_t = transmute(a);
5450 simd_shuffle!(ret_val, ret_val, [1, 0])
5451 }
5452}
5453#[doc = "Insert vector element from another vector element"]
5454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
5455#[inline]
5456#[cfg(target_endian = "little")]
5457#[target_feature(enable = "neon")]
5458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5460#[cfg_attr(
5461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5462 assert_instr(nop)
5463)]
5464#[cfg_attr(
5465 not(target_arch = "arm"),
5466 stable(feature = "neon_intrinsics", since = "1.59.0")
5467)]
5468#[cfg_attr(
5469 target_arch = "arm",
5470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5471)]
5472pub fn vcreate_s8(a: u64) -> int8x8_t {
5473 unsafe { transmute(a) }
5474}
5475#[doc = "Insert vector element from another vector element"]
5476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
5477#[inline]
5478#[cfg(target_endian = "big")]
5479#[target_feature(enable = "neon")]
5480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5482#[cfg_attr(
5483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5484 assert_instr(nop)
5485)]
5486#[cfg_attr(
5487 not(target_arch = "arm"),
5488 stable(feature = "neon_intrinsics", since = "1.59.0")
5489)]
5490#[cfg_attr(
5491 target_arch = "arm",
5492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5493)]
5494pub fn vcreate_s8(a: u64) -> int8x8_t {
5495 unsafe {
5496 let ret_val: int8x8_t = transmute(a);
5497 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5498 }
5499}
5500#[doc = "Insert vector element from another vector element"]
5501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
5502#[inline]
5503#[cfg(target_endian = "little")]
5504#[target_feature(enable = "neon")]
5505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5507#[cfg_attr(
5508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5509 assert_instr(nop)
5510)]
5511#[cfg_attr(
5512 not(target_arch = "arm"),
5513 stable(feature = "neon_intrinsics", since = "1.59.0")
5514)]
5515#[cfg_attr(
5516 target_arch = "arm",
5517 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5518)]
5519pub fn vcreate_s16(a: u64) -> int16x4_t {
5520 unsafe { transmute(a) }
5521}
5522#[doc = "Insert vector element from another vector element"]
5523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
5524#[inline]
5525#[cfg(target_endian = "big")]
5526#[target_feature(enable = "neon")]
5527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5529#[cfg_attr(
5530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5531 assert_instr(nop)
5532)]
5533#[cfg_attr(
5534 not(target_arch = "arm"),
5535 stable(feature = "neon_intrinsics", since = "1.59.0")
5536)]
5537#[cfg_attr(
5538 target_arch = "arm",
5539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5540)]
5541pub fn vcreate_s16(a: u64) -> int16x4_t {
5542 unsafe {
5543 let ret_val: int16x4_t = transmute(a);
5544 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
5545 }
5546}
5547#[doc = "Insert vector element from another vector element"]
5548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
5549#[inline]
5550#[cfg(target_endian = "little")]
5551#[target_feature(enable = "neon")]
5552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5553#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5554#[cfg_attr(
5555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5556 assert_instr(nop)
5557)]
5558#[cfg_attr(
5559 not(target_arch = "arm"),
5560 stable(feature = "neon_intrinsics", since = "1.59.0")
5561)]
5562#[cfg_attr(
5563 target_arch = "arm",
5564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5565)]
5566pub fn vcreate_s32(a: u64) -> int32x2_t {
5567 unsafe { transmute(a) }
5568}
5569#[doc = "Insert vector element from another vector element"]
5570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
5571#[inline]
5572#[cfg(target_endian = "big")]
5573#[target_feature(enable = "neon")]
5574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5576#[cfg_attr(
5577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5578 assert_instr(nop)
5579)]
5580#[cfg_attr(
5581 not(target_arch = "arm"),
5582 stable(feature = "neon_intrinsics", since = "1.59.0")
5583)]
5584#[cfg_attr(
5585 target_arch = "arm",
5586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5587)]
5588pub fn vcreate_s32(a: u64) -> int32x2_t {
5589 unsafe {
5590 let ret_val: int32x2_t = transmute(a);
5591 simd_shuffle!(ret_val, ret_val, [1, 0])
5592 }
5593}
5594#[doc = "Insert vector element from another vector element"]
5595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
5596#[inline]
5597#[target_feature(enable = "neon")]
5598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5600#[cfg_attr(
5601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5602 assert_instr(nop)
5603)]
5604#[cfg_attr(
5605 not(target_arch = "arm"),
5606 stable(feature = "neon_intrinsics", since = "1.59.0")
5607)]
5608#[cfg_attr(
5609 target_arch = "arm",
5610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5611)]
5612pub fn vcreate_s64(a: u64) -> int64x1_t {
5613 unsafe { transmute(a) }
5614}
5615#[doc = "Insert vector element from another vector element"]
5616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
5617#[inline]
5618#[cfg(target_endian = "little")]
5619#[target_feature(enable = "neon")]
5620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5622#[cfg_attr(
5623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5624 assert_instr(nop)
5625)]
5626#[cfg_attr(
5627 not(target_arch = "arm"),
5628 stable(feature = "neon_intrinsics", since = "1.59.0")
5629)]
5630#[cfg_attr(
5631 target_arch = "arm",
5632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5633)]
5634pub fn vcreate_u8(a: u64) -> uint8x8_t {
5635 unsafe { transmute(a) }
5636}
5637#[doc = "Insert vector element from another vector element"]
5638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
5639#[inline]
5640#[cfg(target_endian = "big")]
5641#[target_feature(enable = "neon")]
5642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5644#[cfg_attr(
5645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5646 assert_instr(nop)
5647)]
5648#[cfg_attr(
5649 not(target_arch = "arm"),
5650 stable(feature = "neon_intrinsics", since = "1.59.0")
5651)]
5652#[cfg_attr(
5653 target_arch = "arm",
5654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5655)]
5656pub fn vcreate_u8(a: u64) -> uint8x8_t {
5657 unsafe {
5658 let ret_val: uint8x8_t = transmute(a);
5659 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5660 }
5661}
5662#[doc = "Insert vector element from another vector element"]
5663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
5664#[inline]
5665#[cfg(target_endian = "little")]
5666#[target_feature(enable = "neon")]
5667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5669#[cfg_attr(
5670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5671 assert_instr(nop)
5672)]
5673#[cfg_attr(
5674 not(target_arch = "arm"),
5675 stable(feature = "neon_intrinsics", since = "1.59.0")
5676)]
5677#[cfg_attr(
5678 target_arch = "arm",
5679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5680)]
5681pub fn vcreate_u16(a: u64) -> uint16x4_t {
5682 unsafe { transmute(a) }
5683}
5684#[doc = "Insert vector element from another vector element"]
5685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
5686#[inline]
5687#[cfg(target_endian = "big")]
5688#[target_feature(enable = "neon")]
5689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5691#[cfg_attr(
5692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5693 assert_instr(nop)
5694)]
5695#[cfg_attr(
5696 not(target_arch = "arm"),
5697 stable(feature = "neon_intrinsics", since = "1.59.0")
5698)]
5699#[cfg_attr(
5700 target_arch = "arm",
5701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5702)]
5703pub fn vcreate_u16(a: u64) -> uint16x4_t {
5704 unsafe {
5705 let ret_val: uint16x4_t = transmute(a);
5706 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
5707 }
5708}
5709#[doc = "Insert vector element from another vector element"]
5710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
5711#[inline]
5712#[cfg(target_endian = "little")]
5713#[target_feature(enable = "neon")]
5714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5716#[cfg_attr(
5717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5718 assert_instr(nop)
5719)]
5720#[cfg_attr(
5721 not(target_arch = "arm"),
5722 stable(feature = "neon_intrinsics", since = "1.59.0")
5723)]
5724#[cfg_attr(
5725 target_arch = "arm",
5726 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5727)]
5728pub fn vcreate_u32(a: u64) -> uint32x2_t {
5729 unsafe { transmute(a) }
5730}
5731#[doc = "Insert vector element from another vector element"]
5732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
5733#[inline]
5734#[cfg(target_endian = "big")]
5735#[target_feature(enable = "neon")]
5736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5738#[cfg_attr(
5739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5740 assert_instr(nop)
5741)]
5742#[cfg_attr(
5743 not(target_arch = "arm"),
5744 stable(feature = "neon_intrinsics", since = "1.59.0")
5745)]
5746#[cfg_attr(
5747 target_arch = "arm",
5748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5749)]
5750pub fn vcreate_u32(a: u64) -> uint32x2_t {
5751 unsafe {
5752 let ret_val: uint32x2_t = transmute(a);
5753 simd_shuffle!(ret_val, ret_val, [1, 0])
5754 }
5755}
5756#[doc = "Insert vector element from another vector element"]
5757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
5758#[inline]
5759#[target_feature(enable = "neon")]
5760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5762#[cfg_attr(
5763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5764 assert_instr(nop)
5765)]
5766#[cfg_attr(
5767 not(target_arch = "arm"),
5768 stable(feature = "neon_intrinsics", since = "1.59.0")
5769)]
5770#[cfg_attr(
5771 target_arch = "arm",
5772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5773)]
5774pub fn vcreate_u64(a: u64) -> uint64x1_t {
5775 unsafe { transmute(a) }
5776}
5777#[doc = "Insert vector element from another vector element"]
5778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
5779#[inline]
5780#[cfg(target_endian = "little")]
5781#[target_feature(enable = "neon")]
5782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5784#[cfg_attr(
5785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5786 assert_instr(nop)
5787)]
5788#[cfg_attr(
5789 not(target_arch = "arm"),
5790 stable(feature = "neon_intrinsics", since = "1.59.0")
5791)]
5792#[cfg_attr(
5793 target_arch = "arm",
5794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5795)]
5796pub fn vcreate_p8(a: u64) -> poly8x8_t {
5797 unsafe { transmute(a) }
5798}
5799#[doc = "Insert vector element from another vector element"]
5800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
5801#[inline]
5802#[cfg(target_endian = "big")]
5803#[target_feature(enable = "neon")]
5804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5806#[cfg_attr(
5807 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5808 assert_instr(nop)
5809)]
5810#[cfg_attr(
5811 not(target_arch = "arm"),
5812 stable(feature = "neon_intrinsics", since = "1.59.0")
5813)]
5814#[cfg_attr(
5815 target_arch = "arm",
5816 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5817)]
5818pub fn vcreate_p8(a: u64) -> poly8x8_t {
5819 unsafe {
5820 let ret_val: poly8x8_t = transmute(a);
5821 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5822 }
5823}
5824#[doc = "Insert vector element from another vector element"]
5825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
5826#[inline]
5827#[cfg(target_endian = "little")]
5828#[target_feature(enable = "neon")]
5829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5831#[cfg_attr(
5832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5833 assert_instr(nop)
5834)]
5835#[cfg_attr(
5836 not(target_arch = "arm"),
5837 stable(feature = "neon_intrinsics", since = "1.59.0")
5838)]
5839#[cfg_attr(
5840 target_arch = "arm",
5841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5842)]
5843pub fn vcreate_p16(a: u64) -> poly16x4_t {
5844 unsafe { transmute(a) }
5845}
5846#[doc = "Insert vector element from another vector element"]
5847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
5848#[inline]
5849#[cfg(target_endian = "big")]
5850#[target_feature(enable = "neon")]
5851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5853#[cfg_attr(
5854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5855 assert_instr(nop)
5856)]
5857#[cfg_attr(
5858 not(target_arch = "arm"),
5859 stable(feature = "neon_intrinsics", since = "1.59.0")
5860)]
5861#[cfg_attr(
5862 target_arch = "arm",
5863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5864)]
5865pub fn vcreate_p16(a: u64) -> poly16x4_t {
5866 unsafe {
5867 let ret_val: poly16x4_t = transmute(a);
5868 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
5869 }
5870}
5871#[doc = "Insert vector element from another vector element"]
5872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
5873#[inline]
5874#[target_feature(enable = "neon,aes")]
5875#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
5877#[cfg_attr(
5878 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5879 assert_instr(nop)
5880)]
5881#[cfg_attr(
5882 not(target_arch = "arm"),
5883 stable(feature = "neon_intrinsics", since = "1.59.0")
5884)]
5885#[cfg_attr(
5886 target_arch = "arm",
5887 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5888)]
5889pub fn vcreate_p64(a: u64) -> poly64x1_t {
5890 unsafe { transmute(a) }
5891}
5892#[doc = "Floating-point convert to lower precision narrow"]
5893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
5894#[inline]
5895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5896# [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
5897#[cfg_attr(
5898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5899 assert_instr(fcvtn)
5900)]
5901#[target_feature(enable = "neon,fp16")]
5902#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5903pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
5904 unsafe { simd_cast(a) }
5905}
5906#[doc = "Fixed-point convert to floating-point"]
5907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
5908#[inline]
5909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5910#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
5911#[cfg_attr(
5912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5913 assert_instr(scvtf)
5914)]
5915#[target_feature(enable = "neon,fp16")]
5916#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5917pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
5918 unsafe { simd_cast(a) }
5919}
5920#[doc = "Fixed-point convert to floating-point"]
5921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
5922#[inline]
5923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
5925#[cfg_attr(
5926 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5927 assert_instr(scvtf)
5928)]
5929#[target_feature(enable = "neon,fp16")]
5930#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5931pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
5932 unsafe { simd_cast(a) }
5933}
5934#[doc = "Fixed-point convert to floating-point"]
5935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
5936#[inline]
5937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
5939#[cfg_attr(
5940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5941 assert_instr(ucvtf)
5942)]
5943#[target_feature(enable = "neon,fp16")]
5944#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5945pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
5946 unsafe { simd_cast(a) }
5947}
5948#[doc = "Fixed-point convert to floating-point"]
5949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
5950#[inline]
5951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5952#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
5953#[cfg_attr(
5954 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5955 assert_instr(ucvtf)
5956)]
5957#[target_feature(enable = "neon,fp16")]
5958#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5959pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
5960 unsafe { simd_cast(a) }
5961}
5962#[doc = "Floating-point convert to higher precision long"]
5963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
5964#[inline]
5965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
5967#[cfg_attr(
5968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5969 assert_instr(fcvtl)
5970)]
5971#[target_feature(enable = "neon,fp16")]
5972#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5973pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
5974 unsafe { simd_cast(a) }
5975}
5976#[doc = "Fixed-point convert to floating-point"]
5977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
5978#[inline]
5979#[target_feature(enable = "neon")]
5980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
5982#[cfg_attr(
5983 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5984 assert_instr(scvtf)
5985)]
5986#[cfg_attr(
5987 not(target_arch = "arm"),
5988 stable(feature = "neon_intrinsics", since = "1.59.0")
5989)]
5990#[cfg_attr(
5991 target_arch = "arm",
5992 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5993)]
5994pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
5995 unsafe { simd_cast(a) }
5996}
5997#[doc = "Fixed-point convert to floating-point"]
5998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
5999#[inline]
6000#[target_feature(enable = "neon")]
6001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6002#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6003#[cfg_attr(
6004 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6005 assert_instr(scvtf)
6006)]
6007#[cfg_attr(
6008 not(target_arch = "arm"),
6009 stable(feature = "neon_intrinsics", since = "1.59.0")
6010)]
6011#[cfg_attr(
6012 target_arch = "arm",
6013 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6014)]
6015pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
6016 unsafe { simd_cast(a) }
6017}
6018#[doc = "Fixed-point convert to floating-point"]
6019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
6020#[inline]
6021#[target_feature(enable = "neon")]
6022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6024#[cfg_attr(
6025 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6026 assert_instr(ucvtf)
6027)]
6028#[cfg_attr(
6029 not(target_arch = "arm"),
6030 stable(feature = "neon_intrinsics", since = "1.59.0")
6031)]
6032#[cfg_attr(
6033 target_arch = "arm",
6034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6035)]
6036pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
6037 unsafe { simd_cast(a) }
6038}
6039#[doc = "Fixed-point convert to floating-point"]
6040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
6041#[inline]
6042#[target_feature(enable = "neon")]
6043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6044#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6045#[cfg_attr(
6046 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6047 assert_instr(ucvtf)
6048)]
6049#[cfg_attr(
6050 not(target_arch = "arm"),
6051 stable(feature = "neon_intrinsics", since = "1.59.0")
6052)]
6053#[cfg_attr(
6054 target_arch = "arm",
6055 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6056)]
6057pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
6058 unsafe { simd_cast(a) }
6059}
6060#[doc = "Fixed-point convert to floating-point"]
6061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
6062#[inline]
6063#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6064#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6065#[cfg_attr(
6066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6067 assert_instr(scvtf, N = 1)
6068)]
6069#[rustc_legacy_const_generics(1)]
6070#[target_feature(enable = "neon,fp16")]
6071#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6072pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
6073 static_assert!(N >= 1 && N <= 16);
6074 unsafe extern "unadjusted" {
6075 #[cfg_attr(
6076 target_arch = "arm",
6077 link_name = "llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16"
6078 )]
6079 #[cfg_attr(
6080 any(target_arch = "aarch64", target_arch = "arm64ec"),
6081 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16"
6082 )]
6083 fn _vcvt_n_f16_s16(a: int16x4_t, n: i32) -> float16x4_t;
6084 }
6085 unsafe { _vcvt_n_f16_s16(a, N) }
6086}
6087#[doc = "Fixed-point convert to floating-point"]
6088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
6089#[inline]
6090#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6091#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6092#[cfg_attr(
6093 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6094 assert_instr(scvtf, N = 1)
6095)]
6096#[rustc_legacy_const_generics(1)]
6097#[target_feature(enable = "neon,fp16")]
6098#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6099pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
6100 static_assert!(N >= 1 && N <= 16);
6101 unsafe extern "unadjusted" {
6102 #[cfg_attr(
6103 target_arch = "arm",
6104 link_name = "llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16"
6105 )]
6106 #[cfg_attr(
6107 any(target_arch = "aarch64", target_arch = "arm64ec"),
6108 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16"
6109 )]
6110 fn _vcvtq_n_f16_s16(a: int16x8_t, n: i32) -> float16x8_t;
6111 }
6112 unsafe { _vcvtq_n_f16_s16(a, N) }
6113}
6114#[doc = "Fixed-point convert to floating-point"]
6115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
6116#[inline]
6117#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6118#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6119#[cfg_attr(
6120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6121 assert_instr(ucvtf, N = 1)
6122)]
6123#[rustc_legacy_const_generics(1)]
6124#[target_feature(enable = "neon,fp16")]
6125#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6126pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
6127 static_assert!(N >= 1 && N <= 16);
6128 unsafe extern "unadjusted" {
6129 #[cfg_attr(
6130 target_arch = "arm",
6131 link_name = "llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16"
6132 )]
6133 #[cfg_attr(
6134 any(target_arch = "aarch64", target_arch = "arm64ec"),
6135 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16"
6136 )]
6137 fn _vcvt_n_f16_u16(a: uint16x4_t, n: i32) -> float16x4_t;
6138 }
6139 unsafe { _vcvt_n_f16_u16(a, N) }
6140}
6141#[doc = "Fixed-point convert to floating-point"]
6142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
6143#[inline]
6144#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6145#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6146#[cfg_attr(
6147 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6148 assert_instr(ucvtf, N = 1)
6149)]
6150#[rustc_legacy_const_generics(1)]
6151#[target_feature(enable = "neon,fp16")]
6152#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6153pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
6154 static_assert!(N >= 1 && N <= 16);
6155 unsafe extern "unadjusted" {
6156 #[cfg_attr(
6157 target_arch = "arm",
6158 link_name = "llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16"
6159 )]
6160 #[cfg_attr(
6161 any(target_arch = "aarch64", target_arch = "arm64ec"),
6162 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16"
6163 )]
6164 fn _vcvtq_n_f16_u16(a: uint16x8_t, n: i32) -> float16x8_t;
6165 }
6166 unsafe { _vcvtq_n_f16_u16(a, N) }
6167}
6168#[doc = "Fixed-point convert to floating-point"]
6169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
6170#[inline]
6171#[cfg(target_arch = "arm")]
6172#[target_feature(enable = "neon,v7")]
6173#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6174#[rustc_legacy_const_generics(1)]
6175#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6176pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
6177 static_assert!(N >= 1 && N <= 32);
6178 unsafe extern "unadjusted" {
6179 #[cfg_attr(
6180 target_arch = "arm",
6181 link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32"
6182 )]
6183 fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
6184 }
6185 unsafe { _vcvt_n_f32_s32(a, N) }
6186}
6187#[doc = "Fixed-point convert to floating-point"]
6188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
6189#[inline]
6190#[cfg(target_arch = "arm")]
6191#[target_feature(enable = "neon,v7")]
6192#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6193#[rustc_legacy_const_generics(1)]
6194#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6195pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
6196 static_assert!(N >= 1 && N <= 32);
6197 unsafe extern "unadjusted" {
6198 #[cfg_attr(
6199 target_arch = "arm",
6200 link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32"
6201 )]
6202 fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
6203 }
6204 unsafe { _vcvtq_n_f32_s32(a, N) }
6205}
6206#[doc = "Fixed-point convert to floating-point"]
6207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
6208#[inline]
6209#[target_feature(enable = "neon")]
6210#[cfg(not(target_arch = "arm"))]
6211#[cfg_attr(test, assert_instr(scvtf, N = 2))]
6212#[rustc_legacy_const_generics(1)]
6213#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6214pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
6215 static_assert!(N >= 1 && N <= 32);
6216 unsafe extern "unadjusted" {
6217 #[cfg_attr(
6218 any(target_arch = "aarch64", target_arch = "arm64ec"),
6219 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32"
6220 )]
6221 fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
6222 }
6223 unsafe { _vcvt_n_f32_s32(a, N) }
6224}
6225#[doc = "Fixed-point convert to floating-point"]
6226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
6227#[inline]
6228#[target_feature(enable = "neon")]
6229#[cfg(not(target_arch = "arm"))]
6230#[cfg_attr(test, assert_instr(scvtf, N = 2))]
6231#[rustc_legacy_const_generics(1)]
6232#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6233pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
6234 static_assert!(N >= 1 && N <= 32);
6235 unsafe extern "unadjusted" {
6236 #[cfg_attr(
6237 any(target_arch = "aarch64", target_arch = "arm64ec"),
6238 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32"
6239 )]
6240 fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
6241 }
6242 unsafe { _vcvtq_n_f32_s32(a, N) }
6243}
6244#[doc = "Fixed-point convert to floating-point"]
6245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
6246#[inline]
6247#[cfg(target_arch = "arm")]
6248#[target_feature(enable = "neon,v7")]
6249#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6250#[rustc_legacy_const_generics(1)]
6251#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6252pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
6253 static_assert!(N >= 1 && N <= 32);
6254 unsafe extern "unadjusted" {
6255 #[cfg_attr(
6256 target_arch = "arm",
6257 link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32"
6258 )]
6259 fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
6260 }
6261 unsafe { _vcvt_n_f32_u32(a, N) }
6262}
6263#[doc = "Fixed-point convert to floating-point"]
6264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
6265#[inline]
6266#[cfg(target_arch = "arm")]
6267#[target_feature(enable = "neon,v7")]
6268#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6269#[rustc_legacy_const_generics(1)]
6270#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6271pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
6272 static_assert!(N >= 1 && N <= 32);
6273 unsafe extern "unadjusted" {
6274 #[cfg_attr(
6275 target_arch = "arm",
6276 link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32"
6277 )]
6278 fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
6279 }
6280 unsafe { _vcvtq_n_f32_u32(a, N) }
6281}
6282#[doc = "Fixed-point convert to floating-point"]
6283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
6284#[inline]
6285#[target_feature(enable = "neon")]
6286#[cfg(not(target_arch = "arm"))]
6287#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
6288#[rustc_legacy_const_generics(1)]
6289#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6290pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
6291 static_assert!(N >= 1 && N <= 32);
6292 unsafe extern "unadjusted" {
6293 #[cfg_attr(
6294 any(target_arch = "aarch64", target_arch = "arm64ec"),
6295 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32"
6296 )]
6297 fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
6298 }
6299 unsafe { _vcvt_n_f32_u32(a, N) }
6300}
6301#[doc = "Fixed-point convert to floating-point"]
6302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
6303#[inline]
6304#[target_feature(enable = "neon")]
6305#[cfg(not(target_arch = "arm"))]
6306#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
6307#[rustc_legacy_const_generics(1)]
6308#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6309pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
6310 static_assert!(N >= 1 && N <= 32);
6311 unsafe extern "unadjusted" {
6312 #[cfg_attr(
6313 any(target_arch = "aarch64", target_arch = "arm64ec"),
6314 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32"
6315 )]
6316 fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
6317 }
6318 unsafe { _vcvtq_n_f32_u32(a, N) }
6319}
6320#[doc = "Floating-point convert to signed fixed-point"]
6321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
6322#[inline]
6323#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6324#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6325#[cfg_attr(
6326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6327 assert_instr(fcvtzs, N = 1)
6328)]
6329#[rustc_legacy_const_generics(1)]
6330#[target_feature(enable = "neon,fp16")]
6331#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6332pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
6333 static_assert!(N >= 1 && N <= 16);
6334 unsafe extern "unadjusted" {
6335 #[cfg_attr(
6336 target_arch = "arm",
6337 link_name = "llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16"
6338 )]
6339 #[cfg_attr(
6340 any(target_arch = "aarch64", target_arch = "arm64ec"),
6341 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16"
6342 )]
6343 fn _vcvt_n_s16_f16(a: float16x4_t, n: i32) -> int16x4_t;
6344 }
6345 unsafe { _vcvt_n_s16_f16(a, N) }
6346}
6347#[doc = "Floating-point convert to signed fixed-point"]
6348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
6349#[inline]
6350#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6351#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6352#[cfg_attr(
6353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6354 assert_instr(fcvtzs, N = 1)
6355)]
6356#[rustc_legacy_const_generics(1)]
6357#[target_feature(enable = "neon,fp16")]
6358#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6359pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
6360 static_assert!(N >= 1 && N <= 16);
6361 unsafe extern "unadjusted" {
6362 #[cfg_attr(
6363 target_arch = "arm",
6364 link_name = "llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16"
6365 )]
6366 #[cfg_attr(
6367 any(target_arch = "aarch64", target_arch = "arm64ec"),
6368 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16"
6369 )]
6370 fn _vcvtq_n_s16_f16(a: float16x8_t, n: i32) -> int16x8_t;
6371 }
6372 unsafe { _vcvtq_n_s16_f16(a, N) }
6373}
6374#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
6376#[inline]
6377#[cfg(target_arch = "arm")]
6378#[target_feature(enable = "neon,v7")]
6379#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6380#[rustc_legacy_const_generics(1)]
6381#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6382pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
6383 static_assert!(N >= 1 && N <= 32);
6384 unsafe extern "unadjusted" {
6385 #[cfg_attr(
6386 target_arch = "arm",
6387 link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32"
6388 )]
6389 fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
6390 }
6391 unsafe { _vcvt_n_s32_f32(a, N) }
6392}
6393#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
6395#[inline]
6396#[cfg(target_arch = "arm")]
6397#[target_feature(enable = "neon,v7")]
6398#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6399#[rustc_legacy_const_generics(1)]
6400#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6401pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
6402 static_assert!(N >= 1 && N <= 32);
6403 unsafe extern "unadjusted" {
6404 #[cfg_attr(
6405 target_arch = "arm",
6406 link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32"
6407 )]
6408 fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
6409 }
6410 unsafe { _vcvtq_n_s32_f32(a, N) }
6411}
6412#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
6414#[inline]
6415#[target_feature(enable = "neon")]
6416#[cfg(not(target_arch = "arm"))]
6417#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
6418#[rustc_legacy_const_generics(1)]
6419#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6420pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
6421 static_assert!(N >= 1 && N <= 32);
6422 unsafe extern "unadjusted" {
6423 #[cfg_attr(
6424 any(target_arch = "aarch64", target_arch = "arm64ec"),
6425 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32"
6426 )]
6427 fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
6428 }
6429 unsafe { _vcvt_n_s32_f32(a, N) }
6430}
6431#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
6433#[inline]
6434#[target_feature(enable = "neon")]
6435#[cfg(not(target_arch = "arm"))]
6436#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
6437#[rustc_legacy_const_generics(1)]
6438#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6439pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
6440 static_assert!(N >= 1 && N <= 32);
6441 unsafe extern "unadjusted" {
6442 #[cfg_attr(
6443 any(target_arch = "aarch64", target_arch = "arm64ec"),
6444 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32"
6445 )]
6446 fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
6447 }
6448 unsafe { _vcvtq_n_s32_f32(a, N) }
6449}
6450#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
6451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
6452#[inline]
6453#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6455#[cfg_attr(
6456 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6457 assert_instr(fcvtzu, N = 1)
6458)]
6459#[rustc_legacy_const_generics(1)]
6460#[target_feature(enable = "neon,fp16")]
6461#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6462pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
6463 static_assert!(N >= 1 && N <= 16);
6464 unsafe extern "unadjusted" {
6465 #[cfg_attr(
6466 target_arch = "arm",
6467 link_name = "llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16"
6468 )]
6469 #[cfg_attr(
6470 any(target_arch = "aarch64", target_arch = "arm64ec"),
6471 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16"
6472 )]
6473 fn _vcvt_n_u16_f16(a: float16x4_t, n: i32) -> uint16x4_t;
6474 }
6475 unsafe { _vcvt_n_u16_f16(a, N) }
6476}
6477#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
6478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
6479#[inline]
6480#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6481#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
6482#[cfg_attr(
6483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6484 assert_instr(fcvtzu, N = 1)
6485)]
6486#[rustc_legacy_const_generics(1)]
6487#[target_feature(enable = "neon,fp16")]
6488#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6489pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
6490 static_assert!(N >= 1 && N <= 16);
6491 unsafe extern "unadjusted" {
6492 #[cfg_attr(
6493 target_arch = "arm",
6494 link_name = "llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16"
6495 )]
6496 #[cfg_attr(
6497 any(target_arch = "aarch64", target_arch = "arm64ec"),
6498 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16"
6499 )]
6500 fn _vcvtq_n_u16_f16(a: float16x8_t, n: i32) -> uint16x8_t;
6501 }
6502 unsafe { _vcvtq_n_u16_f16(a, N) }
6503}
6504#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
6506#[inline]
6507#[cfg(target_arch = "arm")]
6508#[target_feature(enable = "neon,v7")]
6509#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6510#[rustc_legacy_const_generics(1)]
6511#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6512pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
6513 static_assert!(N >= 1 && N <= 32);
6514 unsafe extern "unadjusted" {
6515 #[cfg_attr(
6516 target_arch = "arm",
6517 link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32"
6518 )]
6519 fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
6520 }
6521 unsafe { _vcvt_n_u32_f32(a, N) }
6522}
6523#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
6525#[inline]
6526#[cfg(target_arch = "arm")]
6527#[target_feature(enable = "neon,v7")]
6528#[cfg_attr(test, assert_instr(vcvt, N = 2))]
6529#[rustc_legacy_const_generics(1)]
6530#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
6531pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
6532 static_assert!(N >= 1 && N <= 32);
6533 unsafe extern "unadjusted" {
6534 #[cfg_attr(
6535 target_arch = "arm",
6536 link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32"
6537 )]
6538 fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
6539 }
6540 unsafe { _vcvtq_n_u32_f32(a, N) }
6541}
6542#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
6544#[inline]
6545#[target_feature(enable = "neon")]
6546#[cfg(not(target_arch = "arm"))]
6547#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
6548#[rustc_legacy_const_generics(1)]
6549#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6550pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
6551 static_assert!(N >= 1 && N <= 32);
6552 unsafe extern "unadjusted" {
6553 #[cfg_attr(
6554 any(target_arch = "aarch64", target_arch = "arm64ec"),
6555 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32"
6556 )]
6557 fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
6558 }
6559 unsafe { _vcvt_n_u32_f32(a, N) }
6560}
6561#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
6563#[inline]
6564#[target_feature(enable = "neon")]
6565#[cfg(not(target_arch = "arm"))]
6566#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
6567#[rustc_legacy_const_generics(1)]
6568#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6569pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
6570 static_assert!(N >= 1 && N <= 32);
6571 unsafe extern "unadjusted" {
6572 #[cfg_attr(
6573 any(target_arch = "aarch64", target_arch = "arm64ec"),
6574 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32"
6575 )]
6576 fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
6577 }
6578 unsafe { _vcvtq_n_u32_f32(a, N) }
6579}
6580#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
6581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
6582#[inline]
6583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6585#[cfg_attr(
6586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6587 assert_instr(fcvtzs)
6588)]
6589#[target_feature(enable = "neon,fp16")]
6590#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6591pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
6592 unsafe { simd_cast(a) }
6593}
6594#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
6595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
6596#[inline]
6597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6599#[cfg_attr(
6600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6601 assert_instr(fcvtzs)
6602)]
6603#[target_feature(enable = "neon,fp16")]
6604#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6605pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
6606 unsafe { simd_cast(a) }
6607}
6608#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
6609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
6610#[inline]
6611#[target_feature(enable = "neon")]
6612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6614#[cfg_attr(
6615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6616 assert_instr(fcvtzs)
6617)]
6618#[cfg_attr(
6619 not(target_arch = "arm"),
6620 stable(feature = "neon_intrinsics", since = "1.59.0")
6621)]
6622#[cfg_attr(
6623 target_arch = "arm",
6624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6625)]
6626pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
6627 unsafe extern "unadjusted" {
6628 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")]
6629 #[cfg_attr(
6630 any(target_arch = "aarch64", target_arch = "arm64ec"),
6631 link_name = "llvm.fptosi.sat.v2i32.v2f32"
6632 )]
6633 fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t;
6634 }
6635 unsafe { _vcvt_s32_f32(a) }
6636}
6637#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
6638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
6639#[inline]
6640#[target_feature(enable = "neon")]
6641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6643#[cfg_attr(
6644 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6645 assert_instr(fcvtzs)
6646)]
6647#[cfg_attr(
6648 not(target_arch = "arm"),
6649 stable(feature = "neon_intrinsics", since = "1.59.0")
6650)]
6651#[cfg_attr(
6652 target_arch = "arm",
6653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6654)]
6655pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
6656 unsafe extern "unadjusted" {
6657 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")]
6658 #[cfg_attr(
6659 any(target_arch = "aarch64", target_arch = "arm64ec"),
6660 link_name = "llvm.fptosi.sat.v4i32.v4f32"
6661 )]
6662 fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t;
6663 }
6664 unsafe { _vcvtq_s32_f32(a) }
6665}
6666#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
6667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
6668#[inline]
6669#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6671#[cfg_attr(
6672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6673 assert_instr(fcvtzu)
6674)]
6675#[target_feature(enable = "neon,fp16")]
6676#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6677pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
6678 unsafe { simd_cast(a) }
6679}
6680#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
6681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
6682#[inline]
6683#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6685#[cfg_attr(
6686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6687 assert_instr(fcvtzu)
6688)]
6689#[target_feature(enable = "neon,fp16")]
6690#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6691pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
6692 unsafe { simd_cast(a) }
6693}
6694#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
6695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
6696#[inline]
6697#[target_feature(enable = "neon")]
6698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6700#[cfg_attr(
6701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6702 assert_instr(fcvtzu)
6703)]
6704#[cfg_attr(
6705 not(target_arch = "arm"),
6706 stable(feature = "neon_intrinsics", since = "1.59.0")
6707)]
6708#[cfg_attr(
6709 target_arch = "arm",
6710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6711)]
6712pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
6713 unsafe extern "unadjusted" {
6714 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")]
6715 #[cfg_attr(
6716 any(target_arch = "aarch64", target_arch = "arm64ec"),
6717 link_name = "llvm.fptoui.sat.v2i32.v2f32"
6718 )]
6719 fn _vcvt_u32_f32(a: float32x2_t) -> uint32x2_t;
6720 }
6721 unsafe { _vcvt_u32_f32(a) }
6722}
6723#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
6724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
6725#[inline]
6726#[target_feature(enable = "neon")]
6727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
6729#[cfg_attr(
6730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6731 assert_instr(fcvtzu)
6732)]
6733#[cfg_attr(
6734 not(target_arch = "arm"),
6735 stable(feature = "neon_intrinsics", since = "1.59.0")
6736)]
6737#[cfg_attr(
6738 target_arch = "arm",
6739 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6740)]
6741pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
6742 unsafe extern "unadjusted" {
6743 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")]
6744 #[cfg_attr(
6745 any(target_arch = "aarch64", target_arch = "arm64ec"),
6746 link_name = "llvm.fptoui.sat.v4i32.v4f32"
6747 )]
6748 fn _vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t;
6749 }
6750 unsafe { _vcvtq_u32_f32(a) }
6751}
6752#[doc = "Dot product arithmetic (indexed)"]
6753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
6754#[inline]
6755#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6756#[target_feature(enable = "neon,dotprod")]
6757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
6758#[cfg_attr(
6759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6760 assert_instr(sdot, LANE = 0)
6761)]
6762#[rustc_legacy_const_generics(3)]
6763#[cfg_attr(
6764 not(target_arch = "arm"),
6765 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6766)]
6767#[cfg_attr(
6768 target_arch = "arm",
6769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6770)]
6771pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
6772 static_assert_uimm_bits!(LANE, 1);
6773 unsafe {
6774 let c: int32x2_t = transmute(c);
6775 let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
6776 vdot_s32(a, b, transmute(c))
6777 }
6778}
6779#[doc = "Dot product arithmetic (indexed)"]
6780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
6781#[inline]
6782#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6783#[target_feature(enable = "neon,dotprod")]
6784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
6785#[cfg_attr(
6786 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6787 assert_instr(sdot, LANE = 0)
6788)]
6789#[rustc_legacy_const_generics(3)]
6790#[cfg_attr(
6791 not(target_arch = "arm"),
6792 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6793)]
6794#[cfg_attr(
6795 target_arch = "arm",
6796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6797)]
6798pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
6799 static_assert_uimm_bits!(LANE, 1);
6800 unsafe {
6801 let c: int32x2_t = transmute(c);
6802 let c: int32x4_t =
6803 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
6804 vdotq_s32(a, b, transmute(c))
6805 }
6806}
6807#[doc = "Dot product arithmetic (indexed)"]
6808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
6809#[inline]
6810#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6811#[target_feature(enable = "neon,dotprod")]
6812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
6813#[cfg_attr(
6814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6815 assert_instr(udot, LANE = 0)
6816)]
6817#[rustc_legacy_const_generics(3)]
6818#[cfg_attr(
6819 not(target_arch = "arm"),
6820 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6821)]
6822#[cfg_attr(
6823 target_arch = "arm",
6824 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6825)]
6826pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
6827 static_assert_uimm_bits!(LANE, 1);
6828 unsafe {
6829 let c: uint32x2_t = transmute(c);
6830 let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
6831 vdot_u32(a, b, transmute(c))
6832 }
6833}
6834#[doc = "Dot product arithmetic (indexed)"]
6835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
6836#[inline]
6837#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6838#[target_feature(enable = "neon,dotprod")]
6839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
6840#[cfg_attr(
6841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6842 assert_instr(udot, LANE = 0)
6843)]
6844#[rustc_legacy_const_generics(3)]
6845#[cfg_attr(
6846 not(target_arch = "arm"),
6847 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6848)]
6849#[cfg_attr(
6850 target_arch = "arm",
6851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6852)]
6853pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
6854 static_assert_uimm_bits!(LANE, 1);
6855 unsafe {
6856 let c: uint32x2_t = transmute(c);
6857 let c: uint32x4_t =
6858 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
6859 vdotq_u32(a, b, transmute(c))
6860 }
6861}
6862#[doc = "Dot product arithmetic (vector)"]
6863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
6864#[inline]
6865#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6866#[target_feature(enable = "neon,dotprod")]
6867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
6868#[cfg_attr(
6869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6870 assert_instr(sdot)
6871)]
6872#[cfg_attr(
6873 not(target_arch = "arm"),
6874 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6875)]
6876#[cfg_attr(
6877 target_arch = "arm",
6878 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6879)]
6880pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
6881 unsafe extern "unadjusted" {
6882 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")]
6883 #[cfg_attr(
6884 any(target_arch = "aarch64", target_arch = "arm64ec"),
6885 link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8"
6886 )]
6887 fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t;
6888 }
6889 unsafe { _vdot_s32(a, b, c) }
6890}
6891#[doc = "Dot product arithmetic (vector)"]
6892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
6893#[inline]
6894#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6895#[target_feature(enable = "neon,dotprod")]
6896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
6897#[cfg_attr(
6898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6899 assert_instr(sdot)
6900)]
6901#[cfg_attr(
6902 not(target_arch = "arm"),
6903 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6904)]
6905#[cfg_attr(
6906 target_arch = "arm",
6907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6908)]
6909pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
6910 unsafe extern "unadjusted" {
6911 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")]
6912 #[cfg_attr(
6913 any(target_arch = "aarch64", target_arch = "arm64ec"),
6914 link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8"
6915 )]
6916 fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
6917 }
6918 unsafe { _vdotq_s32(a, b, c) }
6919}
6920#[doc = "Dot product arithmetic (vector)"]
6921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
6922#[inline]
6923#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6924#[target_feature(enable = "neon,dotprod")]
6925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
6926#[cfg_attr(
6927 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6928 assert_instr(udot)
6929)]
6930#[cfg_attr(
6931 not(target_arch = "arm"),
6932 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6933)]
6934#[cfg_attr(
6935 target_arch = "arm",
6936 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6937)]
6938pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
6939 unsafe extern "unadjusted" {
6940 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")]
6941 #[cfg_attr(
6942 any(target_arch = "aarch64", target_arch = "arm64ec"),
6943 link_name = "llvm.aarch64.neon.udot.v2i32.v8i8"
6944 )]
6945 fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t;
6946 }
6947 unsafe { _vdot_u32(a, b, c) }
6948}
6949#[doc = "Dot product arithmetic (vector)"]
6950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
6951#[inline]
6952#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6953#[target_feature(enable = "neon,dotprod")]
6954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
6955#[cfg_attr(
6956 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6957 assert_instr(udot)
6958)]
6959#[cfg_attr(
6960 not(target_arch = "arm"),
6961 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
6962)]
6963#[cfg_attr(
6964 target_arch = "arm",
6965 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6966)]
6967pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
6968 unsafe extern "unadjusted" {
6969 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")]
6970 #[cfg_attr(
6971 any(target_arch = "aarch64", target_arch = "arm64ec"),
6972 link_name = "llvm.aarch64.neon.udot.v4i32.v16i8"
6973 )]
6974 fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
6975 }
6976 unsafe { _vdotq_u32(a, b, c) }
6977}
6978#[doc = "Set all vector lanes to the same value"]
6979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
6980#[inline]
6981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6982#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
6983#[cfg_attr(
6984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6985 assert_instr(dup, N = 2)
6986)]
6987#[rustc_legacy_const_generics(1)]
6988#[target_feature(enable = "neon,fp16")]
6989#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6990pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
6991 static_assert_uimm_bits!(N, 2);
6992 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
6993}
6994#[doc = "Set all vector lanes to the same value"]
6995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
6996#[inline]
6997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6998#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
6999#[cfg_attr(
7000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7001 assert_instr(dup, N = 2)
7002)]
7003#[rustc_legacy_const_generics(1)]
7004#[target_feature(enable = "neon,fp16")]
7005#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7006pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
7007 static_assert_uimm_bits!(N, 2);
7008 unsafe {
7009 simd_shuffle!(
7010 a,
7011 a,
7012 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7013 )
7014 }
7015}
7016#[doc = "Set all vector lanes to the same value"]
7017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
7018#[inline]
7019#[target_feature(enable = "neon")]
7020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7021#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
7022#[cfg_attr(
7023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7024 assert_instr(dup, N = 1)
7025)]
7026#[rustc_legacy_const_generics(1)]
7027#[cfg_attr(
7028 not(target_arch = "arm"),
7029 stable(feature = "neon_intrinsics", since = "1.59.0")
7030)]
7031#[cfg_attr(
7032 target_arch = "arm",
7033 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7034)]
7035pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
7036 static_assert_uimm_bits!(N, 1);
7037 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
7038}
7039#[doc = "Set all vector lanes to the same value"]
7040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
7041#[inline]
7042#[target_feature(enable = "neon")]
7043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7044#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
7045#[cfg_attr(
7046 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7047 assert_instr(dup, N = 1)
7048)]
7049#[rustc_legacy_const_generics(1)]
7050#[cfg_attr(
7051 not(target_arch = "arm"),
7052 stable(feature = "neon_intrinsics", since = "1.59.0")
7053)]
7054#[cfg_attr(
7055 target_arch = "arm",
7056 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7057)]
7058pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
7059 static_assert_uimm_bits!(N, 1);
7060 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
7061}
7062#[doc = "Set all vector lanes to the same value"]
7063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
7064#[inline]
7065#[target_feature(enable = "neon")]
7066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7067#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
7068#[cfg_attr(
7069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7070 assert_instr(dup, N = 1)
7071)]
7072#[rustc_legacy_const_generics(1)]
7073#[cfg_attr(
7074 not(target_arch = "arm"),
7075 stable(feature = "neon_intrinsics", since = "1.59.0")
7076)]
7077#[cfg_attr(
7078 target_arch = "arm",
7079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7080)]
7081pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
7082 static_assert_uimm_bits!(N, 1);
7083 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
7084}
7085#[doc = "Set all vector lanes to the same value"]
7086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
7087#[inline]
7088#[target_feature(enable = "neon")]
7089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7090#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
7091#[cfg_attr(
7092 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7093 assert_instr(dup, N = 1)
7094)]
7095#[rustc_legacy_const_generics(1)]
7096#[cfg_attr(
7097 not(target_arch = "arm"),
7098 stable(feature = "neon_intrinsics", since = "1.59.0")
7099)]
7100#[cfg_attr(
7101 target_arch = "arm",
7102 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7103)]
7104pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
7105 static_assert_uimm_bits!(N, 1);
7106 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7107}
7108#[doc = "Set all vector lanes to the same value"]
7109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
7110#[inline]
7111#[target_feature(enable = "neon")]
7112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7113#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
7114#[cfg_attr(
7115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7116 assert_instr(dup, N = 1)
7117)]
7118#[rustc_legacy_const_generics(1)]
7119#[cfg_attr(
7120 not(target_arch = "arm"),
7121 stable(feature = "neon_intrinsics", since = "1.59.0")
7122)]
7123#[cfg_attr(
7124 target_arch = "arm",
7125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7126)]
7127pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
7128 static_assert_uimm_bits!(N, 1);
7129 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7130}
7131#[doc = "Set all vector lanes to the same value"]
7132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
7133#[inline]
7134#[target_feature(enable = "neon")]
7135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7136#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
7137#[cfg_attr(
7138 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7139 assert_instr(dup, N = 1)
7140)]
7141#[rustc_legacy_const_generics(1)]
7142#[cfg_attr(
7143 not(target_arch = "arm"),
7144 stable(feature = "neon_intrinsics", since = "1.59.0")
7145)]
7146#[cfg_attr(
7147 target_arch = "arm",
7148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7149)]
7150pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
7151 static_assert_uimm_bits!(N, 1);
7152 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7153}
7154#[doc = "Set all vector lanes to the same value"]
7155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
7156#[inline]
7157#[target_feature(enable = "neon")]
7158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7159#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
7160#[cfg_attr(
7161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7162 assert_instr(dup, N = 2)
7163)]
7164#[rustc_legacy_const_generics(1)]
7165#[cfg_attr(
7166 not(target_arch = "arm"),
7167 stable(feature = "neon_intrinsics", since = "1.59.0")
7168)]
7169#[cfg_attr(
7170 target_arch = "arm",
7171 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7172)]
7173pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
7174 static_assert_uimm_bits!(N, 2);
7175 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7176}
7177#[doc = "Set all vector lanes to the same value"]
7178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
7179#[inline]
7180#[target_feature(enable = "neon")]
7181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7182#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
7183#[cfg_attr(
7184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7185 assert_instr(dup, N = 2)
7186)]
7187#[rustc_legacy_const_generics(1)]
7188#[cfg_attr(
7189 not(target_arch = "arm"),
7190 stable(feature = "neon_intrinsics", since = "1.59.0")
7191)]
7192#[cfg_attr(
7193 target_arch = "arm",
7194 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7195)]
7196pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
7197 static_assert_uimm_bits!(N, 2);
7198 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7199}
7200#[doc = "Set all vector lanes to the same value"]
7201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
7202#[inline]
7203#[target_feature(enable = "neon")]
7204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7205#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
7206#[cfg_attr(
7207 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7208 assert_instr(dup, N = 2)
7209)]
7210#[rustc_legacy_const_generics(1)]
7211#[cfg_attr(
7212 not(target_arch = "arm"),
7213 stable(feature = "neon_intrinsics", since = "1.59.0")
7214)]
7215#[cfg_attr(
7216 target_arch = "arm",
7217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7218)]
7219pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
7220 static_assert_uimm_bits!(N, 2);
7221 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7222}
7223#[doc = "Set all vector lanes to the same value"]
7224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
7225#[inline]
7226#[target_feature(enable = "neon")]
7227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
7229#[cfg_attr(
7230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7231 assert_instr(dup, N = 2)
7232)]
7233#[rustc_legacy_const_generics(1)]
7234#[cfg_attr(
7235 not(target_arch = "arm"),
7236 stable(feature = "neon_intrinsics", since = "1.59.0")
7237)]
7238#[cfg_attr(
7239 target_arch = "arm",
7240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7241)]
7242pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
7243 static_assert_uimm_bits!(N, 2);
7244 unsafe {
7245 simd_shuffle!(
7246 a,
7247 a,
7248 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7249 )
7250 }
7251}
7252#[doc = "Set all vector lanes to the same value"]
7253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
7254#[inline]
7255#[target_feature(enable = "neon")]
7256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7257#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
7258#[cfg_attr(
7259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7260 assert_instr(dup, N = 2)
7261)]
7262#[rustc_legacy_const_generics(1)]
7263#[cfg_attr(
7264 not(target_arch = "arm"),
7265 stable(feature = "neon_intrinsics", since = "1.59.0")
7266)]
7267#[cfg_attr(
7268 target_arch = "arm",
7269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7270)]
7271pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
7272 static_assert_uimm_bits!(N, 2);
7273 unsafe {
7274 simd_shuffle!(
7275 a,
7276 a,
7277 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7278 )
7279 }
7280}
7281#[doc = "Set all vector lanes to the same value"]
7282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
7283#[inline]
7284#[target_feature(enable = "neon")]
7285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7286#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
7287#[cfg_attr(
7288 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7289 assert_instr(dup, N = 2)
7290)]
7291#[rustc_legacy_const_generics(1)]
7292#[cfg_attr(
7293 not(target_arch = "arm"),
7294 stable(feature = "neon_intrinsics", since = "1.59.0")
7295)]
7296#[cfg_attr(
7297 target_arch = "arm",
7298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7299)]
7300pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
7301 static_assert_uimm_bits!(N, 2);
7302 unsafe {
7303 simd_shuffle!(
7304 a,
7305 a,
7306 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7307 )
7308 }
7309}
7310#[doc = "Set all vector lanes to the same value"]
7311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
7312#[inline]
7313#[target_feature(enable = "neon")]
7314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
7316#[cfg_attr(
7317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7318 assert_instr(dup, N = 4)
7319)]
7320#[rustc_legacy_const_generics(1)]
7321#[cfg_attr(
7322 not(target_arch = "arm"),
7323 stable(feature = "neon_intrinsics", since = "1.59.0")
7324)]
7325#[cfg_attr(
7326 target_arch = "arm",
7327 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7328)]
7329pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
7330 static_assert_uimm_bits!(N, 3);
7331 unsafe {
7332 simd_shuffle!(
7333 a,
7334 a,
7335 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7336 )
7337 }
7338}
7339#[doc = "Set all vector lanes to the same value"]
7340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
7341#[inline]
7342#[target_feature(enable = "neon")]
7343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
7345#[cfg_attr(
7346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7347 assert_instr(dup, N = 4)
7348)]
7349#[rustc_legacy_const_generics(1)]
7350#[cfg_attr(
7351 not(target_arch = "arm"),
7352 stable(feature = "neon_intrinsics", since = "1.59.0")
7353)]
7354#[cfg_attr(
7355 target_arch = "arm",
7356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7357)]
7358pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
7359 static_assert_uimm_bits!(N, 3);
7360 unsafe {
7361 simd_shuffle!(
7362 a,
7363 a,
7364 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7365 )
7366 }
7367}
7368#[doc = "Set all vector lanes to the same value"]
7369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
7370#[inline]
7371#[target_feature(enable = "neon")]
7372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7373#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
7374#[cfg_attr(
7375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7376 assert_instr(dup, N = 4)
7377)]
7378#[rustc_legacy_const_generics(1)]
7379#[cfg_attr(
7380 not(target_arch = "arm"),
7381 stable(feature = "neon_intrinsics", since = "1.59.0")
7382)]
7383#[cfg_attr(
7384 target_arch = "arm",
7385 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7386)]
7387pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
7388 static_assert_uimm_bits!(N, 3);
7389 unsafe {
7390 simd_shuffle!(
7391 a,
7392 a,
7393 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7394 )
7395 }
7396}
7397#[doc = "Set all vector lanes to the same value"]
7398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
7399#[inline]
7400#[target_feature(enable = "neon")]
7401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
7403#[cfg_attr(
7404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7405 assert_instr(dup, N = 4)
7406)]
7407#[rustc_legacy_const_generics(1)]
7408#[cfg_attr(
7409 not(target_arch = "arm"),
7410 stable(feature = "neon_intrinsics", since = "1.59.0")
7411)]
7412#[cfg_attr(
7413 target_arch = "arm",
7414 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7415)]
7416pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
7417 static_assert_uimm_bits!(N, 3);
7418 unsafe {
7419 simd_shuffle!(
7420 a,
7421 a,
7422 [
7423 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
7424 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
7425 ]
7426 )
7427 }
7428}
7429#[doc = "Set all vector lanes to the same value"]
7430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
7431#[inline]
7432#[target_feature(enable = "neon")]
7433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7434#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
7435#[cfg_attr(
7436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7437 assert_instr(dup, N = 4)
7438)]
7439#[rustc_legacy_const_generics(1)]
7440#[cfg_attr(
7441 not(target_arch = "arm"),
7442 stable(feature = "neon_intrinsics", since = "1.59.0")
7443)]
7444#[cfg_attr(
7445 target_arch = "arm",
7446 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7447)]
7448pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
7449 static_assert_uimm_bits!(N, 3);
7450 unsafe {
7451 simd_shuffle!(
7452 a,
7453 a,
7454 [
7455 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
7456 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
7457 ]
7458 )
7459 }
7460}
7461#[doc = "Set all vector lanes to the same value"]
7462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
7463#[inline]
7464#[target_feature(enable = "neon")]
7465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7466#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
7467#[cfg_attr(
7468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7469 assert_instr(dup, N = 4)
7470)]
7471#[rustc_legacy_const_generics(1)]
7472#[cfg_attr(
7473 not(target_arch = "arm"),
7474 stable(feature = "neon_intrinsics", since = "1.59.0")
7475)]
7476#[cfg_attr(
7477 target_arch = "arm",
7478 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7479)]
7480pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
7481 static_assert_uimm_bits!(N, 3);
7482 unsafe {
7483 simd_shuffle!(
7484 a,
7485 a,
7486 [
7487 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
7488 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
7489 ]
7490 )
7491 }
7492}
7493#[doc = "Set all vector lanes to the same value"]
7494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
7495#[inline]
7496#[target_feature(enable = "neon")]
7497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
7499#[cfg_attr(
7500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7501 assert_instr(nop, N = 0)
7502)]
7503#[rustc_legacy_const_generics(1)]
7504#[cfg_attr(
7505 not(target_arch = "arm"),
7506 stable(feature = "neon_intrinsics", since = "1.59.0")
7507)]
7508#[cfg_attr(
7509 target_arch = "arm",
7510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7511)]
7512pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
7513 static_assert!(N == 0);
7514 a
7515}
7516#[doc = "Set all vector lanes to the same value"]
7517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
7518#[inline]
7519#[target_feature(enable = "neon")]
7520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
7522#[cfg_attr(
7523 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7524 assert_instr(nop, N = 0)
7525)]
7526#[rustc_legacy_const_generics(1)]
7527#[cfg_attr(
7528 not(target_arch = "arm"),
7529 stable(feature = "neon_intrinsics", since = "1.59.0")
7530)]
7531#[cfg_attr(
7532 target_arch = "arm",
7533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7534)]
7535pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
7536 static_assert!(N == 0);
7537 a
7538}
7539#[doc = "Set all vector lanes to the same value"]
7540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
7541#[inline]
7542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7544#[cfg_attr(
7545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7546 assert_instr(dup, N = 4)
7547)]
7548#[rustc_legacy_const_generics(1)]
7549#[target_feature(enable = "neon,fp16")]
7550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7551pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
7552 static_assert_uimm_bits!(N, 3);
7553 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7554}
7555#[doc = "Set all vector lanes to the same value"]
7556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
7557#[inline]
7558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7559#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7560#[cfg_attr(
7561 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7562 assert_instr(dup, N = 4)
7563)]
7564#[rustc_legacy_const_generics(1)]
7565#[target_feature(enable = "neon,fp16")]
7566#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7567pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
7568 static_assert_uimm_bits!(N, 3);
7569 unsafe {
7570 simd_shuffle!(
7571 a,
7572 a,
7573 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7574 )
7575 }
7576}
7577#[doc = "Set all vector lanes to the same value"]
7578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
7579#[inline]
7580#[target_feature(enable = "neon")]
7581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
7583#[cfg_attr(
7584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7585 assert_instr(dup, N = 2)
7586)]
7587#[rustc_legacy_const_generics(1)]
7588#[cfg_attr(
7589 not(target_arch = "arm"),
7590 stable(feature = "neon_intrinsics", since = "1.59.0")
7591)]
7592#[cfg_attr(
7593 target_arch = "arm",
7594 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7595)]
7596pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
7597 static_assert_uimm_bits!(N, 2);
7598 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
7599}
7600#[doc = "Set all vector lanes to the same value"]
7601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
7602#[inline]
7603#[target_feature(enable = "neon")]
7604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7605#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
7606#[cfg_attr(
7607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7608 assert_instr(dup, N = 2)
7609)]
7610#[rustc_legacy_const_generics(1)]
7611#[cfg_attr(
7612 not(target_arch = "arm"),
7613 stable(feature = "neon_intrinsics", since = "1.59.0")
7614)]
7615#[cfg_attr(
7616 target_arch = "arm",
7617 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7618)]
7619pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
7620 static_assert_uimm_bits!(N, 2);
7621 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
7622}
7623#[doc = "Set all vector lanes to the same value"]
7624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
7625#[inline]
7626#[target_feature(enable = "neon")]
7627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7628#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
7629#[cfg_attr(
7630 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7631 assert_instr(dup, N = 2)
7632)]
7633#[rustc_legacy_const_generics(1)]
7634#[cfg_attr(
7635 not(target_arch = "arm"),
7636 stable(feature = "neon_intrinsics", since = "1.59.0")
7637)]
7638#[cfg_attr(
7639 target_arch = "arm",
7640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7641)]
7642pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
7643 static_assert_uimm_bits!(N, 2);
7644 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
7645}
7646#[doc = "Set all vector lanes to the same value"]
7647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
7648#[inline]
7649#[target_feature(enable = "neon")]
7650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7651#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
7652#[cfg_attr(
7653 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7654 assert_instr(dup, N = 2)
7655)]
7656#[rustc_legacy_const_generics(1)]
7657#[cfg_attr(
7658 not(target_arch = "arm"),
7659 stable(feature = "neon_intrinsics", since = "1.59.0")
7660)]
7661#[cfg_attr(
7662 target_arch = "arm",
7663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7664)]
7665pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
7666 static_assert_uimm_bits!(N, 2);
7667 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7668}
7669#[doc = "Set all vector lanes to the same value"]
7670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
7671#[inline]
7672#[target_feature(enable = "neon")]
7673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7674#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
7675#[cfg_attr(
7676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7677 assert_instr(dup, N = 2)
7678)]
7679#[rustc_legacy_const_generics(1)]
7680#[cfg_attr(
7681 not(target_arch = "arm"),
7682 stable(feature = "neon_intrinsics", since = "1.59.0")
7683)]
7684#[cfg_attr(
7685 target_arch = "arm",
7686 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7687)]
7688pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
7689 static_assert_uimm_bits!(N, 2);
7690 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7691}
7692#[doc = "Set all vector lanes to the same value"]
7693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
7694#[inline]
7695#[target_feature(enable = "neon")]
7696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7697#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
7698#[cfg_attr(
7699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7700 assert_instr(dup, N = 2)
7701)]
7702#[rustc_legacy_const_generics(1)]
7703#[cfg_attr(
7704 not(target_arch = "arm"),
7705 stable(feature = "neon_intrinsics", since = "1.59.0")
7706)]
7707#[cfg_attr(
7708 target_arch = "arm",
7709 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7710)]
7711pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
7712 static_assert_uimm_bits!(N, 2);
7713 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7714}
7715#[doc = "Set all vector lanes to the same value"]
7716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
7717#[inline]
7718#[target_feature(enable = "neon")]
7719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7720#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7721#[cfg_attr(
7722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7723 assert_instr(dup, N = 4)
7724)]
7725#[rustc_legacy_const_generics(1)]
7726#[cfg_attr(
7727 not(target_arch = "arm"),
7728 stable(feature = "neon_intrinsics", since = "1.59.0")
7729)]
7730#[cfg_attr(
7731 target_arch = "arm",
7732 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7733)]
7734pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
7735 static_assert_uimm_bits!(N, 3);
7736 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7737}
7738#[doc = "Set all vector lanes to the same value"]
7739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
7740#[inline]
7741#[target_feature(enable = "neon")]
7742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7743#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7744#[cfg_attr(
7745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7746 assert_instr(dup, N = 4)
7747)]
7748#[rustc_legacy_const_generics(1)]
7749#[cfg_attr(
7750 not(target_arch = "arm"),
7751 stable(feature = "neon_intrinsics", since = "1.59.0")
7752)]
7753#[cfg_attr(
7754 target_arch = "arm",
7755 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7756)]
7757pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
7758 static_assert_uimm_bits!(N, 3);
7759 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7760}
7761#[doc = "Set all vector lanes to the same value"]
7762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
7763#[inline]
7764#[target_feature(enable = "neon")]
7765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7766#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7767#[cfg_attr(
7768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7769 assert_instr(dup, N = 4)
7770)]
7771#[rustc_legacy_const_generics(1)]
7772#[cfg_attr(
7773 not(target_arch = "arm"),
7774 stable(feature = "neon_intrinsics", since = "1.59.0")
7775)]
7776#[cfg_attr(
7777 target_arch = "arm",
7778 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7779)]
7780pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
7781 static_assert_uimm_bits!(N, 3);
7782 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
7783}
7784#[doc = "Set all vector lanes to the same value"]
7785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
7786#[inline]
7787#[target_feature(enable = "neon")]
7788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7789#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7790#[cfg_attr(
7791 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7792 assert_instr(dup, N = 4)
7793)]
7794#[rustc_legacy_const_generics(1)]
7795#[cfg_attr(
7796 not(target_arch = "arm"),
7797 stable(feature = "neon_intrinsics", since = "1.59.0")
7798)]
7799#[cfg_attr(
7800 target_arch = "arm",
7801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7802)]
7803pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
7804 static_assert_uimm_bits!(N, 3);
7805 unsafe {
7806 simd_shuffle!(
7807 a,
7808 a,
7809 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7810 )
7811 }
7812}
7813#[doc = "Set all vector lanes to the same value"]
7814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
7815#[inline]
7816#[target_feature(enable = "neon")]
7817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7818#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7819#[cfg_attr(
7820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7821 assert_instr(dup, N = 4)
7822)]
7823#[rustc_legacy_const_generics(1)]
7824#[cfg_attr(
7825 not(target_arch = "arm"),
7826 stable(feature = "neon_intrinsics", since = "1.59.0")
7827)]
7828#[cfg_attr(
7829 target_arch = "arm",
7830 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7831)]
7832pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
7833 static_assert_uimm_bits!(N, 3);
7834 unsafe {
7835 simd_shuffle!(
7836 a,
7837 a,
7838 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7839 )
7840 }
7841}
7842#[doc = "Set all vector lanes to the same value"]
7843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
7844#[inline]
7845#[target_feature(enable = "neon")]
7846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7847#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
7848#[cfg_attr(
7849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7850 assert_instr(dup, N = 4)
7851)]
7852#[rustc_legacy_const_generics(1)]
7853#[cfg_attr(
7854 not(target_arch = "arm"),
7855 stable(feature = "neon_intrinsics", since = "1.59.0")
7856)]
7857#[cfg_attr(
7858 target_arch = "arm",
7859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7860)]
7861pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
7862 static_assert_uimm_bits!(N, 3);
7863 unsafe {
7864 simd_shuffle!(
7865 a,
7866 a,
7867 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7868 )
7869 }
7870}
7871#[doc = "Set all vector lanes to the same value"]
7872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
7873#[inline]
7874#[target_feature(enable = "neon")]
7875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7876#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
7877#[cfg_attr(
7878 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7879 assert_instr(dup, N = 8)
7880)]
7881#[rustc_legacy_const_generics(1)]
7882#[cfg_attr(
7883 not(target_arch = "arm"),
7884 stable(feature = "neon_intrinsics", since = "1.59.0")
7885)]
7886#[cfg_attr(
7887 target_arch = "arm",
7888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7889)]
7890pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
7891 static_assert_uimm_bits!(N, 4);
7892 unsafe {
7893 simd_shuffle!(
7894 a,
7895 a,
7896 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7897 )
7898 }
7899}
7900#[doc = "Set all vector lanes to the same value"]
7901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
7902#[inline]
7903#[target_feature(enable = "neon")]
7904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7905#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
7906#[cfg_attr(
7907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7908 assert_instr(dup, N = 8)
7909)]
7910#[rustc_legacy_const_generics(1)]
7911#[cfg_attr(
7912 not(target_arch = "arm"),
7913 stable(feature = "neon_intrinsics", since = "1.59.0")
7914)]
7915#[cfg_attr(
7916 target_arch = "arm",
7917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7918)]
7919pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
7920 static_assert_uimm_bits!(N, 4);
7921 unsafe {
7922 simd_shuffle!(
7923 a,
7924 a,
7925 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7926 )
7927 }
7928}
7929#[doc = "Set all vector lanes to the same value"]
7930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
7931#[inline]
7932#[target_feature(enable = "neon")]
7933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7934#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
7935#[cfg_attr(
7936 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7937 assert_instr(dup, N = 8)
7938)]
7939#[rustc_legacy_const_generics(1)]
7940#[cfg_attr(
7941 not(target_arch = "arm"),
7942 stable(feature = "neon_intrinsics", since = "1.59.0")
7943)]
7944#[cfg_attr(
7945 target_arch = "arm",
7946 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7947)]
7948pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
7949 static_assert_uimm_bits!(N, 4);
7950 unsafe {
7951 simd_shuffle!(
7952 a,
7953 a,
7954 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
7955 )
7956 }
7957}
7958#[doc = "Set all vector lanes to the same value"]
7959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
7960#[inline]
7961#[target_feature(enable = "neon")]
7962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7963#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
7964#[cfg_attr(
7965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7966 assert_instr(dup, N = 8)
7967)]
7968#[rustc_legacy_const_generics(1)]
7969#[cfg_attr(
7970 not(target_arch = "arm"),
7971 stable(feature = "neon_intrinsics", since = "1.59.0")
7972)]
7973#[cfg_attr(
7974 target_arch = "arm",
7975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7976)]
7977pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
7978 static_assert_uimm_bits!(N, 4);
7979 unsafe {
7980 simd_shuffle!(
7981 a,
7982 a,
7983 [
7984 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
7985 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
7986 ]
7987 )
7988 }
7989}
7990#[doc = "Set all vector lanes to the same value"]
7991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
7992#[inline]
7993#[target_feature(enable = "neon")]
7994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7995#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
7996#[cfg_attr(
7997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7998 assert_instr(dup, N = 8)
7999)]
8000#[rustc_legacy_const_generics(1)]
8001#[cfg_attr(
8002 not(target_arch = "arm"),
8003 stable(feature = "neon_intrinsics", since = "1.59.0")
8004)]
8005#[cfg_attr(
8006 target_arch = "arm",
8007 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8008)]
8009pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
8010 static_assert_uimm_bits!(N, 4);
8011 unsafe {
8012 simd_shuffle!(
8013 a,
8014 a,
8015 [
8016 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
8017 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
8018 ]
8019 )
8020 }
8021}
8022#[doc = "Set all vector lanes to the same value"]
8023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
8024#[inline]
8025#[target_feature(enable = "neon")]
8026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8027#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
8028#[cfg_attr(
8029 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8030 assert_instr(dup, N = 8)
8031)]
8032#[rustc_legacy_const_generics(1)]
8033#[cfg_attr(
8034 not(target_arch = "arm"),
8035 stable(feature = "neon_intrinsics", since = "1.59.0")
8036)]
8037#[cfg_attr(
8038 target_arch = "arm",
8039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8040)]
8041pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
8042 static_assert_uimm_bits!(N, 4);
8043 unsafe {
8044 simd_shuffle!(
8045 a,
8046 a,
8047 [
8048 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
8049 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
8050 ]
8051 )
8052 }
8053}
8054#[doc = "Set all vector lanes to the same value"]
8055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
8056#[inline]
8057#[target_feature(enable = "neon")]
8058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
8060#[cfg_attr(
8061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8062 assert_instr(nop, N = 1)
8063)]
8064#[rustc_legacy_const_generics(1)]
8065#[cfg_attr(
8066 not(target_arch = "arm"),
8067 stable(feature = "neon_intrinsics", since = "1.59.0")
8068)]
8069#[cfg_attr(
8070 target_arch = "arm",
8071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8072)]
8073pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
8074 static_assert_uimm_bits!(N, 1);
8075 unsafe { transmute::<i64, _>(simd_extract!(a, N as u32)) }
8076}
8077#[doc = "Set all vector lanes to the same value"]
8078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
8079#[inline]
8080#[target_feature(enable = "neon")]
8081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
8083#[cfg_attr(
8084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8085 assert_instr(nop, N = 1)
8086)]
8087#[rustc_legacy_const_generics(1)]
8088#[cfg_attr(
8089 not(target_arch = "arm"),
8090 stable(feature = "neon_intrinsics", since = "1.59.0")
8091)]
8092#[cfg_attr(
8093 target_arch = "arm",
8094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8095)]
8096pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
8097 static_assert_uimm_bits!(N, 1);
8098 unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
8099}
8100#[doc = "Create a new vector with all lanes set to a value"]
8101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
8102#[inline]
8103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8104#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
8105#[cfg_attr(
8106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8107 assert_instr(dup)
8108)]
8109#[target_feature(enable = "neon,fp16")]
8110#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8111pub fn vdup_n_f16(a: f16) -> float16x4_t {
8112 float16x4_t::splat(a)
8113}
8114#[doc = "Create a new vector with all lanes set to a value"]
8115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
8116#[inline]
8117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8118#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
8119#[cfg_attr(
8120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8121 assert_instr(dup)
8122)]
8123#[target_feature(enable = "neon,fp16")]
8124#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8125pub fn vdupq_n_f16(a: f16) -> float16x8_t {
8126 float16x8_t::splat(a)
8127}
8128#[doc = "Set all vector lanes to the same value"]
8129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
8130#[inline]
8131#[target_feature(enable = "neon")]
8132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
8134#[cfg_attr(
8135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8136 assert_instr(dup, N = 0)
8137)]
8138#[rustc_legacy_const_generics(1)]
8139#[cfg_attr(
8140 not(target_arch = "arm"),
8141 stable(feature = "neon_intrinsics", since = "1.59.0")
8142)]
8143#[cfg_attr(
8144 target_arch = "arm",
8145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8146)]
8147pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
8148 static_assert!(N == 0);
8149 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8150}
8151#[doc = "Set all vector lanes to the same value"]
8152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
8153#[inline]
8154#[target_feature(enable = "neon")]
8155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
8157#[cfg_attr(
8158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8159 assert_instr(dup, N = 0)
8160)]
8161#[rustc_legacy_const_generics(1)]
8162#[cfg_attr(
8163 not(target_arch = "arm"),
8164 stable(feature = "neon_intrinsics", since = "1.59.0")
8165)]
8166#[cfg_attr(
8167 target_arch = "arm",
8168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8169)]
8170pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
8171 static_assert!(N == 0);
8172 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8173}
8174#[doc = "Set all vector lanes to the same value"]
8175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
8176#[inline]
8177#[target_feature(enable = "neon")]
8178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
8180#[cfg_attr(
8181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8182 assert_instr(dup, N = 1)
8183)]
8184#[rustc_legacy_const_generics(1)]
8185#[cfg_attr(
8186 not(target_arch = "arm"),
8187 stable(feature = "neon_intrinsics", since = "1.59.0")
8188)]
8189#[cfg_attr(
8190 target_arch = "arm",
8191 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8192)]
8193pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
8194 static_assert_uimm_bits!(N, 1);
8195 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8196}
8197#[doc = "Set all vector lanes to the same value"]
8198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
8199#[inline]
8200#[target_feature(enable = "neon")]
8201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
8203#[cfg_attr(
8204 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8205 assert_instr(dup, N = 1)
8206)]
8207#[rustc_legacy_const_generics(1)]
8208#[cfg_attr(
8209 not(target_arch = "arm"),
8210 stable(feature = "neon_intrinsics", since = "1.59.0")
8211)]
8212#[cfg_attr(
8213 target_arch = "arm",
8214 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8215)]
8216pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
8217 static_assert_uimm_bits!(N, 1);
8218 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8219}
8220#[doc = "Vector bitwise exclusive or (vector)"]
8221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
8222#[inline]
8223#[target_feature(enable = "neon")]
8224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8226#[cfg_attr(
8227 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8228 assert_instr(eor)
8229)]
8230#[cfg_attr(
8231 not(target_arch = "arm"),
8232 stable(feature = "neon_intrinsics", since = "1.59.0")
8233)]
8234#[cfg_attr(
8235 target_arch = "arm",
8236 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8237)]
8238pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
8239 unsafe { simd_xor(a, b) }
8240}
8241#[doc = "Vector bitwise exclusive or (vector)"]
8242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
8243#[inline]
8244#[target_feature(enable = "neon")]
8245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8247#[cfg_attr(
8248 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8249 assert_instr(eor)
8250)]
8251#[cfg_attr(
8252 not(target_arch = "arm"),
8253 stable(feature = "neon_intrinsics", since = "1.59.0")
8254)]
8255#[cfg_attr(
8256 target_arch = "arm",
8257 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8258)]
8259pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
8260 unsafe { simd_xor(a, b) }
8261}
8262#[doc = "Vector bitwise exclusive or (vector)"]
8263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
8264#[inline]
8265#[target_feature(enable = "neon")]
8266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8268#[cfg_attr(
8269 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8270 assert_instr(eor)
8271)]
8272#[cfg_attr(
8273 not(target_arch = "arm"),
8274 stable(feature = "neon_intrinsics", since = "1.59.0")
8275)]
8276#[cfg_attr(
8277 target_arch = "arm",
8278 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8279)]
8280pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
8281 unsafe { simd_xor(a, b) }
8282}
8283#[doc = "Vector bitwise exclusive or (vector)"]
8284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
8285#[inline]
8286#[target_feature(enable = "neon")]
8287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8289#[cfg_attr(
8290 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8291 assert_instr(eor)
8292)]
8293#[cfg_attr(
8294 not(target_arch = "arm"),
8295 stable(feature = "neon_intrinsics", since = "1.59.0")
8296)]
8297#[cfg_attr(
8298 target_arch = "arm",
8299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8300)]
8301pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
8302 unsafe { simd_xor(a, b) }
8303}
8304#[doc = "Vector bitwise exclusive or (vector)"]
8305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
8306#[inline]
8307#[target_feature(enable = "neon")]
8308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8310#[cfg_attr(
8311 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8312 assert_instr(eor)
8313)]
8314#[cfg_attr(
8315 not(target_arch = "arm"),
8316 stable(feature = "neon_intrinsics", since = "1.59.0")
8317)]
8318#[cfg_attr(
8319 target_arch = "arm",
8320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8321)]
8322pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
8323 unsafe { simd_xor(a, b) }
8324}
8325#[doc = "Vector bitwise exclusive or (vector)"]
8326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
8327#[inline]
8328#[target_feature(enable = "neon")]
8329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8331#[cfg_attr(
8332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8333 assert_instr(eor)
8334)]
8335#[cfg_attr(
8336 not(target_arch = "arm"),
8337 stable(feature = "neon_intrinsics", since = "1.59.0")
8338)]
8339#[cfg_attr(
8340 target_arch = "arm",
8341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8342)]
8343pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
8344 unsafe { simd_xor(a, b) }
8345}
8346#[doc = "Vector bitwise exclusive or (vector)"]
8347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
8348#[inline]
8349#[target_feature(enable = "neon")]
8350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8352#[cfg_attr(
8353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8354 assert_instr(eor)
8355)]
8356#[cfg_attr(
8357 not(target_arch = "arm"),
8358 stable(feature = "neon_intrinsics", since = "1.59.0")
8359)]
8360#[cfg_attr(
8361 target_arch = "arm",
8362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8363)]
8364pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
8365 unsafe { simd_xor(a, b) }
8366}
8367#[doc = "Vector bitwise exclusive or (vector)"]
8368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
8369#[inline]
8370#[target_feature(enable = "neon")]
8371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8373#[cfg_attr(
8374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8375 assert_instr(eor)
8376)]
8377#[cfg_attr(
8378 not(target_arch = "arm"),
8379 stable(feature = "neon_intrinsics", since = "1.59.0")
8380)]
8381#[cfg_attr(
8382 target_arch = "arm",
8383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8384)]
8385pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
8386 unsafe { simd_xor(a, b) }
8387}
8388#[doc = "Vector bitwise exclusive or (vector)"]
8389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
8390#[inline]
8391#[target_feature(enable = "neon")]
8392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8394#[cfg_attr(
8395 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8396 assert_instr(eor)
8397)]
8398#[cfg_attr(
8399 not(target_arch = "arm"),
8400 stable(feature = "neon_intrinsics", since = "1.59.0")
8401)]
8402#[cfg_attr(
8403 target_arch = "arm",
8404 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8405)]
8406pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
8407 unsafe { simd_xor(a, b) }
8408}
8409#[doc = "Vector bitwise exclusive or (vector)"]
8410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
8411#[inline]
8412#[target_feature(enable = "neon")]
8413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8415#[cfg_attr(
8416 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8417 assert_instr(eor)
8418)]
8419#[cfg_attr(
8420 not(target_arch = "arm"),
8421 stable(feature = "neon_intrinsics", since = "1.59.0")
8422)]
8423#[cfg_attr(
8424 target_arch = "arm",
8425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8426)]
8427pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
8428 unsafe { simd_xor(a, b) }
8429}
8430#[doc = "Vector bitwise exclusive or (vector)"]
8431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
8432#[inline]
8433#[target_feature(enable = "neon")]
8434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8436#[cfg_attr(
8437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8438 assert_instr(eor)
8439)]
8440#[cfg_attr(
8441 not(target_arch = "arm"),
8442 stable(feature = "neon_intrinsics", since = "1.59.0")
8443)]
8444#[cfg_attr(
8445 target_arch = "arm",
8446 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8447)]
8448pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
8449 unsafe { simd_xor(a, b) }
8450}
8451#[doc = "Vector bitwise exclusive or (vector)"]
8452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
8453#[inline]
8454#[target_feature(enable = "neon")]
8455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8457#[cfg_attr(
8458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8459 assert_instr(eor)
8460)]
8461#[cfg_attr(
8462 not(target_arch = "arm"),
8463 stable(feature = "neon_intrinsics", since = "1.59.0")
8464)]
8465#[cfg_attr(
8466 target_arch = "arm",
8467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8468)]
8469pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
8470 unsafe { simd_xor(a, b) }
8471}
8472#[doc = "Vector bitwise exclusive or (vector)"]
8473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
8474#[inline]
8475#[target_feature(enable = "neon")]
8476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8477#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8478#[cfg_attr(
8479 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8480 assert_instr(eor)
8481)]
8482#[cfg_attr(
8483 not(target_arch = "arm"),
8484 stable(feature = "neon_intrinsics", since = "1.59.0")
8485)]
8486#[cfg_attr(
8487 target_arch = "arm",
8488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8489)]
8490pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
8491 unsafe { simd_xor(a, b) }
8492}
8493#[doc = "Vector bitwise exclusive or (vector)"]
8494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
8495#[inline]
8496#[target_feature(enable = "neon")]
8497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8499#[cfg_attr(
8500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8501 assert_instr(eor)
8502)]
8503#[cfg_attr(
8504 not(target_arch = "arm"),
8505 stable(feature = "neon_intrinsics", since = "1.59.0")
8506)]
8507#[cfg_attr(
8508 target_arch = "arm",
8509 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8510)]
8511pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
8512 unsafe { simd_xor(a, b) }
8513}
8514#[doc = "Vector bitwise exclusive or (vector)"]
8515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
8516#[inline]
8517#[target_feature(enable = "neon")]
8518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8520#[cfg_attr(
8521 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8522 assert_instr(eor)
8523)]
8524#[cfg_attr(
8525 not(target_arch = "arm"),
8526 stable(feature = "neon_intrinsics", since = "1.59.0")
8527)]
8528#[cfg_attr(
8529 target_arch = "arm",
8530 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8531)]
8532pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
8533 unsafe { simd_xor(a, b) }
8534}
8535#[doc = "Vector bitwise exclusive or (vector)"]
8536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
8537#[inline]
8538#[target_feature(enable = "neon")]
8539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
8541#[cfg_attr(
8542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8543 assert_instr(eor)
8544)]
8545#[cfg_attr(
8546 not(target_arch = "arm"),
8547 stable(feature = "neon_intrinsics", since = "1.59.0")
8548)]
8549#[cfg_attr(
8550 target_arch = "arm",
8551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8552)]
8553pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
8554 unsafe { simd_xor(a, b) }
8555}
8556#[doc = "Extract vector from pair of vectors"]
8557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
8558#[inline]
8559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8560#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
8561#[cfg_attr(
8562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8563 assert_instr(ext, N = 3)
8564)]
8565#[rustc_legacy_const_generics(2)]
8566#[target_feature(enable = "neon,fp16")]
8567#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8568pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
8569 static_assert_uimm_bits!(N, 2);
8570 unsafe {
8571 match N & 0b11 {
8572 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
8573 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
8574 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
8575 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
8576 _ => unreachable_unchecked(),
8577 }
8578 }
8579}
8580#[doc = "Extract vector from pair of vectors"]
8581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
8582#[inline]
8583#[target_feature(enable = "neon")]
8584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8585#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
8586#[cfg_attr(
8587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8588 assert_instr(ext, N = 1)
8589)]
8590#[rustc_legacy_const_generics(2)]
8591#[cfg_attr(
8592 not(target_arch = "arm"),
8593 stable(feature = "neon_intrinsics", since = "1.59.0")
8594)]
8595#[cfg_attr(
8596 target_arch = "arm",
8597 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8598)]
8599pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
8600 static_assert_uimm_bits!(N, 1);
8601 unsafe {
8602 match N & 0b1 {
8603 0 => simd_shuffle!(a, b, [0, 1]),
8604 1 => simd_shuffle!(a, b, [1, 2]),
8605 _ => unreachable_unchecked(),
8606 }
8607 }
8608}
8609#[doc = "Extract vector from pair of vectors"]
8610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
8611#[inline]
8612#[target_feature(enable = "neon")]
8613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8614#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
8615#[cfg_attr(
8616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8617 assert_instr(ext, N = 1)
8618)]
8619#[rustc_legacy_const_generics(2)]
8620#[cfg_attr(
8621 not(target_arch = "arm"),
8622 stable(feature = "neon_intrinsics", since = "1.59.0")
8623)]
8624#[cfg_attr(
8625 target_arch = "arm",
8626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8627)]
8628pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
8629 static_assert_uimm_bits!(N, 1);
8630 unsafe {
8631 match N & 0b1 {
8632 0 => simd_shuffle!(a, b, [0, 1]),
8633 1 => simd_shuffle!(a, b, [1, 2]),
8634 _ => unreachable_unchecked(),
8635 }
8636 }
8637}
8638#[doc = "Extract vector from pair of vectors"]
8639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
8640#[inline]
8641#[target_feature(enable = "neon")]
8642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
8644#[cfg_attr(
8645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8646 assert_instr(ext, N = 1)
8647)]
8648#[rustc_legacy_const_generics(2)]
8649#[cfg_attr(
8650 not(target_arch = "arm"),
8651 stable(feature = "neon_intrinsics", since = "1.59.0")
8652)]
8653#[cfg_attr(
8654 target_arch = "arm",
8655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8656)]
8657pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
8658 static_assert_uimm_bits!(N, 1);
8659 unsafe {
8660 match N & 0b1 {
8661 0 => simd_shuffle!(a, b, [0, 1]),
8662 1 => simd_shuffle!(a, b, [1, 2]),
8663 _ => unreachable_unchecked(),
8664 }
8665 }
8666}
8667#[doc = "Extract vector from pair of vectors"]
8668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
8669#[inline]
8670#[target_feature(enable = "neon")]
8671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8672#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8673#[cfg_attr(
8674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8675 assert_instr(ext, N = 7)
8676)]
8677#[rustc_legacy_const_generics(2)]
8678#[cfg_attr(
8679 not(target_arch = "arm"),
8680 stable(feature = "neon_intrinsics", since = "1.59.0")
8681)]
8682#[cfg_attr(
8683 target_arch = "arm",
8684 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8685)]
8686pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
8687 static_assert_uimm_bits!(N, 3);
8688 unsafe {
8689 match N & 0b111 {
8690 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8691 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8692 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8693 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8694 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8695 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8696 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8697 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8698 _ => unreachable_unchecked(),
8699 }
8700 }
8701}
8702#[doc = "Extract vector from pair of vectors"]
8703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
8704#[inline]
8705#[target_feature(enable = "neon")]
8706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8707#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8708#[cfg_attr(
8709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8710 assert_instr(ext, N = 7)
8711)]
8712#[rustc_legacy_const_generics(2)]
8713#[cfg_attr(
8714 not(target_arch = "arm"),
8715 stable(feature = "neon_intrinsics", since = "1.59.0")
8716)]
8717#[cfg_attr(
8718 target_arch = "arm",
8719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8720)]
8721pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
8722 static_assert_uimm_bits!(N, 3);
8723 unsafe {
8724 match N & 0b111 {
8725 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8726 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8727 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8728 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8729 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8730 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8731 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8732 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8733 _ => unreachable_unchecked(),
8734 }
8735 }
8736}
8737#[doc = "Extract vector from pair of vectors"]
8738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
8739#[inline]
8740#[target_feature(enable = "neon")]
8741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8743#[cfg_attr(
8744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8745 assert_instr(ext, N = 7)
8746)]
8747#[rustc_legacy_const_generics(2)]
8748#[cfg_attr(
8749 not(target_arch = "arm"),
8750 stable(feature = "neon_intrinsics", since = "1.59.0")
8751)]
8752#[cfg_attr(
8753 target_arch = "arm",
8754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8755)]
8756pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
8757 static_assert_uimm_bits!(N, 3);
8758 unsafe {
8759 match N & 0b111 {
8760 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8761 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8762 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8763 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8764 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8765 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8766 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8767 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8768 _ => unreachable_unchecked(),
8769 }
8770 }
8771}
8772#[doc = "Extract vector from pair of vectors"]
8773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
8774#[inline]
8775#[target_feature(enable = "neon")]
8776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8777#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8778#[cfg_attr(
8779 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8780 assert_instr(ext, N = 7)
8781)]
8782#[rustc_legacy_const_generics(2)]
8783#[cfg_attr(
8784 not(target_arch = "arm"),
8785 stable(feature = "neon_intrinsics", since = "1.59.0")
8786)]
8787#[cfg_attr(
8788 target_arch = "arm",
8789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8790)]
8791pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
8792 static_assert_uimm_bits!(N, 3);
8793 unsafe {
8794 match N & 0b111 {
8795 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8796 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8797 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8798 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8799 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8800 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8801 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8802 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8803 _ => unreachable_unchecked(),
8804 }
8805 }
8806}
8807#[doc = "Extract vector from pair of vectors"]
8808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
8809#[inline]
8810#[target_feature(enable = "neon")]
8811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8812#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8813#[cfg_attr(
8814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8815 assert_instr(ext, N = 7)
8816)]
8817#[rustc_legacy_const_generics(2)]
8818#[cfg_attr(
8819 not(target_arch = "arm"),
8820 stable(feature = "neon_intrinsics", since = "1.59.0")
8821)]
8822#[cfg_attr(
8823 target_arch = "arm",
8824 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8825)]
8826pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
8827 static_assert_uimm_bits!(N, 3);
8828 unsafe {
8829 match N & 0b111 {
8830 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8831 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8832 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8833 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8834 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8835 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8836 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8837 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8838 _ => unreachable_unchecked(),
8839 }
8840 }
8841}
8842#[doc = "Extract vector from pair of vectors"]
8843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
8844#[inline]
8845#[target_feature(enable = "neon")]
8846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8847#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8848#[cfg_attr(
8849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8850 assert_instr(ext, N = 7)
8851)]
8852#[rustc_legacy_const_generics(2)]
8853#[cfg_attr(
8854 not(target_arch = "arm"),
8855 stable(feature = "neon_intrinsics", since = "1.59.0")
8856)]
8857#[cfg_attr(
8858 target_arch = "arm",
8859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8860)]
8861pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
8862 static_assert_uimm_bits!(N, 3);
8863 unsafe {
8864 match N & 0b111 {
8865 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8866 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8867 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8868 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8869 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8870 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8871 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8872 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8873 _ => unreachable_unchecked(),
8874 }
8875 }
8876}
8877#[doc = "Extract vector from pair of vectors"]
8878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
8879#[inline]
8880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8881#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
8882#[cfg_attr(
8883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8884 assert_instr(ext, N = 7)
8885)]
8886#[rustc_legacy_const_generics(2)]
8887#[target_feature(enable = "neon,fp16")]
8888#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8889pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
8890 static_assert_uimm_bits!(N, 3);
8891 unsafe {
8892 match N & 0b111 {
8893 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
8894 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
8895 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
8896 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
8897 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
8898 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
8899 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
8900 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
8901 _ => unreachable_unchecked(),
8902 }
8903 }
8904}
8905#[doc = "Extract vector from pair of vectors"]
8906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
8907#[inline]
8908#[target_feature(enable = "neon")]
8909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8910#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
8911#[cfg_attr(
8912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8913 assert_instr(ext, N = 3)
8914)]
8915#[rustc_legacy_const_generics(2)]
8916#[cfg_attr(
8917 not(target_arch = "arm"),
8918 stable(feature = "neon_intrinsics", since = "1.59.0")
8919)]
8920#[cfg_attr(
8921 target_arch = "arm",
8922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8923)]
8924pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
8925 static_assert_uimm_bits!(N, 2);
8926 unsafe {
8927 match N & 0b11 {
8928 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
8929 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
8930 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
8931 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
8932 _ => unreachable_unchecked(),
8933 }
8934 }
8935}
8936#[doc = "Extract vector from pair of vectors"]
8937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
8938#[inline]
8939#[target_feature(enable = "neon")]
8940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
8942#[cfg_attr(
8943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8944 assert_instr(ext, N = 3)
8945)]
8946#[rustc_legacy_const_generics(2)]
8947#[cfg_attr(
8948 not(target_arch = "arm"),
8949 stable(feature = "neon_intrinsics", since = "1.59.0")
8950)]
8951#[cfg_attr(
8952 target_arch = "arm",
8953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8954)]
8955pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
8956 static_assert_uimm_bits!(N, 2);
8957 unsafe {
8958 match N & 0b11 {
8959 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
8960 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
8961 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
8962 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
8963 _ => unreachable_unchecked(),
8964 }
8965 }
8966}
8967#[doc = "Extract vector from pair of vectors"]
8968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
8969#[inline]
8970#[target_feature(enable = "neon")]
8971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8972#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
8973#[cfg_attr(
8974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8975 assert_instr(ext, N = 3)
8976)]
8977#[rustc_legacy_const_generics(2)]
8978#[cfg_attr(
8979 not(target_arch = "arm"),
8980 stable(feature = "neon_intrinsics", since = "1.59.0")
8981)]
8982#[cfg_attr(
8983 target_arch = "arm",
8984 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8985)]
8986pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
8987 static_assert_uimm_bits!(N, 2);
8988 unsafe {
8989 match N & 0b11 {
8990 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
8991 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
8992 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
8993 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
8994 _ => unreachable_unchecked(),
8995 }
8996 }
8997}
8998#[doc = "Extract vector from pair of vectors"]
8999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
9000#[inline]
9001#[target_feature(enable = "neon")]
9002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
9004#[cfg_attr(
9005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9006 assert_instr(ext, N = 3)
9007)]
9008#[rustc_legacy_const_generics(2)]
9009#[cfg_attr(
9010 not(target_arch = "arm"),
9011 stable(feature = "neon_intrinsics", since = "1.59.0")
9012)]
9013#[cfg_attr(
9014 target_arch = "arm",
9015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9016)]
9017pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
9018 static_assert_uimm_bits!(N, 2);
9019 unsafe {
9020 match N & 0b11 {
9021 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
9022 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
9023 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
9024 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
9025 _ => unreachable_unchecked(),
9026 }
9027 }
9028}
9029#[doc = "Extract vector from pair of vectors"]
9030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
9031#[inline]
9032#[target_feature(enable = "neon")]
9033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9034#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
9035#[cfg_attr(
9036 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9037 assert_instr(ext, N = 3)
9038)]
9039#[rustc_legacy_const_generics(2)]
9040#[cfg_attr(
9041 not(target_arch = "arm"),
9042 stable(feature = "neon_intrinsics", since = "1.59.0")
9043)]
9044#[cfg_attr(
9045 target_arch = "arm",
9046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9047)]
9048pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
9049 static_assert_uimm_bits!(N, 2);
9050 unsafe {
9051 match N & 0b11 {
9052 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
9053 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
9054 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
9055 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
9056 _ => unreachable_unchecked(),
9057 }
9058 }
9059}
9060#[doc = "Extract vector from pair of vectors"]
9061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
9062#[inline]
9063#[target_feature(enable = "neon")]
9064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
9066#[cfg_attr(
9067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9068 assert_instr(ext, N = 3)
9069)]
9070#[rustc_legacy_const_generics(2)]
9071#[cfg_attr(
9072 not(target_arch = "arm"),
9073 stable(feature = "neon_intrinsics", since = "1.59.0")
9074)]
9075#[cfg_attr(
9076 target_arch = "arm",
9077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9078)]
9079pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
9080 static_assert_uimm_bits!(N, 2);
9081 unsafe {
9082 match N & 0b11 {
9083 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
9084 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
9085 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
9086 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
9087 _ => unreachable_unchecked(),
9088 }
9089 }
9090}
9091#[doc = "Extract vector from pair of vectors"]
9092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
9093#[inline]
9094#[target_feature(enable = "neon")]
9095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
9097#[cfg_attr(
9098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9099 assert_instr(ext, N = 1)
9100)]
9101#[rustc_legacy_const_generics(2)]
9102#[cfg_attr(
9103 not(target_arch = "arm"),
9104 stable(feature = "neon_intrinsics", since = "1.59.0")
9105)]
9106#[cfg_attr(
9107 target_arch = "arm",
9108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9109)]
9110pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
9111 static_assert_uimm_bits!(N, 1);
9112 unsafe {
9113 match N & 0b1 {
9114 0 => simd_shuffle!(a, b, [0, 1]),
9115 1 => simd_shuffle!(a, b, [1, 2]),
9116 _ => unreachable_unchecked(),
9117 }
9118 }
9119}
9120#[doc = "Extract vector from pair of vectors"]
9121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
9122#[inline]
9123#[target_feature(enable = "neon")]
9124#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9125#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
9126#[cfg_attr(
9127 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9128 assert_instr(ext, N = 1)
9129)]
9130#[rustc_legacy_const_generics(2)]
9131#[cfg_attr(
9132 not(target_arch = "arm"),
9133 stable(feature = "neon_intrinsics", since = "1.59.0")
9134)]
9135#[cfg_attr(
9136 target_arch = "arm",
9137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9138)]
9139pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
9140 static_assert_uimm_bits!(N, 1);
9141 unsafe {
9142 match N & 0b1 {
9143 0 => simd_shuffle!(a, b, [0, 1]),
9144 1 => simd_shuffle!(a, b, [1, 2]),
9145 _ => unreachable_unchecked(),
9146 }
9147 }
9148}
9149#[doc = "Extract vector from pair of vectors"]
9150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
9151#[inline]
9152#[target_feature(enable = "neon")]
9153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9154#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
9155#[cfg_attr(
9156 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9157 assert_instr(ext, N = 15)
9158)]
9159#[rustc_legacy_const_generics(2)]
9160#[cfg_attr(
9161 not(target_arch = "arm"),
9162 stable(feature = "neon_intrinsics", since = "1.59.0")
9163)]
9164#[cfg_attr(
9165 target_arch = "arm",
9166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9167)]
9168pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
9169 static_assert_uimm_bits!(N, 4);
9170 unsafe {
9171 match N & 0b1111 {
9172 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
9173 1 => simd_shuffle!(
9174 a,
9175 b,
9176 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
9177 ),
9178 2 => simd_shuffle!(
9179 a,
9180 b,
9181 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
9182 ),
9183 3 => simd_shuffle!(
9184 a,
9185 b,
9186 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
9187 ),
9188 4 => simd_shuffle!(
9189 a,
9190 b,
9191 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
9192 ),
9193 5 => simd_shuffle!(
9194 a,
9195 b,
9196 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
9197 ),
9198 6 => simd_shuffle!(
9199 a,
9200 b,
9201 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
9202 ),
9203 7 => simd_shuffle!(
9204 a,
9205 b,
9206 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
9207 ),
9208 8 => simd_shuffle!(
9209 a,
9210 b,
9211 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
9212 ),
9213 9 => simd_shuffle!(
9214 a,
9215 b,
9216 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
9217 ),
9218 10 => simd_shuffle!(
9219 a,
9220 b,
9221 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
9222 ),
9223 11 => simd_shuffle!(
9224 a,
9225 b,
9226 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
9227 ),
9228 12 => simd_shuffle!(
9229 a,
9230 b,
9231 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
9232 ),
9233 13 => simd_shuffle!(
9234 a,
9235 b,
9236 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
9237 ),
9238 14 => simd_shuffle!(
9239 a,
9240 b,
9241 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
9242 ),
9243 15 => simd_shuffle!(
9244 a,
9245 b,
9246 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
9247 ),
9248 _ => unreachable_unchecked(),
9249 }
9250 }
9251}
9252#[doc = "Extract vector from pair of vectors"]
9253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
9254#[inline]
9255#[target_feature(enable = "neon")]
9256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9257#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
9258#[cfg_attr(
9259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9260 assert_instr(ext, N = 15)
9261)]
9262#[rustc_legacy_const_generics(2)]
9263#[cfg_attr(
9264 not(target_arch = "arm"),
9265 stable(feature = "neon_intrinsics", since = "1.59.0")
9266)]
9267#[cfg_attr(
9268 target_arch = "arm",
9269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9270)]
9271pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
9272 static_assert_uimm_bits!(N, 4);
9273 unsafe {
9274 match N & 0b1111 {
9275 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
9276 1 => simd_shuffle!(
9277 a,
9278 b,
9279 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
9280 ),
9281 2 => simd_shuffle!(
9282 a,
9283 b,
9284 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
9285 ),
9286 3 => simd_shuffle!(
9287 a,
9288 b,
9289 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
9290 ),
9291 4 => simd_shuffle!(
9292 a,
9293 b,
9294 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
9295 ),
9296 5 => simd_shuffle!(
9297 a,
9298 b,
9299 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
9300 ),
9301 6 => simd_shuffle!(
9302 a,
9303 b,
9304 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
9305 ),
9306 7 => simd_shuffle!(
9307 a,
9308 b,
9309 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
9310 ),
9311 8 => simd_shuffle!(
9312 a,
9313 b,
9314 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
9315 ),
9316 9 => simd_shuffle!(
9317 a,
9318 b,
9319 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
9320 ),
9321 10 => simd_shuffle!(
9322 a,
9323 b,
9324 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
9325 ),
9326 11 => simd_shuffle!(
9327 a,
9328 b,
9329 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
9330 ),
9331 12 => simd_shuffle!(
9332 a,
9333 b,
9334 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
9335 ),
9336 13 => simd_shuffle!(
9337 a,
9338 b,
9339 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
9340 ),
9341 14 => simd_shuffle!(
9342 a,
9343 b,
9344 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
9345 ),
9346 15 => simd_shuffle!(
9347 a,
9348 b,
9349 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
9350 ),
9351 _ => unreachable_unchecked(),
9352 }
9353 }
9354}
9355#[doc = "Extract vector from pair of vectors"]
9356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
9357#[inline]
9358#[target_feature(enable = "neon")]
9359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9360#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
9361#[cfg_attr(
9362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9363 assert_instr(ext, N = 15)
9364)]
9365#[rustc_legacy_const_generics(2)]
9366#[cfg_attr(
9367 not(target_arch = "arm"),
9368 stable(feature = "neon_intrinsics", since = "1.59.0")
9369)]
9370#[cfg_attr(
9371 target_arch = "arm",
9372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9373)]
9374pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
9375 static_assert_uimm_bits!(N, 4);
9376 unsafe {
9377 match N & 0b1111 {
9378 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
9379 1 => simd_shuffle!(
9380 a,
9381 b,
9382 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
9383 ),
9384 2 => simd_shuffle!(
9385 a,
9386 b,
9387 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
9388 ),
9389 3 => simd_shuffle!(
9390 a,
9391 b,
9392 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
9393 ),
9394 4 => simd_shuffle!(
9395 a,
9396 b,
9397 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
9398 ),
9399 5 => simd_shuffle!(
9400 a,
9401 b,
9402 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
9403 ),
9404 6 => simd_shuffle!(
9405 a,
9406 b,
9407 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
9408 ),
9409 7 => simd_shuffle!(
9410 a,
9411 b,
9412 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
9413 ),
9414 8 => simd_shuffle!(
9415 a,
9416 b,
9417 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
9418 ),
9419 9 => simd_shuffle!(
9420 a,
9421 b,
9422 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
9423 ),
9424 10 => simd_shuffle!(
9425 a,
9426 b,
9427 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
9428 ),
9429 11 => simd_shuffle!(
9430 a,
9431 b,
9432 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
9433 ),
9434 12 => simd_shuffle!(
9435 a,
9436 b,
9437 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
9438 ),
9439 13 => simd_shuffle!(
9440 a,
9441 b,
9442 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
9443 ),
9444 14 => simd_shuffle!(
9445 a,
9446 b,
9447 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
9448 ),
9449 15 => simd_shuffle!(
9450 a,
9451 b,
9452 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
9453 ),
9454 _ => unreachable_unchecked(),
9455 }
9456 }
9457}
9458#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
9459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
9460#[inline]
9461#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
9463#[cfg_attr(
9464 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9465 assert_instr(fmla)
9466)]
9467#[target_feature(enable = "neon,fp16")]
9468#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9469pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
9470 unsafe extern "unadjusted" {
9471 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f16")]
9472 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f16")]
9473 fn _vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
9474 }
9475 unsafe { _vfma_f16(b, c, a) }
9476}
9477#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
9478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
9479#[inline]
9480#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
9482#[cfg_attr(
9483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9484 assert_instr(fmla)
9485)]
9486#[target_feature(enable = "neon,fp16")]
9487#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9488pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
9489 unsafe extern "unadjusted" {
9490 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v8f16")]
9491 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v8f16")]
9492 fn _vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
9493 }
9494 unsafe { _vfmaq_f16(b, c, a) }
9495}
9496#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
9497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
9498#[inline]
9499#[target_feature(enable = "neon")]
9500#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
9502#[cfg_attr(
9503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9504 assert_instr(fmla)
9505)]
9506#[cfg_attr(
9507 not(target_arch = "arm"),
9508 stable(feature = "neon_intrinsics", since = "1.59.0")
9509)]
9510#[cfg_attr(
9511 target_arch = "arm",
9512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9513)]
9514pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
9515 unsafe extern "unadjusted" {
9516 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f32")]
9517 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v2f32")]
9518 fn _vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
9519 }
9520 unsafe { _vfma_f32(b, c, a) }
9521}
9522#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
9523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
9524#[inline]
9525#[target_feature(enable = "neon")]
9526#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
9528#[cfg_attr(
9529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9530 assert_instr(fmla)
9531)]
9532#[cfg_attr(
9533 not(target_arch = "arm"),
9534 stable(feature = "neon_intrinsics", since = "1.59.0")
9535)]
9536#[cfg_attr(
9537 target_arch = "arm",
9538 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9539)]
9540pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
9541 unsafe extern "unadjusted" {
9542 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f32")]
9543 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f32")]
9544 fn _vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
9545 }
9546 unsafe { _vfmaq_f32(b, c, a) }
9547}
9548#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
9549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
9550#[inline]
9551#[target_feature(enable = "neon")]
9552#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9553#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
9554#[cfg_attr(
9555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9556 assert_instr(fmla)
9557)]
9558#[cfg_attr(
9559 not(target_arch = "arm"),
9560 stable(feature = "neon_intrinsics", since = "1.59.0")
9561)]
9562#[cfg_attr(
9563 target_arch = "arm",
9564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9565)]
9566pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
9567 vfma_f32(a, b, vdup_n_f32_vfp4(c))
9568}
9569#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
9570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
9571#[inline]
9572#[target_feature(enable = "neon")]
9573#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
9575#[cfg_attr(
9576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9577 assert_instr(fmla)
9578)]
9579#[cfg_attr(
9580 not(target_arch = "arm"),
9581 stable(feature = "neon_intrinsics", since = "1.59.0")
9582)]
9583#[cfg_attr(
9584 target_arch = "arm",
9585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9586)]
9587pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
9588 vfmaq_f32(a, b, vdupq_n_f32_vfp4(c))
9589}
9590#[doc = "Floating-point fused multiply-subtract from accumulator"]
9591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
9592#[inline]
9593#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9594#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
9596#[cfg_attr(
9597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9598 assert_instr(fmls)
9599)]
9600#[target_feature(enable = "neon,fp16")]
9601#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9602pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
9603 unsafe {
9604 let b: float16x4_t = simd_neg(b);
9605 vfma_f16(a, b, c)
9606 }
9607}
9608#[doc = "Floating-point fused multiply-subtract from accumulator"]
9609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
9610#[inline]
9611#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9612#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
9614#[cfg_attr(
9615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9616 assert_instr(fmls)
9617)]
9618#[target_feature(enable = "neon,fp16")]
9619#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9620pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
9621 unsafe {
9622 let b: float16x8_t = simd_neg(b);
9623 vfmaq_f16(a, b, c)
9624 }
9625}
9626#[doc = "Floating-point fused multiply-subtract from accumulator"]
9627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
9628#[inline]
9629#[target_feature(enable = "neon")]
9630#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
9632#[cfg_attr(
9633 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9634 assert_instr(fmls)
9635)]
9636#[cfg_attr(
9637 not(target_arch = "arm"),
9638 stable(feature = "neon_intrinsics", since = "1.59.0")
9639)]
9640#[cfg_attr(
9641 target_arch = "arm",
9642 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9643)]
9644pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
9645 unsafe {
9646 let b: float32x2_t = simd_neg(b);
9647 vfma_f32(a, b, c)
9648 }
9649}
9650#[doc = "Floating-point fused multiply-subtract from accumulator"]
9651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
9652#[inline]
9653#[target_feature(enable = "neon")]
9654#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
9656#[cfg_attr(
9657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9658 assert_instr(fmls)
9659)]
9660#[cfg_attr(
9661 not(target_arch = "arm"),
9662 stable(feature = "neon_intrinsics", since = "1.59.0")
9663)]
9664#[cfg_attr(
9665 target_arch = "arm",
9666 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9667)]
9668pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
9669 unsafe {
9670 let b: float32x4_t = simd_neg(b);
9671 vfmaq_f32(a, b, c)
9672 }
9673}
9674#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
9675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
9676#[inline]
9677#[target_feature(enable = "neon")]
9678#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
9680#[cfg_attr(
9681 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9682 assert_instr(fmls)
9683)]
9684#[cfg_attr(
9685 not(target_arch = "arm"),
9686 stable(feature = "neon_intrinsics", since = "1.59.0")
9687)]
9688#[cfg_attr(
9689 target_arch = "arm",
9690 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9691)]
9692pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
9693 vfms_f32(a, b, vdup_n_f32_vfp4(c))
9694}
9695#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
9696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
9697#[inline]
9698#[target_feature(enable = "neon")]
9699#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
9700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
9701#[cfg_attr(
9702 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9703 assert_instr(fmls)
9704)]
9705#[cfg_attr(
9706 not(target_arch = "arm"),
9707 stable(feature = "neon_intrinsics", since = "1.59.0")
9708)]
9709#[cfg_attr(
9710 target_arch = "arm",
9711 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9712)]
9713pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
9714 vfmsq_f32(a, b, vdupq_n_f32_vfp4(c))
9715}
9716#[doc = "Duplicate vector element to vector"]
9717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
9718#[inline]
9719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9720#[target_feature(enable = "neon,fp16")]
9721#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9722#[cfg_attr(test, assert_instr(nop))]
9723pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
9724 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
9725}
9726#[doc = "Duplicate vector element to vector"]
9727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
9728#[inline]
9729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9730#[target_feature(enable = "neon,fp16")]
9731#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9732#[cfg_attr(test, assert_instr(nop))]
9733pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
9734 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
9735}
9736#[doc = "Duplicate vector element to scalar"]
9737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
9738#[inline]
9739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9740#[target_feature(enable = "neon,fp16")]
9741#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
9742#[cfg_attr(
9743 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9744 assert_instr(nop, LANE = 0)
9745)]
9746#[rustc_legacy_const_generics(1)]
9747#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9748pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
9749 static_assert_uimm_bits!(LANE, 2);
9750 unsafe { simd_extract!(a, LANE as u32) }
9751}
9752#[doc = "Duplicate vector element to scalar"]
9753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
9754#[inline]
9755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9756#[target_feature(enable = "neon,fp16")]
9757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
9758#[cfg_attr(
9759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9760 assert_instr(nop, LANE = 0)
9761)]
9762#[rustc_legacy_const_generics(1)]
9763#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9764pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
9765 static_assert_uimm_bits!(LANE, 3);
9766 unsafe { simd_extract!(a, LANE as u32) }
9767}
9768#[doc = "Halving add"]
9769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
9770#[inline]
9771#[target_feature(enable = "neon")]
9772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9773#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
9774#[cfg_attr(
9775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9776 assert_instr(shadd)
9777)]
9778#[cfg_attr(
9779 not(target_arch = "arm"),
9780 stable(feature = "neon_intrinsics", since = "1.59.0")
9781)]
9782#[cfg_attr(
9783 target_arch = "arm",
9784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9785)]
9786pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
9787 unsafe extern "unadjusted" {
9788 #[cfg_attr(
9789 any(target_arch = "aarch64", target_arch = "arm64ec"),
9790 link_name = "llvm.aarch64.neon.shadd.v8i8"
9791 )]
9792 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")]
9793 fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
9794 }
9795 unsafe { _vhadd_s8(a, b) }
9796}
9797#[doc = "Halving add"]
9798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
9799#[inline]
9800#[target_feature(enable = "neon")]
9801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
9803#[cfg_attr(
9804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9805 assert_instr(shadd)
9806)]
9807#[cfg_attr(
9808 not(target_arch = "arm"),
9809 stable(feature = "neon_intrinsics", since = "1.59.0")
9810)]
9811#[cfg_attr(
9812 target_arch = "arm",
9813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9814)]
9815pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
9816 unsafe extern "unadjusted" {
9817 #[cfg_attr(
9818 any(target_arch = "aarch64", target_arch = "arm64ec"),
9819 link_name = "llvm.aarch64.neon.shadd.v16i8"
9820 )]
9821 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")]
9822 fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
9823 }
9824 unsafe { _vhaddq_s8(a, b) }
9825}
9826#[doc = "Halving add"]
9827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
9828#[inline]
9829#[target_feature(enable = "neon")]
9830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9831#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
9832#[cfg_attr(
9833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9834 assert_instr(shadd)
9835)]
9836#[cfg_attr(
9837 not(target_arch = "arm"),
9838 stable(feature = "neon_intrinsics", since = "1.59.0")
9839)]
9840#[cfg_attr(
9841 target_arch = "arm",
9842 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9843)]
9844pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
9845 unsafe extern "unadjusted" {
9846 #[cfg_attr(
9847 any(target_arch = "aarch64", target_arch = "arm64ec"),
9848 link_name = "llvm.aarch64.neon.shadd.v4i16"
9849 )]
9850 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")]
9851 fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
9852 }
9853 unsafe { _vhadd_s16(a, b) }
9854}
9855#[doc = "Halving add"]
9856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
9857#[inline]
9858#[target_feature(enable = "neon")]
9859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9860#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
9861#[cfg_attr(
9862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9863 assert_instr(shadd)
9864)]
9865#[cfg_attr(
9866 not(target_arch = "arm"),
9867 stable(feature = "neon_intrinsics", since = "1.59.0")
9868)]
9869#[cfg_attr(
9870 target_arch = "arm",
9871 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9872)]
9873pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
9874 unsafe extern "unadjusted" {
9875 #[cfg_attr(
9876 any(target_arch = "aarch64", target_arch = "arm64ec"),
9877 link_name = "llvm.aarch64.neon.shadd.v8i16"
9878 )]
9879 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")]
9880 fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
9881 }
9882 unsafe { _vhaddq_s16(a, b) }
9883}
9884#[doc = "Halving add"]
9885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
9886#[inline]
9887#[target_feature(enable = "neon")]
9888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9889#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
9890#[cfg_attr(
9891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9892 assert_instr(shadd)
9893)]
9894#[cfg_attr(
9895 not(target_arch = "arm"),
9896 stable(feature = "neon_intrinsics", since = "1.59.0")
9897)]
9898#[cfg_attr(
9899 target_arch = "arm",
9900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9901)]
9902pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
9903 unsafe extern "unadjusted" {
9904 #[cfg_attr(
9905 any(target_arch = "aarch64", target_arch = "arm64ec"),
9906 link_name = "llvm.aarch64.neon.shadd.v2i32"
9907 )]
9908 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")]
9909 fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
9910 }
9911 unsafe { _vhadd_s32(a, b) }
9912}
9913#[doc = "Halving add"]
9914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
9915#[inline]
9916#[target_feature(enable = "neon")]
9917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9918#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
9919#[cfg_attr(
9920 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9921 assert_instr(shadd)
9922)]
9923#[cfg_attr(
9924 not(target_arch = "arm"),
9925 stable(feature = "neon_intrinsics", since = "1.59.0")
9926)]
9927#[cfg_attr(
9928 target_arch = "arm",
9929 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9930)]
9931pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
9932 unsafe extern "unadjusted" {
9933 #[cfg_attr(
9934 any(target_arch = "aarch64", target_arch = "arm64ec"),
9935 link_name = "llvm.aarch64.neon.shadd.v4i32"
9936 )]
9937 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")]
9938 fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
9939 }
9940 unsafe { _vhaddq_s32(a, b) }
9941}
9942#[doc = "Halving add"]
9943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
9944#[inline]
9945#[target_feature(enable = "neon")]
9946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
9948#[cfg_attr(
9949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9950 assert_instr(uhadd)
9951)]
9952#[cfg_attr(
9953 not(target_arch = "arm"),
9954 stable(feature = "neon_intrinsics", since = "1.59.0")
9955)]
9956#[cfg_attr(
9957 target_arch = "arm",
9958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9959)]
9960pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
9961 unsafe extern "unadjusted" {
9962 #[cfg_attr(
9963 any(target_arch = "aarch64", target_arch = "arm64ec"),
9964 link_name = "llvm.aarch64.neon.uhadd.v8i8"
9965 )]
9966 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")]
9967 fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
9968 }
9969 unsafe { _vhadd_u8(a, b) }
9970}
9971#[doc = "Halving add"]
9972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
9973#[inline]
9974#[target_feature(enable = "neon")]
9975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9976#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
9977#[cfg_attr(
9978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9979 assert_instr(uhadd)
9980)]
9981#[cfg_attr(
9982 not(target_arch = "arm"),
9983 stable(feature = "neon_intrinsics", since = "1.59.0")
9984)]
9985#[cfg_attr(
9986 target_arch = "arm",
9987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9988)]
9989pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
9990 unsafe extern "unadjusted" {
9991 #[cfg_attr(
9992 any(target_arch = "aarch64", target_arch = "arm64ec"),
9993 link_name = "llvm.aarch64.neon.uhadd.v16i8"
9994 )]
9995 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")]
9996 fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
9997 }
9998 unsafe { _vhaddq_u8(a, b) }
9999}
10000#[doc = "Halving add"]
10001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
10002#[inline]
10003#[target_feature(enable = "neon")]
10004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10005#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
10006#[cfg_attr(
10007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10008 assert_instr(uhadd)
10009)]
10010#[cfg_attr(
10011 not(target_arch = "arm"),
10012 stable(feature = "neon_intrinsics", since = "1.59.0")
10013)]
10014#[cfg_attr(
10015 target_arch = "arm",
10016 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10017)]
10018pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
10019 unsafe extern "unadjusted" {
10020 #[cfg_attr(
10021 any(target_arch = "aarch64", target_arch = "arm64ec"),
10022 link_name = "llvm.aarch64.neon.uhadd.v4i16"
10023 )]
10024 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")]
10025 fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
10026 }
10027 unsafe { _vhadd_u16(a, b) }
10028}
10029#[doc = "Halving add"]
10030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
10031#[inline]
10032#[target_feature(enable = "neon")]
10033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10034#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
10035#[cfg_attr(
10036 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10037 assert_instr(uhadd)
10038)]
10039#[cfg_attr(
10040 not(target_arch = "arm"),
10041 stable(feature = "neon_intrinsics", since = "1.59.0")
10042)]
10043#[cfg_attr(
10044 target_arch = "arm",
10045 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10046)]
10047pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
10048 unsafe extern "unadjusted" {
10049 #[cfg_attr(
10050 any(target_arch = "aarch64", target_arch = "arm64ec"),
10051 link_name = "llvm.aarch64.neon.uhadd.v8i16"
10052 )]
10053 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")]
10054 fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
10055 }
10056 unsafe { _vhaddq_u16(a, b) }
10057}
10058#[doc = "Halving add"]
10059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
10060#[inline]
10061#[target_feature(enable = "neon")]
10062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10063#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
10064#[cfg_attr(
10065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10066 assert_instr(uhadd)
10067)]
10068#[cfg_attr(
10069 not(target_arch = "arm"),
10070 stable(feature = "neon_intrinsics", since = "1.59.0")
10071)]
10072#[cfg_attr(
10073 target_arch = "arm",
10074 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10075)]
10076pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
10077 unsafe extern "unadjusted" {
10078 #[cfg_attr(
10079 any(target_arch = "aarch64", target_arch = "arm64ec"),
10080 link_name = "llvm.aarch64.neon.uhadd.v2i32"
10081 )]
10082 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")]
10083 fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
10084 }
10085 unsafe { _vhadd_u32(a, b) }
10086}
10087#[doc = "Halving add"]
10088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
10089#[inline]
10090#[target_feature(enable = "neon")]
10091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10092#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
10093#[cfg_attr(
10094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10095 assert_instr(uhadd)
10096)]
10097#[cfg_attr(
10098 not(target_arch = "arm"),
10099 stable(feature = "neon_intrinsics", since = "1.59.0")
10100)]
10101#[cfg_attr(
10102 target_arch = "arm",
10103 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10104)]
10105pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
10106 unsafe extern "unadjusted" {
10107 #[cfg_attr(
10108 any(target_arch = "aarch64", target_arch = "arm64ec"),
10109 link_name = "llvm.aarch64.neon.uhadd.v4i32"
10110 )]
10111 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")]
10112 fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
10113 }
10114 unsafe { _vhaddq_u32(a, b) }
10115}
10116#[doc = "Signed halving subtract"]
10117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
10118#[inline]
10119#[target_feature(enable = "neon")]
10120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10121#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
10122#[cfg_attr(
10123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10124 assert_instr(shsub)
10125)]
10126#[cfg_attr(
10127 not(target_arch = "arm"),
10128 stable(feature = "neon_intrinsics", since = "1.59.0")
10129)]
10130#[cfg_attr(
10131 target_arch = "arm",
10132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10133)]
10134pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
10135 unsafe extern "unadjusted" {
10136 #[cfg_attr(
10137 any(target_arch = "aarch64", target_arch = "arm64ec"),
10138 link_name = "llvm.aarch64.neon.shsub.v4i16"
10139 )]
10140 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")]
10141 fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
10142 }
10143 unsafe { _vhsub_s16(a, b) }
10144}
10145#[doc = "Signed halving subtract"]
10146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
10147#[inline]
10148#[target_feature(enable = "neon")]
10149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10150#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
10151#[cfg_attr(
10152 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10153 assert_instr(shsub)
10154)]
10155#[cfg_attr(
10156 not(target_arch = "arm"),
10157 stable(feature = "neon_intrinsics", since = "1.59.0")
10158)]
10159#[cfg_attr(
10160 target_arch = "arm",
10161 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10162)]
10163pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
10164 unsafe extern "unadjusted" {
10165 #[cfg_attr(
10166 any(target_arch = "aarch64", target_arch = "arm64ec"),
10167 link_name = "llvm.aarch64.neon.shsub.v8i16"
10168 )]
10169 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")]
10170 fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
10171 }
10172 unsafe { _vhsubq_s16(a, b) }
10173}
10174#[doc = "Signed halving subtract"]
10175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
10176#[inline]
10177#[target_feature(enable = "neon")]
10178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10179#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
10180#[cfg_attr(
10181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10182 assert_instr(shsub)
10183)]
10184#[cfg_attr(
10185 not(target_arch = "arm"),
10186 stable(feature = "neon_intrinsics", since = "1.59.0")
10187)]
10188#[cfg_attr(
10189 target_arch = "arm",
10190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10191)]
10192pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
10193 unsafe extern "unadjusted" {
10194 #[cfg_attr(
10195 any(target_arch = "aarch64", target_arch = "arm64ec"),
10196 link_name = "llvm.aarch64.neon.shsub.v2i32"
10197 )]
10198 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")]
10199 fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
10200 }
10201 unsafe { _vhsub_s32(a, b) }
10202}
10203#[doc = "Signed halving subtract"]
10204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
10205#[inline]
10206#[target_feature(enable = "neon")]
10207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10208#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
10209#[cfg_attr(
10210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10211 assert_instr(shsub)
10212)]
10213#[cfg_attr(
10214 not(target_arch = "arm"),
10215 stable(feature = "neon_intrinsics", since = "1.59.0")
10216)]
10217#[cfg_attr(
10218 target_arch = "arm",
10219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10220)]
10221pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
10222 unsafe extern "unadjusted" {
10223 #[cfg_attr(
10224 any(target_arch = "aarch64", target_arch = "arm64ec"),
10225 link_name = "llvm.aarch64.neon.shsub.v4i32"
10226 )]
10227 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")]
10228 fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
10229 }
10230 unsafe { _vhsubq_s32(a, b) }
10231}
10232#[doc = "Signed halving subtract"]
10233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
10234#[inline]
10235#[target_feature(enable = "neon")]
10236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10237#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
10238#[cfg_attr(
10239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10240 assert_instr(shsub)
10241)]
10242#[cfg_attr(
10243 not(target_arch = "arm"),
10244 stable(feature = "neon_intrinsics", since = "1.59.0")
10245)]
10246#[cfg_attr(
10247 target_arch = "arm",
10248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10249)]
10250pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
10251 unsafe extern "unadjusted" {
10252 #[cfg_attr(
10253 any(target_arch = "aarch64", target_arch = "arm64ec"),
10254 link_name = "llvm.aarch64.neon.shsub.v8i8"
10255 )]
10256 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")]
10257 fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
10258 }
10259 unsafe { _vhsub_s8(a, b) }
10260}
10261#[doc = "Signed halving subtract"]
10262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
10263#[inline]
10264#[target_feature(enable = "neon")]
10265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10266#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
10267#[cfg_attr(
10268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10269 assert_instr(shsub)
10270)]
10271#[cfg_attr(
10272 not(target_arch = "arm"),
10273 stable(feature = "neon_intrinsics", since = "1.59.0")
10274)]
10275#[cfg_attr(
10276 target_arch = "arm",
10277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10278)]
10279pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
10280 unsafe extern "unadjusted" {
10281 #[cfg_attr(
10282 any(target_arch = "aarch64", target_arch = "arm64ec"),
10283 link_name = "llvm.aarch64.neon.shsub.v16i8"
10284 )]
10285 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")]
10286 fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
10287 }
10288 unsafe { _vhsubq_s8(a, b) }
10289}
10290#[doc = "Signed halving subtract"]
10291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
10292#[inline]
10293#[target_feature(enable = "neon")]
10294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10295#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
10296#[cfg_attr(
10297 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10298 assert_instr(uhsub)
10299)]
10300#[cfg_attr(
10301 not(target_arch = "arm"),
10302 stable(feature = "neon_intrinsics", since = "1.59.0")
10303)]
10304#[cfg_attr(
10305 target_arch = "arm",
10306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10307)]
10308pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
10309 unsafe extern "unadjusted" {
10310 #[cfg_attr(
10311 any(target_arch = "aarch64", target_arch = "arm64ec"),
10312 link_name = "llvm.aarch64.neon.uhsub.v8i8"
10313 )]
10314 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")]
10315 fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
10316 }
10317 unsafe { _vhsub_u8(a, b) }
10318}
10319#[doc = "Signed halving subtract"]
10320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
10321#[inline]
10322#[target_feature(enable = "neon")]
10323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10324#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
10325#[cfg_attr(
10326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10327 assert_instr(uhsub)
10328)]
10329#[cfg_attr(
10330 not(target_arch = "arm"),
10331 stable(feature = "neon_intrinsics", since = "1.59.0")
10332)]
10333#[cfg_attr(
10334 target_arch = "arm",
10335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10336)]
10337pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
10338 unsafe extern "unadjusted" {
10339 #[cfg_attr(
10340 any(target_arch = "aarch64", target_arch = "arm64ec"),
10341 link_name = "llvm.aarch64.neon.uhsub.v16i8"
10342 )]
10343 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")]
10344 fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
10345 }
10346 unsafe { _vhsubq_u8(a, b) }
10347}
10348#[doc = "Signed halving subtract"]
10349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
10350#[inline]
10351#[target_feature(enable = "neon")]
10352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10353#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
10354#[cfg_attr(
10355 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10356 assert_instr(uhsub)
10357)]
10358#[cfg_attr(
10359 not(target_arch = "arm"),
10360 stable(feature = "neon_intrinsics", since = "1.59.0")
10361)]
10362#[cfg_attr(
10363 target_arch = "arm",
10364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10365)]
10366pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
10367 unsafe extern "unadjusted" {
10368 #[cfg_attr(
10369 any(target_arch = "aarch64", target_arch = "arm64ec"),
10370 link_name = "llvm.aarch64.neon.uhsub.v4i16"
10371 )]
10372 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")]
10373 fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
10374 }
10375 unsafe { _vhsub_u16(a, b) }
10376}
10377#[doc = "Signed halving subtract"]
10378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
10379#[inline]
10380#[target_feature(enable = "neon")]
10381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10382#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
10383#[cfg_attr(
10384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10385 assert_instr(uhsub)
10386)]
10387#[cfg_attr(
10388 not(target_arch = "arm"),
10389 stable(feature = "neon_intrinsics", since = "1.59.0")
10390)]
10391#[cfg_attr(
10392 target_arch = "arm",
10393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10394)]
10395pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
10396 unsafe extern "unadjusted" {
10397 #[cfg_attr(
10398 any(target_arch = "aarch64", target_arch = "arm64ec"),
10399 link_name = "llvm.aarch64.neon.uhsub.v8i16"
10400 )]
10401 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")]
10402 fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
10403 }
10404 unsafe { _vhsubq_u16(a, b) }
10405}
10406#[doc = "Signed halving subtract"]
10407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
10408#[inline]
10409#[target_feature(enable = "neon")]
10410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10411#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
10412#[cfg_attr(
10413 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10414 assert_instr(uhsub)
10415)]
10416#[cfg_attr(
10417 not(target_arch = "arm"),
10418 stable(feature = "neon_intrinsics", since = "1.59.0")
10419)]
10420#[cfg_attr(
10421 target_arch = "arm",
10422 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10423)]
10424pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
10425 unsafe extern "unadjusted" {
10426 #[cfg_attr(
10427 any(target_arch = "aarch64", target_arch = "arm64ec"),
10428 link_name = "llvm.aarch64.neon.uhsub.v2i32"
10429 )]
10430 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")]
10431 fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
10432 }
10433 unsafe { _vhsub_u32(a, b) }
10434}
10435#[doc = "Signed halving subtract"]
10436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
10437#[inline]
10438#[target_feature(enable = "neon")]
10439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10440#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
10441#[cfg_attr(
10442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10443 assert_instr(uhsub)
10444)]
10445#[cfg_attr(
10446 not(target_arch = "arm"),
10447 stable(feature = "neon_intrinsics", since = "1.59.0")
10448)]
10449#[cfg_attr(
10450 target_arch = "arm",
10451 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10452)]
10453pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
10454 unsafe extern "unadjusted" {
10455 #[cfg_attr(
10456 any(target_arch = "aarch64", target_arch = "arm64ec"),
10457 link_name = "llvm.aarch64.neon.uhsub.v4i32"
10458 )]
10459 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")]
10460 fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
10461 }
10462 unsafe { _vhsubq_u32(a, b) }
10463}
10464#[doc = "Load one single-element structure and replicate to all lanes of one register"]
10465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
10466#[doc = "## Safety"]
10467#[doc = " * Neon instrinsic unsafe"]
10468#[inline]
10469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10470#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10471#[cfg_attr(
10472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10473 assert_instr(ld1r)
10474)]
10475#[target_feature(enable = "neon,fp16")]
10476#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10477pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
10478 let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.)));
10479 simd_shuffle!(x, x, [0, 0, 0, 0])
10480}
10481#[doc = "Load one single-element structure and replicate to all lanes of one register"]
10482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
10483#[doc = "## Safety"]
10484#[doc = " * Neon instrinsic unsafe"]
10485#[inline]
10486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10488#[cfg_attr(
10489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10490 assert_instr(ld1r)
10491)]
10492#[target_feature(enable = "neon,fp16")]
10493#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10494pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
10495 let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.)));
10496 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
10497}
10498#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
10500#[doc = "## Safety"]
10501#[doc = " * Neon instrinsic unsafe"]
10502#[inline]
10503#[cfg(target_endian = "little")]
10504#[cfg(target_arch = "arm")]
10505#[target_feature(enable = "neon,v7")]
10506#[target_feature(enable = "neon,fp16")]
10507#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10509pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
10510 transmute(vld1_v4f16(
10511 ptr as *const i8,
10512 crate::mem::align_of::<f16>() as i32,
10513 ))
10514}
10515#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
10517#[doc = "## Safety"]
10518#[doc = " * Neon instrinsic unsafe"]
10519#[inline]
10520#[cfg(target_endian = "big")]
10521#[cfg(target_arch = "arm")]
10522#[target_feature(enable = "neon,v7")]
10523#[target_feature(enable = "neon,fp16")]
10524#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10525#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10526pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
10527 let ret_val: float16x4_t = transmute(vld1_v4f16(
10528 ptr as *const i8,
10529 crate::mem::align_of::<f16>() as i32,
10530 ));
10531 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
10532}
10533#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
10535#[doc = "## Safety"]
10536#[doc = " * Neon instrinsic unsafe"]
10537#[inline]
10538#[cfg(target_endian = "little")]
10539#[cfg(target_arch = "arm")]
10540#[target_feature(enable = "neon,v7")]
10541#[target_feature(enable = "neon,fp16")]
10542#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10544pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
10545 transmute(vld1q_v8f16(
10546 ptr as *const i8,
10547 crate::mem::align_of::<f16>() as i32,
10548 ))
10549}
10550#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
10552#[doc = "## Safety"]
10553#[doc = " * Neon instrinsic unsafe"]
10554#[inline]
10555#[cfg(target_endian = "big")]
10556#[cfg(target_arch = "arm")]
10557#[target_feature(enable = "neon,v7")]
10558#[target_feature(enable = "neon,fp16")]
10559#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10560#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10561pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
10562 let ret_val: float16x8_t = transmute(vld1q_v8f16(
10563 ptr as *const i8,
10564 crate::mem::align_of::<f16>() as i32,
10565 ));
10566 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
10567}
10568#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
10570#[doc = "## Safety"]
10571#[doc = " * Neon instrinsic unsafe"]
10572#[inline]
10573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10575#[cfg_attr(
10576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10577 assert_instr(ld1)
10578)]
10579#[target_feature(enable = "neon,fp16")]
10580#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10581pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
10582 unsafe extern "unadjusted" {
10583 #[cfg_attr(
10584 any(target_arch = "aarch64", target_arch = "arm64ec"),
10585 link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0f16"
10586 )]
10587 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0f16")]
10588 fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t;
10589 }
10590 _vld1_f16_x2(a)
10591}
10592#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
10594#[doc = "## Safety"]
10595#[doc = " * Neon instrinsic unsafe"]
10596#[inline]
10597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10599#[cfg_attr(
10600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10601 assert_instr(ld1)
10602)]
10603#[target_feature(enable = "neon,fp16")]
10604#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10605pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
10606 unsafe extern "unadjusted" {
10607 #[cfg_attr(
10608 any(target_arch = "aarch64", target_arch = "arm64ec"),
10609 link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0f16"
10610 )]
10611 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0f16")]
10612 fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t;
10613 }
10614 _vld1_f16_x3(a)
10615}
10616#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
10618#[doc = "## Safety"]
10619#[doc = " * Neon instrinsic unsafe"]
10620#[inline]
10621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10623#[cfg_attr(
10624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10625 assert_instr(ld1)
10626)]
10627#[target_feature(enable = "neon,fp16")]
10628#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10629pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
10630 unsafe extern "unadjusted" {
10631 #[cfg_attr(
10632 any(target_arch = "aarch64", target_arch = "arm64ec"),
10633 link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0f16"
10634 )]
10635 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0f16")]
10636 fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t;
10637 }
10638 _vld1_f16_x4(a)
10639}
10640#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
10642#[doc = "## Safety"]
10643#[doc = " * Neon instrinsic unsafe"]
10644#[inline]
10645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10647#[cfg_attr(
10648 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10649 assert_instr(ld1)
10650)]
10651#[target_feature(enable = "neon,fp16")]
10652#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10653pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
10654 unsafe extern "unadjusted" {
10655 #[cfg_attr(
10656 any(target_arch = "aarch64", target_arch = "arm64ec"),
10657 link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0f16"
10658 )]
10659 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0f16")]
10660 fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t;
10661 }
10662 _vld1q_f16_x2(a)
10663}
10664#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
10666#[doc = "## Safety"]
10667#[doc = " * Neon instrinsic unsafe"]
10668#[inline]
10669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10671#[cfg_attr(
10672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10673 assert_instr(ld1)
10674)]
10675#[target_feature(enable = "neon,fp16")]
10676#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10677pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
10678 unsafe extern "unadjusted" {
10679 #[cfg_attr(
10680 any(target_arch = "aarch64", target_arch = "arm64ec"),
10681 link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0f16"
10682 )]
10683 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0f16")]
10684 fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t;
10685 }
10686 _vld1q_f16_x3(a)
10687}
10688#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
10690#[doc = "## Safety"]
10691#[doc = " * Neon instrinsic unsafe"]
10692#[inline]
10693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
10695#[cfg_attr(
10696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10697 assert_instr(ld1)
10698)]
10699#[target_feature(enable = "neon,fp16")]
10700#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10701pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
10702 unsafe extern "unadjusted" {
10703 #[cfg_attr(
10704 any(target_arch = "aarch64", target_arch = "arm64ec"),
10705 link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0f16"
10706 )]
10707 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0f16")]
10708 fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t;
10709 }
10710 _vld1q_f16_x4(a)
10711}
10712#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
10714#[doc = "## Safety"]
10715#[doc = " * Neon instrinsic unsafe"]
10716#[inline]
10717#[cfg(target_endian = "little")]
10718#[cfg(target_arch = "arm")]
10719#[target_feature(enable = "neon,v7")]
10720#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10721#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
10722pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
10723 transmute(vld1_v2f32(
10724 ptr as *const i8,
10725 crate::mem::align_of::<f32>() as i32,
10726 ))
10727}
10728#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
10730#[doc = "## Safety"]
10731#[doc = " * Neon instrinsic unsafe"]
10732#[inline]
10733#[cfg(target_endian = "big")]
10734#[cfg(target_arch = "arm")]
10735#[target_feature(enable = "neon,v7")]
10736#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
10738pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
10739 let ret_val: float32x2_t = transmute(vld1_v2f32(
10740 ptr as *const i8,
10741 crate::mem::align_of::<f32>() as i32,
10742 ));
10743 simd_shuffle!(ret_val, ret_val, [1, 0])
10744}
10745#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
10747#[doc = "## Safety"]
10748#[doc = " * Neon instrinsic unsafe"]
10749#[inline]
10750#[cfg(target_endian = "little")]
10751#[cfg(target_arch = "arm")]
10752#[target_feature(enable = "neon,v7")]
10753#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10754#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
10755pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
10756 transmute(vld1q_v4f32(
10757 ptr as *const i8,
10758 crate::mem::align_of::<f32>() as i32,
10759 ))
10760}
10761#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
10763#[doc = "## Safety"]
10764#[doc = " * Neon instrinsic unsafe"]
10765#[inline]
10766#[cfg(target_endian = "big")]
10767#[cfg(target_arch = "arm")]
10768#[target_feature(enable = "neon,v7")]
10769#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10770#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
10771pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
10772 let ret_val: float32x4_t = transmute(vld1q_v4f32(
10773 ptr as *const i8,
10774 crate::mem::align_of::<f32>() as i32,
10775 ));
10776 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
10777}
10778#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
10780#[doc = "## Safety"]
10781#[doc = " * Neon instrinsic unsafe"]
10782#[inline]
10783#[cfg(target_endian = "little")]
10784#[cfg(target_arch = "arm")]
10785#[target_feature(enable = "neon,v7")]
10786#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
10788pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
10789 transmute(vld1_v8i8(
10790 ptr as *const i8,
10791 crate::mem::align_of::<u8>() as i32,
10792 ))
10793}
10794#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
10796#[doc = "## Safety"]
10797#[doc = " * Neon instrinsic unsafe"]
10798#[inline]
10799#[cfg(target_endian = "big")]
10800#[cfg(target_arch = "arm")]
10801#[target_feature(enable = "neon,v7")]
10802#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10803#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
10804pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
10805 let ret_val: uint8x8_t = transmute(vld1_v8i8(
10806 ptr as *const i8,
10807 crate::mem::align_of::<u8>() as i32,
10808 ));
10809 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
10810}
10811#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
10813#[doc = "## Safety"]
10814#[doc = " * Neon instrinsic unsafe"]
10815#[inline]
10816#[cfg(target_endian = "little")]
10817#[cfg(target_arch = "arm")]
10818#[target_feature(enable = "neon,v7")]
10819#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10820#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
10821pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
10822 transmute(vld1q_v16i8(
10823 ptr as *const i8,
10824 crate::mem::align_of::<u8>() as i32,
10825 ))
10826}
10827#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
10829#[doc = "## Safety"]
10830#[doc = " * Neon instrinsic unsafe"]
10831#[inline]
10832#[cfg(target_endian = "big")]
10833#[cfg(target_arch = "arm")]
10834#[target_feature(enable = "neon,v7")]
10835#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10836#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
10837pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
10838 let ret_val: uint8x16_t = transmute(vld1q_v16i8(
10839 ptr as *const i8,
10840 crate::mem::align_of::<u8>() as i32,
10841 ));
10842 simd_shuffle!(
10843 ret_val,
10844 ret_val,
10845 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
10846 )
10847}
10848#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
10850#[doc = "## Safety"]
10851#[doc = " * Neon instrinsic unsafe"]
10852#[inline]
10853#[cfg(target_endian = "little")]
10854#[cfg(target_arch = "arm")]
10855#[target_feature(enable = "neon,v7")]
10856#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10857#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10858pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
10859 transmute(vld1_v4i16(
10860 ptr as *const i8,
10861 crate::mem::align_of::<u16>() as i32,
10862 ))
10863}
10864#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
10866#[doc = "## Safety"]
10867#[doc = " * Neon instrinsic unsafe"]
10868#[inline]
10869#[cfg(target_endian = "big")]
10870#[cfg(target_arch = "arm")]
10871#[target_feature(enable = "neon,v7")]
10872#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10873#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10874pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
10875 let ret_val: uint16x4_t = transmute(vld1_v4i16(
10876 ptr as *const i8,
10877 crate::mem::align_of::<u16>() as i32,
10878 ));
10879 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
10880}
10881#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
10883#[doc = "## Safety"]
10884#[doc = " * Neon instrinsic unsafe"]
10885#[inline]
10886#[cfg(target_endian = "little")]
10887#[cfg(target_arch = "arm")]
10888#[target_feature(enable = "neon,v7")]
10889#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10890#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10891pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
10892 transmute(vld1q_v8i16(
10893 ptr as *const i8,
10894 crate::mem::align_of::<u16>() as i32,
10895 ))
10896}
10897#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
10899#[doc = "## Safety"]
10900#[doc = " * Neon instrinsic unsafe"]
10901#[inline]
10902#[cfg(target_endian = "big")]
10903#[cfg(target_arch = "arm")]
10904#[target_feature(enable = "neon,v7")]
10905#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
10907pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
10908 let ret_val: uint16x8_t = transmute(vld1q_v8i16(
10909 ptr as *const i8,
10910 crate::mem::align_of::<u16>() as i32,
10911 ));
10912 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
10913}
10914#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
10916#[doc = "## Safety"]
10917#[doc = " * Neon instrinsic unsafe"]
10918#[inline]
10919#[cfg(target_endian = "little")]
10920#[cfg(target_arch = "arm")]
10921#[target_feature(enable = "neon,v7")]
10922#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
10924pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
10925 transmute(vld1_v2i32(
10926 ptr as *const i8,
10927 crate::mem::align_of::<u32>() as i32,
10928 ))
10929}
10930#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
10932#[doc = "## Safety"]
10933#[doc = " * Neon instrinsic unsafe"]
10934#[inline]
10935#[cfg(target_endian = "big")]
10936#[cfg(target_arch = "arm")]
10937#[target_feature(enable = "neon,v7")]
10938#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
10940pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
10941 let ret_val: uint32x2_t = transmute(vld1_v2i32(
10942 ptr as *const i8,
10943 crate::mem::align_of::<u32>() as i32,
10944 ));
10945 simd_shuffle!(ret_val, ret_val, [1, 0])
10946}
10947#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
10949#[doc = "## Safety"]
10950#[doc = " * Neon instrinsic unsafe"]
10951#[inline]
10952#[cfg(target_endian = "little")]
10953#[cfg(target_arch = "arm")]
10954#[target_feature(enable = "neon,v7")]
10955#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10956#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
10957pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
10958 transmute(vld1q_v4i32(
10959 ptr as *const i8,
10960 crate::mem::align_of::<u32>() as i32,
10961 ))
10962}
10963#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
10965#[doc = "## Safety"]
10966#[doc = " * Neon instrinsic unsafe"]
10967#[inline]
10968#[cfg(target_endian = "big")]
10969#[cfg(target_arch = "arm")]
10970#[target_feature(enable = "neon,v7")]
10971#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10972#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
10973pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
10974 let ret_val: uint32x4_t = transmute(vld1q_v4i32(
10975 ptr as *const i8,
10976 crate::mem::align_of::<u32>() as i32,
10977 ));
10978 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
10979}
10980#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
10982#[doc = "## Safety"]
10983#[doc = " * Neon instrinsic unsafe"]
10984#[inline]
10985#[cfg(target_arch = "arm")]
10986#[target_feature(enable = "neon,v7")]
10987#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
10988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
10989pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
10990 transmute(vld1_v1i64(
10991 ptr as *const i8,
10992 crate::mem::align_of::<u64>() as i32,
10993 ))
10994}
10995#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
10996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
10997#[doc = "## Safety"]
10998#[doc = " * Neon instrinsic unsafe"]
10999#[inline]
11000#[cfg(target_endian = "little")]
11001#[cfg(target_arch = "arm")]
11002#[target_feature(enable = "neon,v7")]
11003#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11004#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
11005pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
11006 transmute(vld1q_v2i64(
11007 ptr as *const i8,
11008 crate::mem::align_of::<u64>() as i32,
11009 ))
11010}
11011#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
11013#[doc = "## Safety"]
11014#[doc = " * Neon instrinsic unsafe"]
11015#[inline]
11016#[cfg(target_endian = "big")]
11017#[cfg(target_arch = "arm")]
11018#[target_feature(enable = "neon,v7")]
11019#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11020#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
11021pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
11022 let ret_val: uint64x2_t = transmute(vld1q_v2i64(
11023 ptr as *const i8,
11024 crate::mem::align_of::<u64>() as i32,
11025 ));
11026 simd_shuffle!(ret_val, ret_val, [1, 0])
11027}
11028#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
11030#[doc = "## Safety"]
11031#[doc = " * Neon instrinsic unsafe"]
11032#[inline]
11033#[cfg(target_endian = "little")]
11034#[cfg(target_arch = "arm")]
11035#[target_feature(enable = "neon,v7")]
11036#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11037#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
11038pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
11039 transmute(vld1_v8i8(
11040 ptr as *const i8,
11041 crate::mem::align_of::<p8>() as i32,
11042 ))
11043}
11044#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
11046#[doc = "## Safety"]
11047#[doc = " * Neon instrinsic unsafe"]
11048#[inline]
11049#[cfg(target_endian = "big")]
11050#[cfg(target_arch = "arm")]
11051#[target_feature(enable = "neon,v7")]
11052#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11053#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
11054pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
11055 let ret_val: poly8x8_t = transmute(vld1_v8i8(
11056 ptr as *const i8,
11057 crate::mem::align_of::<p8>() as i32,
11058 ));
11059 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
11060}
11061#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
11063#[doc = "## Safety"]
11064#[doc = " * Neon instrinsic unsafe"]
11065#[inline]
11066#[cfg(target_endian = "little")]
11067#[cfg(target_arch = "arm")]
11068#[target_feature(enable = "neon,v7")]
11069#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11070#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
11071pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
11072 transmute(vld1q_v16i8(
11073 ptr as *const i8,
11074 crate::mem::align_of::<p8>() as i32,
11075 ))
11076}
11077#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
11079#[doc = "## Safety"]
11080#[doc = " * Neon instrinsic unsafe"]
11081#[inline]
11082#[cfg(target_endian = "big")]
11083#[cfg(target_arch = "arm")]
11084#[target_feature(enable = "neon,v7")]
11085#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11086#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
11087pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
11088 let ret_val: poly8x16_t = transmute(vld1q_v16i8(
11089 ptr as *const i8,
11090 crate::mem::align_of::<p8>() as i32,
11091 ));
11092 simd_shuffle!(
11093 ret_val,
11094 ret_val,
11095 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
11096 )
11097}
11098#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
11100#[doc = "## Safety"]
11101#[doc = " * Neon instrinsic unsafe"]
11102#[inline]
11103#[cfg(target_endian = "little")]
11104#[cfg(target_arch = "arm")]
11105#[target_feature(enable = "neon,v7")]
11106#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11107#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
11108pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
11109 transmute(vld1_v4i16(
11110 ptr as *const i8,
11111 crate::mem::align_of::<p16>() as i32,
11112 ))
11113}
11114#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
11116#[doc = "## Safety"]
11117#[doc = " * Neon instrinsic unsafe"]
11118#[inline]
11119#[cfg(target_endian = "big")]
11120#[cfg(target_arch = "arm")]
11121#[target_feature(enable = "neon,v7")]
11122#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11123#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
11124pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
11125 let ret_val: poly16x4_t = transmute(vld1_v4i16(
11126 ptr as *const i8,
11127 crate::mem::align_of::<p16>() as i32,
11128 ));
11129 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
11130}
11131#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
11133#[doc = "## Safety"]
11134#[doc = " * Neon instrinsic unsafe"]
11135#[inline]
11136#[cfg(target_endian = "little")]
11137#[cfg(target_arch = "arm")]
11138#[target_feature(enable = "neon,v7")]
11139#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11140#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
11141pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
11142 transmute(vld1q_v8i16(
11143 ptr as *const i8,
11144 crate::mem::align_of::<p16>() as i32,
11145 ))
11146}
11147#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
11149#[doc = "## Safety"]
11150#[doc = " * Neon instrinsic unsafe"]
11151#[inline]
11152#[cfg(target_endian = "big")]
11153#[cfg(target_arch = "arm")]
11154#[target_feature(enable = "neon,v7")]
11155#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
11157pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
11158 let ret_val: poly16x8_t = transmute(vld1q_v8i16(
11159 ptr as *const i8,
11160 crate::mem::align_of::<p16>() as i32,
11161 ));
11162 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
11163}
11164#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
11166#[doc = "## Safety"]
11167#[doc = " * Neon instrinsic unsafe"]
11168#[inline]
11169#[cfg(target_endian = "little")]
11170#[cfg(target_arch = "arm")]
11171#[target_feature(enable = "neon,aes")]
11172#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11173#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
11174pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
11175 transmute(vld1q_v2i64(
11176 ptr as *const i8,
11177 crate::mem::align_of::<p64>() as i32,
11178 ))
11179}
11180#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
11182#[doc = "## Safety"]
11183#[doc = " * Neon instrinsic unsafe"]
11184#[inline]
11185#[cfg(target_endian = "big")]
11186#[cfg(target_arch = "arm")]
11187#[target_feature(enable = "neon,aes")]
11188#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11189#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
11190pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
11191 let ret_val: poly64x2_t = transmute(vld1q_v2i64(
11192 ptr as *const i8,
11193 crate::mem::align_of::<p64>() as i32,
11194 ));
11195 simd_shuffle!(ret_val, ret_val, [1, 0])
11196}
11197#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
11199#[doc = "## Safety"]
11200#[doc = " * Neon instrinsic unsafe"]
11201#[inline]
11202#[target_feature(enable = "neon")]
11203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11205#[cfg_attr(
11206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11207 assert_instr(ld1)
11208)]
11209#[cfg_attr(
11210 not(target_arch = "arm"),
11211 stable(feature = "neon_intrinsics", since = "1.59.0")
11212)]
11213#[cfg_attr(
11214 target_arch = "arm",
11215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11216)]
11217pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
11218 unsafe extern "unadjusted" {
11219 #[cfg_attr(
11220 any(target_arch = "aarch64", target_arch = "arm64ec"),
11221 link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0"
11222 )]
11223 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")]
11224 fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t;
11225 }
11226 _vld1_f32_x2(a)
11227}
11228#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
11230#[doc = "## Safety"]
11231#[doc = " * Neon instrinsic unsafe"]
11232#[inline]
11233#[target_feature(enable = "neon")]
11234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11236#[cfg_attr(
11237 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11238 assert_instr(ld1)
11239)]
11240#[cfg_attr(
11241 not(target_arch = "arm"),
11242 stable(feature = "neon_intrinsics", since = "1.59.0")
11243)]
11244#[cfg_attr(
11245 target_arch = "arm",
11246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11247)]
11248pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
11249 unsafe extern "unadjusted" {
11250 #[cfg_attr(
11251 any(target_arch = "aarch64", target_arch = "arm64ec"),
11252 link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0"
11253 )]
11254 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")]
11255 fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t;
11256 }
11257 _vld1_f32_x3(a)
11258}
11259#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
11261#[doc = "## Safety"]
11262#[doc = " * Neon instrinsic unsafe"]
11263#[inline]
11264#[target_feature(enable = "neon")]
11265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11267#[cfg_attr(
11268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11269 assert_instr(ld1)
11270)]
11271#[cfg_attr(
11272 not(target_arch = "arm"),
11273 stable(feature = "neon_intrinsics", since = "1.59.0")
11274)]
11275#[cfg_attr(
11276 target_arch = "arm",
11277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11278)]
11279pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
11280 unsafe extern "unadjusted" {
11281 #[cfg_attr(
11282 any(target_arch = "aarch64", target_arch = "arm64ec"),
11283 link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0"
11284 )]
11285 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")]
11286 fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t;
11287 }
11288 _vld1_f32_x4(a)
11289}
11290#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
11292#[doc = "## Safety"]
11293#[doc = " * Neon instrinsic unsafe"]
11294#[inline]
11295#[target_feature(enable = "neon")]
11296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11298#[cfg_attr(
11299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11300 assert_instr(ld1)
11301)]
11302#[cfg_attr(
11303 not(target_arch = "arm"),
11304 stable(feature = "neon_intrinsics", since = "1.59.0")
11305)]
11306#[cfg_attr(
11307 target_arch = "arm",
11308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11309)]
11310pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
11311 unsafe extern "unadjusted" {
11312 #[cfg_attr(
11313 any(target_arch = "aarch64", target_arch = "arm64ec"),
11314 link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0"
11315 )]
11316 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")]
11317 fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t;
11318 }
11319 _vld1q_f32_x2(a)
11320}
11321#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
11323#[doc = "## Safety"]
11324#[doc = " * Neon instrinsic unsafe"]
11325#[inline]
11326#[target_feature(enable = "neon")]
11327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11329#[cfg_attr(
11330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11331 assert_instr(ld1)
11332)]
11333#[cfg_attr(
11334 not(target_arch = "arm"),
11335 stable(feature = "neon_intrinsics", since = "1.59.0")
11336)]
11337#[cfg_attr(
11338 target_arch = "arm",
11339 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11340)]
11341pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
11342 unsafe extern "unadjusted" {
11343 #[cfg_attr(
11344 any(target_arch = "aarch64", target_arch = "arm64ec"),
11345 link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0"
11346 )]
11347 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")]
11348 fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t;
11349 }
11350 _vld1q_f32_x3(a)
11351}
11352#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
11354#[doc = "## Safety"]
11355#[doc = " * Neon instrinsic unsafe"]
11356#[inline]
11357#[target_feature(enable = "neon")]
11358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11360#[cfg_attr(
11361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11362 assert_instr(ld1)
11363)]
11364#[cfg_attr(
11365 not(target_arch = "arm"),
11366 stable(feature = "neon_intrinsics", since = "1.59.0")
11367)]
11368#[cfg_attr(
11369 target_arch = "arm",
11370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11371)]
11372pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
11373 unsafe extern "unadjusted" {
11374 #[cfg_attr(
11375 any(target_arch = "aarch64", target_arch = "arm64ec"),
11376 link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0"
11377 )]
11378 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")]
11379 fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t;
11380 }
11381 _vld1q_f32_x4(a)
11382}
11383#[doc = "Load one single-element structure to one lane of one register"]
11384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
11385#[doc = "## Safety"]
11386#[doc = " * Neon instrinsic unsafe"]
11387#[inline]
11388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
11390#[cfg_attr(
11391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11392 assert_instr(ld1, LANE = 0)
11393)]
11394#[rustc_legacy_const_generics(2)]
11395#[target_feature(enable = "neon,fp16")]
11396#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11397pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t) -> float16x4_t {
11398 static_assert_uimm_bits!(LANE, 2);
11399 simd_insert!(src, LANE as u32, *ptr)
11400}
11401#[doc = "Load one single-element structure to one lane of one register"]
11402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
11403#[doc = "## Safety"]
11404#[doc = " * Neon instrinsic unsafe"]
11405#[inline]
11406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
11408#[cfg_attr(
11409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11410 assert_instr(ld1, LANE = 0)
11411)]
11412#[rustc_legacy_const_generics(2)]
11413#[target_feature(enable = "neon,fp16")]
11414#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11415pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t) -> float16x8_t {
11416 static_assert_uimm_bits!(LANE, 3);
11417 simd_insert!(src, LANE as u32, *ptr)
11418}
11419#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
11421#[doc = "## Safety"]
11422#[doc = " * Neon instrinsic unsafe"]
11423#[inline]
11424#[cfg(target_arch = "arm")]
11425#[target_feature(enable = "neon,aes")]
11426#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11427#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
11428pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
11429 let a: *const i8 = ptr as *const i8;
11430 let b: i32 = crate::mem::align_of::<p64>() as i32;
11431 unsafe extern "unadjusted" {
11432 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
11433 fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
11434 }
11435 transmute(_vld1_v1i64(a, b))
11436}
11437#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
11439#[doc = "## Safety"]
11440#[doc = " * Neon instrinsic unsafe"]
11441#[inline]
11442#[target_feature(enable = "neon,aes")]
11443#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11445#[cfg_attr(
11446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11447 assert_instr(ld1)
11448)]
11449#[cfg_attr(
11450 not(target_arch = "arm"),
11451 stable(feature = "neon_intrinsics", since = "1.59.0")
11452)]
11453#[cfg_attr(
11454 target_arch = "arm",
11455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11456)]
11457pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
11458 transmute(vld1_s64_x2(transmute(a)))
11459}
11460#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
11462#[doc = "## Safety"]
11463#[doc = " * Neon instrinsic unsafe"]
11464#[inline]
11465#[target_feature(enable = "neon,aes")]
11466#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11468#[cfg_attr(
11469 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11470 assert_instr(ld1)
11471)]
11472#[cfg_attr(
11473 not(target_arch = "arm"),
11474 stable(feature = "neon_intrinsics", since = "1.59.0")
11475)]
11476#[cfg_attr(
11477 target_arch = "arm",
11478 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11479)]
11480pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
11481 transmute(vld1_s64_x3(transmute(a)))
11482}
11483#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
11485#[doc = "## Safety"]
11486#[doc = " * Neon instrinsic unsafe"]
11487#[inline]
11488#[target_feature(enable = "neon,aes")]
11489#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11491#[cfg_attr(
11492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11493 assert_instr(ld1)
11494)]
11495#[cfg_attr(
11496 not(target_arch = "arm"),
11497 stable(feature = "neon_intrinsics", since = "1.59.0")
11498)]
11499#[cfg_attr(
11500 target_arch = "arm",
11501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11502)]
11503pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
11504 transmute(vld1_s64_x4(transmute(a)))
11505}
11506#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
11508#[doc = "## Safety"]
11509#[doc = " * Neon instrinsic unsafe"]
11510#[inline]
11511#[cfg(target_endian = "little")]
11512#[target_feature(enable = "neon,aes")]
11513#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11515#[cfg_attr(
11516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11517 assert_instr(ld1)
11518)]
11519#[cfg_attr(
11520 not(target_arch = "arm"),
11521 stable(feature = "neon_intrinsics", since = "1.59.0")
11522)]
11523#[cfg_attr(
11524 target_arch = "arm",
11525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11526)]
11527pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
11528 transmute(vld1q_s64_x2(transmute(a)))
11529}
11530#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
11532#[doc = "## Safety"]
11533#[doc = " * Neon instrinsic unsafe"]
11534#[inline]
11535#[cfg(target_endian = "big")]
11536#[target_feature(enable = "neon,aes")]
11537#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11539#[cfg_attr(
11540 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11541 assert_instr(ld1)
11542)]
11543#[cfg_attr(
11544 not(target_arch = "arm"),
11545 stable(feature = "neon_intrinsics", since = "1.59.0")
11546)]
11547#[cfg_attr(
11548 target_arch = "arm",
11549 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11550)]
11551pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
11552 let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
11553 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
11554 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
11555 ret_val
11556}
11557#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
11559#[doc = "## Safety"]
11560#[doc = " * Neon instrinsic unsafe"]
11561#[inline]
11562#[cfg(target_endian = "little")]
11563#[target_feature(enable = "neon,aes")]
11564#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11566#[cfg_attr(
11567 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11568 assert_instr(ld1)
11569)]
11570#[cfg_attr(
11571 not(target_arch = "arm"),
11572 stable(feature = "neon_intrinsics", since = "1.59.0")
11573)]
11574#[cfg_attr(
11575 target_arch = "arm",
11576 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11577)]
11578pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
11579 transmute(vld1q_s64_x3(transmute(a)))
11580}
11581#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
11583#[doc = "## Safety"]
11584#[doc = " * Neon instrinsic unsafe"]
11585#[inline]
11586#[cfg(target_endian = "big")]
11587#[target_feature(enable = "neon,aes")]
11588#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11590#[cfg_attr(
11591 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11592 assert_instr(ld1)
11593)]
11594#[cfg_attr(
11595 not(target_arch = "arm"),
11596 stable(feature = "neon_intrinsics", since = "1.59.0")
11597)]
11598#[cfg_attr(
11599 target_arch = "arm",
11600 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11601)]
11602pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
11603 let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
11604 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
11605 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
11606 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
11607 ret_val
11608}
11609#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
11611#[doc = "## Safety"]
11612#[doc = " * Neon instrinsic unsafe"]
11613#[inline]
11614#[cfg(target_endian = "little")]
11615#[target_feature(enable = "neon,aes")]
11616#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11618#[cfg_attr(
11619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11620 assert_instr(ld1)
11621)]
11622#[cfg_attr(
11623 not(target_arch = "arm"),
11624 stable(feature = "neon_intrinsics", since = "1.59.0")
11625)]
11626#[cfg_attr(
11627 target_arch = "arm",
11628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11629)]
11630pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
11631 transmute(vld1q_s64_x4(transmute(a)))
11632}
11633#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
11635#[doc = "## Safety"]
11636#[doc = " * Neon instrinsic unsafe"]
11637#[inline]
11638#[cfg(target_endian = "big")]
11639#[target_feature(enable = "neon,aes")]
11640#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
11641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
11642#[cfg_attr(
11643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11644 assert_instr(ld1)
11645)]
11646#[cfg_attr(
11647 not(target_arch = "arm"),
11648 stable(feature = "neon_intrinsics", since = "1.59.0")
11649)]
11650#[cfg_attr(
11651 target_arch = "arm",
11652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11653)]
11654pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
11655 let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
11656 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
11657 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
11658 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
11659 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
11660 ret_val
11661}
11662#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
11664#[doc = "## Safety"]
11665#[doc = " * Neon instrinsic unsafe"]
11666#[inline]
11667#[cfg(target_arch = "arm")]
11668#[target_feature(enable = "neon,v7")]
11669#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11670#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
11671pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
11672 vld1_v8i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
11673}
11674#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
11676#[doc = "## Safety"]
11677#[doc = " * Neon instrinsic unsafe"]
11678#[inline]
11679#[cfg(target_arch = "arm")]
11680#[target_feature(enable = "neon,v7")]
11681#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
11683pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
11684 vld1q_v16i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
11685}
11686#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
11688#[doc = "## Safety"]
11689#[doc = " * Neon instrinsic unsafe"]
11690#[inline]
11691#[cfg(target_arch = "arm")]
11692#[target_feature(enable = "neon,v7")]
11693#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11694#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
11695pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
11696 vld1_v4i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
11697}
11698#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
11700#[doc = "## Safety"]
11701#[doc = " * Neon instrinsic unsafe"]
11702#[inline]
11703#[cfg(target_arch = "arm")]
11704#[target_feature(enable = "neon,v7")]
11705#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
11707pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
11708 vld1q_v8i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
11709}
11710#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
11712#[doc = "## Safety"]
11713#[doc = " * Neon instrinsic unsafe"]
11714#[inline]
11715#[cfg(target_arch = "arm")]
11716#[target_feature(enable = "neon,v7")]
11717#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
11719pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
11720 vld1_v2i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
11721}
11722#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
11724#[doc = "## Safety"]
11725#[doc = " * Neon instrinsic unsafe"]
11726#[inline]
11727#[cfg(target_arch = "arm")]
11728#[target_feature(enable = "neon,v7")]
11729#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11730#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
11731pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
11732 vld1q_v4i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
11733}
11734#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
11736#[doc = "## Safety"]
11737#[doc = " * Neon instrinsic unsafe"]
11738#[inline]
11739#[cfg(target_arch = "arm")]
11740#[target_feature(enable = "neon,v7")]
11741#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
11743pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
11744 vld1_v1i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
11745}
11746#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
11747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
11748#[doc = "## Safety"]
11749#[doc = " * Neon instrinsic unsafe"]
11750#[inline]
11751#[cfg(target_arch = "arm")]
11752#[target_feature(enable = "neon,v7")]
11753#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
11754#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
11755pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
11756 vld1q_v2i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
11757}
11758#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
11760#[doc = "## Safety"]
11761#[doc = " * Neon instrinsic unsafe"]
11762#[inline]
11763#[target_feature(enable = "neon")]
11764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11766#[cfg_attr(
11767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11768 assert_instr(ld1)
11769)]
11770#[cfg_attr(
11771 not(target_arch = "arm"),
11772 stable(feature = "neon_intrinsics", since = "1.59.0")
11773)]
11774#[cfg_attr(
11775 target_arch = "arm",
11776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11777)]
11778pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
11779 unsafe extern "unadjusted" {
11780 #[cfg_attr(
11781 any(target_arch = "aarch64", target_arch = "arm64ec"),
11782 link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0"
11783 )]
11784 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")]
11785 fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t;
11786 }
11787 _vld1_s8_x2(a)
11788}
11789#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
11791#[doc = "## Safety"]
11792#[doc = " * Neon instrinsic unsafe"]
11793#[inline]
11794#[target_feature(enable = "neon")]
11795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11797#[cfg_attr(
11798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11799 assert_instr(ld1)
11800)]
11801#[cfg_attr(
11802 not(target_arch = "arm"),
11803 stable(feature = "neon_intrinsics", since = "1.59.0")
11804)]
11805#[cfg_attr(
11806 target_arch = "arm",
11807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11808)]
11809pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
11810 unsafe extern "unadjusted" {
11811 #[cfg_attr(
11812 any(target_arch = "aarch64", target_arch = "arm64ec"),
11813 link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0"
11814 )]
11815 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")]
11816 fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t;
11817 }
11818 _vld1_s8_x3(a)
11819}
11820#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
11822#[doc = "## Safety"]
11823#[doc = " * Neon instrinsic unsafe"]
11824#[inline]
11825#[target_feature(enable = "neon")]
11826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11827#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11828#[cfg_attr(
11829 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11830 assert_instr(ld1)
11831)]
11832#[cfg_attr(
11833 not(target_arch = "arm"),
11834 stable(feature = "neon_intrinsics", since = "1.59.0")
11835)]
11836#[cfg_attr(
11837 target_arch = "arm",
11838 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11839)]
11840pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
11841 unsafe extern "unadjusted" {
11842 #[cfg_attr(
11843 any(target_arch = "aarch64", target_arch = "arm64ec"),
11844 link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0"
11845 )]
11846 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")]
11847 fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t;
11848 }
11849 _vld1_s8_x4(a)
11850}
11851#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
11853#[doc = "## Safety"]
11854#[doc = " * Neon instrinsic unsafe"]
11855#[inline]
11856#[target_feature(enable = "neon")]
11857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11859#[cfg_attr(
11860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11861 assert_instr(ld1)
11862)]
11863#[cfg_attr(
11864 not(target_arch = "arm"),
11865 stable(feature = "neon_intrinsics", since = "1.59.0")
11866)]
11867#[cfg_attr(
11868 target_arch = "arm",
11869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11870)]
11871pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
11872 unsafe extern "unadjusted" {
11873 #[cfg_attr(
11874 any(target_arch = "aarch64", target_arch = "arm64ec"),
11875 link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0"
11876 )]
11877 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")]
11878 fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t;
11879 }
11880 _vld1q_s8_x2(a)
11881}
11882#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
11884#[doc = "## Safety"]
11885#[doc = " * Neon instrinsic unsafe"]
11886#[inline]
11887#[target_feature(enable = "neon")]
11888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11890#[cfg_attr(
11891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11892 assert_instr(ld1)
11893)]
11894#[cfg_attr(
11895 not(target_arch = "arm"),
11896 stable(feature = "neon_intrinsics", since = "1.59.0")
11897)]
11898#[cfg_attr(
11899 target_arch = "arm",
11900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11901)]
11902pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
11903 unsafe extern "unadjusted" {
11904 #[cfg_attr(
11905 any(target_arch = "aarch64", target_arch = "arm64ec"),
11906 link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0"
11907 )]
11908 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")]
11909 fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t;
11910 }
11911 _vld1q_s8_x3(a)
11912}
11913#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
11915#[doc = "## Safety"]
11916#[doc = " * Neon instrinsic unsafe"]
11917#[inline]
11918#[target_feature(enable = "neon")]
11919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11921#[cfg_attr(
11922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11923 assert_instr(ld1)
11924)]
11925#[cfg_attr(
11926 not(target_arch = "arm"),
11927 stable(feature = "neon_intrinsics", since = "1.59.0")
11928)]
11929#[cfg_attr(
11930 target_arch = "arm",
11931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11932)]
11933pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
11934 unsafe extern "unadjusted" {
11935 #[cfg_attr(
11936 any(target_arch = "aarch64", target_arch = "arm64ec"),
11937 link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0"
11938 )]
11939 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")]
11940 fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t;
11941 }
11942 _vld1q_s8_x4(a)
11943}
11944#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
11946#[doc = "## Safety"]
11947#[doc = " * Neon instrinsic unsafe"]
11948#[inline]
11949#[target_feature(enable = "neon")]
11950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11952#[cfg_attr(
11953 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11954 assert_instr(ld1)
11955)]
11956#[cfg_attr(
11957 not(target_arch = "arm"),
11958 stable(feature = "neon_intrinsics", since = "1.59.0")
11959)]
11960#[cfg_attr(
11961 target_arch = "arm",
11962 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11963)]
11964pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
11965 unsafe extern "unadjusted" {
11966 #[cfg_attr(
11967 any(target_arch = "aarch64", target_arch = "arm64ec"),
11968 link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0"
11969 )]
11970 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")]
11971 fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t;
11972 }
11973 _vld1_s16_x2(a)
11974}
11975#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
11976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
11977#[doc = "## Safety"]
11978#[doc = " * Neon instrinsic unsafe"]
11979#[inline]
11980#[target_feature(enable = "neon")]
11981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
11983#[cfg_attr(
11984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11985 assert_instr(ld1)
11986)]
11987#[cfg_attr(
11988 not(target_arch = "arm"),
11989 stable(feature = "neon_intrinsics", since = "1.59.0")
11990)]
11991#[cfg_attr(
11992 target_arch = "arm",
11993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11994)]
11995pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
11996 unsafe extern "unadjusted" {
11997 #[cfg_attr(
11998 any(target_arch = "aarch64", target_arch = "arm64ec"),
11999 link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0"
12000 )]
12001 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")]
12002 fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t;
12003 }
12004 _vld1_s16_x3(a)
12005}
12006#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
12008#[doc = "## Safety"]
12009#[doc = " * Neon instrinsic unsafe"]
12010#[inline]
12011#[target_feature(enable = "neon")]
12012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12014#[cfg_attr(
12015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12016 assert_instr(ld1)
12017)]
12018#[cfg_attr(
12019 not(target_arch = "arm"),
12020 stable(feature = "neon_intrinsics", since = "1.59.0")
12021)]
12022#[cfg_attr(
12023 target_arch = "arm",
12024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12025)]
12026pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
12027 unsafe extern "unadjusted" {
12028 #[cfg_attr(
12029 any(target_arch = "aarch64", target_arch = "arm64ec"),
12030 link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0"
12031 )]
12032 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")]
12033 fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t;
12034 }
12035 _vld1_s16_x4(a)
12036}
12037#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
12039#[doc = "## Safety"]
12040#[doc = " * Neon instrinsic unsafe"]
12041#[inline]
12042#[target_feature(enable = "neon")]
12043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12044#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12045#[cfg_attr(
12046 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12047 assert_instr(ld1)
12048)]
12049#[cfg_attr(
12050 not(target_arch = "arm"),
12051 stable(feature = "neon_intrinsics", since = "1.59.0")
12052)]
12053#[cfg_attr(
12054 target_arch = "arm",
12055 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12056)]
12057pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
12058 unsafe extern "unadjusted" {
12059 #[cfg_attr(
12060 any(target_arch = "aarch64", target_arch = "arm64ec"),
12061 link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0"
12062 )]
12063 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")]
12064 fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t;
12065 }
12066 _vld1q_s16_x2(a)
12067}
12068#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
12070#[doc = "## Safety"]
12071#[doc = " * Neon instrinsic unsafe"]
12072#[inline]
12073#[target_feature(enable = "neon")]
12074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12076#[cfg_attr(
12077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12078 assert_instr(ld1)
12079)]
12080#[cfg_attr(
12081 not(target_arch = "arm"),
12082 stable(feature = "neon_intrinsics", since = "1.59.0")
12083)]
12084#[cfg_attr(
12085 target_arch = "arm",
12086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12087)]
12088pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
12089 unsafe extern "unadjusted" {
12090 #[cfg_attr(
12091 any(target_arch = "aarch64", target_arch = "arm64ec"),
12092 link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0"
12093 )]
12094 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")]
12095 fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t;
12096 }
12097 _vld1q_s16_x3(a)
12098}
12099#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
12101#[doc = "## Safety"]
12102#[doc = " * Neon instrinsic unsafe"]
12103#[inline]
12104#[target_feature(enable = "neon")]
12105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12107#[cfg_attr(
12108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12109 assert_instr(ld1)
12110)]
12111#[cfg_attr(
12112 not(target_arch = "arm"),
12113 stable(feature = "neon_intrinsics", since = "1.59.0")
12114)]
12115#[cfg_attr(
12116 target_arch = "arm",
12117 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12118)]
12119pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
12120 unsafe extern "unadjusted" {
12121 #[cfg_attr(
12122 any(target_arch = "aarch64", target_arch = "arm64ec"),
12123 link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0"
12124 )]
12125 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")]
12126 fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t;
12127 }
12128 _vld1q_s16_x4(a)
12129}
12130#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
12132#[doc = "## Safety"]
12133#[doc = " * Neon instrinsic unsafe"]
12134#[inline]
12135#[target_feature(enable = "neon")]
12136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12138#[cfg_attr(
12139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12140 assert_instr(ld1)
12141)]
12142#[cfg_attr(
12143 not(target_arch = "arm"),
12144 stable(feature = "neon_intrinsics", since = "1.59.0")
12145)]
12146#[cfg_attr(
12147 target_arch = "arm",
12148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12149)]
12150pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
12151 unsafe extern "unadjusted" {
12152 #[cfg_attr(
12153 any(target_arch = "aarch64", target_arch = "arm64ec"),
12154 link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0"
12155 )]
12156 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")]
12157 fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t;
12158 }
12159 _vld1_s32_x2(a)
12160}
12161#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
12163#[doc = "## Safety"]
12164#[doc = " * Neon instrinsic unsafe"]
12165#[inline]
12166#[target_feature(enable = "neon")]
12167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12169#[cfg_attr(
12170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12171 assert_instr(ld1)
12172)]
12173#[cfg_attr(
12174 not(target_arch = "arm"),
12175 stable(feature = "neon_intrinsics", since = "1.59.0")
12176)]
12177#[cfg_attr(
12178 target_arch = "arm",
12179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12180)]
12181pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
12182 unsafe extern "unadjusted" {
12183 #[cfg_attr(
12184 any(target_arch = "aarch64", target_arch = "arm64ec"),
12185 link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0"
12186 )]
12187 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")]
12188 fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t;
12189 }
12190 _vld1_s32_x3(a)
12191}
12192#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
12194#[doc = "## Safety"]
12195#[doc = " * Neon instrinsic unsafe"]
12196#[inline]
12197#[target_feature(enable = "neon")]
12198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12200#[cfg_attr(
12201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12202 assert_instr(ld1)
12203)]
12204#[cfg_attr(
12205 not(target_arch = "arm"),
12206 stable(feature = "neon_intrinsics", since = "1.59.0")
12207)]
12208#[cfg_attr(
12209 target_arch = "arm",
12210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12211)]
12212pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
12213 unsafe extern "unadjusted" {
12214 #[cfg_attr(
12215 any(target_arch = "aarch64", target_arch = "arm64ec"),
12216 link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0"
12217 )]
12218 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")]
12219 fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t;
12220 }
12221 _vld1_s32_x4(a)
12222}
12223#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
12225#[doc = "## Safety"]
12226#[doc = " * Neon instrinsic unsafe"]
12227#[inline]
12228#[target_feature(enable = "neon")]
12229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12231#[cfg_attr(
12232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12233 assert_instr(ld1)
12234)]
12235#[cfg_attr(
12236 not(target_arch = "arm"),
12237 stable(feature = "neon_intrinsics", since = "1.59.0")
12238)]
12239#[cfg_attr(
12240 target_arch = "arm",
12241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12242)]
12243pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
12244 unsafe extern "unadjusted" {
12245 #[cfg_attr(
12246 any(target_arch = "aarch64", target_arch = "arm64ec"),
12247 link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0"
12248 )]
12249 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")]
12250 fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t;
12251 }
12252 _vld1q_s32_x2(a)
12253}
12254#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
12256#[doc = "## Safety"]
12257#[doc = " * Neon instrinsic unsafe"]
12258#[inline]
12259#[target_feature(enable = "neon")]
12260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12261#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12262#[cfg_attr(
12263 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12264 assert_instr(ld1)
12265)]
12266#[cfg_attr(
12267 not(target_arch = "arm"),
12268 stable(feature = "neon_intrinsics", since = "1.59.0")
12269)]
12270#[cfg_attr(
12271 target_arch = "arm",
12272 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12273)]
12274pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
12275 unsafe extern "unadjusted" {
12276 #[cfg_attr(
12277 any(target_arch = "aarch64", target_arch = "arm64ec"),
12278 link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0"
12279 )]
12280 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")]
12281 fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t;
12282 }
12283 _vld1q_s32_x3(a)
12284}
12285#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
12287#[doc = "## Safety"]
12288#[doc = " * Neon instrinsic unsafe"]
12289#[inline]
12290#[target_feature(enable = "neon")]
12291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12293#[cfg_attr(
12294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12295 assert_instr(ld1)
12296)]
12297#[cfg_attr(
12298 not(target_arch = "arm"),
12299 stable(feature = "neon_intrinsics", since = "1.59.0")
12300)]
12301#[cfg_attr(
12302 target_arch = "arm",
12303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12304)]
12305pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
12306 unsafe extern "unadjusted" {
12307 #[cfg_attr(
12308 any(target_arch = "aarch64", target_arch = "arm64ec"),
12309 link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0"
12310 )]
12311 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")]
12312 fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t;
12313 }
12314 _vld1q_s32_x4(a)
12315}
12316#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
12318#[doc = "## Safety"]
12319#[doc = " * Neon instrinsic unsafe"]
12320#[inline]
12321#[target_feature(enable = "neon")]
12322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12324#[cfg_attr(
12325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12326 assert_instr(ld1)
12327)]
12328#[cfg_attr(
12329 not(target_arch = "arm"),
12330 stable(feature = "neon_intrinsics", since = "1.59.0")
12331)]
12332#[cfg_attr(
12333 target_arch = "arm",
12334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12335)]
12336pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
12337 unsafe extern "unadjusted" {
12338 #[cfg_attr(
12339 any(target_arch = "aarch64", target_arch = "arm64ec"),
12340 link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0"
12341 )]
12342 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")]
12343 fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t;
12344 }
12345 _vld1_s64_x2(a)
12346}
12347#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
12349#[doc = "## Safety"]
12350#[doc = " * Neon instrinsic unsafe"]
12351#[inline]
12352#[target_feature(enable = "neon")]
12353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12355#[cfg_attr(
12356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12357 assert_instr(ld1)
12358)]
12359#[cfg_attr(
12360 not(target_arch = "arm"),
12361 stable(feature = "neon_intrinsics", since = "1.59.0")
12362)]
12363#[cfg_attr(
12364 target_arch = "arm",
12365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12366)]
12367pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
12368 unsafe extern "unadjusted" {
12369 #[cfg_attr(
12370 any(target_arch = "aarch64", target_arch = "arm64ec"),
12371 link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0"
12372 )]
12373 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")]
12374 fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t;
12375 }
12376 _vld1_s64_x3(a)
12377}
12378#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
12380#[doc = "## Safety"]
12381#[doc = " * Neon instrinsic unsafe"]
12382#[inline]
12383#[target_feature(enable = "neon")]
12384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12386#[cfg_attr(
12387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12388 assert_instr(ld1)
12389)]
12390#[cfg_attr(
12391 not(target_arch = "arm"),
12392 stable(feature = "neon_intrinsics", since = "1.59.0")
12393)]
12394#[cfg_attr(
12395 target_arch = "arm",
12396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12397)]
12398pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
12399 unsafe extern "unadjusted" {
12400 #[cfg_attr(
12401 any(target_arch = "aarch64", target_arch = "arm64ec"),
12402 link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0"
12403 )]
12404 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")]
12405 fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t;
12406 }
12407 _vld1_s64_x4(a)
12408}
12409#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
12411#[doc = "## Safety"]
12412#[doc = " * Neon instrinsic unsafe"]
12413#[inline]
12414#[target_feature(enable = "neon")]
12415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12417#[cfg_attr(
12418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12419 assert_instr(ld1)
12420)]
12421#[cfg_attr(
12422 not(target_arch = "arm"),
12423 stable(feature = "neon_intrinsics", since = "1.59.0")
12424)]
12425#[cfg_attr(
12426 target_arch = "arm",
12427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12428)]
12429pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
12430 unsafe extern "unadjusted" {
12431 #[cfg_attr(
12432 any(target_arch = "aarch64", target_arch = "arm64ec"),
12433 link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0"
12434 )]
12435 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")]
12436 fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t;
12437 }
12438 _vld1q_s64_x2(a)
12439}
12440#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
12442#[doc = "## Safety"]
12443#[doc = " * Neon instrinsic unsafe"]
12444#[inline]
12445#[target_feature(enable = "neon")]
12446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12448#[cfg_attr(
12449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12450 assert_instr(ld1)
12451)]
12452#[cfg_attr(
12453 not(target_arch = "arm"),
12454 stable(feature = "neon_intrinsics", since = "1.59.0")
12455)]
12456#[cfg_attr(
12457 target_arch = "arm",
12458 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12459)]
12460pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
12461 unsafe extern "unadjusted" {
12462 #[cfg_attr(
12463 any(target_arch = "aarch64", target_arch = "arm64ec"),
12464 link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0"
12465 )]
12466 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")]
12467 fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t;
12468 }
12469 _vld1q_s64_x3(a)
12470}
12471#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
12473#[doc = "## Safety"]
12474#[doc = " * Neon instrinsic unsafe"]
12475#[inline]
12476#[target_feature(enable = "neon")]
12477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12479#[cfg_attr(
12480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12481 assert_instr(ld1)
12482)]
12483#[cfg_attr(
12484 not(target_arch = "arm"),
12485 stable(feature = "neon_intrinsics", since = "1.59.0")
12486)]
12487#[cfg_attr(
12488 target_arch = "arm",
12489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12490)]
12491pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
12492 unsafe extern "unadjusted" {
12493 #[cfg_attr(
12494 any(target_arch = "aarch64", target_arch = "arm64ec"),
12495 link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0"
12496 )]
12497 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")]
12498 fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t;
12499 }
12500 _vld1q_s64_x4(a)
12501}
12502#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
12504#[doc = "## Safety"]
12505#[doc = " * Neon instrinsic unsafe"]
12506#[inline]
12507#[cfg(target_endian = "little")]
12508#[target_feature(enable = "neon")]
12509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12511#[cfg_attr(
12512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12513 assert_instr(ld1)
12514)]
12515#[cfg_attr(
12516 not(target_arch = "arm"),
12517 stable(feature = "neon_intrinsics", since = "1.59.0")
12518)]
12519#[cfg_attr(
12520 target_arch = "arm",
12521 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12522)]
12523pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
12524 transmute(vld1_s8_x2(transmute(a)))
12525}
12526#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
12528#[doc = "## Safety"]
12529#[doc = " * Neon instrinsic unsafe"]
12530#[inline]
12531#[cfg(target_endian = "big")]
12532#[target_feature(enable = "neon")]
12533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12535#[cfg_attr(
12536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12537 assert_instr(ld1)
12538)]
12539#[cfg_attr(
12540 not(target_arch = "arm"),
12541 stable(feature = "neon_intrinsics", since = "1.59.0")
12542)]
12543#[cfg_attr(
12544 target_arch = "arm",
12545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12546)]
12547pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
12548 let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
12549 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
12550 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
12551 ret_val
12552}
12553#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
12555#[doc = "## Safety"]
12556#[doc = " * Neon instrinsic unsafe"]
12557#[inline]
12558#[cfg(target_endian = "little")]
12559#[target_feature(enable = "neon")]
12560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12562#[cfg_attr(
12563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12564 assert_instr(ld1)
12565)]
12566#[cfg_attr(
12567 not(target_arch = "arm"),
12568 stable(feature = "neon_intrinsics", since = "1.59.0")
12569)]
12570#[cfg_attr(
12571 target_arch = "arm",
12572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12573)]
12574pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
12575 transmute(vld1_s8_x3(transmute(a)))
12576}
12577#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
12579#[doc = "## Safety"]
12580#[doc = " * Neon instrinsic unsafe"]
12581#[inline]
12582#[cfg(target_endian = "big")]
12583#[target_feature(enable = "neon")]
12584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12586#[cfg_attr(
12587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12588 assert_instr(ld1)
12589)]
12590#[cfg_attr(
12591 not(target_arch = "arm"),
12592 stable(feature = "neon_intrinsics", since = "1.59.0")
12593)]
12594#[cfg_attr(
12595 target_arch = "arm",
12596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12597)]
12598pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
12599 let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
12600 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
12601 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
12602 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
12603 ret_val
12604}
12605#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
12607#[doc = "## Safety"]
12608#[doc = " * Neon instrinsic unsafe"]
12609#[inline]
12610#[cfg(target_endian = "little")]
12611#[target_feature(enable = "neon")]
12612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12614#[cfg_attr(
12615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12616 assert_instr(ld1)
12617)]
12618#[cfg_attr(
12619 not(target_arch = "arm"),
12620 stable(feature = "neon_intrinsics", since = "1.59.0")
12621)]
12622#[cfg_attr(
12623 target_arch = "arm",
12624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12625)]
12626pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
12627 transmute(vld1_s8_x4(transmute(a)))
12628}
12629#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
12631#[doc = "## Safety"]
12632#[doc = " * Neon instrinsic unsafe"]
12633#[inline]
12634#[cfg(target_endian = "big")]
12635#[target_feature(enable = "neon")]
12636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12638#[cfg_attr(
12639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12640 assert_instr(ld1)
12641)]
12642#[cfg_attr(
12643 not(target_arch = "arm"),
12644 stable(feature = "neon_intrinsics", since = "1.59.0")
12645)]
12646#[cfg_attr(
12647 target_arch = "arm",
12648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12649)]
12650pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
12651 let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
12652 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
12653 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
12654 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
12655 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
12656 ret_val
12657}
12658#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
12660#[doc = "## Safety"]
12661#[doc = " * Neon instrinsic unsafe"]
12662#[inline]
12663#[cfg(target_endian = "little")]
12664#[target_feature(enable = "neon")]
12665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12667#[cfg_attr(
12668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12669 assert_instr(ld1)
12670)]
12671#[cfg_attr(
12672 not(target_arch = "arm"),
12673 stable(feature = "neon_intrinsics", since = "1.59.0")
12674)]
12675#[cfg_attr(
12676 target_arch = "arm",
12677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12678)]
12679pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
12680 transmute(vld1q_s8_x2(transmute(a)))
12681}
12682#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
12684#[doc = "## Safety"]
12685#[doc = " * Neon instrinsic unsafe"]
12686#[inline]
12687#[cfg(target_endian = "big")]
12688#[target_feature(enable = "neon")]
12689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12691#[cfg_attr(
12692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12693 assert_instr(ld1)
12694)]
12695#[cfg_attr(
12696 not(target_arch = "arm"),
12697 stable(feature = "neon_intrinsics", since = "1.59.0")
12698)]
12699#[cfg_attr(
12700 target_arch = "arm",
12701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12702)]
12703pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
12704 let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
12705 ret_val.0 = unsafe {
12706 simd_shuffle!(
12707 ret_val.0,
12708 ret_val.0,
12709 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12710 )
12711 };
12712 ret_val.1 = unsafe {
12713 simd_shuffle!(
12714 ret_val.1,
12715 ret_val.1,
12716 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12717 )
12718 };
12719 ret_val
12720}
12721#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
12723#[doc = "## Safety"]
12724#[doc = " * Neon instrinsic unsafe"]
12725#[inline]
12726#[cfg(target_endian = "little")]
12727#[target_feature(enable = "neon")]
12728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12730#[cfg_attr(
12731 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12732 assert_instr(ld1)
12733)]
12734#[cfg_attr(
12735 not(target_arch = "arm"),
12736 stable(feature = "neon_intrinsics", since = "1.59.0")
12737)]
12738#[cfg_attr(
12739 target_arch = "arm",
12740 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12741)]
12742pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
12743 transmute(vld1q_s8_x3(transmute(a)))
12744}
12745#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
12747#[doc = "## Safety"]
12748#[doc = " * Neon instrinsic unsafe"]
12749#[inline]
12750#[cfg(target_endian = "big")]
12751#[target_feature(enable = "neon")]
12752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12754#[cfg_attr(
12755 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12756 assert_instr(ld1)
12757)]
12758#[cfg_attr(
12759 not(target_arch = "arm"),
12760 stable(feature = "neon_intrinsics", since = "1.59.0")
12761)]
12762#[cfg_attr(
12763 target_arch = "arm",
12764 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12765)]
12766pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
12767 let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
12768 ret_val.0 = unsafe {
12769 simd_shuffle!(
12770 ret_val.0,
12771 ret_val.0,
12772 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12773 )
12774 };
12775 ret_val.1 = unsafe {
12776 simd_shuffle!(
12777 ret_val.1,
12778 ret_val.1,
12779 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12780 )
12781 };
12782 ret_val.2 = unsafe {
12783 simd_shuffle!(
12784 ret_val.2,
12785 ret_val.2,
12786 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12787 )
12788 };
12789 ret_val
12790}
12791#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
12793#[doc = "## Safety"]
12794#[doc = " * Neon instrinsic unsafe"]
12795#[inline]
12796#[cfg(target_endian = "little")]
12797#[target_feature(enable = "neon")]
12798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12800#[cfg_attr(
12801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12802 assert_instr(ld1)
12803)]
12804#[cfg_attr(
12805 not(target_arch = "arm"),
12806 stable(feature = "neon_intrinsics", since = "1.59.0")
12807)]
12808#[cfg_attr(
12809 target_arch = "arm",
12810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12811)]
12812pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
12813 transmute(vld1q_s8_x4(transmute(a)))
12814}
12815#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
12817#[doc = "## Safety"]
12818#[doc = " * Neon instrinsic unsafe"]
12819#[inline]
12820#[cfg(target_endian = "big")]
12821#[target_feature(enable = "neon")]
12822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12824#[cfg_attr(
12825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12826 assert_instr(ld1)
12827)]
12828#[cfg_attr(
12829 not(target_arch = "arm"),
12830 stable(feature = "neon_intrinsics", since = "1.59.0")
12831)]
12832#[cfg_attr(
12833 target_arch = "arm",
12834 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12835)]
12836pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
12837 let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
12838 ret_val.0 = unsafe {
12839 simd_shuffle!(
12840 ret_val.0,
12841 ret_val.0,
12842 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12843 )
12844 };
12845 ret_val.1 = unsafe {
12846 simd_shuffle!(
12847 ret_val.1,
12848 ret_val.1,
12849 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12850 )
12851 };
12852 ret_val.2 = unsafe {
12853 simd_shuffle!(
12854 ret_val.2,
12855 ret_val.2,
12856 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12857 )
12858 };
12859 ret_val.3 = unsafe {
12860 simd_shuffle!(
12861 ret_val.3,
12862 ret_val.3,
12863 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
12864 )
12865 };
12866 ret_val
12867}
12868#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
12870#[doc = "## Safety"]
12871#[doc = " * Neon instrinsic unsafe"]
12872#[inline]
12873#[cfg(target_endian = "little")]
12874#[target_feature(enable = "neon")]
12875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12877#[cfg_attr(
12878 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12879 assert_instr(ld1)
12880)]
12881#[cfg_attr(
12882 not(target_arch = "arm"),
12883 stable(feature = "neon_intrinsics", since = "1.59.0")
12884)]
12885#[cfg_attr(
12886 target_arch = "arm",
12887 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12888)]
12889pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
12890 transmute(vld1_s16_x2(transmute(a)))
12891}
12892#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
12894#[doc = "## Safety"]
12895#[doc = " * Neon instrinsic unsafe"]
12896#[inline]
12897#[cfg(target_endian = "big")]
12898#[target_feature(enable = "neon")]
12899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12901#[cfg_attr(
12902 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12903 assert_instr(ld1)
12904)]
12905#[cfg_attr(
12906 not(target_arch = "arm"),
12907 stable(feature = "neon_intrinsics", since = "1.59.0")
12908)]
12909#[cfg_attr(
12910 target_arch = "arm",
12911 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12912)]
12913pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
12914 let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
12915 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
12916 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
12917 ret_val
12918}
12919#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
12921#[doc = "## Safety"]
12922#[doc = " * Neon instrinsic unsafe"]
12923#[inline]
12924#[cfg(target_endian = "little")]
12925#[target_feature(enable = "neon")]
12926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12928#[cfg_attr(
12929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12930 assert_instr(ld1)
12931)]
12932#[cfg_attr(
12933 not(target_arch = "arm"),
12934 stable(feature = "neon_intrinsics", since = "1.59.0")
12935)]
12936#[cfg_attr(
12937 target_arch = "arm",
12938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12939)]
12940pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
12941 transmute(vld1_s16_x3(transmute(a)))
12942}
12943#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
12945#[doc = "## Safety"]
12946#[doc = " * Neon instrinsic unsafe"]
12947#[inline]
12948#[cfg(target_endian = "big")]
12949#[target_feature(enable = "neon")]
12950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12952#[cfg_attr(
12953 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12954 assert_instr(ld1)
12955)]
12956#[cfg_attr(
12957 not(target_arch = "arm"),
12958 stable(feature = "neon_intrinsics", since = "1.59.0")
12959)]
12960#[cfg_attr(
12961 target_arch = "arm",
12962 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12963)]
12964pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
12965 let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
12966 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
12967 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
12968 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
12969 ret_val
12970}
12971#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
12973#[doc = "## Safety"]
12974#[doc = " * Neon instrinsic unsafe"]
12975#[inline]
12976#[cfg(target_endian = "little")]
12977#[target_feature(enable = "neon")]
12978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12979#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
12980#[cfg_attr(
12981 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12982 assert_instr(ld1)
12983)]
12984#[cfg_attr(
12985 not(target_arch = "arm"),
12986 stable(feature = "neon_intrinsics", since = "1.59.0")
12987)]
12988#[cfg_attr(
12989 target_arch = "arm",
12990 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12991)]
12992pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
12993 transmute(vld1_s16_x4(transmute(a)))
12994}
12995#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
12996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
12997#[doc = "## Safety"]
12998#[doc = " * Neon instrinsic unsafe"]
12999#[inline]
13000#[cfg(target_endian = "big")]
13001#[target_feature(enable = "neon")]
13002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13004#[cfg_attr(
13005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13006 assert_instr(ld1)
13007)]
13008#[cfg_attr(
13009 not(target_arch = "arm"),
13010 stable(feature = "neon_intrinsics", since = "1.59.0")
13011)]
13012#[cfg_attr(
13013 target_arch = "arm",
13014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13015)]
13016pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
13017 let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
13018 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
13019 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
13020 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
13021 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
13022 ret_val
13023}
13024#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
13026#[doc = "## Safety"]
13027#[doc = " * Neon instrinsic unsafe"]
13028#[inline]
13029#[cfg(target_endian = "little")]
13030#[target_feature(enable = "neon")]
13031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13033#[cfg_attr(
13034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13035 assert_instr(ld1)
13036)]
13037#[cfg_attr(
13038 not(target_arch = "arm"),
13039 stable(feature = "neon_intrinsics", since = "1.59.0")
13040)]
13041#[cfg_attr(
13042 target_arch = "arm",
13043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13044)]
13045pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
13046 transmute(vld1q_s16_x2(transmute(a)))
13047}
13048#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
13050#[doc = "## Safety"]
13051#[doc = " * Neon instrinsic unsafe"]
13052#[inline]
13053#[cfg(target_endian = "big")]
13054#[target_feature(enable = "neon")]
13055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13057#[cfg_attr(
13058 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13059 assert_instr(ld1)
13060)]
13061#[cfg_attr(
13062 not(target_arch = "arm"),
13063 stable(feature = "neon_intrinsics", since = "1.59.0")
13064)]
13065#[cfg_attr(
13066 target_arch = "arm",
13067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13068)]
13069pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
13070 let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
13071 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
13072 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
13073 ret_val
13074}
13075#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
13077#[doc = "## Safety"]
13078#[doc = " * Neon instrinsic unsafe"]
13079#[inline]
13080#[cfg(target_endian = "little")]
13081#[target_feature(enable = "neon")]
13082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13083#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13084#[cfg_attr(
13085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13086 assert_instr(ld1)
13087)]
13088#[cfg_attr(
13089 not(target_arch = "arm"),
13090 stable(feature = "neon_intrinsics", since = "1.59.0")
13091)]
13092#[cfg_attr(
13093 target_arch = "arm",
13094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13095)]
13096pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
13097 transmute(vld1q_s16_x3(transmute(a)))
13098}
13099#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
13101#[doc = "## Safety"]
13102#[doc = " * Neon instrinsic unsafe"]
13103#[inline]
13104#[cfg(target_endian = "big")]
13105#[target_feature(enable = "neon")]
13106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13108#[cfg_attr(
13109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13110 assert_instr(ld1)
13111)]
13112#[cfg_attr(
13113 not(target_arch = "arm"),
13114 stable(feature = "neon_intrinsics", since = "1.59.0")
13115)]
13116#[cfg_attr(
13117 target_arch = "arm",
13118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13119)]
13120pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
13121 let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
13122 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
13123 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
13124 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
13125 ret_val
13126}
13127#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
13129#[doc = "## Safety"]
13130#[doc = " * Neon instrinsic unsafe"]
13131#[inline]
13132#[cfg(target_endian = "little")]
13133#[target_feature(enable = "neon")]
13134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13136#[cfg_attr(
13137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13138 assert_instr(ld1)
13139)]
13140#[cfg_attr(
13141 not(target_arch = "arm"),
13142 stable(feature = "neon_intrinsics", since = "1.59.0")
13143)]
13144#[cfg_attr(
13145 target_arch = "arm",
13146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13147)]
13148pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
13149 transmute(vld1q_s16_x4(transmute(a)))
13150}
13151#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
13153#[doc = "## Safety"]
13154#[doc = " * Neon instrinsic unsafe"]
13155#[inline]
13156#[cfg(target_endian = "big")]
13157#[target_feature(enable = "neon")]
13158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13160#[cfg_attr(
13161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13162 assert_instr(ld1)
13163)]
13164#[cfg_attr(
13165 not(target_arch = "arm"),
13166 stable(feature = "neon_intrinsics", since = "1.59.0")
13167)]
13168#[cfg_attr(
13169 target_arch = "arm",
13170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13171)]
13172pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
13173 let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
13174 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
13175 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
13176 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
13177 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
13178 ret_val
13179}
13180#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
13182#[doc = "## Safety"]
13183#[doc = " * Neon instrinsic unsafe"]
13184#[inline]
13185#[cfg(target_endian = "little")]
13186#[target_feature(enable = "neon")]
13187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13189#[cfg_attr(
13190 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13191 assert_instr(ld1)
13192)]
13193#[cfg_attr(
13194 not(target_arch = "arm"),
13195 stable(feature = "neon_intrinsics", since = "1.59.0")
13196)]
13197#[cfg_attr(
13198 target_arch = "arm",
13199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13200)]
13201pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
13202 transmute(vld1_s32_x2(transmute(a)))
13203}
13204#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
13206#[doc = "## Safety"]
13207#[doc = " * Neon instrinsic unsafe"]
13208#[inline]
13209#[cfg(target_endian = "big")]
13210#[target_feature(enable = "neon")]
13211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13213#[cfg_attr(
13214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13215 assert_instr(ld1)
13216)]
13217#[cfg_attr(
13218 not(target_arch = "arm"),
13219 stable(feature = "neon_intrinsics", since = "1.59.0")
13220)]
13221#[cfg_attr(
13222 target_arch = "arm",
13223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13224)]
13225pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
13226 let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a)));
13227 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
13228 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
13229 ret_val
13230}
13231#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
13233#[doc = "## Safety"]
13234#[doc = " * Neon instrinsic unsafe"]
13235#[inline]
13236#[cfg(target_endian = "little")]
13237#[target_feature(enable = "neon")]
13238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13240#[cfg_attr(
13241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13242 assert_instr(ld1)
13243)]
13244#[cfg_attr(
13245 not(target_arch = "arm"),
13246 stable(feature = "neon_intrinsics", since = "1.59.0")
13247)]
13248#[cfg_attr(
13249 target_arch = "arm",
13250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13251)]
13252pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
13253 transmute(vld1_s32_x3(transmute(a)))
13254}
13255#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
13257#[doc = "## Safety"]
13258#[doc = " * Neon instrinsic unsafe"]
13259#[inline]
13260#[cfg(target_endian = "big")]
13261#[target_feature(enable = "neon")]
13262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13264#[cfg_attr(
13265 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13266 assert_instr(ld1)
13267)]
13268#[cfg_attr(
13269 not(target_arch = "arm"),
13270 stable(feature = "neon_intrinsics", since = "1.59.0")
13271)]
13272#[cfg_attr(
13273 target_arch = "arm",
13274 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13275)]
13276pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
13277 let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a)));
13278 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
13279 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
13280 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
13281 ret_val
13282}
13283#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
13285#[doc = "## Safety"]
13286#[doc = " * Neon instrinsic unsafe"]
13287#[inline]
13288#[cfg(target_endian = "little")]
13289#[target_feature(enable = "neon")]
13290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13292#[cfg_attr(
13293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13294 assert_instr(ld1)
13295)]
13296#[cfg_attr(
13297 not(target_arch = "arm"),
13298 stable(feature = "neon_intrinsics", since = "1.59.0")
13299)]
13300#[cfg_attr(
13301 target_arch = "arm",
13302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13303)]
13304pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
13305 transmute(vld1_s32_x4(transmute(a)))
13306}
13307#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
13309#[doc = "## Safety"]
13310#[doc = " * Neon instrinsic unsafe"]
13311#[inline]
13312#[cfg(target_endian = "big")]
13313#[target_feature(enable = "neon")]
13314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13316#[cfg_attr(
13317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13318 assert_instr(ld1)
13319)]
13320#[cfg_attr(
13321 not(target_arch = "arm"),
13322 stable(feature = "neon_intrinsics", since = "1.59.0")
13323)]
13324#[cfg_attr(
13325 target_arch = "arm",
13326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13327)]
13328pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
13329 let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a)));
13330 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
13331 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
13332 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
13333 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
13334 ret_val
13335}
13336#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
13338#[doc = "## Safety"]
13339#[doc = " * Neon instrinsic unsafe"]
13340#[inline]
13341#[cfg(target_endian = "little")]
13342#[target_feature(enable = "neon")]
13343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13345#[cfg_attr(
13346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13347 assert_instr(ld1)
13348)]
13349#[cfg_attr(
13350 not(target_arch = "arm"),
13351 stable(feature = "neon_intrinsics", since = "1.59.0")
13352)]
13353#[cfg_attr(
13354 target_arch = "arm",
13355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13356)]
13357pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
13358 transmute(vld1q_s32_x2(transmute(a)))
13359}
13360#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
13362#[doc = "## Safety"]
13363#[doc = " * Neon instrinsic unsafe"]
13364#[inline]
13365#[cfg(target_endian = "big")]
13366#[target_feature(enable = "neon")]
13367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13369#[cfg_attr(
13370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13371 assert_instr(ld1)
13372)]
13373#[cfg_attr(
13374 not(target_arch = "arm"),
13375 stable(feature = "neon_intrinsics", since = "1.59.0")
13376)]
13377#[cfg_attr(
13378 target_arch = "arm",
13379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13380)]
13381pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
13382 let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a)));
13383 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
13384 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
13385 ret_val
13386}
13387#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
13389#[doc = "## Safety"]
13390#[doc = " * Neon instrinsic unsafe"]
13391#[inline]
13392#[cfg(target_endian = "little")]
13393#[target_feature(enable = "neon")]
13394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13396#[cfg_attr(
13397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13398 assert_instr(ld1)
13399)]
13400#[cfg_attr(
13401 not(target_arch = "arm"),
13402 stable(feature = "neon_intrinsics", since = "1.59.0")
13403)]
13404#[cfg_attr(
13405 target_arch = "arm",
13406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13407)]
13408pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
13409 transmute(vld1q_s32_x3(transmute(a)))
13410}
13411#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
13413#[doc = "## Safety"]
13414#[doc = " * Neon instrinsic unsafe"]
13415#[inline]
13416#[cfg(target_endian = "big")]
13417#[target_feature(enable = "neon")]
13418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13419#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13420#[cfg_attr(
13421 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13422 assert_instr(ld1)
13423)]
13424#[cfg_attr(
13425 not(target_arch = "arm"),
13426 stable(feature = "neon_intrinsics", since = "1.59.0")
13427)]
13428#[cfg_attr(
13429 target_arch = "arm",
13430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13431)]
13432pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
13433 let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a)));
13434 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
13435 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
13436 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
13437 ret_val
13438}
13439#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
13441#[doc = "## Safety"]
13442#[doc = " * Neon instrinsic unsafe"]
13443#[inline]
13444#[cfg(target_endian = "little")]
13445#[target_feature(enable = "neon")]
13446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13448#[cfg_attr(
13449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13450 assert_instr(ld1)
13451)]
13452#[cfg_attr(
13453 not(target_arch = "arm"),
13454 stable(feature = "neon_intrinsics", since = "1.59.0")
13455)]
13456#[cfg_attr(
13457 target_arch = "arm",
13458 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13459)]
13460pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
13461 transmute(vld1q_s32_x4(transmute(a)))
13462}
13463#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
13465#[doc = "## Safety"]
13466#[doc = " * Neon instrinsic unsafe"]
13467#[inline]
13468#[cfg(target_endian = "big")]
13469#[target_feature(enable = "neon")]
13470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13472#[cfg_attr(
13473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13474 assert_instr(ld1)
13475)]
13476#[cfg_attr(
13477 not(target_arch = "arm"),
13478 stable(feature = "neon_intrinsics", since = "1.59.0")
13479)]
13480#[cfg_attr(
13481 target_arch = "arm",
13482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13483)]
13484pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
13485 let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a)));
13486 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
13487 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
13488 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
13489 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
13490 ret_val
13491}
13492#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
13494#[doc = "## Safety"]
13495#[doc = " * Neon instrinsic unsafe"]
13496#[inline]
13497#[target_feature(enable = "neon")]
13498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13500#[cfg_attr(
13501 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13502 assert_instr(ld1)
13503)]
13504#[cfg_attr(
13505 not(target_arch = "arm"),
13506 stable(feature = "neon_intrinsics", since = "1.59.0")
13507)]
13508#[cfg_attr(
13509 target_arch = "arm",
13510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13511)]
13512pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
13513 transmute(vld1_s64_x2(transmute(a)))
13514}
13515#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
13517#[doc = "## Safety"]
13518#[doc = " * Neon instrinsic unsafe"]
13519#[inline]
13520#[target_feature(enable = "neon")]
13521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13522#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13523#[cfg_attr(
13524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13525 assert_instr(ld1)
13526)]
13527#[cfg_attr(
13528 not(target_arch = "arm"),
13529 stable(feature = "neon_intrinsics", since = "1.59.0")
13530)]
13531#[cfg_attr(
13532 target_arch = "arm",
13533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13534)]
13535pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
13536 transmute(vld1_s64_x3(transmute(a)))
13537}
13538#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
13540#[doc = "## Safety"]
13541#[doc = " * Neon instrinsic unsafe"]
13542#[inline]
13543#[target_feature(enable = "neon")]
13544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13546#[cfg_attr(
13547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13548 assert_instr(ld1)
13549)]
13550#[cfg_attr(
13551 not(target_arch = "arm"),
13552 stable(feature = "neon_intrinsics", since = "1.59.0")
13553)]
13554#[cfg_attr(
13555 target_arch = "arm",
13556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13557)]
13558pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
13559 transmute(vld1_s64_x4(transmute(a)))
13560}
13561#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
13563#[doc = "## Safety"]
13564#[doc = " * Neon instrinsic unsafe"]
13565#[inline]
13566#[cfg(target_endian = "little")]
13567#[target_feature(enable = "neon")]
13568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13570#[cfg_attr(
13571 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13572 assert_instr(ld1)
13573)]
13574#[cfg_attr(
13575 not(target_arch = "arm"),
13576 stable(feature = "neon_intrinsics", since = "1.59.0")
13577)]
13578#[cfg_attr(
13579 target_arch = "arm",
13580 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13581)]
13582pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
13583 transmute(vld1q_s64_x2(transmute(a)))
13584}
13585#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
13587#[doc = "## Safety"]
13588#[doc = " * Neon instrinsic unsafe"]
13589#[inline]
13590#[cfg(target_endian = "big")]
13591#[target_feature(enable = "neon")]
13592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13594#[cfg_attr(
13595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13596 assert_instr(ld1)
13597)]
13598#[cfg_attr(
13599 not(target_arch = "arm"),
13600 stable(feature = "neon_intrinsics", since = "1.59.0")
13601)]
13602#[cfg_attr(
13603 target_arch = "arm",
13604 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13605)]
13606pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
13607 let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
13608 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
13609 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
13610 ret_val
13611}
13612#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
13614#[doc = "## Safety"]
13615#[doc = " * Neon instrinsic unsafe"]
13616#[inline]
13617#[cfg(target_endian = "little")]
13618#[target_feature(enable = "neon")]
13619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13621#[cfg_attr(
13622 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13623 assert_instr(ld1)
13624)]
13625#[cfg_attr(
13626 not(target_arch = "arm"),
13627 stable(feature = "neon_intrinsics", since = "1.59.0")
13628)]
13629#[cfg_attr(
13630 target_arch = "arm",
13631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13632)]
13633pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
13634 transmute(vld1q_s64_x3(transmute(a)))
13635}
13636#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
13638#[doc = "## Safety"]
13639#[doc = " * Neon instrinsic unsafe"]
13640#[inline]
13641#[cfg(target_endian = "big")]
13642#[target_feature(enable = "neon")]
13643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13645#[cfg_attr(
13646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13647 assert_instr(ld1)
13648)]
13649#[cfg_attr(
13650 not(target_arch = "arm"),
13651 stable(feature = "neon_intrinsics", since = "1.59.0")
13652)]
13653#[cfg_attr(
13654 target_arch = "arm",
13655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13656)]
13657pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
13658 let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
13659 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
13660 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
13661 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
13662 ret_val
13663}
13664#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
13666#[doc = "## Safety"]
13667#[doc = " * Neon instrinsic unsafe"]
13668#[inline]
13669#[cfg(target_endian = "little")]
13670#[target_feature(enable = "neon")]
13671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13673#[cfg_attr(
13674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13675 assert_instr(ld1)
13676)]
13677#[cfg_attr(
13678 not(target_arch = "arm"),
13679 stable(feature = "neon_intrinsics", since = "1.59.0")
13680)]
13681#[cfg_attr(
13682 target_arch = "arm",
13683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13684)]
13685pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
13686 transmute(vld1q_s64_x4(transmute(a)))
13687}
13688#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
13690#[doc = "## Safety"]
13691#[doc = " * Neon instrinsic unsafe"]
13692#[inline]
13693#[cfg(target_endian = "big")]
13694#[target_feature(enable = "neon")]
13695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13697#[cfg_attr(
13698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13699 assert_instr(ld1)
13700)]
13701#[cfg_attr(
13702 not(target_arch = "arm"),
13703 stable(feature = "neon_intrinsics", since = "1.59.0")
13704)]
13705#[cfg_attr(
13706 target_arch = "arm",
13707 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13708)]
13709pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
13710 let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
13711 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
13712 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
13713 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
13714 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
13715 ret_val
13716}
13717#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
13719#[doc = "## Safety"]
13720#[doc = " * Neon instrinsic unsafe"]
13721#[inline]
13722#[cfg(target_endian = "little")]
13723#[target_feature(enable = "neon")]
13724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13726#[cfg_attr(
13727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13728 assert_instr(ld1)
13729)]
13730#[cfg_attr(
13731 not(target_arch = "arm"),
13732 stable(feature = "neon_intrinsics", since = "1.59.0")
13733)]
13734#[cfg_attr(
13735 target_arch = "arm",
13736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13737)]
13738pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
13739 transmute(vld1_s8_x2(transmute(a)))
13740}
13741#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
13743#[doc = "## Safety"]
13744#[doc = " * Neon instrinsic unsafe"]
13745#[inline]
13746#[cfg(target_endian = "big")]
13747#[target_feature(enable = "neon")]
13748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13750#[cfg_attr(
13751 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13752 assert_instr(ld1)
13753)]
13754#[cfg_attr(
13755 not(target_arch = "arm"),
13756 stable(feature = "neon_intrinsics", since = "1.59.0")
13757)]
13758#[cfg_attr(
13759 target_arch = "arm",
13760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13761)]
13762pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
13763 let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
13764 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
13765 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
13766 ret_val
13767}
13768#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
13770#[doc = "## Safety"]
13771#[doc = " * Neon instrinsic unsafe"]
13772#[inline]
13773#[cfg(target_endian = "little")]
13774#[target_feature(enable = "neon")]
13775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13776#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13777#[cfg_attr(
13778 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13779 assert_instr(ld1)
13780)]
13781#[cfg_attr(
13782 not(target_arch = "arm"),
13783 stable(feature = "neon_intrinsics", since = "1.59.0")
13784)]
13785#[cfg_attr(
13786 target_arch = "arm",
13787 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13788)]
13789pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
13790 transmute(vld1_s8_x3(transmute(a)))
13791}
13792#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
13794#[doc = "## Safety"]
13795#[doc = " * Neon instrinsic unsafe"]
13796#[inline]
13797#[cfg(target_endian = "big")]
13798#[target_feature(enable = "neon")]
13799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13800#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13801#[cfg_attr(
13802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13803 assert_instr(ld1)
13804)]
13805#[cfg_attr(
13806 not(target_arch = "arm"),
13807 stable(feature = "neon_intrinsics", since = "1.59.0")
13808)]
13809#[cfg_attr(
13810 target_arch = "arm",
13811 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13812)]
13813pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
13814 let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
13815 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
13816 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
13817 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
13818 ret_val
13819}
13820#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
13822#[doc = "## Safety"]
13823#[doc = " * Neon instrinsic unsafe"]
13824#[inline]
13825#[cfg(target_endian = "little")]
13826#[target_feature(enable = "neon")]
13827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13829#[cfg_attr(
13830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13831 assert_instr(ld1)
13832)]
13833#[cfg_attr(
13834 not(target_arch = "arm"),
13835 stable(feature = "neon_intrinsics", since = "1.59.0")
13836)]
13837#[cfg_attr(
13838 target_arch = "arm",
13839 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13840)]
13841pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
13842 transmute(vld1_s8_x4(transmute(a)))
13843}
13844#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
13846#[doc = "## Safety"]
13847#[doc = " * Neon instrinsic unsafe"]
13848#[inline]
13849#[cfg(target_endian = "big")]
13850#[target_feature(enable = "neon")]
13851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13853#[cfg_attr(
13854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13855 assert_instr(ld1)
13856)]
13857#[cfg_attr(
13858 not(target_arch = "arm"),
13859 stable(feature = "neon_intrinsics", since = "1.59.0")
13860)]
13861#[cfg_attr(
13862 target_arch = "arm",
13863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13864)]
13865pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
13866 let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
13867 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
13868 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
13869 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
13870 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
13871 ret_val
13872}
13873#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
13875#[doc = "## Safety"]
13876#[doc = " * Neon instrinsic unsafe"]
13877#[inline]
13878#[cfg(target_endian = "little")]
13879#[target_feature(enable = "neon")]
13880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13882#[cfg_attr(
13883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13884 assert_instr(ld1)
13885)]
13886#[cfg_attr(
13887 not(target_arch = "arm"),
13888 stable(feature = "neon_intrinsics", since = "1.59.0")
13889)]
13890#[cfg_attr(
13891 target_arch = "arm",
13892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13893)]
13894pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
13895 transmute(vld1q_s8_x2(transmute(a)))
13896}
13897#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
13899#[doc = "## Safety"]
13900#[doc = " * Neon instrinsic unsafe"]
13901#[inline]
13902#[cfg(target_endian = "big")]
13903#[target_feature(enable = "neon")]
13904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13906#[cfg_attr(
13907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13908 assert_instr(ld1)
13909)]
13910#[cfg_attr(
13911 not(target_arch = "arm"),
13912 stable(feature = "neon_intrinsics", since = "1.59.0")
13913)]
13914#[cfg_attr(
13915 target_arch = "arm",
13916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13917)]
13918pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
13919 let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
13920 ret_val.0 = unsafe {
13921 simd_shuffle!(
13922 ret_val.0,
13923 ret_val.0,
13924 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
13925 )
13926 };
13927 ret_val.1 = unsafe {
13928 simd_shuffle!(
13929 ret_val.1,
13930 ret_val.1,
13931 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
13932 )
13933 };
13934 ret_val
13935}
13936#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
13938#[doc = "## Safety"]
13939#[doc = " * Neon instrinsic unsafe"]
13940#[inline]
13941#[cfg(target_endian = "little")]
13942#[target_feature(enable = "neon")]
13943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13945#[cfg_attr(
13946 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13947 assert_instr(ld1)
13948)]
13949#[cfg_attr(
13950 not(target_arch = "arm"),
13951 stable(feature = "neon_intrinsics", since = "1.59.0")
13952)]
13953#[cfg_attr(
13954 target_arch = "arm",
13955 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13956)]
13957pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
13958 transmute(vld1q_s8_x3(transmute(a)))
13959}
13960#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
13961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
13962#[doc = "## Safety"]
13963#[doc = " * Neon instrinsic unsafe"]
13964#[inline]
13965#[cfg(target_endian = "big")]
13966#[target_feature(enable = "neon")]
13967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
13969#[cfg_attr(
13970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13971 assert_instr(ld1)
13972)]
13973#[cfg_attr(
13974 not(target_arch = "arm"),
13975 stable(feature = "neon_intrinsics", since = "1.59.0")
13976)]
13977#[cfg_attr(
13978 target_arch = "arm",
13979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13980)]
13981pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
13982 let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
13983 ret_val.0 = unsafe {
13984 simd_shuffle!(
13985 ret_val.0,
13986 ret_val.0,
13987 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
13988 )
13989 };
13990 ret_val.1 = unsafe {
13991 simd_shuffle!(
13992 ret_val.1,
13993 ret_val.1,
13994 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
13995 )
13996 };
13997 ret_val.2 = unsafe {
13998 simd_shuffle!(
13999 ret_val.2,
14000 ret_val.2,
14001 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14002 )
14003 };
14004 ret_val
14005}
14006#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
14008#[doc = "## Safety"]
14009#[doc = " * Neon instrinsic unsafe"]
14010#[inline]
14011#[cfg(target_endian = "little")]
14012#[target_feature(enable = "neon")]
14013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14015#[cfg_attr(
14016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14017 assert_instr(ld1)
14018)]
14019#[cfg_attr(
14020 not(target_arch = "arm"),
14021 stable(feature = "neon_intrinsics", since = "1.59.0")
14022)]
14023#[cfg_attr(
14024 target_arch = "arm",
14025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14026)]
14027pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
14028 transmute(vld1q_s8_x4(transmute(a)))
14029}
14030#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
14032#[doc = "## Safety"]
14033#[doc = " * Neon instrinsic unsafe"]
14034#[inline]
14035#[cfg(target_endian = "big")]
14036#[target_feature(enable = "neon")]
14037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14039#[cfg_attr(
14040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14041 assert_instr(ld1)
14042)]
14043#[cfg_attr(
14044 not(target_arch = "arm"),
14045 stable(feature = "neon_intrinsics", since = "1.59.0")
14046)]
14047#[cfg_attr(
14048 target_arch = "arm",
14049 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14050)]
14051pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
14052 let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
14053 ret_val.0 = unsafe {
14054 simd_shuffle!(
14055 ret_val.0,
14056 ret_val.0,
14057 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14058 )
14059 };
14060 ret_val.1 = unsafe {
14061 simd_shuffle!(
14062 ret_val.1,
14063 ret_val.1,
14064 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14065 )
14066 };
14067 ret_val.2 = unsafe {
14068 simd_shuffle!(
14069 ret_val.2,
14070 ret_val.2,
14071 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14072 )
14073 };
14074 ret_val.3 = unsafe {
14075 simd_shuffle!(
14076 ret_val.3,
14077 ret_val.3,
14078 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14079 )
14080 };
14081 ret_val
14082}
14083#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
14085#[doc = "## Safety"]
14086#[doc = " * Neon instrinsic unsafe"]
14087#[inline]
14088#[cfg(target_endian = "little")]
14089#[target_feature(enable = "neon")]
14090#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14091#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14092#[cfg_attr(
14093 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14094 assert_instr(ld1)
14095)]
14096#[cfg_attr(
14097 not(target_arch = "arm"),
14098 stable(feature = "neon_intrinsics", since = "1.59.0")
14099)]
14100#[cfg_attr(
14101 target_arch = "arm",
14102 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14103)]
14104pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
14105 transmute(vld1_s16_x2(transmute(a)))
14106}
14107#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
14109#[doc = "## Safety"]
14110#[doc = " * Neon instrinsic unsafe"]
14111#[inline]
14112#[cfg(target_endian = "big")]
14113#[target_feature(enable = "neon")]
14114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14116#[cfg_attr(
14117 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14118 assert_instr(ld1)
14119)]
14120#[cfg_attr(
14121 not(target_arch = "arm"),
14122 stable(feature = "neon_intrinsics", since = "1.59.0")
14123)]
14124#[cfg_attr(
14125 target_arch = "arm",
14126 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14127)]
14128pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
14129 let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
14130 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
14131 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
14132 ret_val
14133}
14134#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
14136#[doc = "## Safety"]
14137#[doc = " * Neon instrinsic unsafe"]
14138#[inline]
14139#[cfg(target_endian = "little")]
14140#[target_feature(enable = "neon")]
14141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14143#[cfg_attr(
14144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14145 assert_instr(ld1)
14146)]
14147#[cfg_attr(
14148 not(target_arch = "arm"),
14149 stable(feature = "neon_intrinsics", since = "1.59.0")
14150)]
14151#[cfg_attr(
14152 target_arch = "arm",
14153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14154)]
14155pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
14156 transmute(vld1_s16_x3(transmute(a)))
14157}
14158#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
14160#[doc = "## Safety"]
14161#[doc = " * Neon instrinsic unsafe"]
14162#[inline]
14163#[cfg(target_endian = "big")]
14164#[target_feature(enable = "neon")]
14165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14167#[cfg_attr(
14168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14169 assert_instr(ld1)
14170)]
14171#[cfg_attr(
14172 not(target_arch = "arm"),
14173 stable(feature = "neon_intrinsics", since = "1.59.0")
14174)]
14175#[cfg_attr(
14176 target_arch = "arm",
14177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14178)]
14179pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
14180 let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
14181 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
14182 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
14183 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
14184 ret_val
14185}
14186#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
14188#[doc = "## Safety"]
14189#[doc = " * Neon instrinsic unsafe"]
14190#[inline]
14191#[cfg(target_endian = "little")]
14192#[target_feature(enable = "neon")]
14193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14195#[cfg_attr(
14196 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14197 assert_instr(ld1)
14198)]
14199#[cfg_attr(
14200 not(target_arch = "arm"),
14201 stable(feature = "neon_intrinsics", since = "1.59.0")
14202)]
14203#[cfg_attr(
14204 target_arch = "arm",
14205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14206)]
14207pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
14208 transmute(vld1_s16_x4(transmute(a)))
14209}
14210#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
14212#[doc = "## Safety"]
14213#[doc = " * Neon instrinsic unsafe"]
14214#[inline]
14215#[cfg(target_endian = "big")]
14216#[target_feature(enable = "neon")]
14217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14219#[cfg_attr(
14220 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14221 assert_instr(ld1)
14222)]
14223#[cfg_attr(
14224 not(target_arch = "arm"),
14225 stable(feature = "neon_intrinsics", since = "1.59.0")
14226)]
14227#[cfg_attr(
14228 target_arch = "arm",
14229 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14230)]
14231pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
14232 let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
14233 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
14234 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
14235 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
14236 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
14237 ret_val
14238}
14239#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
14241#[doc = "## Safety"]
14242#[doc = " * Neon instrinsic unsafe"]
14243#[inline]
14244#[cfg(target_endian = "little")]
14245#[target_feature(enable = "neon")]
14246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14248#[cfg_attr(
14249 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14250 assert_instr(ld1)
14251)]
14252#[cfg_attr(
14253 not(target_arch = "arm"),
14254 stable(feature = "neon_intrinsics", since = "1.59.0")
14255)]
14256#[cfg_attr(
14257 target_arch = "arm",
14258 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14259)]
14260pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
14261 transmute(vld1q_s16_x2(transmute(a)))
14262}
14263#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
14265#[doc = "## Safety"]
14266#[doc = " * Neon instrinsic unsafe"]
14267#[inline]
14268#[cfg(target_endian = "big")]
14269#[target_feature(enable = "neon")]
14270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14272#[cfg_attr(
14273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14274 assert_instr(ld1)
14275)]
14276#[cfg_attr(
14277 not(target_arch = "arm"),
14278 stable(feature = "neon_intrinsics", since = "1.59.0")
14279)]
14280#[cfg_attr(
14281 target_arch = "arm",
14282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14283)]
14284pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
14285 let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
14286 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
14287 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
14288 ret_val
14289}
14290#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
14292#[doc = "## Safety"]
14293#[doc = " * Neon instrinsic unsafe"]
14294#[inline]
14295#[cfg(target_endian = "little")]
14296#[target_feature(enable = "neon")]
14297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14299#[cfg_attr(
14300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14301 assert_instr(ld1)
14302)]
14303#[cfg_attr(
14304 not(target_arch = "arm"),
14305 stable(feature = "neon_intrinsics", since = "1.59.0")
14306)]
14307#[cfg_attr(
14308 target_arch = "arm",
14309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14310)]
14311pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
14312 transmute(vld1q_s16_x3(transmute(a)))
14313}
14314#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
14316#[doc = "## Safety"]
14317#[doc = " * Neon instrinsic unsafe"]
14318#[inline]
14319#[cfg(target_endian = "big")]
14320#[target_feature(enable = "neon")]
14321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14323#[cfg_attr(
14324 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14325 assert_instr(ld1)
14326)]
14327#[cfg_attr(
14328 not(target_arch = "arm"),
14329 stable(feature = "neon_intrinsics", since = "1.59.0")
14330)]
14331#[cfg_attr(
14332 target_arch = "arm",
14333 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14334)]
14335pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
14336 let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
14337 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
14338 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
14339 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
14340 ret_val
14341}
14342#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
14344#[doc = "## Safety"]
14345#[doc = " * Neon instrinsic unsafe"]
14346#[inline]
14347#[cfg(target_endian = "little")]
14348#[target_feature(enable = "neon")]
14349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14351#[cfg_attr(
14352 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14353 assert_instr(ld1)
14354)]
14355#[cfg_attr(
14356 not(target_arch = "arm"),
14357 stable(feature = "neon_intrinsics", since = "1.59.0")
14358)]
14359#[cfg_attr(
14360 target_arch = "arm",
14361 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14362)]
14363pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
14364 transmute(vld1q_s16_x4(transmute(a)))
14365}
14366#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
14368#[doc = "## Safety"]
14369#[doc = " * Neon instrinsic unsafe"]
14370#[inline]
14371#[cfg(target_endian = "big")]
14372#[target_feature(enable = "neon")]
14373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14375#[cfg_attr(
14376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14377 assert_instr(ld1)
14378)]
14379#[cfg_attr(
14380 not(target_arch = "arm"),
14381 stable(feature = "neon_intrinsics", since = "1.59.0")
14382)]
14383#[cfg_attr(
14384 target_arch = "arm",
14385 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14386)]
14387pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
14388 let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
14389 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
14390 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
14391 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
14392 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
14393 ret_val
14394}
14395#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v1i64)"]
14397#[doc = "## Safety"]
14398#[doc = " * Neon instrinsic unsafe"]
14399#[inline]
14400#[cfg(target_arch = "arm")]
14401#[target_feature(enable = "neon,v7")]
14402#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14403unsafe fn vld1_v1i64(a: *const i8, b: i32) -> int64x1_t {
14404 unsafe extern "unadjusted" {
14405 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
14406 fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
14407 }
14408 _vld1_v1i64(a, b)
14409}
14410#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2f32)"]
14412#[doc = "## Safety"]
14413#[doc = " * Neon instrinsic unsafe"]
14414#[inline]
14415#[cfg(target_arch = "arm")]
14416#[target_feature(enable = "neon,v7")]
14417#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14418unsafe fn vld1_v2f32(a: *const i8, b: i32) -> float32x2_t {
14419 unsafe extern "unadjusted" {
14420 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")]
14421 fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t;
14422 }
14423 _vld1_v2f32(a, b)
14424}
14425#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2i32)"]
14427#[doc = "## Safety"]
14428#[doc = " * Neon instrinsic unsafe"]
14429#[inline]
14430#[cfg(target_arch = "arm")]
14431#[target_feature(enable = "neon,v7")]
14432#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14433unsafe fn vld1_v2i32(a: *const i8, b: i32) -> int32x2_t {
14434 unsafe extern "unadjusted" {
14435 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")]
14436 fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t;
14437 }
14438 _vld1_v2i32(a, b)
14439}
14440#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4i16)"]
14442#[doc = "## Safety"]
14443#[doc = " * Neon instrinsic unsafe"]
14444#[inline]
14445#[cfg(target_arch = "arm")]
14446#[target_feature(enable = "neon,v7")]
14447#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14448unsafe fn vld1_v4i16(a: *const i8, b: i32) -> int16x4_t {
14449 unsafe extern "unadjusted" {
14450 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")]
14451 fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t;
14452 }
14453 _vld1_v4i16(a, b)
14454}
14455#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v8i8)"]
14457#[doc = "## Safety"]
14458#[doc = " * Neon instrinsic unsafe"]
14459#[inline]
14460#[cfg(target_arch = "arm")]
14461#[target_feature(enable = "neon,v7")]
14462#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14463unsafe fn vld1_v8i8(a: *const i8, b: i32) -> int8x8_t {
14464 unsafe extern "unadjusted" {
14465 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")]
14466 fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t;
14467 }
14468 _vld1_v8i8(a, b)
14469}
14470#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v16i8)"]
14472#[doc = "## Safety"]
14473#[doc = " * Neon instrinsic unsafe"]
14474#[inline]
14475#[cfg(target_arch = "arm")]
14476#[target_feature(enable = "neon,v7")]
14477#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14478unsafe fn vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t {
14479 unsafe extern "unadjusted" {
14480 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")]
14481 fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t;
14482 }
14483 _vld1q_v16i8(a, b)
14484}
14485#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v2i64)"]
14487#[doc = "## Safety"]
14488#[doc = " * Neon instrinsic unsafe"]
14489#[inline]
14490#[cfg(target_arch = "arm")]
14491#[target_feature(enable = "neon,v7")]
14492#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14493unsafe fn vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t {
14494 unsafe extern "unadjusted" {
14495 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")]
14496 fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t;
14497 }
14498 _vld1q_v2i64(a, b)
14499}
14500#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4f32)"]
14502#[doc = "## Safety"]
14503#[doc = " * Neon instrinsic unsafe"]
14504#[inline]
14505#[cfg(target_arch = "arm")]
14506#[target_feature(enable = "neon,v7")]
14507#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14508unsafe fn vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t {
14509 unsafe extern "unadjusted" {
14510 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")]
14511 fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t;
14512 }
14513 _vld1q_v4f32(a, b)
14514}
14515#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4i32)"]
14517#[doc = "## Safety"]
14518#[doc = " * Neon instrinsic unsafe"]
14519#[inline]
14520#[cfg(target_arch = "arm")]
14521#[target_feature(enable = "neon,v7")]
14522#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14523unsafe fn vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t {
14524 unsafe extern "unadjusted" {
14525 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")]
14526 fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t;
14527 }
14528 _vld1q_v4i32(a, b)
14529}
14530#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8i16)"]
14532#[doc = "## Safety"]
14533#[doc = " * Neon instrinsic unsafe"]
14534#[inline]
14535#[cfg(target_arch = "arm")]
14536#[target_feature(enable = "neon,v7")]
14537#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14538unsafe fn vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t {
14539 unsafe extern "unadjusted" {
14540 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")]
14541 fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t;
14542 }
14543 _vld1q_v8i16(a, b)
14544}
14545#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4f16)"]
14547#[doc = "## Safety"]
14548#[doc = " * Neon instrinsic unsafe"]
14549#[inline]
14550#[cfg(target_arch = "arm")]
14551#[target_feature(enable = "neon,v7")]
14552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
14553#[target_feature(enable = "neon,fp16")]
14554#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14555unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
14556 unsafe extern "unadjusted" {
14557 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")]
14558 fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t;
14559 }
14560 _vld1_v4f16(a, b)
14561}
14562#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8f16)"]
14564#[doc = "## Safety"]
14565#[doc = " * Neon instrinsic unsafe"]
14566#[inline]
14567#[cfg(target_arch = "arm")]
14568#[target_feature(enable = "neon,v7")]
14569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
14570#[target_feature(enable = "neon,fp16")]
14571#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14572unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
14573 unsafe extern "unadjusted" {
14574 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")]
14575 fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t;
14576 }
14577 _vld1q_v8f16(a, b)
14578}
14579#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
14581#[doc = "## Safety"]
14582#[doc = " * Neon instrinsic unsafe"]
14583#[inline]
14584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14585#[cfg(target_arch = "arm")]
14586#[target_feature(enable = "neon,fp16")]
14587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
14588#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14589pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
14590 unsafe extern "unadjusted" {
14591 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0f16")]
14592 fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
14593 }
14594 _vld2_dup_f16(a as _, 2)
14595}
14596#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
14598#[doc = "## Safety"]
14599#[doc = " * Neon instrinsic unsafe"]
14600#[inline]
14601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14602#[cfg(target_arch = "arm")]
14603#[target_feature(enable = "neon,fp16")]
14604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
14605#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14606pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
14607 unsafe extern "unadjusted" {
14608 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0f16")]
14609 fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
14610 }
14611 _vld2q_dup_f16(a as _, 2)
14612}
14613#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
14615#[doc = "## Safety"]
14616#[doc = " * Neon instrinsic unsafe"]
14617#[inline]
14618#[cfg(not(target_arch = "arm"))]
14619#[cfg_attr(
14620 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14621 assert_instr(ld2r)
14622)]
14623#[target_feature(enable = "neon,fp16")]
14624#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14625pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
14626 unsafe extern "unadjusted" {
14627 #[cfg_attr(
14628 any(target_arch = "aarch64", target_arch = "arm64ec"),
14629 link_name = "llvm.aarch64.neon.ld2r.v4f16.p0f16"
14630 )]
14631 fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t;
14632 }
14633 _vld2_dup_f16(a as _)
14634}
14635#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
14637#[doc = "## Safety"]
14638#[doc = " * Neon instrinsic unsafe"]
14639#[inline]
14640#[cfg(not(target_arch = "arm"))]
14641#[cfg_attr(
14642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14643 assert_instr(ld2r)
14644)]
14645#[target_feature(enable = "neon,fp16")]
14646#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14647pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
14648 unsafe extern "unadjusted" {
14649 #[cfg_attr(
14650 any(target_arch = "aarch64", target_arch = "arm64ec"),
14651 link_name = "llvm.aarch64.neon.ld2r.v8f16.p0f16"
14652 )]
14653 fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t;
14654 }
14655 _vld2q_dup_f16(a as _)
14656}
14657#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
14659#[doc = "## Safety"]
14660#[doc = " * Neon instrinsic unsafe"]
14661#[inline]
14662#[target_feature(enable = "neon,v7")]
14663#[cfg(target_arch = "arm")]
14664#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14665#[cfg_attr(test, assert_instr(vld2))]
14666pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
14667 unsafe extern "unadjusted" {
14668 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")]
14669 fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
14670 }
14671 _vld2_dup_f32(a as *const i8, 4)
14672}
14673#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
14675#[doc = "## Safety"]
14676#[doc = " * Neon instrinsic unsafe"]
14677#[inline]
14678#[target_feature(enable = "neon,v7")]
14679#[cfg(target_arch = "arm")]
14680#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14681#[cfg_attr(test, assert_instr(vld2))]
14682pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
14683 unsafe extern "unadjusted" {
14684 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")]
14685 fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
14686 }
14687 _vld2q_dup_f32(a as *const i8, 4)
14688}
14689#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
14691#[doc = "## Safety"]
14692#[doc = " * Neon instrinsic unsafe"]
14693#[inline]
14694#[target_feature(enable = "neon,v7")]
14695#[cfg(target_arch = "arm")]
14696#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14697#[cfg_attr(test, assert_instr(vld2))]
14698pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
14699 unsafe extern "unadjusted" {
14700 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")]
14701 fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
14702 }
14703 _vld2_dup_s8(a as *const i8, 1)
14704}
14705#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
14707#[doc = "## Safety"]
14708#[doc = " * Neon instrinsic unsafe"]
14709#[inline]
14710#[target_feature(enable = "neon,v7")]
14711#[cfg(target_arch = "arm")]
14712#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14713#[cfg_attr(test, assert_instr(vld2))]
14714pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
14715 unsafe extern "unadjusted" {
14716 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")]
14717 fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
14718 }
14719 _vld2q_dup_s8(a as *const i8, 1)
14720}
14721#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
14723#[doc = "## Safety"]
14724#[doc = " * Neon instrinsic unsafe"]
14725#[inline]
14726#[target_feature(enable = "neon,v7")]
14727#[cfg(target_arch = "arm")]
14728#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14729#[cfg_attr(test, assert_instr(vld2))]
14730pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
14731 unsafe extern "unadjusted" {
14732 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")]
14733 fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
14734 }
14735 _vld2_dup_s16(a as *const i8, 2)
14736}
14737#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
14739#[doc = "## Safety"]
14740#[doc = " * Neon instrinsic unsafe"]
14741#[inline]
14742#[target_feature(enable = "neon,v7")]
14743#[cfg(target_arch = "arm")]
14744#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14745#[cfg_attr(test, assert_instr(vld2))]
14746pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
14747 unsafe extern "unadjusted" {
14748 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")]
14749 fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
14750 }
14751 _vld2q_dup_s16(a as *const i8, 2)
14752}
14753#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
14755#[doc = "## Safety"]
14756#[doc = " * Neon instrinsic unsafe"]
14757#[inline]
14758#[target_feature(enable = "neon,v7")]
14759#[cfg(target_arch = "arm")]
14760#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14761#[cfg_attr(test, assert_instr(vld2))]
14762pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
14763 unsafe extern "unadjusted" {
14764 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")]
14765 fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
14766 }
14767 _vld2_dup_s32(a as *const i8, 4)
14768}
14769#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
14771#[doc = "## Safety"]
14772#[doc = " * Neon instrinsic unsafe"]
14773#[inline]
14774#[target_feature(enable = "neon,v7")]
14775#[cfg(target_arch = "arm")]
14776#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14777#[cfg_attr(test, assert_instr(vld2))]
14778pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
14779 unsafe extern "unadjusted" {
14780 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")]
14781 fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
14782 }
14783 _vld2q_dup_s32(a as *const i8, 4)
14784}
14785#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
14787#[doc = "## Safety"]
14788#[doc = " * Neon instrinsic unsafe"]
14789#[inline]
14790#[target_feature(enable = "neon")]
14791#[cfg(not(target_arch = "arm"))]
14792#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14793#[cfg_attr(test, assert_instr(ld2r))]
14794pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
14795 unsafe extern "unadjusted" {
14796 #[cfg_attr(
14797 any(target_arch = "aarch64", target_arch = "arm64ec"),
14798 link_name = "llvm.aarch64.neon.ld2r.v2f32.p0"
14799 )]
14800 fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t;
14801 }
14802 _vld2_dup_f32(a as _)
14803}
14804#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
14806#[doc = "## Safety"]
14807#[doc = " * Neon instrinsic unsafe"]
14808#[inline]
14809#[target_feature(enable = "neon")]
14810#[cfg(not(target_arch = "arm"))]
14811#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14812#[cfg_attr(test, assert_instr(ld2r))]
14813pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
14814 unsafe extern "unadjusted" {
14815 #[cfg_attr(
14816 any(target_arch = "aarch64", target_arch = "arm64ec"),
14817 link_name = "llvm.aarch64.neon.ld2r.v4f32.p0"
14818 )]
14819 fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t;
14820 }
14821 _vld2q_dup_f32(a as _)
14822}
14823#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
14825#[doc = "## Safety"]
14826#[doc = " * Neon instrinsic unsafe"]
14827#[inline]
14828#[target_feature(enable = "neon")]
14829#[cfg(not(target_arch = "arm"))]
14830#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14831#[cfg_attr(test, assert_instr(ld2r))]
14832pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
14833 unsafe extern "unadjusted" {
14834 #[cfg_attr(
14835 any(target_arch = "aarch64", target_arch = "arm64ec"),
14836 link_name = "llvm.aarch64.neon.ld2r.v8i8.p0"
14837 )]
14838 fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t;
14839 }
14840 _vld2_dup_s8(a as _)
14841}
14842#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
14844#[doc = "## Safety"]
14845#[doc = " * Neon instrinsic unsafe"]
14846#[inline]
14847#[target_feature(enable = "neon")]
14848#[cfg(not(target_arch = "arm"))]
14849#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14850#[cfg_attr(test, assert_instr(ld2r))]
14851pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
14852 unsafe extern "unadjusted" {
14853 #[cfg_attr(
14854 any(target_arch = "aarch64", target_arch = "arm64ec"),
14855 link_name = "llvm.aarch64.neon.ld2r.v16i8.p0"
14856 )]
14857 fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t;
14858 }
14859 _vld2q_dup_s8(a as _)
14860}
14861#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
14863#[doc = "## Safety"]
14864#[doc = " * Neon instrinsic unsafe"]
14865#[inline]
14866#[target_feature(enable = "neon")]
14867#[cfg(not(target_arch = "arm"))]
14868#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14869#[cfg_attr(test, assert_instr(ld2r))]
14870pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
14871 unsafe extern "unadjusted" {
14872 #[cfg_attr(
14873 any(target_arch = "aarch64", target_arch = "arm64ec"),
14874 link_name = "llvm.aarch64.neon.ld2r.v4i16.p0"
14875 )]
14876 fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t;
14877 }
14878 _vld2_dup_s16(a as _)
14879}
14880#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
14882#[doc = "## Safety"]
14883#[doc = " * Neon instrinsic unsafe"]
14884#[inline]
14885#[target_feature(enable = "neon")]
14886#[cfg(not(target_arch = "arm"))]
14887#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14888#[cfg_attr(test, assert_instr(ld2r))]
14889pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
14890 unsafe extern "unadjusted" {
14891 #[cfg_attr(
14892 any(target_arch = "aarch64", target_arch = "arm64ec"),
14893 link_name = "llvm.aarch64.neon.ld2r.v8i16.p0"
14894 )]
14895 fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t;
14896 }
14897 _vld2q_dup_s16(a as _)
14898}
14899#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
14901#[doc = "## Safety"]
14902#[doc = " * Neon instrinsic unsafe"]
14903#[inline]
14904#[target_feature(enable = "neon")]
14905#[cfg(not(target_arch = "arm"))]
14906#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14907#[cfg_attr(test, assert_instr(ld2r))]
14908pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
14909 unsafe extern "unadjusted" {
14910 #[cfg_attr(
14911 any(target_arch = "aarch64", target_arch = "arm64ec"),
14912 link_name = "llvm.aarch64.neon.ld2r.v2i32.p0"
14913 )]
14914 fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t;
14915 }
14916 _vld2_dup_s32(a as _)
14917}
14918#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
14920#[doc = "## Safety"]
14921#[doc = " * Neon instrinsic unsafe"]
14922#[inline]
14923#[target_feature(enable = "neon")]
14924#[cfg(not(target_arch = "arm"))]
14925#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14926#[cfg_attr(test, assert_instr(ld2r))]
14927pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
14928 unsafe extern "unadjusted" {
14929 #[cfg_attr(
14930 any(target_arch = "aarch64", target_arch = "arm64ec"),
14931 link_name = "llvm.aarch64.neon.ld2r.v4i32.p0"
14932 )]
14933 fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t;
14934 }
14935 _vld2q_dup_s32(a as _)
14936}
14937#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
14939#[doc = "## Safety"]
14940#[doc = " * Neon instrinsic unsafe"]
14941#[inline]
14942#[target_feature(enable = "neon,aes")]
14943#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
14944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
14945#[cfg_attr(
14946 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14947 assert_instr(ld2r)
14948)]
14949#[cfg_attr(
14950 not(target_arch = "arm"),
14951 stable(feature = "neon_intrinsics", since = "1.59.0")
14952)]
14953#[cfg_attr(
14954 target_arch = "arm",
14955 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14956)]
14957pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
14958 transmute(vld2_dup_s64(transmute(a)))
14959}
14960#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
14962#[doc = "## Safety"]
14963#[doc = " * Neon instrinsic unsafe"]
14964#[inline]
14965#[target_feature(enable = "neon,v7")]
14966#[cfg(target_arch = "arm")]
14967#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
14968#[cfg_attr(test, assert_instr(nop))]
14969pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
14970 unsafe extern "unadjusted" {
14971 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")]
14972 fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
14973 }
14974 _vld2_dup_s64(a as *const i8, 8)
14975}
14976#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
14978#[doc = "## Safety"]
14979#[doc = " * Neon instrinsic unsafe"]
14980#[inline]
14981#[target_feature(enable = "neon")]
14982#[cfg(not(target_arch = "arm"))]
14983#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14984#[cfg_attr(test, assert_instr(ld2r))]
14985pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
14986 unsafe extern "unadjusted" {
14987 #[cfg_attr(
14988 any(target_arch = "aarch64", target_arch = "arm64ec"),
14989 link_name = "llvm.aarch64.neon.ld2r.v1i64.p0"
14990 )]
14991 fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t;
14992 }
14993 _vld2_dup_s64(a as _)
14994}
14995#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
14996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
14997#[doc = "## Safety"]
14998#[doc = " * Neon instrinsic unsafe"]
14999#[inline]
15000#[target_feature(enable = "neon")]
15001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15002#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
15003#[cfg_attr(
15004 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15005 assert_instr(ld2r)
15006)]
15007#[cfg_attr(
15008 not(target_arch = "arm"),
15009 stable(feature = "neon_intrinsics", since = "1.59.0")
15010)]
15011#[cfg_attr(
15012 target_arch = "arm",
15013 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15014)]
15015pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
15016 transmute(vld2_dup_s64(transmute(a)))
15017}
15018#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
15020#[doc = "## Safety"]
15021#[doc = " * Neon instrinsic unsafe"]
15022#[inline]
15023#[cfg(target_endian = "little")]
15024#[target_feature(enable = "neon")]
15025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15027#[cfg_attr(
15028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15029 assert_instr(ld2r)
15030)]
15031#[cfg_attr(
15032 not(target_arch = "arm"),
15033 stable(feature = "neon_intrinsics", since = "1.59.0")
15034)]
15035#[cfg_attr(
15036 target_arch = "arm",
15037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15038)]
15039pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
15040 transmute(vld2_dup_s8(transmute(a)))
15041}
15042#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
15044#[doc = "## Safety"]
15045#[doc = " * Neon instrinsic unsafe"]
15046#[inline]
15047#[cfg(target_endian = "big")]
15048#[target_feature(enable = "neon")]
15049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15051#[cfg_attr(
15052 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15053 assert_instr(ld2r)
15054)]
15055#[cfg_attr(
15056 not(target_arch = "arm"),
15057 stable(feature = "neon_intrinsics", since = "1.59.0")
15058)]
15059#[cfg_attr(
15060 target_arch = "arm",
15061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15062)]
15063pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
15064 let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
15065 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
15066 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
15067 ret_val
15068}
15069#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
15071#[doc = "## Safety"]
15072#[doc = " * Neon instrinsic unsafe"]
15073#[inline]
15074#[cfg(target_endian = "little")]
15075#[target_feature(enable = "neon")]
15076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15077#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15078#[cfg_attr(
15079 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15080 assert_instr(ld2r)
15081)]
15082#[cfg_attr(
15083 not(target_arch = "arm"),
15084 stable(feature = "neon_intrinsics", since = "1.59.0")
15085)]
15086#[cfg_attr(
15087 target_arch = "arm",
15088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15089)]
15090pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
15091 transmute(vld2q_dup_s8(transmute(a)))
15092}
15093#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
15095#[doc = "## Safety"]
15096#[doc = " * Neon instrinsic unsafe"]
15097#[inline]
15098#[cfg(target_endian = "big")]
15099#[target_feature(enable = "neon")]
15100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15102#[cfg_attr(
15103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15104 assert_instr(ld2r)
15105)]
15106#[cfg_attr(
15107 not(target_arch = "arm"),
15108 stable(feature = "neon_intrinsics", since = "1.59.0")
15109)]
15110#[cfg_attr(
15111 target_arch = "arm",
15112 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15113)]
15114pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
15115 let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
15116 ret_val.0 = unsafe {
15117 simd_shuffle!(
15118 ret_val.0,
15119 ret_val.0,
15120 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15121 )
15122 };
15123 ret_val.1 = unsafe {
15124 simd_shuffle!(
15125 ret_val.1,
15126 ret_val.1,
15127 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15128 )
15129 };
15130 ret_val
15131}
15132#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
15134#[doc = "## Safety"]
15135#[doc = " * Neon instrinsic unsafe"]
15136#[inline]
15137#[cfg(target_endian = "little")]
15138#[target_feature(enable = "neon")]
15139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15141#[cfg_attr(
15142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15143 assert_instr(ld2r)
15144)]
15145#[cfg_attr(
15146 not(target_arch = "arm"),
15147 stable(feature = "neon_intrinsics", since = "1.59.0")
15148)]
15149#[cfg_attr(
15150 target_arch = "arm",
15151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15152)]
15153pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
15154 transmute(vld2_dup_s16(transmute(a)))
15155}
15156#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
15158#[doc = "## Safety"]
15159#[doc = " * Neon instrinsic unsafe"]
15160#[inline]
15161#[cfg(target_endian = "big")]
15162#[target_feature(enable = "neon")]
15163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15165#[cfg_attr(
15166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15167 assert_instr(ld2r)
15168)]
15169#[cfg_attr(
15170 not(target_arch = "arm"),
15171 stable(feature = "neon_intrinsics", since = "1.59.0")
15172)]
15173#[cfg_attr(
15174 target_arch = "arm",
15175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15176)]
15177pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
15178 let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
15179 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
15180 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
15181 ret_val
15182}
15183#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
15185#[doc = "## Safety"]
15186#[doc = " * Neon instrinsic unsafe"]
15187#[inline]
15188#[cfg(target_endian = "little")]
15189#[target_feature(enable = "neon")]
15190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15192#[cfg_attr(
15193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15194 assert_instr(ld2r)
15195)]
15196#[cfg_attr(
15197 not(target_arch = "arm"),
15198 stable(feature = "neon_intrinsics", since = "1.59.0")
15199)]
15200#[cfg_attr(
15201 target_arch = "arm",
15202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15203)]
15204pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
15205 transmute(vld2q_dup_s16(transmute(a)))
15206}
15207#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
15209#[doc = "## Safety"]
15210#[doc = " * Neon instrinsic unsafe"]
15211#[inline]
15212#[cfg(target_endian = "big")]
15213#[target_feature(enable = "neon")]
15214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15216#[cfg_attr(
15217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15218 assert_instr(ld2r)
15219)]
15220#[cfg_attr(
15221 not(target_arch = "arm"),
15222 stable(feature = "neon_intrinsics", since = "1.59.0")
15223)]
15224#[cfg_attr(
15225 target_arch = "arm",
15226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15227)]
15228pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
15229 let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
15230 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
15231 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
15232 ret_val
15233}
15234#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
15236#[doc = "## Safety"]
15237#[doc = " * Neon instrinsic unsafe"]
15238#[inline]
15239#[cfg(target_endian = "little")]
15240#[target_feature(enable = "neon")]
15241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15243#[cfg_attr(
15244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15245 assert_instr(ld2r)
15246)]
15247#[cfg_attr(
15248 not(target_arch = "arm"),
15249 stable(feature = "neon_intrinsics", since = "1.59.0")
15250)]
15251#[cfg_attr(
15252 target_arch = "arm",
15253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15254)]
15255pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
15256 transmute(vld2_dup_s32(transmute(a)))
15257}
15258#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
15260#[doc = "## Safety"]
15261#[doc = " * Neon instrinsic unsafe"]
15262#[inline]
15263#[cfg(target_endian = "big")]
15264#[target_feature(enable = "neon")]
15265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15267#[cfg_attr(
15268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15269 assert_instr(ld2r)
15270)]
15271#[cfg_attr(
15272 not(target_arch = "arm"),
15273 stable(feature = "neon_intrinsics", since = "1.59.0")
15274)]
15275#[cfg_attr(
15276 target_arch = "arm",
15277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15278)]
15279pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
15280 let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
15281 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
15282 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
15283 ret_val
15284}
15285#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
15287#[doc = "## Safety"]
15288#[doc = " * Neon instrinsic unsafe"]
15289#[inline]
15290#[cfg(target_endian = "little")]
15291#[target_feature(enable = "neon")]
15292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15294#[cfg_attr(
15295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15296 assert_instr(ld2r)
15297)]
15298#[cfg_attr(
15299 not(target_arch = "arm"),
15300 stable(feature = "neon_intrinsics", since = "1.59.0")
15301)]
15302#[cfg_attr(
15303 target_arch = "arm",
15304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15305)]
15306pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
15307 transmute(vld2q_dup_s32(transmute(a)))
15308}
15309#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
15311#[doc = "## Safety"]
15312#[doc = " * Neon instrinsic unsafe"]
15313#[inline]
15314#[cfg(target_endian = "big")]
15315#[target_feature(enable = "neon")]
15316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15318#[cfg_attr(
15319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15320 assert_instr(ld2r)
15321)]
15322#[cfg_attr(
15323 not(target_arch = "arm"),
15324 stable(feature = "neon_intrinsics", since = "1.59.0")
15325)]
15326#[cfg_attr(
15327 target_arch = "arm",
15328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15329)]
15330pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
15331 let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
15332 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
15333 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
15334 ret_val
15335}
15336#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
15338#[doc = "## Safety"]
15339#[doc = " * Neon instrinsic unsafe"]
15340#[inline]
15341#[cfg(target_endian = "little")]
15342#[target_feature(enable = "neon")]
15343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15345#[cfg_attr(
15346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15347 assert_instr(ld2r)
15348)]
15349#[cfg_attr(
15350 not(target_arch = "arm"),
15351 stable(feature = "neon_intrinsics", since = "1.59.0")
15352)]
15353#[cfg_attr(
15354 target_arch = "arm",
15355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15356)]
15357pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
15358 transmute(vld2_dup_s8(transmute(a)))
15359}
15360#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
15362#[doc = "## Safety"]
15363#[doc = " * Neon instrinsic unsafe"]
15364#[inline]
15365#[cfg(target_endian = "big")]
15366#[target_feature(enable = "neon")]
15367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15369#[cfg_attr(
15370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15371 assert_instr(ld2r)
15372)]
15373#[cfg_attr(
15374 not(target_arch = "arm"),
15375 stable(feature = "neon_intrinsics", since = "1.59.0")
15376)]
15377#[cfg_attr(
15378 target_arch = "arm",
15379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15380)]
15381pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
15382 let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
15383 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
15384 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
15385 ret_val
15386}
15387#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
15389#[doc = "## Safety"]
15390#[doc = " * Neon instrinsic unsafe"]
15391#[inline]
15392#[cfg(target_endian = "little")]
15393#[target_feature(enable = "neon")]
15394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15396#[cfg_attr(
15397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15398 assert_instr(ld2r)
15399)]
15400#[cfg_attr(
15401 not(target_arch = "arm"),
15402 stable(feature = "neon_intrinsics", since = "1.59.0")
15403)]
15404#[cfg_attr(
15405 target_arch = "arm",
15406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15407)]
15408pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
15409 transmute(vld2q_dup_s8(transmute(a)))
15410}
15411#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
15413#[doc = "## Safety"]
15414#[doc = " * Neon instrinsic unsafe"]
15415#[inline]
15416#[cfg(target_endian = "big")]
15417#[target_feature(enable = "neon")]
15418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15419#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15420#[cfg_attr(
15421 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15422 assert_instr(ld2r)
15423)]
15424#[cfg_attr(
15425 not(target_arch = "arm"),
15426 stable(feature = "neon_intrinsics", since = "1.59.0")
15427)]
15428#[cfg_attr(
15429 target_arch = "arm",
15430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15431)]
15432pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
15433 let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
15434 ret_val.0 = unsafe {
15435 simd_shuffle!(
15436 ret_val.0,
15437 ret_val.0,
15438 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15439 )
15440 };
15441 ret_val.1 = unsafe {
15442 simd_shuffle!(
15443 ret_val.1,
15444 ret_val.1,
15445 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15446 )
15447 };
15448 ret_val
15449}
15450#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
15452#[doc = "## Safety"]
15453#[doc = " * Neon instrinsic unsafe"]
15454#[inline]
15455#[cfg(target_endian = "little")]
15456#[target_feature(enable = "neon")]
15457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15459#[cfg_attr(
15460 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15461 assert_instr(ld2r)
15462)]
15463#[cfg_attr(
15464 not(target_arch = "arm"),
15465 stable(feature = "neon_intrinsics", since = "1.59.0")
15466)]
15467#[cfg_attr(
15468 target_arch = "arm",
15469 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15470)]
15471pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
15472 transmute(vld2_dup_s16(transmute(a)))
15473}
15474#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
15476#[doc = "## Safety"]
15477#[doc = " * Neon instrinsic unsafe"]
15478#[inline]
15479#[cfg(target_endian = "big")]
15480#[target_feature(enable = "neon")]
15481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15483#[cfg_attr(
15484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15485 assert_instr(ld2r)
15486)]
15487#[cfg_attr(
15488 not(target_arch = "arm"),
15489 stable(feature = "neon_intrinsics", since = "1.59.0")
15490)]
15491#[cfg_attr(
15492 target_arch = "arm",
15493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15494)]
15495pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
15496 let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
15497 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
15498 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
15499 ret_val
15500}
15501#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
15503#[doc = "## Safety"]
15504#[doc = " * Neon instrinsic unsafe"]
15505#[inline]
15506#[cfg(target_endian = "little")]
15507#[target_feature(enable = "neon")]
15508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15510#[cfg_attr(
15511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15512 assert_instr(ld2r)
15513)]
15514#[cfg_attr(
15515 not(target_arch = "arm"),
15516 stable(feature = "neon_intrinsics", since = "1.59.0")
15517)]
15518#[cfg_attr(
15519 target_arch = "arm",
15520 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15521)]
15522pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
15523 transmute(vld2q_dup_s16(transmute(a)))
15524}
15525#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
15527#[doc = "## Safety"]
15528#[doc = " * Neon instrinsic unsafe"]
15529#[inline]
15530#[cfg(target_endian = "big")]
15531#[target_feature(enable = "neon")]
15532#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15534#[cfg_attr(
15535 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15536 assert_instr(ld2r)
15537)]
15538#[cfg_attr(
15539 not(target_arch = "arm"),
15540 stable(feature = "neon_intrinsics", since = "1.59.0")
15541)]
15542#[cfg_attr(
15543 target_arch = "arm",
15544 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15545)]
15546pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
15547 let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
15548 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
15549 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
15550 ret_val
15551}
15552#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
15554#[doc = "## Safety"]
15555#[doc = " * Neon instrinsic unsafe"]
15556#[inline]
15557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15558#[cfg(target_arch = "arm")]
15559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15560#[target_feature(enable = "neon,fp16")]
15561#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15562pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
15563 unsafe extern "unadjusted" {
15564 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0f16")]
15565 fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
15566 }
15567 _vld2_f16(a as _, 2)
15568}
15569#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
15571#[doc = "## Safety"]
15572#[doc = " * Neon instrinsic unsafe"]
15573#[inline]
15574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15575#[cfg(target_arch = "arm")]
15576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
15577#[target_feature(enable = "neon,fp16")]
15578#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15579pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
15580 unsafe extern "unadjusted" {
15581 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0f16")]
15582 fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
15583 }
15584 _vld2q_f16(a as _, 2)
15585}
15586#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
15588#[doc = "## Safety"]
15589#[doc = " * Neon instrinsic unsafe"]
15590#[inline]
15591#[cfg(not(target_arch = "arm"))]
15592#[cfg_attr(
15593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15594 assert_instr(ld2)
15595)]
15596#[target_feature(enable = "neon,fp16")]
15597#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15598pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
15599 unsafe extern "unadjusted" {
15600 #[cfg_attr(
15601 any(target_arch = "aarch64", target_arch = "arm64ec"),
15602 link_name = "llvm.aarch64.neon.ld2.v4f16.p0f16"
15603 )]
15604 fn _vld2_f16(ptr: *const f16) -> float16x4x2_t;
15605 }
15606 _vld2_f16(a as _)
15607}
15608#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
15609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
15610#[doc = "## Safety"]
15611#[doc = " * Neon instrinsic unsafe"]
15612#[inline]
15613#[cfg(not(target_arch = "arm"))]
15614#[cfg_attr(
15615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15616 assert_instr(ld2)
15617)]
15618#[target_feature(enable = "neon,fp16")]
15619#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15620pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
15621 unsafe extern "unadjusted" {
15622 #[cfg_attr(
15623 any(target_arch = "aarch64", target_arch = "arm64ec"),
15624 link_name = "llvm.aarch64.neon.ld2.v8f16.p0f16"
15625 )]
15626 fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t;
15627 }
15628 _vld2q_f16(a as _)
15629}
15630#[doc = "Load multiple 2-element structures to two registers"]
15631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
15632#[doc = "## Safety"]
15633#[doc = " * Neon instrinsic unsafe"]
15634#[inline]
15635#[target_feature(enable = "neon,v7")]
15636#[cfg(target_arch = "arm")]
15637#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15638#[cfg_attr(test, assert_instr(vld2))]
15639pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
15640 unsafe extern "unadjusted" {
15641 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")]
15642 fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
15643 }
15644 _vld2_f32(a as *const i8, 4)
15645}
15646#[doc = "Load multiple 2-element structures to two registers"]
15647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
15648#[doc = "## Safety"]
15649#[doc = " * Neon instrinsic unsafe"]
15650#[inline]
15651#[target_feature(enable = "neon,v7")]
15652#[cfg(target_arch = "arm")]
15653#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15654#[cfg_attr(test, assert_instr(vld2))]
15655pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
15656 unsafe extern "unadjusted" {
15657 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")]
15658 fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
15659 }
15660 _vld2q_f32(a as *const i8, 4)
15661}
15662#[doc = "Load multiple 2-element structures to two registers"]
15663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
15664#[doc = "## Safety"]
15665#[doc = " * Neon instrinsic unsafe"]
15666#[inline]
15667#[target_feature(enable = "neon,v7")]
15668#[cfg(target_arch = "arm")]
15669#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15670#[cfg_attr(test, assert_instr(vld2))]
15671pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
15672 unsafe extern "unadjusted" {
15673 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")]
15674 fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
15675 }
15676 _vld2_s8(a as *const i8, 1)
15677}
15678#[doc = "Load multiple 2-element structures to two registers"]
15679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
15680#[doc = "## Safety"]
15681#[doc = " * Neon instrinsic unsafe"]
15682#[inline]
15683#[target_feature(enable = "neon,v7")]
15684#[cfg(target_arch = "arm")]
15685#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15686#[cfg_attr(test, assert_instr(vld2))]
15687pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
15688 unsafe extern "unadjusted" {
15689 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")]
15690 fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
15691 }
15692 _vld2q_s8(a as *const i8, 1)
15693}
15694#[doc = "Load multiple 2-element structures to two registers"]
15695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
15696#[doc = "## Safety"]
15697#[doc = " * Neon instrinsic unsafe"]
15698#[inline]
15699#[target_feature(enable = "neon,v7")]
15700#[cfg(target_arch = "arm")]
15701#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15702#[cfg_attr(test, assert_instr(vld2))]
15703pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
15704 unsafe extern "unadjusted" {
15705 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")]
15706 fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
15707 }
15708 _vld2_s16(a as *const i8, 2)
15709}
15710#[doc = "Load multiple 2-element structures to two registers"]
15711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
15712#[doc = "## Safety"]
15713#[doc = " * Neon instrinsic unsafe"]
15714#[inline]
15715#[target_feature(enable = "neon,v7")]
15716#[cfg(target_arch = "arm")]
15717#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15718#[cfg_attr(test, assert_instr(vld2))]
15719pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
15720 unsafe extern "unadjusted" {
15721 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")]
15722 fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
15723 }
15724 _vld2q_s16(a as *const i8, 2)
15725}
15726#[doc = "Load multiple 2-element structures to two registers"]
15727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
15728#[doc = "## Safety"]
15729#[doc = " * Neon instrinsic unsafe"]
15730#[inline]
15731#[target_feature(enable = "neon,v7")]
15732#[cfg(target_arch = "arm")]
15733#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15734#[cfg_attr(test, assert_instr(vld2))]
15735pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
15736 unsafe extern "unadjusted" {
15737 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")]
15738 fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
15739 }
15740 _vld2_s32(a as *const i8, 4)
15741}
15742#[doc = "Load multiple 2-element structures to two registers"]
15743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
15744#[doc = "## Safety"]
15745#[doc = " * Neon instrinsic unsafe"]
15746#[inline]
15747#[target_feature(enable = "neon,v7")]
15748#[cfg(target_arch = "arm")]
15749#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15750#[cfg_attr(test, assert_instr(vld2))]
15751pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
15752 unsafe extern "unadjusted" {
15753 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")]
15754 fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
15755 }
15756 _vld2q_s32(a as *const i8, 4)
15757}
15758#[doc = "Load multiple 2-element structures to two registers"]
15759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
15760#[doc = "## Safety"]
15761#[doc = " * Neon instrinsic unsafe"]
15762#[inline]
15763#[target_feature(enable = "neon")]
15764#[cfg(not(target_arch = "arm"))]
15765#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15766#[cfg_attr(test, assert_instr(ld2))]
15767pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
15768 unsafe extern "unadjusted" {
15769 #[cfg_attr(
15770 any(target_arch = "aarch64", target_arch = "arm64ec"),
15771 link_name = "llvm.aarch64.neon.ld2.v2f32.p0"
15772 )]
15773 fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t;
15774 }
15775 _vld2_f32(a as _)
15776}
15777#[doc = "Load multiple 2-element structures to two registers"]
15778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
15779#[doc = "## Safety"]
15780#[doc = " * Neon instrinsic unsafe"]
15781#[inline]
15782#[target_feature(enable = "neon")]
15783#[cfg(not(target_arch = "arm"))]
15784#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15785#[cfg_attr(test, assert_instr(ld2))]
15786pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
15787 unsafe extern "unadjusted" {
15788 #[cfg_attr(
15789 any(target_arch = "aarch64", target_arch = "arm64ec"),
15790 link_name = "llvm.aarch64.neon.ld2.v4f32.p0"
15791 )]
15792 fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t;
15793 }
15794 _vld2q_f32(a as _)
15795}
15796#[doc = "Load multiple 2-element structures to two registers"]
15797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
15798#[doc = "## Safety"]
15799#[doc = " * Neon instrinsic unsafe"]
15800#[inline]
15801#[target_feature(enable = "neon")]
15802#[cfg(not(target_arch = "arm"))]
15803#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15804#[cfg_attr(test, assert_instr(ld2))]
15805pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
15806 unsafe extern "unadjusted" {
15807 #[cfg_attr(
15808 any(target_arch = "aarch64", target_arch = "arm64ec"),
15809 link_name = "llvm.aarch64.neon.ld2.v8i8.p0"
15810 )]
15811 fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t;
15812 }
15813 _vld2_s8(a as _)
15814}
15815#[doc = "Load multiple 2-element structures to two registers"]
15816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
15817#[doc = "## Safety"]
15818#[doc = " * Neon instrinsic unsafe"]
15819#[inline]
15820#[target_feature(enable = "neon")]
15821#[cfg(not(target_arch = "arm"))]
15822#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15823#[cfg_attr(test, assert_instr(ld2))]
15824pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
15825 unsafe extern "unadjusted" {
15826 #[cfg_attr(
15827 any(target_arch = "aarch64", target_arch = "arm64ec"),
15828 link_name = "llvm.aarch64.neon.ld2.v16i8.p0"
15829 )]
15830 fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t;
15831 }
15832 _vld2q_s8(a as _)
15833}
15834#[doc = "Load multiple 2-element structures to two registers"]
15835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
15836#[doc = "## Safety"]
15837#[doc = " * Neon instrinsic unsafe"]
15838#[inline]
15839#[target_feature(enable = "neon")]
15840#[cfg(not(target_arch = "arm"))]
15841#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15842#[cfg_attr(test, assert_instr(ld2))]
15843pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
15844 unsafe extern "unadjusted" {
15845 #[cfg_attr(
15846 any(target_arch = "aarch64", target_arch = "arm64ec"),
15847 link_name = "llvm.aarch64.neon.ld2.v4i16.p0"
15848 )]
15849 fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t;
15850 }
15851 _vld2_s16(a as _)
15852}
15853#[doc = "Load multiple 2-element structures to two registers"]
15854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
15855#[doc = "## Safety"]
15856#[doc = " * Neon instrinsic unsafe"]
15857#[inline]
15858#[target_feature(enable = "neon")]
15859#[cfg(not(target_arch = "arm"))]
15860#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15861#[cfg_attr(test, assert_instr(ld2))]
15862pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
15863 unsafe extern "unadjusted" {
15864 #[cfg_attr(
15865 any(target_arch = "aarch64", target_arch = "arm64ec"),
15866 link_name = "llvm.aarch64.neon.ld2.v8i16.p0"
15867 )]
15868 fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t;
15869 }
15870 _vld2q_s16(a as _)
15871}
15872#[doc = "Load multiple 2-element structures to two registers"]
15873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
15874#[doc = "## Safety"]
15875#[doc = " * Neon instrinsic unsafe"]
15876#[inline]
15877#[target_feature(enable = "neon")]
15878#[cfg(not(target_arch = "arm"))]
15879#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15880#[cfg_attr(test, assert_instr(ld2))]
15881pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
15882 unsafe extern "unadjusted" {
15883 #[cfg_attr(
15884 any(target_arch = "aarch64", target_arch = "arm64ec"),
15885 link_name = "llvm.aarch64.neon.ld2.v2i32.p0"
15886 )]
15887 fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t;
15888 }
15889 _vld2_s32(a as _)
15890}
15891#[doc = "Load multiple 2-element structures to two registers"]
15892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
15893#[doc = "## Safety"]
15894#[doc = " * Neon instrinsic unsafe"]
15895#[inline]
15896#[target_feature(enable = "neon")]
15897#[cfg(not(target_arch = "arm"))]
15898#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15899#[cfg_attr(test, assert_instr(ld2))]
15900pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
15901 unsafe extern "unadjusted" {
15902 #[cfg_attr(
15903 any(target_arch = "aarch64", target_arch = "arm64ec"),
15904 link_name = "llvm.aarch64.neon.ld2.v4i32.p0"
15905 )]
15906 fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t;
15907 }
15908 _vld2q_s32(a as _)
15909}
15910#[doc = "Load multiple 2-element structures to two registers"]
15911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
15912#[doc = "## Safety"]
15913#[doc = " * Neon instrinsic unsafe"]
15914#[inline]
15915#[target_feature(enable = "neon,v7")]
15916#[cfg(target_arch = "arm")]
15917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
15918#[rustc_legacy_const_generics(2)]
15919#[target_feature(enable = "neon,fp16")]
15920#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15921pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
15922 static_assert_uimm_bits!(LANE, 2);
15923 unsafe extern "unadjusted" {
15924 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")]
15925 fn _vld2_lane_f16(
15926 ptr: *const f16,
15927 a: float16x4_t,
15928 b: float16x4_t,
15929 n: i32,
15930 size: i32,
15931 ) -> float16x4x2_t;
15932 }
15933 _vld2_lane_f16(a as _, b.0, b.1, LANE, 2)
15934}
15935#[doc = "Load multiple 2-element structures to two registers"]
15936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
15937#[doc = "## Safety"]
15938#[doc = " * Neon instrinsic unsafe"]
15939#[inline]
15940#[target_feature(enable = "neon,v7")]
15941#[cfg(target_arch = "arm")]
15942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
15943#[rustc_legacy_const_generics(2)]
15944#[target_feature(enable = "neon,fp16")]
15945#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15946pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
15947 static_assert_uimm_bits!(LANE, 3);
15948 unsafe extern "unadjusted" {
15949 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")]
15950 fn _vld2q_lane_f16(
15951 ptr: *const f16,
15952 a: float16x8_t,
15953 b: float16x8_t,
15954 n: i32,
15955 size: i32,
15956 ) -> float16x8x2_t;
15957 }
15958 _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2)
15959}
15960#[doc = "Load multiple 2-element structures to two registers"]
15961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
15962#[doc = "## Safety"]
15963#[doc = " * Neon instrinsic unsafe"]
15964#[inline]
15965#[cfg(not(target_arch = "arm"))]
15966#[cfg_attr(
15967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15968 assert_instr(ld2, LANE = 0)
15969)]
15970#[rustc_legacy_const_generics(2)]
15971#[target_feature(enable = "neon,fp16")]
15972#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15973pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
15974 static_assert_uimm_bits!(LANE, 2);
15975 unsafe extern "unadjusted" {
15976 #[cfg_attr(
15977 any(target_arch = "aarch64", target_arch = "arm64ec"),
15978 link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0"
15979 )]
15980 fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16)
15981 -> float16x4x2_t;
15982 }
15983 _vld2_lane_f16(b.0, b.1, LANE as i64, a as _)
15984}
15985#[doc = "Load multiple 2-element structures to two registers"]
15986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
15987#[doc = "## Safety"]
15988#[doc = " * Neon instrinsic unsafe"]
15989#[inline]
15990#[cfg(not(target_arch = "arm"))]
15991#[cfg_attr(
15992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15993 assert_instr(ld2, LANE = 0)
15994)]
15995#[rustc_legacy_const_generics(2)]
15996#[target_feature(enable = "neon,fp16")]
15997#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15998pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
15999 static_assert_uimm_bits!(LANE, 3);
16000 unsafe extern "unadjusted" {
16001 #[cfg_attr(
16002 any(target_arch = "aarch64", target_arch = "arm64ec"),
16003 link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0"
16004 )]
16005 fn _vld2q_lane_f16(
16006 a: float16x8_t,
16007 b: float16x8_t,
16008 n: i64,
16009 ptr: *const f16,
16010 ) -> float16x8x2_t;
16011 }
16012 _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _)
16013}
16014#[doc = "Load multiple 2-element structures to two registers"]
16015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
16016#[doc = "## Safety"]
16017#[doc = " * Neon instrinsic unsafe"]
16018#[inline]
16019#[target_feature(enable = "neon")]
16020#[cfg(not(target_arch = "arm"))]
16021#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16022#[rustc_legacy_const_generics(2)]
16023#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16024pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
16025 static_assert_uimm_bits!(LANE, 2);
16026 unsafe extern "unadjusted" {
16027 #[cfg_attr(
16028 any(target_arch = "aarch64", target_arch = "arm64ec"),
16029 link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0"
16030 )]
16031 fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t;
16032 }
16033 _vld2_lane_f32(b.0, b.1, LANE as i64, a as _)
16034}
16035#[doc = "Load multiple 2-element structures to two registers"]
16036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
16037#[doc = "## Safety"]
16038#[doc = " * Neon instrinsic unsafe"]
16039#[inline]
16040#[target_feature(enable = "neon")]
16041#[cfg(not(target_arch = "arm"))]
16042#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16043#[rustc_legacy_const_generics(2)]
16044#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16045pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
16046 static_assert_uimm_bits!(LANE, 2);
16047 unsafe extern "unadjusted" {
16048 #[cfg_attr(
16049 any(target_arch = "aarch64", target_arch = "arm64ec"),
16050 link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0"
16051 )]
16052 fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8)
16053 -> float32x4x2_t;
16054 }
16055 _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _)
16056}
16057#[doc = "Load multiple 2-element structures to two registers"]
16058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
16059#[doc = "## Safety"]
16060#[doc = " * Neon instrinsic unsafe"]
16061#[inline]
16062#[target_feature(enable = "neon")]
16063#[cfg(not(target_arch = "arm"))]
16064#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16065#[rustc_legacy_const_generics(2)]
16066#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16067pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
16068 static_assert_uimm_bits!(LANE, 3);
16069 unsafe extern "unadjusted" {
16070 #[cfg_attr(
16071 any(target_arch = "aarch64", target_arch = "arm64ec"),
16072 link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0"
16073 )]
16074 fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t;
16075 }
16076 _vld2_lane_s8(b.0, b.1, LANE as i64, a as _)
16077}
16078#[doc = "Load multiple 2-element structures to two registers"]
16079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
16080#[doc = "## Safety"]
16081#[doc = " * Neon instrinsic unsafe"]
16082#[inline]
16083#[target_feature(enable = "neon")]
16084#[cfg(not(target_arch = "arm"))]
16085#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16086#[rustc_legacy_const_generics(2)]
16087#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16088pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
16089 static_assert_uimm_bits!(LANE, 2);
16090 unsafe extern "unadjusted" {
16091 #[cfg_attr(
16092 any(target_arch = "aarch64", target_arch = "arm64ec"),
16093 link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0"
16094 )]
16095 fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t;
16096 }
16097 _vld2_lane_s16(b.0, b.1, LANE as i64, a as _)
16098}
16099#[doc = "Load multiple 2-element structures to two registers"]
16100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
16101#[doc = "## Safety"]
16102#[doc = " * Neon instrinsic unsafe"]
16103#[inline]
16104#[target_feature(enable = "neon")]
16105#[cfg(not(target_arch = "arm"))]
16106#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16107#[rustc_legacy_const_generics(2)]
16108#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16109pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
16110 static_assert_uimm_bits!(LANE, 3);
16111 unsafe extern "unadjusted" {
16112 #[cfg_attr(
16113 any(target_arch = "aarch64", target_arch = "arm64ec"),
16114 link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0"
16115 )]
16116 fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t;
16117 }
16118 _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _)
16119}
16120#[doc = "Load multiple 2-element structures to two registers"]
16121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
16122#[doc = "## Safety"]
16123#[doc = " * Neon instrinsic unsafe"]
16124#[inline]
16125#[target_feature(enable = "neon")]
16126#[cfg(not(target_arch = "arm"))]
16127#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16128#[rustc_legacy_const_generics(2)]
16129#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16130pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
16131 static_assert_uimm_bits!(LANE, 1);
16132 unsafe extern "unadjusted" {
16133 #[cfg_attr(
16134 any(target_arch = "aarch64", target_arch = "arm64ec"),
16135 link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0"
16136 )]
16137 fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t;
16138 }
16139 _vld2_lane_s32(b.0, b.1, LANE as i64, a as _)
16140}
16141#[doc = "Load multiple 2-element structures to two registers"]
16142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
16143#[doc = "## Safety"]
16144#[doc = " * Neon instrinsic unsafe"]
16145#[inline]
16146#[target_feature(enable = "neon")]
16147#[cfg(not(target_arch = "arm"))]
16148#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
16149#[rustc_legacy_const_generics(2)]
16150#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16151pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
16152 static_assert_uimm_bits!(LANE, 2);
16153 unsafe extern "unadjusted" {
16154 #[cfg_attr(
16155 any(target_arch = "aarch64", target_arch = "arm64ec"),
16156 link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0"
16157 )]
16158 fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t;
16159 }
16160 _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _)
16161}
16162#[doc = "Load multiple 2-element structures to two registers"]
16163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
16164#[doc = "## Safety"]
16165#[doc = " * Neon instrinsic unsafe"]
16166#[inline]
16167#[target_feature(enable = "neon,v7")]
16168#[cfg(target_arch = "arm")]
16169#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16170#[rustc_legacy_const_generics(2)]
16171#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16172pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
16173 static_assert_uimm_bits!(LANE, 1);
16174 unsafe extern "unadjusted" {
16175 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")]
16176 fn _vld2_lane_f32(
16177 ptr: *const i8,
16178 a: float32x2_t,
16179 b: float32x2_t,
16180 n: i32,
16181 size: i32,
16182 ) -> float32x2x2_t;
16183 }
16184 _vld2_lane_f32(a as _, b.0, b.1, LANE, 4)
16185}
16186#[doc = "Load multiple 2-element structures to two registers"]
16187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
16188#[doc = "## Safety"]
16189#[doc = " * Neon instrinsic unsafe"]
16190#[inline]
16191#[target_feature(enable = "neon,v7")]
16192#[cfg(target_arch = "arm")]
16193#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16194#[rustc_legacy_const_generics(2)]
16195#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16196pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
16197 static_assert_uimm_bits!(LANE, 2);
16198 unsafe extern "unadjusted" {
16199 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")]
16200 fn _vld2q_lane_f32(
16201 ptr: *const i8,
16202 a: float32x4_t,
16203 b: float32x4_t,
16204 n: i32,
16205 size: i32,
16206 ) -> float32x4x2_t;
16207 }
16208 _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4)
16209}
16210#[doc = "Load multiple 2-element structures to two registers"]
16211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
16212#[doc = "## Safety"]
16213#[doc = " * Neon instrinsic unsafe"]
16214#[inline]
16215#[target_feature(enable = "neon,v7")]
16216#[cfg(target_arch = "arm")]
16217#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16218#[rustc_legacy_const_generics(2)]
16219#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16220pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
16221 static_assert_uimm_bits!(LANE, 3);
16222 unsafe extern "unadjusted" {
16223 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")]
16224 fn _vld2q_lane_s16(
16225 ptr: *const i8,
16226 a: int16x8_t,
16227 b: int16x8_t,
16228 n: i32,
16229 size: i32,
16230 ) -> int16x8x2_t;
16231 }
16232 _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2)
16233}
16234#[doc = "Load multiple 2-element structures to two registers"]
16235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
16236#[doc = "## Safety"]
16237#[doc = " * Neon instrinsic unsafe"]
16238#[inline]
16239#[target_feature(enable = "neon,v7")]
16240#[cfg(target_arch = "arm")]
16241#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16242#[rustc_legacy_const_generics(2)]
16243#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16244pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
16245 static_assert_uimm_bits!(LANE, 2);
16246 unsafe extern "unadjusted" {
16247 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")]
16248 fn _vld2q_lane_s32(
16249 ptr: *const i8,
16250 a: int32x4_t,
16251 b: int32x4_t,
16252 n: i32,
16253 size: i32,
16254 ) -> int32x4x2_t;
16255 }
16256 _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4)
16257}
16258#[doc = "Load multiple 2-element structures to two registers"]
16259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
16260#[doc = "## Safety"]
16261#[doc = " * Neon instrinsic unsafe"]
16262#[inline]
16263#[target_feature(enable = "neon,v7")]
16264#[cfg(target_arch = "arm")]
16265#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16266#[rustc_legacy_const_generics(2)]
16267#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16268pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
16269 static_assert_uimm_bits!(LANE, 3);
16270 unsafe extern "unadjusted" {
16271 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")]
16272 fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32)
16273 -> int8x8x2_t;
16274 }
16275 _vld2_lane_s8(a as _, b.0, b.1, LANE, 1)
16276}
16277#[doc = "Load multiple 2-element structures to two registers"]
16278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
16279#[doc = "## Safety"]
16280#[doc = " * Neon instrinsic unsafe"]
16281#[inline]
16282#[target_feature(enable = "neon,v7")]
16283#[cfg(target_arch = "arm")]
16284#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16285#[rustc_legacy_const_generics(2)]
16286#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16287pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
16288 static_assert_uimm_bits!(LANE, 2);
16289 unsafe extern "unadjusted" {
16290 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")]
16291 fn _vld2_lane_s16(
16292 ptr: *const i8,
16293 a: int16x4_t,
16294 b: int16x4_t,
16295 n: i32,
16296 size: i32,
16297 ) -> int16x4x2_t;
16298 }
16299 _vld2_lane_s16(a as _, b.0, b.1, LANE, 2)
16300}
16301#[doc = "Load multiple 2-element structures to two registers"]
16302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
16303#[doc = "## Safety"]
16304#[doc = " * Neon instrinsic unsafe"]
16305#[inline]
16306#[target_feature(enable = "neon,v7")]
16307#[cfg(target_arch = "arm")]
16308#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
16309#[rustc_legacy_const_generics(2)]
16310#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16311pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
16312 static_assert_uimm_bits!(LANE, 1);
16313 unsafe extern "unadjusted" {
16314 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")]
16315 fn _vld2_lane_s32(
16316 ptr: *const i8,
16317 a: int32x2_t,
16318 b: int32x2_t,
16319 n: i32,
16320 size: i32,
16321 ) -> int32x2x2_t;
16322 }
16323 _vld2_lane_s32(a as _, b.0, b.1, LANE, 4)
16324}
16325#[doc = "Load multiple 2-element structures to two registers"]
16326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
16327#[doc = "## Safety"]
16328#[doc = " * Neon instrinsic unsafe"]
16329#[inline]
16330#[target_feature(enable = "neon")]
16331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16333#[cfg_attr(
16334 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16335 assert_instr(ld2, LANE = 0)
16336)]
16337#[rustc_legacy_const_generics(2)]
16338#[cfg_attr(
16339 not(target_arch = "arm"),
16340 stable(feature = "neon_intrinsics", since = "1.59.0")
16341)]
16342#[cfg_attr(
16343 target_arch = "arm",
16344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16345)]
16346pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t {
16347 static_assert_uimm_bits!(LANE, 3);
16348 transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
16349}
16350#[doc = "Load multiple 2-element structures to two registers"]
16351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
16352#[doc = "## Safety"]
16353#[doc = " * Neon instrinsic unsafe"]
16354#[inline]
16355#[target_feature(enable = "neon")]
16356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16358#[cfg_attr(
16359 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16360 assert_instr(ld2, LANE = 0)
16361)]
16362#[rustc_legacy_const_generics(2)]
16363#[cfg_attr(
16364 not(target_arch = "arm"),
16365 stable(feature = "neon_intrinsics", since = "1.59.0")
16366)]
16367#[cfg_attr(
16368 target_arch = "arm",
16369 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16370)]
16371pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t {
16372 static_assert_uimm_bits!(LANE, 2);
16373 transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
16374}
16375#[doc = "Load multiple 2-element structures to two registers"]
16376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
16377#[doc = "## Safety"]
16378#[doc = " * Neon instrinsic unsafe"]
16379#[inline]
16380#[target_feature(enable = "neon")]
16381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16383#[cfg_attr(
16384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16385 assert_instr(ld2, LANE = 0)
16386)]
16387#[rustc_legacy_const_generics(2)]
16388#[cfg_attr(
16389 not(target_arch = "arm"),
16390 stable(feature = "neon_intrinsics", since = "1.59.0")
16391)]
16392#[cfg_attr(
16393 target_arch = "arm",
16394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16395)]
16396pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t {
16397 static_assert_uimm_bits!(LANE, 3);
16398 transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
16399}
16400#[doc = "Load multiple 2-element structures to two registers"]
16401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
16402#[doc = "## Safety"]
16403#[doc = " * Neon instrinsic unsafe"]
16404#[inline]
16405#[target_feature(enable = "neon")]
16406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16408#[cfg_attr(
16409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16410 assert_instr(ld2, LANE = 0)
16411)]
16412#[rustc_legacy_const_generics(2)]
16413#[cfg_attr(
16414 not(target_arch = "arm"),
16415 stable(feature = "neon_intrinsics", since = "1.59.0")
16416)]
16417#[cfg_attr(
16418 target_arch = "arm",
16419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16420)]
16421pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t {
16422 static_assert_uimm_bits!(LANE, 1);
16423 transmute(vld2_lane_s32::<LANE>(transmute(a), transmute(b)))
16424}
16425#[doc = "Load multiple 2-element structures to two registers"]
16426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
16427#[doc = "## Safety"]
16428#[doc = " * Neon instrinsic unsafe"]
16429#[inline]
16430#[target_feature(enable = "neon")]
16431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16433#[cfg_attr(
16434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16435 assert_instr(ld2, LANE = 0)
16436)]
16437#[rustc_legacy_const_generics(2)]
16438#[cfg_attr(
16439 not(target_arch = "arm"),
16440 stable(feature = "neon_intrinsics", since = "1.59.0")
16441)]
16442#[cfg_attr(
16443 target_arch = "arm",
16444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16445)]
16446pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t {
16447 static_assert_uimm_bits!(LANE, 2);
16448 transmute(vld2q_lane_s32::<LANE>(transmute(a), transmute(b)))
16449}
16450#[doc = "Load multiple 2-element structures to two registers"]
16451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
16452#[doc = "## Safety"]
16453#[doc = " * Neon instrinsic unsafe"]
16454#[inline]
16455#[target_feature(enable = "neon")]
16456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16458#[cfg_attr(
16459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16460 assert_instr(ld2, LANE = 0)
16461)]
16462#[rustc_legacy_const_generics(2)]
16463#[cfg_attr(
16464 not(target_arch = "arm"),
16465 stable(feature = "neon_intrinsics", since = "1.59.0")
16466)]
16467#[cfg_attr(
16468 target_arch = "arm",
16469 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16470)]
16471pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t {
16472 static_assert_uimm_bits!(LANE, 3);
16473 transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
16474}
16475#[doc = "Load multiple 2-element structures to two registers"]
16476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
16477#[doc = "## Safety"]
16478#[doc = " * Neon instrinsic unsafe"]
16479#[inline]
16480#[target_feature(enable = "neon")]
16481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16483#[cfg_attr(
16484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16485 assert_instr(ld2, LANE = 0)
16486)]
16487#[rustc_legacy_const_generics(2)]
16488#[cfg_attr(
16489 not(target_arch = "arm"),
16490 stable(feature = "neon_intrinsics", since = "1.59.0")
16491)]
16492#[cfg_attr(
16493 target_arch = "arm",
16494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16495)]
16496pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t {
16497 static_assert_uimm_bits!(LANE, 2);
16498 transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
16499}
16500#[doc = "Load multiple 2-element structures to two registers"]
16501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
16502#[doc = "## Safety"]
16503#[doc = " * Neon instrinsic unsafe"]
16504#[inline]
16505#[target_feature(enable = "neon")]
16506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
16508#[cfg_attr(
16509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16510 assert_instr(ld2, LANE = 0)
16511)]
16512#[rustc_legacy_const_generics(2)]
16513#[cfg_attr(
16514 not(target_arch = "arm"),
16515 stable(feature = "neon_intrinsics", since = "1.59.0")
16516)]
16517#[cfg_attr(
16518 target_arch = "arm",
16519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16520)]
16521pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t {
16522 static_assert_uimm_bits!(LANE, 3);
16523 transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
16524}
16525#[doc = "Load multiple 2-element structures to two registers"]
16526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
16527#[doc = "## Safety"]
16528#[doc = " * Neon instrinsic unsafe"]
16529#[inline]
16530#[target_feature(enable = "neon,aes")]
16531#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16533#[cfg_attr(
16534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16535 assert_instr(nop)
16536)]
16537#[cfg_attr(
16538 not(target_arch = "arm"),
16539 stable(feature = "neon_intrinsics", since = "1.59.0")
16540)]
16541#[cfg_attr(
16542 target_arch = "arm",
16543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16544)]
16545pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
16546 transmute(vld2_s64(transmute(a)))
16547}
16548#[doc = "Load multiple 2-element structures to two registers"]
16549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
16550#[doc = "## Safety"]
16551#[doc = " * Neon instrinsic unsafe"]
16552#[inline]
16553#[target_feature(enable = "neon,v7")]
16554#[cfg(target_arch = "arm")]
16555#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16556#[cfg_attr(test, assert_instr(nop))]
16557pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
16558 unsafe extern "unadjusted" {
16559 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")]
16560 fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
16561 }
16562 _vld2_s64(a as *const i8, 8)
16563}
16564#[doc = "Load multiple 2-element structures to two registers"]
16565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
16566#[doc = "## Safety"]
16567#[doc = " * Neon instrinsic unsafe"]
16568#[inline]
16569#[target_feature(enable = "neon")]
16570#[cfg(not(target_arch = "arm"))]
16571#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16572#[cfg_attr(test, assert_instr(nop))]
16573pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
16574 unsafe extern "unadjusted" {
16575 #[cfg_attr(
16576 any(target_arch = "aarch64", target_arch = "arm64ec"),
16577 link_name = "llvm.aarch64.neon.ld2.v1i64.p0"
16578 )]
16579 fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t;
16580 }
16581 _vld2_s64(a as _)
16582}
16583#[doc = "Load multiple 2-element structures to two registers"]
16584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
16585#[doc = "## Safety"]
16586#[doc = " * Neon instrinsic unsafe"]
16587#[inline]
16588#[target_feature(enable = "neon")]
16589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16591#[cfg_attr(
16592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16593 assert_instr(nop)
16594)]
16595#[cfg_attr(
16596 not(target_arch = "arm"),
16597 stable(feature = "neon_intrinsics", since = "1.59.0")
16598)]
16599#[cfg_attr(
16600 target_arch = "arm",
16601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16602)]
16603pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
16604 transmute(vld2_s64(transmute(a)))
16605}
16606#[doc = "Load multiple 2-element structures to two registers"]
16607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
16608#[doc = "## Safety"]
16609#[doc = " * Neon instrinsic unsafe"]
16610#[inline]
16611#[cfg(target_endian = "little")]
16612#[target_feature(enable = "neon")]
16613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16615#[cfg_attr(
16616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16617 assert_instr(ld2)
16618)]
16619#[cfg_attr(
16620 not(target_arch = "arm"),
16621 stable(feature = "neon_intrinsics", since = "1.59.0")
16622)]
16623#[cfg_attr(
16624 target_arch = "arm",
16625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16626)]
16627pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
16628 transmute(vld2_s8(transmute(a)))
16629}
16630#[doc = "Load multiple 2-element structures to two registers"]
16631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
16632#[doc = "## Safety"]
16633#[doc = " * Neon instrinsic unsafe"]
16634#[inline]
16635#[cfg(target_endian = "big")]
16636#[target_feature(enable = "neon")]
16637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16639#[cfg_attr(
16640 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16641 assert_instr(ld2)
16642)]
16643#[cfg_attr(
16644 not(target_arch = "arm"),
16645 stable(feature = "neon_intrinsics", since = "1.59.0")
16646)]
16647#[cfg_attr(
16648 target_arch = "arm",
16649 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16650)]
16651pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
16652 let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a)));
16653 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
16654 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
16655 ret_val
16656}
16657#[doc = "Load multiple 2-element structures to two registers"]
16658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
16659#[doc = "## Safety"]
16660#[doc = " * Neon instrinsic unsafe"]
16661#[inline]
16662#[cfg(target_endian = "little")]
16663#[target_feature(enable = "neon")]
16664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16666#[cfg_attr(
16667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16668 assert_instr(ld2)
16669)]
16670#[cfg_attr(
16671 not(target_arch = "arm"),
16672 stable(feature = "neon_intrinsics", since = "1.59.0")
16673)]
16674#[cfg_attr(
16675 target_arch = "arm",
16676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16677)]
16678pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
16679 transmute(vld2q_s8(transmute(a)))
16680}
16681#[doc = "Load multiple 2-element structures to two registers"]
16682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
16683#[doc = "## Safety"]
16684#[doc = " * Neon instrinsic unsafe"]
16685#[inline]
16686#[cfg(target_endian = "big")]
16687#[target_feature(enable = "neon")]
16688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16690#[cfg_attr(
16691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16692 assert_instr(ld2)
16693)]
16694#[cfg_attr(
16695 not(target_arch = "arm"),
16696 stable(feature = "neon_intrinsics", since = "1.59.0")
16697)]
16698#[cfg_attr(
16699 target_arch = "arm",
16700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16701)]
16702pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
16703 let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a)));
16704 ret_val.0 = unsafe {
16705 simd_shuffle!(
16706 ret_val.0,
16707 ret_val.0,
16708 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
16709 )
16710 };
16711 ret_val.1 = unsafe {
16712 simd_shuffle!(
16713 ret_val.1,
16714 ret_val.1,
16715 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
16716 )
16717 };
16718 ret_val
16719}
16720#[doc = "Load multiple 2-element structures to two registers"]
16721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
16722#[doc = "## Safety"]
16723#[doc = " * Neon instrinsic unsafe"]
16724#[inline]
16725#[cfg(target_endian = "little")]
16726#[target_feature(enable = "neon")]
16727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16729#[cfg_attr(
16730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16731 assert_instr(ld2)
16732)]
16733#[cfg_attr(
16734 not(target_arch = "arm"),
16735 stable(feature = "neon_intrinsics", since = "1.59.0")
16736)]
16737#[cfg_attr(
16738 target_arch = "arm",
16739 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16740)]
16741pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
16742 transmute(vld2_s16(transmute(a)))
16743}
16744#[doc = "Load multiple 2-element structures to two registers"]
16745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
16746#[doc = "## Safety"]
16747#[doc = " * Neon instrinsic unsafe"]
16748#[inline]
16749#[cfg(target_endian = "big")]
16750#[target_feature(enable = "neon")]
16751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16753#[cfg_attr(
16754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16755 assert_instr(ld2)
16756)]
16757#[cfg_attr(
16758 not(target_arch = "arm"),
16759 stable(feature = "neon_intrinsics", since = "1.59.0")
16760)]
16761#[cfg_attr(
16762 target_arch = "arm",
16763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16764)]
16765pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
16766 let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a)));
16767 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
16768 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
16769 ret_val
16770}
16771#[doc = "Load multiple 2-element structures to two registers"]
16772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
16773#[doc = "## Safety"]
16774#[doc = " * Neon instrinsic unsafe"]
16775#[inline]
16776#[cfg(target_endian = "little")]
16777#[target_feature(enable = "neon")]
16778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16780#[cfg_attr(
16781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16782 assert_instr(ld2)
16783)]
16784#[cfg_attr(
16785 not(target_arch = "arm"),
16786 stable(feature = "neon_intrinsics", since = "1.59.0")
16787)]
16788#[cfg_attr(
16789 target_arch = "arm",
16790 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16791)]
16792pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
16793 transmute(vld2q_s16(transmute(a)))
16794}
16795#[doc = "Load multiple 2-element structures to two registers"]
16796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
16797#[doc = "## Safety"]
16798#[doc = " * Neon instrinsic unsafe"]
16799#[inline]
16800#[cfg(target_endian = "big")]
16801#[target_feature(enable = "neon")]
16802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16804#[cfg_attr(
16805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16806 assert_instr(ld2)
16807)]
16808#[cfg_attr(
16809 not(target_arch = "arm"),
16810 stable(feature = "neon_intrinsics", since = "1.59.0")
16811)]
16812#[cfg_attr(
16813 target_arch = "arm",
16814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16815)]
16816pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
16817 let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a)));
16818 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
16819 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
16820 ret_val
16821}
16822#[doc = "Load multiple 2-element structures to two registers"]
16823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
16824#[doc = "## Safety"]
16825#[doc = " * Neon instrinsic unsafe"]
16826#[inline]
16827#[cfg(target_endian = "little")]
16828#[target_feature(enable = "neon")]
16829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16831#[cfg_attr(
16832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16833 assert_instr(ld2)
16834)]
16835#[cfg_attr(
16836 not(target_arch = "arm"),
16837 stable(feature = "neon_intrinsics", since = "1.59.0")
16838)]
16839#[cfg_attr(
16840 target_arch = "arm",
16841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16842)]
16843pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
16844 transmute(vld2_s32(transmute(a)))
16845}
16846#[doc = "Load multiple 2-element structures to two registers"]
16847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
16848#[doc = "## Safety"]
16849#[doc = " * Neon instrinsic unsafe"]
16850#[inline]
16851#[cfg(target_endian = "big")]
16852#[target_feature(enable = "neon")]
16853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16855#[cfg_attr(
16856 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16857 assert_instr(ld2)
16858)]
16859#[cfg_attr(
16860 not(target_arch = "arm"),
16861 stable(feature = "neon_intrinsics", since = "1.59.0")
16862)]
16863#[cfg_attr(
16864 target_arch = "arm",
16865 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16866)]
16867pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
16868 let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a)));
16869 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16870 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16871 ret_val
16872}
16873#[doc = "Load multiple 2-element structures to two registers"]
16874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
16875#[doc = "## Safety"]
16876#[doc = " * Neon instrinsic unsafe"]
16877#[inline]
16878#[cfg(target_endian = "little")]
16879#[target_feature(enable = "neon")]
16880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16882#[cfg_attr(
16883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16884 assert_instr(ld2)
16885)]
16886#[cfg_attr(
16887 not(target_arch = "arm"),
16888 stable(feature = "neon_intrinsics", since = "1.59.0")
16889)]
16890#[cfg_attr(
16891 target_arch = "arm",
16892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16893)]
16894pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
16895 transmute(vld2q_s32(transmute(a)))
16896}
16897#[doc = "Load multiple 2-element structures to two registers"]
16898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
16899#[doc = "## Safety"]
16900#[doc = " * Neon instrinsic unsafe"]
16901#[inline]
16902#[cfg(target_endian = "big")]
16903#[target_feature(enable = "neon")]
16904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16906#[cfg_attr(
16907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16908 assert_instr(ld2)
16909)]
16910#[cfg_attr(
16911 not(target_arch = "arm"),
16912 stable(feature = "neon_intrinsics", since = "1.59.0")
16913)]
16914#[cfg_attr(
16915 target_arch = "arm",
16916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16917)]
16918pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
16919 let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a)));
16920 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
16921 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
16922 ret_val
16923}
16924#[doc = "Load multiple 2-element structures to two registers"]
16925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
16926#[doc = "## Safety"]
16927#[doc = " * Neon instrinsic unsafe"]
16928#[inline]
16929#[cfg(target_endian = "little")]
16930#[target_feature(enable = "neon")]
16931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16933#[cfg_attr(
16934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16935 assert_instr(ld2)
16936)]
16937#[cfg_attr(
16938 not(target_arch = "arm"),
16939 stable(feature = "neon_intrinsics", since = "1.59.0")
16940)]
16941#[cfg_attr(
16942 target_arch = "arm",
16943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16944)]
16945pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
16946 transmute(vld2_s8(transmute(a)))
16947}
16948#[doc = "Load multiple 2-element structures to two registers"]
16949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
16950#[doc = "## Safety"]
16951#[doc = " * Neon instrinsic unsafe"]
16952#[inline]
16953#[cfg(target_endian = "big")]
16954#[target_feature(enable = "neon")]
16955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16957#[cfg_attr(
16958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16959 assert_instr(ld2)
16960)]
16961#[cfg_attr(
16962 not(target_arch = "arm"),
16963 stable(feature = "neon_intrinsics", since = "1.59.0")
16964)]
16965#[cfg_attr(
16966 target_arch = "arm",
16967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16968)]
16969pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
16970 let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a)));
16971 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
16972 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
16973 ret_val
16974}
16975#[doc = "Load multiple 2-element structures to two registers"]
16976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
16977#[doc = "## Safety"]
16978#[doc = " * Neon instrinsic unsafe"]
16979#[inline]
16980#[cfg(target_endian = "little")]
16981#[target_feature(enable = "neon")]
16982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
16984#[cfg_attr(
16985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16986 assert_instr(ld2)
16987)]
16988#[cfg_attr(
16989 not(target_arch = "arm"),
16990 stable(feature = "neon_intrinsics", since = "1.59.0")
16991)]
16992#[cfg_attr(
16993 target_arch = "arm",
16994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16995)]
16996pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
16997 transmute(vld2q_s8(transmute(a)))
16998}
16999#[doc = "Load multiple 2-element structures to two registers"]
17000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
17001#[doc = "## Safety"]
17002#[doc = " * Neon instrinsic unsafe"]
17003#[inline]
17004#[cfg(target_endian = "big")]
17005#[target_feature(enable = "neon")]
17006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
17008#[cfg_attr(
17009 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17010 assert_instr(ld2)
17011)]
17012#[cfg_attr(
17013 not(target_arch = "arm"),
17014 stable(feature = "neon_intrinsics", since = "1.59.0")
17015)]
17016#[cfg_attr(
17017 target_arch = "arm",
17018 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17019)]
17020pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
17021 let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a)));
17022 ret_val.0 = unsafe {
17023 simd_shuffle!(
17024 ret_val.0,
17025 ret_val.0,
17026 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17027 )
17028 };
17029 ret_val.1 = unsafe {
17030 simd_shuffle!(
17031 ret_val.1,
17032 ret_val.1,
17033 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17034 )
17035 };
17036 ret_val
17037}
17038#[doc = "Load multiple 2-element structures to two registers"]
17039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
17040#[doc = "## Safety"]
17041#[doc = " * Neon instrinsic unsafe"]
17042#[inline]
17043#[cfg(target_endian = "little")]
17044#[target_feature(enable = "neon")]
17045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
17047#[cfg_attr(
17048 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17049 assert_instr(ld2)
17050)]
17051#[cfg_attr(
17052 not(target_arch = "arm"),
17053 stable(feature = "neon_intrinsics", since = "1.59.0")
17054)]
17055#[cfg_attr(
17056 target_arch = "arm",
17057 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17058)]
17059pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
17060 transmute(vld2_s16(transmute(a)))
17061}
17062#[doc = "Load multiple 2-element structures to two registers"]
17063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
17064#[doc = "## Safety"]
17065#[doc = " * Neon instrinsic unsafe"]
17066#[inline]
17067#[cfg(target_endian = "big")]
17068#[target_feature(enable = "neon")]
17069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17070#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
17071#[cfg_attr(
17072 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17073 assert_instr(ld2)
17074)]
17075#[cfg_attr(
17076 not(target_arch = "arm"),
17077 stable(feature = "neon_intrinsics", since = "1.59.0")
17078)]
17079#[cfg_attr(
17080 target_arch = "arm",
17081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17082)]
17083pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
17084 let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a)));
17085 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17086 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17087 ret_val
17088}
17089#[doc = "Load multiple 2-element structures to two registers"]
17090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
17091#[doc = "## Safety"]
17092#[doc = " * Neon instrinsic unsafe"]
17093#[inline]
17094#[cfg(target_endian = "little")]
17095#[target_feature(enable = "neon")]
17096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
17098#[cfg_attr(
17099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17100 assert_instr(ld2)
17101)]
17102#[cfg_attr(
17103 not(target_arch = "arm"),
17104 stable(feature = "neon_intrinsics", since = "1.59.0")
17105)]
17106#[cfg_attr(
17107 target_arch = "arm",
17108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17109)]
17110pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
17111 transmute(vld2q_s16(transmute(a)))
17112}
17113#[doc = "Load multiple 2-element structures to two registers"]
17114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
17115#[doc = "## Safety"]
17116#[doc = " * Neon instrinsic unsafe"]
17117#[inline]
17118#[cfg(target_endian = "big")]
17119#[target_feature(enable = "neon")]
17120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
17122#[cfg_attr(
17123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17124 assert_instr(ld2)
17125)]
17126#[cfg_attr(
17127 not(target_arch = "arm"),
17128 stable(feature = "neon_intrinsics", since = "1.59.0")
17129)]
17130#[cfg_attr(
17131 target_arch = "arm",
17132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17133)]
17134pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
17135 let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a)));
17136 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17137 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17138 ret_val
17139}
17140#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
17141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
17142#[doc = "## Safety"]
17143#[doc = " * Neon instrinsic unsafe"]
17144#[inline]
17145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17146#[cfg(target_arch = "arm")]
17147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17148#[target_feature(enable = "neon,fp16")]
17149#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
17150pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
17151 unsafe extern "unadjusted" {
17152 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0f16")]
17153 fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
17154 }
17155 _vld3_dup_f16(a as _, 2)
17156}
17157#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
17158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
17159#[doc = "## Safety"]
17160#[doc = " * Neon instrinsic unsafe"]
17161#[inline]
17162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17163#[cfg(target_arch = "arm")]
17164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17165#[target_feature(enable = "neon,fp16")]
17166#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
17167pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
17168 unsafe extern "unadjusted" {
17169 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0f16")]
17170 fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
17171 }
17172 _vld3q_dup_f16(a as _, 2)
17173}
17174#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
17175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
17176#[doc = "## Safety"]
17177#[doc = " * Neon instrinsic unsafe"]
17178#[inline]
17179#[cfg(not(target_arch = "arm"))]
17180#[cfg_attr(
17181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17182 assert_instr(ld3r)
17183)]
17184#[target_feature(enable = "neon,fp16")]
17185#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
17186pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
17187 unsafe extern "unadjusted" {
17188 #[cfg_attr(
17189 any(target_arch = "aarch64", target_arch = "arm64ec"),
17190 link_name = "llvm.aarch64.neon.ld3r.v4f16.p0f16"
17191 )]
17192 fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
17193 }
17194 _vld3_dup_f16(a as _)
17195}
17196#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
17197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
17198#[doc = "## Safety"]
17199#[doc = " * Neon instrinsic unsafe"]
17200#[inline]
17201#[cfg(not(target_arch = "arm"))]
17202#[cfg_attr(
17203 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17204 assert_instr(ld3r)
17205)]
17206#[target_feature(enable = "neon,fp16")]
17207#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
17208pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
17209 unsafe extern "unadjusted" {
17210 #[cfg_attr(
17211 any(target_arch = "aarch64", target_arch = "arm64ec"),
17212 link_name = "llvm.aarch64.neon.ld3r.v8f16.p0f16"
17213 )]
17214 fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
17215 }
17216 _vld3q_dup_f16(a as _)
17217}
17218#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
17220#[doc = "## Safety"]
17221#[doc = " * Neon instrinsic unsafe"]
17222#[inline]
17223#[target_feature(enable = "neon")]
17224#[cfg(not(target_arch = "arm"))]
17225#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17226#[cfg_attr(test, assert_instr(ld3r))]
17227pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
17228 unsafe extern "unadjusted" {
17229 #[cfg_attr(
17230 any(target_arch = "aarch64", target_arch = "arm64ec"),
17231 link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
17232 )]
17233 fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
17234 }
17235 _vld3_dup_f32(a as _)
17236}
17237#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
17239#[doc = "## Safety"]
17240#[doc = " * Neon instrinsic unsafe"]
17241#[inline]
17242#[target_feature(enable = "neon")]
17243#[cfg(not(target_arch = "arm"))]
17244#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17245#[cfg_attr(test, assert_instr(ld3r))]
17246pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
17247 unsafe extern "unadjusted" {
17248 #[cfg_attr(
17249 any(target_arch = "aarch64", target_arch = "arm64ec"),
17250 link_name = "llvm.aarch64.neon.ld3r.v4f32.p0"
17251 )]
17252 fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t;
17253 }
17254 _vld3q_dup_f32(a as _)
17255}
17256#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
17258#[doc = "## Safety"]
17259#[doc = " * Neon instrinsic unsafe"]
17260#[inline]
17261#[target_feature(enable = "neon")]
17262#[cfg(not(target_arch = "arm"))]
17263#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17264#[cfg_attr(test, assert_instr(ld3r))]
17265pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
17266 unsafe extern "unadjusted" {
17267 #[cfg_attr(
17268 any(target_arch = "aarch64", target_arch = "arm64ec"),
17269 link_name = "llvm.aarch64.neon.ld3r.v8i8.p0"
17270 )]
17271 fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t;
17272 }
17273 _vld3_dup_s8(a as _)
17274}
17275#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
17277#[doc = "## Safety"]
17278#[doc = " * Neon instrinsic unsafe"]
17279#[inline]
17280#[target_feature(enable = "neon")]
17281#[cfg(not(target_arch = "arm"))]
17282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17283#[cfg_attr(test, assert_instr(ld3r))]
17284pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
17285 unsafe extern "unadjusted" {
17286 #[cfg_attr(
17287 any(target_arch = "aarch64", target_arch = "arm64ec"),
17288 link_name = "llvm.aarch64.neon.ld3r.v16i8.p0"
17289 )]
17290 fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t;
17291 }
17292 _vld3q_dup_s8(a as _)
17293}
17294#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
17296#[doc = "## Safety"]
17297#[doc = " * Neon instrinsic unsafe"]
17298#[inline]
17299#[target_feature(enable = "neon")]
17300#[cfg(not(target_arch = "arm"))]
17301#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17302#[cfg_attr(test, assert_instr(ld3r))]
17303pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
17304 unsafe extern "unadjusted" {
17305 #[cfg_attr(
17306 any(target_arch = "aarch64", target_arch = "arm64ec"),
17307 link_name = "llvm.aarch64.neon.ld3r.v4i16.p0"
17308 )]
17309 fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t;
17310 }
17311 _vld3_dup_s16(a as _)
17312}
17313#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
17315#[doc = "## Safety"]
17316#[doc = " * Neon instrinsic unsafe"]
17317#[inline]
17318#[target_feature(enable = "neon")]
17319#[cfg(not(target_arch = "arm"))]
17320#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17321#[cfg_attr(test, assert_instr(ld3r))]
17322pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
17323 unsafe extern "unadjusted" {
17324 #[cfg_attr(
17325 any(target_arch = "aarch64", target_arch = "arm64ec"),
17326 link_name = "llvm.aarch64.neon.ld3r.v8i16.p0"
17327 )]
17328 fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t;
17329 }
17330 _vld3q_dup_s16(a as _)
17331}
17332#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
17334#[doc = "## Safety"]
17335#[doc = " * Neon instrinsic unsafe"]
17336#[inline]
17337#[target_feature(enable = "neon")]
17338#[cfg(not(target_arch = "arm"))]
17339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17340#[cfg_attr(test, assert_instr(ld3r))]
17341pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
17342 unsafe extern "unadjusted" {
17343 #[cfg_attr(
17344 any(target_arch = "aarch64", target_arch = "arm64ec"),
17345 link_name = "llvm.aarch64.neon.ld3r.v2i32.p0"
17346 )]
17347 fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t;
17348 }
17349 _vld3_dup_s32(a as _)
17350}
17351#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
17353#[doc = "## Safety"]
17354#[doc = " * Neon instrinsic unsafe"]
17355#[inline]
17356#[target_feature(enable = "neon")]
17357#[cfg(not(target_arch = "arm"))]
17358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17359#[cfg_attr(test, assert_instr(ld3r))]
17360pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
17361 unsafe extern "unadjusted" {
17362 #[cfg_attr(
17363 any(target_arch = "aarch64", target_arch = "arm64ec"),
17364 link_name = "llvm.aarch64.neon.ld3r.v4i32.p0"
17365 )]
17366 fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t;
17367 }
17368 _vld3q_dup_s32(a as _)
17369}
17370#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
17372#[doc = "## Safety"]
17373#[doc = " * Neon instrinsic unsafe"]
17374#[inline]
17375#[target_feature(enable = "neon")]
17376#[cfg(not(target_arch = "arm"))]
17377#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17378#[cfg_attr(test, assert_instr(ld3r))]
17379pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
17380 unsafe extern "unadjusted" {
17381 #[cfg_attr(
17382 any(target_arch = "aarch64", target_arch = "arm64ec"),
17383 link_name = "llvm.aarch64.neon.ld3r.v1i64.p0"
17384 )]
17385 fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t;
17386 }
17387 _vld3_dup_s64(a as _)
17388}
17389#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
17391#[doc = "## Safety"]
17392#[doc = " * Neon instrinsic unsafe"]
17393#[inline]
17394#[target_feature(enable = "neon,v7")]
17395#[cfg(target_arch = "arm")]
17396#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17397#[cfg_attr(test, assert_instr(vld3))]
17398pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
17399 unsafe extern "unadjusted" {
17400 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")]
17401 fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
17402 }
17403 _vld3_dup_f32(a as *const i8, 4)
17404}
17405#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
17407#[doc = "## Safety"]
17408#[doc = " * Neon instrinsic unsafe"]
17409#[inline]
17410#[target_feature(enable = "neon,v7")]
17411#[cfg(target_arch = "arm")]
17412#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17413#[cfg_attr(test, assert_instr(vld3))]
17414pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
17415 unsafe extern "unadjusted" {
17416 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")]
17417 fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
17418 }
17419 _vld3q_dup_f32(a as *const i8, 4)
17420}
17421#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
17423#[doc = "## Safety"]
17424#[doc = " * Neon instrinsic unsafe"]
17425#[inline]
17426#[target_feature(enable = "neon,v7")]
17427#[cfg(target_arch = "arm")]
17428#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17429#[cfg_attr(test, assert_instr(vld3))]
17430pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
17431 unsafe extern "unadjusted" {
17432 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")]
17433 fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
17434 }
17435 _vld3_dup_s8(a as *const i8, 1)
17436}
17437#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
17439#[doc = "## Safety"]
17440#[doc = " * Neon instrinsic unsafe"]
17441#[inline]
17442#[target_feature(enable = "neon,v7")]
17443#[cfg(target_arch = "arm")]
17444#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17445#[cfg_attr(test, assert_instr(vld3))]
17446pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
17447 unsafe extern "unadjusted" {
17448 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")]
17449 fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
17450 }
17451 _vld3q_dup_s8(a as *const i8, 1)
17452}
17453#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
17455#[doc = "## Safety"]
17456#[doc = " * Neon instrinsic unsafe"]
17457#[inline]
17458#[target_feature(enable = "neon,v7")]
17459#[cfg(target_arch = "arm")]
17460#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17461#[cfg_attr(test, assert_instr(vld3))]
17462pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
17463 unsafe extern "unadjusted" {
17464 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")]
17465 fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
17466 }
17467 _vld3_dup_s16(a as *const i8, 2)
17468}
17469#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
17471#[doc = "## Safety"]
17472#[doc = " * Neon instrinsic unsafe"]
17473#[inline]
17474#[target_feature(enable = "neon,v7")]
17475#[cfg(target_arch = "arm")]
17476#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17477#[cfg_attr(test, assert_instr(vld3))]
17478pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
17479 unsafe extern "unadjusted" {
17480 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")]
17481 fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
17482 }
17483 _vld3q_dup_s16(a as *const i8, 2)
17484}
17485#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
17487#[doc = "## Safety"]
17488#[doc = " * Neon instrinsic unsafe"]
17489#[inline]
17490#[target_feature(enable = "neon,v7")]
17491#[cfg(target_arch = "arm")]
17492#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17493#[cfg_attr(test, assert_instr(vld3))]
17494pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
17495 unsafe extern "unadjusted" {
17496 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")]
17497 fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
17498 }
17499 _vld3_dup_s32(a as *const i8, 4)
17500}
17501#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
17503#[doc = "## Safety"]
17504#[doc = " * Neon instrinsic unsafe"]
17505#[inline]
17506#[target_feature(enable = "neon,v7")]
17507#[cfg(target_arch = "arm")]
17508#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17509#[cfg_attr(test, assert_instr(vld3))]
17510pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
17511 unsafe extern "unadjusted" {
17512 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")]
17513 fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
17514 }
17515 _vld3q_dup_s32(a as *const i8, 4)
17516}
17517#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
17519#[doc = "## Safety"]
17520#[doc = " * Neon instrinsic unsafe"]
17521#[inline]
17522#[target_feature(enable = "neon,aes")]
17523#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
17524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
17525#[cfg_attr(
17526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17527 assert_instr(ld3r)
17528)]
17529#[cfg_attr(
17530 not(target_arch = "arm"),
17531 stable(feature = "neon_intrinsics", since = "1.59.0")
17532)]
17533#[cfg_attr(
17534 target_arch = "arm",
17535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17536)]
17537pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
17538 transmute(vld3_dup_s64(transmute(a)))
17539}
17540#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
17542#[doc = "## Safety"]
17543#[doc = " * Neon instrinsic unsafe"]
17544#[inline]
17545#[cfg(target_arch = "arm")]
17546#[target_feature(enable = "neon,v7")]
17547#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
17548#[cfg_attr(test, assert_instr(nop))]
17549pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
17550 unsafe extern "unadjusted" {
17551 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")]
17552 fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
17553 }
17554 _vld3_dup_s64(a as *const i8, 8)
17555}
17556#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
17558#[doc = "## Safety"]
17559#[doc = " * Neon instrinsic unsafe"]
17560#[inline]
17561#[target_feature(enable = "neon")]
17562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
17564#[cfg_attr(
17565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17566 assert_instr(ld3r)
17567)]
17568#[cfg_attr(
17569 not(target_arch = "arm"),
17570 stable(feature = "neon_intrinsics", since = "1.59.0")
17571)]
17572#[cfg_attr(
17573 target_arch = "arm",
17574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17575)]
17576pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
17577 transmute(vld3_dup_s64(transmute(a)))
17578}
17579#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
17581#[doc = "## Safety"]
17582#[doc = " * Neon instrinsic unsafe"]
17583#[inline]
17584#[cfg(target_endian = "little")]
17585#[target_feature(enable = "neon")]
17586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17588#[cfg_attr(
17589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17590 assert_instr(ld3r)
17591)]
17592#[cfg_attr(
17593 not(target_arch = "arm"),
17594 stable(feature = "neon_intrinsics", since = "1.59.0")
17595)]
17596#[cfg_attr(
17597 target_arch = "arm",
17598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17599)]
17600pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
17601 transmute(vld3_dup_s8(transmute(a)))
17602}
17603#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
17605#[doc = "## Safety"]
17606#[doc = " * Neon instrinsic unsafe"]
17607#[inline]
17608#[cfg(target_endian = "big")]
17609#[target_feature(enable = "neon")]
17610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17612#[cfg_attr(
17613 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17614 assert_instr(ld3r)
17615)]
17616#[cfg_attr(
17617 not(target_arch = "arm"),
17618 stable(feature = "neon_intrinsics", since = "1.59.0")
17619)]
17620#[cfg_attr(
17621 target_arch = "arm",
17622 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17623)]
17624pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
17625 let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
17626 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17627 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17628 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17629 ret_val
17630}
17631#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
17633#[doc = "## Safety"]
17634#[doc = " * Neon instrinsic unsafe"]
17635#[inline]
17636#[cfg(target_endian = "little")]
17637#[target_feature(enable = "neon")]
17638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17640#[cfg_attr(
17641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17642 assert_instr(ld3r)
17643)]
17644#[cfg_attr(
17645 not(target_arch = "arm"),
17646 stable(feature = "neon_intrinsics", since = "1.59.0")
17647)]
17648#[cfg_attr(
17649 target_arch = "arm",
17650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17651)]
17652pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
17653 transmute(vld3q_dup_s8(transmute(a)))
17654}
17655#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
17657#[doc = "## Safety"]
17658#[doc = " * Neon instrinsic unsafe"]
17659#[inline]
17660#[cfg(target_endian = "big")]
17661#[target_feature(enable = "neon")]
17662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17664#[cfg_attr(
17665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17666 assert_instr(ld3r)
17667)]
17668#[cfg_attr(
17669 not(target_arch = "arm"),
17670 stable(feature = "neon_intrinsics", since = "1.59.0")
17671)]
17672#[cfg_attr(
17673 target_arch = "arm",
17674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17675)]
17676pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
17677 let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
17678 ret_val.0 = unsafe {
17679 simd_shuffle!(
17680 ret_val.0,
17681 ret_val.0,
17682 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17683 )
17684 };
17685 ret_val.1 = unsafe {
17686 simd_shuffle!(
17687 ret_val.1,
17688 ret_val.1,
17689 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17690 )
17691 };
17692 ret_val.2 = unsafe {
17693 simd_shuffle!(
17694 ret_val.2,
17695 ret_val.2,
17696 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17697 )
17698 };
17699 ret_val
17700}
17701#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
17703#[doc = "## Safety"]
17704#[doc = " * Neon instrinsic unsafe"]
17705#[inline]
17706#[cfg(target_endian = "little")]
17707#[target_feature(enable = "neon")]
17708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17710#[cfg_attr(
17711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17712 assert_instr(ld3r)
17713)]
17714#[cfg_attr(
17715 not(target_arch = "arm"),
17716 stable(feature = "neon_intrinsics", since = "1.59.0")
17717)]
17718#[cfg_attr(
17719 target_arch = "arm",
17720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17721)]
17722pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
17723 transmute(vld3_dup_s16(transmute(a)))
17724}
17725#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
17727#[doc = "## Safety"]
17728#[doc = " * Neon instrinsic unsafe"]
17729#[inline]
17730#[cfg(target_endian = "big")]
17731#[target_feature(enable = "neon")]
17732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17734#[cfg_attr(
17735 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17736 assert_instr(ld3r)
17737)]
17738#[cfg_attr(
17739 not(target_arch = "arm"),
17740 stable(feature = "neon_intrinsics", since = "1.59.0")
17741)]
17742#[cfg_attr(
17743 target_arch = "arm",
17744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17745)]
17746pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
17747 let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
17748 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17749 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17750 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
17751 ret_val
17752}
17753#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
17755#[doc = "## Safety"]
17756#[doc = " * Neon instrinsic unsafe"]
17757#[inline]
17758#[cfg(target_endian = "little")]
17759#[target_feature(enable = "neon")]
17760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17762#[cfg_attr(
17763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17764 assert_instr(ld3r)
17765)]
17766#[cfg_attr(
17767 not(target_arch = "arm"),
17768 stable(feature = "neon_intrinsics", since = "1.59.0")
17769)]
17770#[cfg_attr(
17771 target_arch = "arm",
17772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17773)]
17774pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
17775 transmute(vld3q_dup_s16(transmute(a)))
17776}
17777#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
17779#[doc = "## Safety"]
17780#[doc = " * Neon instrinsic unsafe"]
17781#[inline]
17782#[cfg(target_endian = "big")]
17783#[target_feature(enable = "neon")]
17784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17786#[cfg_attr(
17787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17788 assert_instr(ld3r)
17789)]
17790#[cfg_attr(
17791 not(target_arch = "arm"),
17792 stable(feature = "neon_intrinsics", since = "1.59.0")
17793)]
17794#[cfg_attr(
17795 target_arch = "arm",
17796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17797)]
17798pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
17799 let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
17800 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17801 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17802 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17803 ret_val
17804}
17805#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
17807#[doc = "## Safety"]
17808#[doc = " * Neon instrinsic unsafe"]
17809#[inline]
17810#[cfg(target_endian = "little")]
17811#[target_feature(enable = "neon")]
17812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17814#[cfg_attr(
17815 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17816 assert_instr(ld3r)
17817)]
17818#[cfg_attr(
17819 not(target_arch = "arm"),
17820 stable(feature = "neon_intrinsics", since = "1.59.0")
17821)]
17822#[cfg_attr(
17823 target_arch = "arm",
17824 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17825)]
17826pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
17827 transmute(vld3_dup_s32(transmute(a)))
17828}
17829#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
17831#[doc = "## Safety"]
17832#[doc = " * Neon instrinsic unsafe"]
17833#[inline]
17834#[cfg(target_endian = "big")]
17835#[target_feature(enable = "neon")]
17836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17838#[cfg_attr(
17839 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17840 assert_instr(ld3r)
17841)]
17842#[cfg_attr(
17843 not(target_arch = "arm"),
17844 stable(feature = "neon_intrinsics", since = "1.59.0")
17845)]
17846#[cfg_attr(
17847 target_arch = "arm",
17848 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17849)]
17850pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
17851 let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
17852 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
17853 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
17854 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
17855 ret_val
17856}
17857#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
17859#[doc = "## Safety"]
17860#[doc = " * Neon instrinsic unsafe"]
17861#[inline]
17862#[cfg(target_endian = "little")]
17863#[target_feature(enable = "neon")]
17864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17866#[cfg_attr(
17867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17868 assert_instr(ld3r)
17869)]
17870#[cfg_attr(
17871 not(target_arch = "arm"),
17872 stable(feature = "neon_intrinsics", since = "1.59.0")
17873)]
17874#[cfg_attr(
17875 target_arch = "arm",
17876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17877)]
17878pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
17879 transmute(vld3q_dup_s32(transmute(a)))
17880}
17881#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
17883#[doc = "## Safety"]
17884#[doc = " * Neon instrinsic unsafe"]
17885#[inline]
17886#[cfg(target_endian = "big")]
17887#[target_feature(enable = "neon")]
17888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17890#[cfg_attr(
17891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17892 assert_instr(ld3r)
17893)]
17894#[cfg_attr(
17895 not(target_arch = "arm"),
17896 stable(feature = "neon_intrinsics", since = "1.59.0")
17897)]
17898#[cfg_attr(
17899 target_arch = "arm",
17900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17901)]
17902pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
17903 let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
17904 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17905 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17906 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
17907 ret_val
17908}
17909#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
17911#[doc = "## Safety"]
17912#[doc = " * Neon instrinsic unsafe"]
17913#[inline]
17914#[cfg(target_endian = "little")]
17915#[target_feature(enable = "neon")]
17916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17918#[cfg_attr(
17919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17920 assert_instr(ld3r)
17921)]
17922#[cfg_attr(
17923 not(target_arch = "arm"),
17924 stable(feature = "neon_intrinsics", since = "1.59.0")
17925)]
17926#[cfg_attr(
17927 target_arch = "arm",
17928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17929)]
17930pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
17931 transmute(vld3_dup_s8(transmute(a)))
17932}
17933#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
17935#[doc = "## Safety"]
17936#[doc = " * Neon instrinsic unsafe"]
17937#[inline]
17938#[cfg(target_endian = "big")]
17939#[target_feature(enable = "neon")]
17940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17942#[cfg_attr(
17943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17944 assert_instr(ld3r)
17945)]
17946#[cfg_attr(
17947 not(target_arch = "arm"),
17948 stable(feature = "neon_intrinsics", since = "1.59.0")
17949)]
17950#[cfg_attr(
17951 target_arch = "arm",
17952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17953)]
17954pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
17955 let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
17956 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17957 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17958 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17959 ret_val
17960}
17961#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
17963#[doc = "## Safety"]
17964#[doc = " * Neon instrinsic unsafe"]
17965#[inline]
17966#[cfg(target_endian = "little")]
17967#[target_feature(enable = "neon")]
17968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17969#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17970#[cfg_attr(
17971 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17972 assert_instr(ld3r)
17973)]
17974#[cfg_attr(
17975 not(target_arch = "arm"),
17976 stable(feature = "neon_intrinsics", since = "1.59.0")
17977)]
17978#[cfg_attr(
17979 target_arch = "arm",
17980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17981)]
17982pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
17983 transmute(vld3q_dup_s8(transmute(a)))
17984}
17985#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
17986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
17987#[doc = "## Safety"]
17988#[doc = " * Neon instrinsic unsafe"]
17989#[inline]
17990#[cfg(target_endian = "big")]
17991#[target_feature(enable = "neon")]
17992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17993#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
17994#[cfg_attr(
17995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17996 assert_instr(ld3r)
17997)]
17998#[cfg_attr(
17999 not(target_arch = "arm"),
18000 stable(feature = "neon_intrinsics", since = "1.59.0")
18001)]
18002#[cfg_attr(
18003 target_arch = "arm",
18004 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18005)]
18006pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
18007 let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
18008 ret_val.0 = unsafe {
18009 simd_shuffle!(
18010 ret_val.0,
18011 ret_val.0,
18012 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18013 )
18014 };
18015 ret_val.1 = unsafe {
18016 simd_shuffle!(
18017 ret_val.1,
18018 ret_val.1,
18019 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18020 )
18021 };
18022 ret_val.2 = unsafe {
18023 simd_shuffle!(
18024 ret_val.2,
18025 ret_val.2,
18026 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18027 )
18028 };
18029 ret_val
18030}
18031#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
18032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
18033#[doc = "## Safety"]
18034#[doc = " * Neon instrinsic unsafe"]
18035#[inline]
18036#[cfg(target_endian = "little")]
18037#[target_feature(enable = "neon")]
18038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
18040#[cfg_attr(
18041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18042 assert_instr(ld3r)
18043)]
18044#[cfg_attr(
18045 not(target_arch = "arm"),
18046 stable(feature = "neon_intrinsics", since = "1.59.0")
18047)]
18048#[cfg_attr(
18049 target_arch = "arm",
18050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18051)]
18052pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
18053 transmute(vld3_dup_s16(transmute(a)))
18054}
18055#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
18056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
18057#[doc = "## Safety"]
18058#[doc = " * Neon instrinsic unsafe"]
18059#[inline]
18060#[cfg(target_endian = "big")]
18061#[target_feature(enable = "neon")]
18062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
18064#[cfg_attr(
18065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18066 assert_instr(ld3r)
18067)]
18068#[cfg_attr(
18069 not(target_arch = "arm"),
18070 stable(feature = "neon_intrinsics", since = "1.59.0")
18071)]
18072#[cfg_attr(
18073 target_arch = "arm",
18074 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18075)]
18076pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
18077 let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
18078 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18079 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18080 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18081 ret_val
18082}
18083#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
18084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
18085#[doc = "## Safety"]
18086#[doc = " * Neon instrinsic unsafe"]
18087#[inline]
18088#[cfg(target_endian = "little")]
18089#[target_feature(enable = "neon")]
18090#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18091#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
18092#[cfg_attr(
18093 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18094 assert_instr(ld3r)
18095)]
18096#[cfg_attr(
18097 not(target_arch = "arm"),
18098 stable(feature = "neon_intrinsics", since = "1.59.0")
18099)]
18100#[cfg_attr(
18101 target_arch = "arm",
18102 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18103)]
18104pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
18105 transmute(vld3q_dup_s16(transmute(a)))
18106}
18107#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
18108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
18109#[doc = "## Safety"]
18110#[doc = " * Neon instrinsic unsafe"]
18111#[inline]
18112#[cfg(target_endian = "big")]
18113#[target_feature(enable = "neon")]
18114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
18116#[cfg_attr(
18117 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18118 assert_instr(ld3r)
18119)]
18120#[cfg_attr(
18121 not(target_arch = "arm"),
18122 stable(feature = "neon_intrinsics", since = "1.59.0")
18123)]
18124#[cfg_attr(
18125 target_arch = "arm",
18126 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18127)]
18128pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
18129 let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
18130 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18131 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18132 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18133 ret_val
18134}
18135#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
18136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
18137#[doc = "## Safety"]
18138#[doc = " * Neon instrinsic unsafe"]
18139#[inline]
18140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18141#[cfg(target_arch = "arm")]
18142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
18143#[target_feature(enable = "neon,fp16")]
18144#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18145pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
18146 unsafe extern "unadjusted" {
18147 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0f16")]
18148 fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
18149 }
18150 _vld3_f16(a as _, 2)
18151}
18152#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
18153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
18154#[doc = "## Safety"]
18155#[doc = " * Neon instrinsic unsafe"]
18156#[inline]
18157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18158#[cfg(target_arch = "arm")]
18159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
18160#[target_feature(enable = "neon,fp16")]
18161#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18162pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
18163 unsafe extern "unadjusted" {
18164 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0f16")]
18165 fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
18166 }
18167 _vld3q_f16(a as _, 2)
18168}
18169#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
18170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
18171#[doc = "## Safety"]
18172#[doc = " * Neon instrinsic unsafe"]
18173#[inline]
18174#[cfg(not(target_arch = "arm"))]
18175#[cfg_attr(
18176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18177 assert_instr(ld3)
18178)]
18179#[target_feature(enable = "neon,fp16")]
18180#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18181pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
18182 unsafe extern "unadjusted" {
18183 #[cfg_attr(
18184 any(target_arch = "aarch64", target_arch = "arm64ec"),
18185 link_name = "llvm.aarch64.neon.ld3.v4f16.p0f16"
18186 )]
18187 fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
18188 }
18189 _vld3_f16(a as _)
18190}
18191#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
18192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
18193#[doc = "## Safety"]
18194#[doc = " * Neon instrinsic unsafe"]
18195#[inline]
18196#[cfg(not(target_arch = "arm"))]
18197#[cfg_attr(
18198 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18199 assert_instr(ld3)
18200)]
18201#[target_feature(enable = "neon,fp16")]
18202#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18203pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
18204 unsafe extern "unadjusted" {
18205 #[cfg_attr(
18206 any(target_arch = "aarch64", target_arch = "arm64ec"),
18207 link_name = "llvm.aarch64.neon.ld3.v8f16.p0f16"
18208 )]
18209 fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
18210 }
18211 _vld3q_f16(a as _)
18212}
18213#[doc = "Load multiple 3-element structures to three registers"]
18214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
18215#[doc = "## Safety"]
18216#[doc = " * Neon instrinsic unsafe"]
18217#[inline]
18218#[target_feature(enable = "neon")]
18219#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18220#[cfg(not(target_arch = "arm"))]
18221#[cfg_attr(test, assert_instr(ld3))]
18222pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
18223 unsafe extern "unadjusted" {
18224 #[cfg_attr(
18225 any(target_arch = "aarch64", target_arch = "arm64ec"),
18226 link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
18227 )]
18228 fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
18229 }
18230 _vld3_f32(a as _)
18231}
18232#[doc = "Load multiple 3-element structures to three registers"]
18233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
18234#[doc = "## Safety"]
18235#[doc = " * Neon instrinsic unsafe"]
18236#[inline]
18237#[target_feature(enable = "neon")]
18238#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18239#[cfg(not(target_arch = "arm"))]
18240#[cfg_attr(test, assert_instr(ld3))]
18241pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
18242 unsafe extern "unadjusted" {
18243 #[cfg_attr(
18244 any(target_arch = "aarch64", target_arch = "arm64ec"),
18245 link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
18246 )]
18247 fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
18248 }
18249 _vld3q_f32(a as _)
18250}
18251#[doc = "Load multiple 3-element structures to three registers"]
18252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
18253#[doc = "## Safety"]
18254#[doc = " * Neon instrinsic unsafe"]
18255#[inline]
18256#[target_feature(enable = "neon")]
18257#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18258#[cfg(not(target_arch = "arm"))]
18259#[cfg_attr(test, assert_instr(ld3))]
18260pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
18261 unsafe extern "unadjusted" {
18262 #[cfg_attr(
18263 any(target_arch = "aarch64", target_arch = "arm64ec"),
18264 link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
18265 )]
18266 fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
18267 }
18268 _vld3_s8(a as _)
18269}
18270#[doc = "Load multiple 3-element structures to three registers"]
18271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
18272#[doc = "## Safety"]
18273#[doc = " * Neon instrinsic unsafe"]
18274#[inline]
18275#[target_feature(enable = "neon")]
18276#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18277#[cfg(not(target_arch = "arm"))]
18278#[cfg_attr(test, assert_instr(ld3))]
18279pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
18280 unsafe extern "unadjusted" {
18281 #[cfg_attr(
18282 any(target_arch = "aarch64", target_arch = "arm64ec"),
18283 link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
18284 )]
18285 fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
18286 }
18287 _vld3q_s8(a as _)
18288}
18289#[doc = "Load multiple 3-element structures to three registers"]
18290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
18291#[doc = "## Safety"]
18292#[doc = " * Neon instrinsic unsafe"]
18293#[inline]
18294#[target_feature(enable = "neon")]
18295#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18296#[cfg(not(target_arch = "arm"))]
18297#[cfg_attr(test, assert_instr(ld3))]
18298pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
18299 unsafe extern "unadjusted" {
18300 #[cfg_attr(
18301 any(target_arch = "aarch64", target_arch = "arm64ec"),
18302 link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
18303 )]
18304 fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
18305 }
18306 _vld3_s16(a as _)
18307}
18308#[doc = "Load multiple 3-element structures to three registers"]
18309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
18310#[doc = "## Safety"]
18311#[doc = " * Neon instrinsic unsafe"]
18312#[inline]
18313#[target_feature(enable = "neon")]
18314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18315#[cfg(not(target_arch = "arm"))]
18316#[cfg_attr(test, assert_instr(ld3))]
18317pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
18318 unsafe extern "unadjusted" {
18319 #[cfg_attr(
18320 any(target_arch = "aarch64", target_arch = "arm64ec"),
18321 link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
18322 )]
18323 fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
18324 }
18325 _vld3q_s16(a as _)
18326}
18327#[doc = "Load multiple 3-element structures to three registers"]
18328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
18329#[doc = "## Safety"]
18330#[doc = " * Neon instrinsic unsafe"]
18331#[inline]
18332#[target_feature(enable = "neon")]
18333#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18334#[cfg(not(target_arch = "arm"))]
18335#[cfg_attr(test, assert_instr(ld3))]
18336pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
18337 unsafe extern "unadjusted" {
18338 #[cfg_attr(
18339 any(target_arch = "aarch64", target_arch = "arm64ec"),
18340 link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
18341 )]
18342 fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
18343 }
18344 _vld3_s32(a as _)
18345}
18346#[doc = "Load multiple 3-element structures to three registers"]
18347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
18348#[doc = "## Safety"]
18349#[doc = " * Neon instrinsic unsafe"]
18350#[inline]
18351#[target_feature(enable = "neon")]
18352#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18353#[cfg(not(target_arch = "arm"))]
18354#[cfg_attr(test, assert_instr(ld3))]
18355pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
18356 unsafe extern "unadjusted" {
18357 #[cfg_attr(
18358 any(target_arch = "aarch64", target_arch = "arm64ec"),
18359 link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
18360 )]
18361 fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
18362 }
18363 _vld3q_s32(a as _)
18364}
18365#[doc = "Load multiple 3-element structures to three registers"]
18366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
18367#[doc = "## Safety"]
18368#[doc = " * Neon instrinsic unsafe"]
18369#[inline]
18370#[cfg(target_arch = "arm")]
18371#[target_feature(enable = "neon,v7")]
18372#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18373#[cfg_attr(test, assert_instr(vld3))]
18374pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
18375 unsafe extern "unadjusted" {
18376 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")]
18377 fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
18378 }
18379 _vld3_f32(a as *const i8, 4)
18380}
18381#[doc = "Load multiple 3-element structures to three registers"]
18382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
18383#[doc = "## Safety"]
18384#[doc = " * Neon instrinsic unsafe"]
18385#[inline]
18386#[cfg(target_arch = "arm")]
18387#[target_feature(enable = "neon,v7")]
18388#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18389#[cfg_attr(test, assert_instr(vld3))]
18390pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
18391 unsafe extern "unadjusted" {
18392 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")]
18393 fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
18394 }
18395 _vld3q_f32(a as *const i8, 4)
18396}
18397#[doc = "Load multiple 3-element structures to three registers"]
18398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
18399#[doc = "## Safety"]
18400#[doc = " * Neon instrinsic unsafe"]
18401#[inline]
18402#[cfg(target_arch = "arm")]
18403#[target_feature(enable = "neon,v7")]
18404#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18405#[cfg_attr(test, assert_instr(vld3))]
18406pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
18407 unsafe extern "unadjusted" {
18408 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")]
18409 fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
18410 }
18411 _vld3_s8(a as *const i8, 1)
18412}
18413#[doc = "Load multiple 3-element structures to three registers"]
18414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
18415#[doc = "## Safety"]
18416#[doc = " * Neon instrinsic unsafe"]
18417#[inline]
18418#[cfg(target_arch = "arm")]
18419#[target_feature(enable = "neon,v7")]
18420#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18421#[cfg_attr(test, assert_instr(vld3))]
18422pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
18423 unsafe extern "unadjusted" {
18424 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")]
18425 fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
18426 }
18427 _vld3q_s8(a as *const i8, 1)
18428}
18429#[doc = "Load multiple 3-element structures to three registers"]
18430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
18431#[doc = "## Safety"]
18432#[doc = " * Neon instrinsic unsafe"]
18433#[inline]
18434#[cfg(target_arch = "arm")]
18435#[target_feature(enable = "neon,v7")]
18436#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18437#[cfg_attr(test, assert_instr(vld3))]
18438pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
18439 unsafe extern "unadjusted" {
18440 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")]
18441 fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
18442 }
18443 _vld3_s16(a as *const i8, 2)
18444}
18445#[doc = "Load multiple 3-element structures to three registers"]
18446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
18447#[doc = "## Safety"]
18448#[doc = " * Neon instrinsic unsafe"]
18449#[inline]
18450#[cfg(target_arch = "arm")]
18451#[target_feature(enable = "neon,v7")]
18452#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18453#[cfg_attr(test, assert_instr(vld3))]
18454pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
18455 unsafe extern "unadjusted" {
18456 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")]
18457 fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
18458 }
18459 _vld3q_s16(a as *const i8, 2)
18460}
18461#[doc = "Load multiple 3-element structures to three registers"]
18462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
18463#[doc = "## Safety"]
18464#[doc = " * Neon instrinsic unsafe"]
18465#[inline]
18466#[cfg(target_arch = "arm")]
18467#[target_feature(enable = "neon,v7")]
18468#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18469#[cfg_attr(test, assert_instr(vld3))]
18470pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
18471 unsafe extern "unadjusted" {
18472 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")]
18473 fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
18474 }
18475 _vld3_s32(a as *const i8, 4)
18476}
18477#[doc = "Load multiple 3-element structures to three registers"]
18478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
18479#[doc = "## Safety"]
18480#[doc = " * Neon instrinsic unsafe"]
18481#[inline]
18482#[cfg(target_arch = "arm")]
18483#[target_feature(enable = "neon,v7")]
18484#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18485#[cfg_attr(test, assert_instr(vld3))]
18486pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
18487 unsafe extern "unadjusted" {
18488 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")]
18489 fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
18490 }
18491 _vld3q_s32(a as *const i8, 4)
18492}
18493#[doc = "Load multiple 3-element structures to two registers"]
18494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
18495#[doc = "## Safety"]
18496#[doc = " * Neon instrinsic unsafe"]
18497#[inline]
18498#[target_feature(enable = "neon,v7")]
18499#[cfg(target_arch = "arm")]
18500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
18501#[rustc_legacy_const_generics(2)]
18502#[target_feature(enable = "neon,fp16")]
18503#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18504pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
18505 static_assert_uimm_bits!(LANE, 2);
18506 unsafe extern "unadjusted" {
18507 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")]
18508 fn _vld3_lane_f16(
18509 ptr: *const f16,
18510 a: float16x4_t,
18511 b: float16x4_t,
18512 c: float16x4_t,
18513 n: i32,
18514 size: i32,
18515 ) -> float16x4x3_t;
18516 }
18517 _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
18518}
18519#[doc = "Load multiple 3-element structures to two registers"]
18520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
18521#[doc = "## Safety"]
18522#[doc = " * Neon instrinsic unsafe"]
18523#[inline]
18524#[target_feature(enable = "neon,v7")]
18525#[cfg(target_arch = "arm")]
18526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
18527#[rustc_legacy_const_generics(2)]
18528#[target_feature(enable = "neon,fp16")]
18529#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18530pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
18531 static_assert_uimm_bits!(LANE, 3);
18532 unsafe extern "unadjusted" {
18533 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")]
18534 fn _vld3q_lane_f16(
18535 ptr: *const f16,
18536 a: float16x8_t,
18537 b: float16x8_t,
18538 c: float16x8_t,
18539 n: i32,
18540 size: i32,
18541 ) -> float16x8x3_t;
18542 }
18543 _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
18544}
18545#[doc = "Load multiple 3-element structures to two registers"]
18546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
18547#[doc = "## Safety"]
18548#[doc = " * Neon instrinsic unsafe"]
18549#[inline]
18550#[cfg(not(target_arch = "arm"))]
18551#[cfg_attr(
18552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18553 assert_instr(ld3, LANE = 0)
18554)]
18555#[rustc_legacy_const_generics(2)]
18556#[target_feature(enable = "neon,fp16")]
18557#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18558pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
18559 static_assert_uimm_bits!(LANE, 2);
18560 unsafe extern "unadjusted" {
18561 #[cfg_attr(
18562 any(target_arch = "aarch64", target_arch = "arm64ec"),
18563 link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0"
18564 )]
18565 fn _vld3_lane_f16(
18566 a: float16x4_t,
18567 b: float16x4_t,
18568 c: float16x4_t,
18569 n: i64,
18570 ptr: *const f16,
18571 ) -> float16x4x3_t;
18572 }
18573 _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
18574}
18575#[doc = "Load multiple 3-element structures to two registers"]
18576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
18577#[doc = "## Safety"]
18578#[doc = " * Neon instrinsic unsafe"]
18579#[inline]
18580#[cfg(not(target_arch = "arm"))]
18581#[cfg_attr(
18582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18583 assert_instr(ld3, LANE = 0)
18584)]
18585#[rustc_legacy_const_generics(2)]
18586#[target_feature(enable = "neon,fp16")]
18587#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
18588pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
18589 static_assert_uimm_bits!(LANE, 3);
18590 unsafe extern "unadjusted" {
18591 #[cfg_attr(
18592 any(target_arch = "aarch64", target_arch = "arm64ec"),
18593 link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0"
18594 )]
18595 fn _vld3q_lane_f16(
18596 a: float16x8_t,
18597 b: float16x8_t,
18598 c: float16x8_t,
18599 n: i64,
18600 ptr: *const f16,
18601 ) -> float16x8x3_t;
18602 }
18603 _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
18604}
18605#[doc = "Load multiple 3-element structures to three registers"]
18606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
18607#[doc = "## Safety"]
18608#[doc = " * Neon instrinsic unsafe"]
18609#[inline]
18610#[target_feature(enable = "neon")]
18611#[cfg(not(target_arch = "arm"))]
18612#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18613#[rustc_legacy_const_generics(2)]
18614#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18615pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
18616 static_assert_uimm_bits!(LANE, 1);
18617 unsafe extern "unadjusted" {
18618 #[cfg_attr(
18619 any(target_arch = "aarch64", target_arch = "arm64ec"),
18620 link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0"
18621 )]
18622 fn _vld3_lane_f32(
18623 a: float32x2_t,
18624 b: float32x2_t,
18625 c: float32x2_t,
18626 n: i64,
18627 ptr: *const i8,
18628 ) -> float32x2x3_t;
18629 }
18630 _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
18631}
18632#[doc = "Load multiple 3-element structures to three registers"]
18633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
18634#[doc = "## Safety"]
18635#[doc = " * Neon instrinsic unsafe"]
18636#[inline]
18637#[target_feature(enable = "neon")]
18638#[cfg(not(target_arch = "arm"))]
18639#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18640#[rustc_legacy_const_generics(2)]
18641#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18642pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
18643 static_assert_uimm_bits!(LANE, 2);
18644 unsafe extern "unadjusted" {
18645 #[cfg_attr(
18646 any(target_arch = "aarch64", target_arch = "arm64ec"),
18647 link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0"
18648 )]
18649 fn _vld3q_lane_f32(
18650 a: float32x4_t,
18651 b: float32x4_t,
18652 c: float32x4_t,
18653 n: i64,
18654 ptr: *const i8,
18655 ) -> float32x4x3_t;
18656 }
18657 _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
18658}
18659#[doc = "Load multiple 3-element structures to three registers"]
18660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
18661#[doc = "## Safety"]
18662#[doc = " * Neon instrinsic unsafe"]
18663#[inline]
18664#[cfg(target_arch = "arm")]
18665#[target_feature(enable = "neon,v7")]
18666#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
18667#[rustc_legacy_const_generics(2)]
18668#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18669pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
18670 static_assert_uimm_bits!(LANE, 1);
18671 unsafe extern "unadjusted" {
18672 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")]
18673 fn _vld3_lane_f32(
18674 ptr: *const i8,
18675 a: float32x2_t,
18676 b: float32x2_t,
18677 c: float32x2_t,
18678 n: i32,
18679 size: i32,
18680 ) -> float32x2x3_t;
18681 }
18682 _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
18683}
18684#[doc = "Load multiple 3-element structures to two registers"]
18685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
18686#[doc = "## Safety"]
18687#[doc = " * Neon instrinsic unsafe"]
18688#[inline]
18689#[target_feature(enable = "neon")]
18690#[cfg(not(target_arch = "arm"))]
18691#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18692#[rustc_legacy_const_generics(2)]
18693#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18694pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
18695 static_assert_uimm_bits!(LANE, 3);
18696 unsafe extern "unadjusted" {
18697 #[cfg_attr(
18698 any(target_arch = "aarch64", target_arch = "arm64ec"),
18699 link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0"
18700 )]
18701 fn _vld3_lane_s8(
18702 a: int8x8_t,
18703 b: int8x8_t,
18704 c: int8x8_t,
18705 n: i64,
18706 ptr: *const i8,
18707 ) -> int8x8x3_t;
18708 }
18709 _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
18710}
18711#[doc = "Load multiple 3-element structures to two registers"]
18712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
18713#[doc = "## Safety"]
18714#[doc = " * Neon instrinsic unsafe"]
18715#[inline]
18716#[target_feature(enable = "neon")]
18717#[cfg(not(target_arch = "arm"))]
18718#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18719#[rustc_legacy_const_generics(2)]
18720#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18721pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
18722 static_assert_uimm_bits!(LANE, 2);
18723 unsafe extern "unadjusted" {
18724 #[cfg_attr(
18725 any(target_arch = "aarch64", target_arch = "arm64ec"),
18726 link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0"
18727 )]
18728 fn _vld3_lane_s16(
18729 a: int16x4_t,
18730 b: int16x4_t,
18731 c: int16x4_t,
18732 n: i64,
18733 ptr: *const i8,
18734 ) -> int16x4x3_t;
18735 }
18736 _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
18737}
18738#[doc = "Load multiple 3-element structures to two registers"]
18739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
18740#[doc = "## Safety"]
18741#[doc = " * Neon instrinsic unsafe"]
18742#[inline]
18743#[target_feature(enable = "neon")]
18744#[cfg(not(target_arch = "arm"))]
18745#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18746#[rustc_legacy_const_generics(2)]
18747#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18748pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
18749 static_assert_uimm_bits!(LANE, 4);
18750 unsafe extern "unadjusted" {
18751 #[cfg_attr(
18752 any(target_arch = "aarch64", target_arch = "arm64ec"),
18753 link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0"
18754 )]
18755 fn _vld3q_lane_s16(
18756 a: int16x8_t,
18757 b: int16x8_t,
18758 c: int16x8_t,
18759 n: i64,
18760 ptr: *const i8,
18761 ) -> int16x8x3_t;
18762 }
18763 _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
18764}
18765#[doc = "Load multiple 3-element structures to two registers"]
18766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
18767#[doc = "## Safety"]
18768#[doc = " * Neon instrinsic unsafe"]
18769#[inline]
18770#[target_feature(enable = "neon")]
18771#[cfg(not(target_arch = "arm"))]
18772#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18773#[rustc_legacy_const_generics(2)]
18774#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18775pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
18776 static_assert_uimm_bits!(LANE, 1);
18777 unsafe extern "unadjusted" {
18778 #[cfg_attr(
18779 any(target_arch = "aarch64", target_arch = "arm64ec"),
18780 link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0"
18781 )]
18782 fn _vld3_lane_s32(
18783 a: int32x2_t,
18784 b: int32x2_t,
18785 c: int32x2_t,
18786 n: i64,
18787 ptr: *const i8,
18788 ) -> int32x2x3_t;
18789 }
18790 _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
18791}
18792#[doc = "Load multiple 3-element structures to two registers"]
18793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
18794#[doc = "## Safety"]
18795#[doc = " * Neon instrinsic unsafe"]
18796#[inline]
18797#[target_feature(enable = "neon")]
18798#[cfg(not(target_arch = "arm"))]
18799#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
18800#[rustc_legacy_const_generics(2)]
18801#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18802pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
18803 static_assert_uimm_bits!(LANE, 2);
18804 unsafe extern "unadjusted" {
18805 #[cfg_attr(
18806 any(target_arch = "aarch64", target_arch = "arm64ec"),
18807 link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0"
18808 )]
18809 fn _vld3q_lane_s32(
18810 a: int32x4_t,
18811 b: int32x4_t,
18812 c: int32x4_t,
18813 n: i64,
18814 ptr: *const i8,
18815 ) -> int32x4x3_t;
18816 }
18817 _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
18818}
18819#[doc = "Load multiple 3-element structures to two registers"]
18820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
18821#[doc = "## Safety"]
18822#[doc = " * Neon instrinsic unsafe"]
18823#[inline]
18824#[cfg(target_arch = "arm")]
18825#[target_feature(enable = "neon,v7")]
18826#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
18827#[rustc_legacy_const_generics(2)]
18828#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18829pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
18830 static_assert_uimm_bits!(LANE, 3);
18831 unsafe extern "unadjusted" {
18832 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")]
18833 fn _vld3_lane_s8(
18834 ptr: *const i8,
18835 a: int8x8_t,
18836 b: int8x8_t,
18837 c: int8x8_t,
18838 n: i32,
18839 size: i32,
18840 ) -> int8x8x3_t;
18841 }
18842 _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
18843}
18844#[doc = "Load multiple 3-element structures to two registers"]
18845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
18846#[doc = "## Safety"]
18847#[doc = " * Neon instrinsic unsafe"]
18848#[inline]
18849#[cfg(target_arch = "arm")]
18850#[target_feature(enable = "neon,v7")]
18851#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
18852#[rustc_legacy_const_generics(2)]
18853#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18854pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
18855 static_assert_uimm_bits!(LANE, 2);
18856 unsafe extern "unadjusted" {
18857 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")]
18858 fn _vld3_lane_s16(
18859 ptr: *const i8,
18860 a: int16x4_t,
18861 b: int16x4_t,
18862 c: int16x4_t,
18863 n: i32,
18864 size: i32,
18865 ) -> int16x4x3_t;
18866 }
18867 _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
18868}
18869#[doc = "Load multiple 3-element structures to two registers"]
18870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
18871#[doc = "## Safety"]
18872#[doc = " * Neon instrinsic unsafe"]
18873#[inline]
18874#[cfg(target_arch = "arm")]
18875#[target_feature(enable = "neon,v7")]
18876#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
18877#[rustc_legacy_const_generics(2)]
18878#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18879pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
18880 static_assert_uimm_bits!(LANE, 3);
18881 unsafe extern "unadjusted" {
18882 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")]
18883 fn _vld3q_lane_s16(
18884 ptr: *const i8,
18885 a: int16x8_t,
18886 b: int16x8_t,
18887 c: int16x8_t,
18888 n: i32,
18889 size: i32,
18890 ) -> int16x8x3_t;
18891 }
18892 _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
18893}
18894#[doc = "Load multiple 3-element structures to two registers"]
18895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
18896#[doc = "## Safety"]
18897#[doc = " * Neon instrinsic unsafe"]
18898#[inline]
18899#[cfg(target_arch = "arm")]
18900#[target_feature(enable = "neon,v7")]
18901#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
18902#[rustc_legacy_const_generics(2)]
18903#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18904pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
18905 static_assert_uimm_bits!(LANE, 1);
18906 unsafe extern "unadjusted" {
18907 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")]
18908 fn _vld3_lane_s32(
18909 ptr: *const i8,
18910 a: int32x2_t,
18911 b: int32x2_t,
18912 c: int32x2_t,
18913 n: i32,
18914 size: i32,
18915 ) -> int32x2x3_t;
18916 }
18917 _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
18918}
18919#[doc = "Load multiple 3-element structures to two registers"]
18920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
18921#[doc = "## Safety"]
18922#[doc = " * Neon instrinsic unsafe"]
18923#[inline]
18924#[cfg(target_arch = "arm")]
18925#[target_feature(enable = "neon,v7")]
18926#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
18927#[rustc_legacy_const_generics(2)]
18928#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
18929pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
18930 static_assert_uimm_bits!(LANE, 2);
18931 unsafe extern "unadjusted" {
18932 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")]
18933 fn _vld3q_lane_s32(
18934 ptr: *const i8,
18935 a: int32x4_t,
18936 b: int32x4_t,
18937 c: int32x4_t,
18938 n: i32,
18939 size: i32,
18940 ) -> int32x4x3_t;
18941 }
18942 _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
18943}
18944#[doc = "Load multiple 3-element structures to three registers"]
18945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
18946#[doc = "## Safety"]
18947#[doc = " * Neon instrinsic unsafe"]
18948#[inline]
18949#[target_feature(enable = "neon")]
18950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
18952#[cfg_attr(
18953 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18954 assert_instr(ld3, LANE = 0)
18955)]
18956#[rustc_legacy_const_generics(2)]
18957#[cfg_attr(
18958 not(target_arch = "arm"),
18959 stable(feature = "neon_intrinsics", since = "1.59.0")
18960)]
18961#[cfg_attr(
18962 target_arch = "arm",
18963 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18964)]
18965pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t {
18966 static_assert_uimm_bits!(LANE, 3);
18967 transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
18968}
18969#[doc = "Load multiple 3-element structures to three registers"]
18970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
18971#[doc = "## Safety"]
18972#[doc = " * Neon instrinsic unsafe"]
18973#[inline]
18974#[target_feature(enable = "neon")]
18975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
18977#[cfg_attr(
18978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18979 assert_instr(ld3, LANE = 0)
18980)]
18981#[rustc_legacy_const_generics(2)]
18982#[cfg_attr(
18983 not(target_arch = "arm"),
18984 stable(feature = "neon_intrinsics", since = "1.59.0")
18985)]
18986#[cfg_attr(
18987 target_arch = "arm",
18988 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18989)]
18990pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t {
18991 static_assert_uimm_bits!(LANE, 2);
18992 transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
18993}
18994#[doc = "Load multiple 3-element structures to three registers"]
18995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
18996#[doc = "## Safety"]
18997#[doc = " * Neon instrinsic unsafe"]
18998#[inline]
18999#[target_feature(enable = "neon")]
19000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
19002#[cfg_attr(
19003 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19004 assert_instr(ld3, LANE = 0)
19005)]
19006#[rustc_legacy_const_generics(2)]
19007#[cfg_attr(
19008 not(target_arch = "arm"),
19009 stable(feature = "neon_intrinsics", since = "1.59.0")
19010)]
19011#[cfg_attr(
19012 target_arch = "arm",
19013 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19014)]
19015pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t {
19016 static_assert_uimm_bits!(LANE, 3);
19017 transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
19018}
19019#[doc = "Load multiple 3-element structures to three registers"]
19020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
19021#[doc = "## Safety"]
19022#[doc = " * Neon instrinsic unsafe"]
19023#[inline]
19024#[target_feature(enable = "neon")]
19025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
19027#[cfg_attr(
19028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19029 assert_instr(ld3, LANE = 0)
19030)]
19031#[rustc_legacy_const_generics(2)]
19032#[cfg_attr(
19033 not(target_arch = "arm"),
19034 stable(feature = "neon_intrinsics", since = "1.59.0")
19035)]
19036#[cfg_attr(
19037 target_arch = "arm",
19038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19039)]
19040pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t {
19041 static_assert_uimm_bits!(LANE, 1);
19042 transmute(vld3_lane_s32::<LANE>(transmute(a), transmute(b)))
19043}
19044#[doc = "Load multiple 3-element structures to three registers"]
19045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
19046#[doc = "## Safety"]
19047#[doc = " * Neon instrinsic unsafe"]
19048#[inline]
19049#[target_feature(enable = "neon")]
19050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
19052#[cfg_attr(
19053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19054 assert_instr(ld3, LANE = 0)
19055)]
19056#[rustc_legacy_const_generics(2)]
19057#[cfg_attr(
19058 not(target_arch = "arm"),
19059 stable(feature = "neon_intrinsics", since = "1.59.0")
19060)]
19061#[cfg_attr(
19062 target_arch = "arm",
19063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19064)]
19065pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t {
19066 static_assert_uimm_bits!(LANE, 2);
19067 transmute(vld3q_lane_s32::<LANE>(transmute(a), transmute(b)))
19068}
19069#[doc = "Load multiple 3-element structures to three registers"]
19070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
19071#[doc = "## Safety"]
19072#[doc = " * Neon instrinsic unsafe"]
19073#[inline]
19074#[target_feature(enable = "neon")]
19075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
19077#[cfg_attr(
19078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19079 assert_instr(ld3, LANE = 0)
19080)]
19081#[rustc_legacy_const_generics(2)]
19082#[cfg_attr(
19083 not(target_arch = "arm"),
19084 stable(feature = "neon_intrinsics", since = "1.59.0")
19085)]
19086#[cfg_attr(
19087 target_arch = "arm",
19088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19089)]
19090pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t {
19091 static_assert_uimm_bits!(LANE, 3);
19092 transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
19093}
19094#[doc = "Load multiple 3-element structures to three registers"]
19095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
19096#[doc = "## Safety"]
19097#[doc = " * Neon instrinsic unsafe"]
19098#[inline]
19099#[target_feature(enable = "neon")]
19100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
19102#[cfg_attr(
19103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19104 assert_instr(ld3, LANE = 0)
19105)]
19106#[rustc_legacy_const_generics(2)]
19107#[cfg_attr(
19108 not(target_arch = "arm"),
19109 stable(feature = "neon_intrinsics", since = "1.59.0")
19110)]
19111#[cfg_attr(
19112 target_arch = "arm",
19113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19114)]
19115pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t {
19116 static_assert_uimm_bits!(LANE, 2);
19117 transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
19118}
19119#[doc = "Load multiple 3-element structures to three registers"]
19120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
19121#[doc = "## Safety"]
19122#[doc = " * Neon instrinsic unsafe"]
19123#[inline]
19124#[target_feature(enable = "neon")]
19125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
19127#[cfg_attr(
19128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19129 assert_instr(ld3, LANE = 0)
19130)]
19131#[rustc_legacy_const_generics(2)]
19132#[cfg_attr(
19133 not(target_arch = "arm"),
19134 stable(feature = "neon_intrinsics", since = "1.59.0")
19135)]
19136#[cfg_attr(
19137 target_arch = "arm",
19138 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19139)]
19140pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t {
19141 static_assert_uimm_bits!(LANE, 3);
19142 transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
19143}
19144#[doc = "Load multiple 3-element structures to three registers"]
19145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
19146#[doc = "## Safety"]
19147#[doc = " * Neon instrinsic unsafe"]
19148#[inline]
19149#[target_feature(enable = "neon,aes")]
19150#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
19151#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19152#[cfg_attr(
19153 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19154 assert_instr(nop)
19155)]
19156#[cfg_attr(
19157 not(target_arch = "arm"),
19158 stable(feature = "neon_intrinsics", since = "1.59.0")
19159)]
19160#[cfg_attr(
19161 target_arch = "arm",
19162 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19163)]
19164pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
19165 transmute(vld3_s64(transmute(a)))
19166}
19167#[doc = "Load multiple 3-element structures to three registers"]
19168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
19169#[doc = "## Safety"]
19170#[doc = " * Neon instrinsic unsafe"]
19171#[inline]
19172#[target_feature(enable = "neon")]
19173#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19174#[cfg(not(target_arch = "arm"))]
19175#[cfg_attr(test, assert_instr(nop))]
19176pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
19177 unsafe extern "unadjusted" {
19178 #[cfg_attr(
19179 any(target_arch = "aarch64", target_arch = "arm64ec"),
19180 link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
19181 )]
19182 fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
19183 }
19184 _vld3_s64(a as _)
19185}
19186#[doc = "Load multiple 3-element structures to three registers"]
19187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
19188#[doc = "## Safety"]
19189#[doc = " * Neon instrinsic unsafe"]
19190#[inline]
19191#[cfg(target_arch = "arm")]
19192#[target_feature(enable = "neon,v7")]
19193#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19194#[cfg_attr(test, assert_instr(nop))]
19195pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
19196 unsafe extern "unadjusted" {
19197 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")]
19198 fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
19199 }
19200 _vld3_s64(a as *const i8, 8)
19201}
19202#[doc = "Load multiple 3-element structures to three registers"]
19203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
19204#[doc = "## Safety"]
19205#[doc = " * Neon instrinsic unsafe"]
19206#[inline]
19207#[target_feature(enable = "neon")]
19208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19210#[cfg_attr(
19211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19212 assert_instr(nop)
19213)]
19214#[cfg_attr(
19215 not(target_arch = "arm"),
19216 stable(feature = "neon_intrinsics", since = "1.59.0")
19217)]
19218#[cfg_attr(
19219 target_arch = "arm",
19220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19221)]
19222pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
19223 transmute(vld3_s64(transmute(a)))
19224}
19225#[doc = "Load multiple 3-element structures to three registers"]
19226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
19227#[doc = "## Safety"]
19228#[doc = " * Neon instrinsic unsafe"]
19229#[inline]
19230#[cfg(target_endian = "little")]
19231#[target_feature(enable = "neon")]
19232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19234#[cfg_attr(
19235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19236 assert_instr(ld3)
19237)]
19238#[cfg_attr(
19239 not(target_arch = "arm"),
19240 stable(feature = "neon_intrinsics", since = "1.59.0")
19241)]
19242#[cfg_attr(
19243 target_arch = "arm",
19244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19245)]
19246pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
19247 transmute(vld3_s8(transmute(a)))
19248}
19249#[doc = "Load multiple 3-element structures to three registers"]
19250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
19251#[doc = "## Safety"]
19252#[doc = " * Neon instrinsic unsafe"]
19253#[inline]
19254#[cfg(target_endian = "big")]
19255#[target_feature(enable = "neon")]
19256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19258#[cfg_attr(
19259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19260 assert_instr(ld3)
19261)]
19262#[cfg_attr(
19263 not(target_arch = "arm"),
19264 stable(feature = "neon_intrinsics", since = "1.59.0")
19265)]
19266#[cfg_attr(
19267 target_arch = "arm",
19268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19269)]
19270pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
19271 let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a)));
19272 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19273 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19274 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19275 ret_val
19276}
19277#[doc = "Load multiple 3-element structures to three registers"]
19278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
19279#[doc = "## Safety"]
19280#[doc = " * Neon instrinsic unsafe"]
19281#[inline]
19282#[cfg(target_endian = "little")]
19283#[target_feature(enable = "neon")]
19284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19285#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19286#[cfg_attr(
19287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19288 assert_instr(ld3)
19289)]
19290#[cfg_attr(
19291 not(target_arch = "arm"),
19292 stable(feature = "neon_intrinsics", since = "1.59.0")
19293)]
19294#[cfg_attr(
19295 target_arch = "arm",
19296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19297)]
19298pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
19299 transmute(vld3q_s8(transmute(a)))
19300}
19301#[doc = "Load multiple 3-element structures to three registers"]
19302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
19303#[doc = "## Safety"]
19304#[doc = " * Neon instrinsic unsafe"]
19305#[inline]
19306#[cfg(target_endian = "big")]
19307#[target_feature(enable = "neon")]
19308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19310#[cfg_attr(
19311 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19312 assert_instr(ld3)
19313)]
19314#[cfg_attr(
19315 not(target_arch = "arm"),
19316 stable(feature = "neon_intrinsics", since = "1.59.0")
19317)]
19318#[cfg_attr(
19319 target_arch = "arm",
19320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19321)]
19322pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
19323 let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a)));
19324 ret_val.0 = unsafe {
19325 simd_shuffle!(
19326 ret_val.0,
19327 ret_val.0,
19328 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19329 )
19330 };
19331 ret_val.1 = unsafe {
19332 simd_shuffle!(
19333 ret_val.1,
19334 ret_val.1,
19335 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19336 )
19337 };
19338 ret_val.2 = unsafe {
19339 simd_shuffle!(
19340 ret_val.2,
19341 ret_val.2,
19342 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19343 )
19344 };
19345 ret_val
19346}
19347#[doc = "Load multiple 3-element structures to three registers"]
19348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
19349#[doc = "## Safety"]
19350#[doc = " * Neon instrinsic unsafe"]
19351#[inline]
19352#[cfg(target_endian = "little")]
19353#[target_feature(enable = "neon")]
19354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19356#[cfg_attr(
19357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19358 assert_instr(ld3)
19359)]
19360#[cfg_attr(
19361 not(target_arch = "arm"),
19362 stable(feature = "neon_intrinsics", since = "1.59.0")
19363)]
19364#[cfg_attr(
19365 target_arch = "arm",
19366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19367)]
19368pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
19369 transmute(vld3_s16(transmute(a)))
19370}
19371#[doc = "Load multiple 3-element structures to three registers"]
19372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
19373#[doc = "## Safety"]
19374#[doc = " * Neon instrinsic unsafe"]
19375#[inline]
19376#[cfg(target_endian = "big")]
19377#[target_feature(enable = "neon")]
19378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19380#[cfg_attr(
19381 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19382 assert_instr(ld3)
19383)]
19384#[cfg_attr(
19385 not(target_arch = "arm"),
19386 stable(feature = "neon_intrinsics", since = "1.59.0")
19387)]
19388#[cfg_attr(
19389 target_arch = "arm",
19390 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19391)]
19392pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
19393 let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a)));
19394 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19395 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19396 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19397 ret_val
19398}
19399#[doc = "Load multiple 3-element structures to three registers"]
19400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
19401#[doc = "## Safety"]
19402#[doc = " * Neon instrinsic unsafe"]
19403#[inline]
19404#[cfg(target_endian = "little")]
19405#[target_feature(enable = "neon")]
19406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19408#[cfg_attr(
19409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19410 assert_instr(ld3)
19411)]
19412#[cfg_attr(
19413 not(target_arch = "arm"),
19414 stable(feature = "neon_intrinsics", since = "1.59.0")
19415)]
19416#[cfg_attr(
19417 target_arch = "arm",
19418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19419)]
19420pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
19421 transmute(vld3q_s16(transmute(a)))
19422}
19423#[doc = "Load multiple 3-element structures to three registers"]
19424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
19425#[doc = "## Safety"]
19426#[doc = " * Neon instrinsic unsafe"]
19427#[inline]
19428#[cfg(target_endian = "big")]
19429#[target_feature(enable = "neon")]
19430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19432#[cfg_attr(
19433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19434 assert_instr(ld3)
19435)]
19436#[cfg_attr(
19437 not(target_arch = "arm"),
19438 stable(feature = "neon_intrinsics", since = "1.59.0")
19439)]
19440#[cfg_attr(
19441 target_arch = "arm",
19442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19443)]
19444pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
19445 let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a)));
19446 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19447 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19448 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19449 ret_val
19450}
19451#[doc = "Load multiple 3-element structures to three registers"]
19452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
19453#[doc = "## Safety"]
19454#[doc = " * Neon instrinsic unsafe"]
19455#[inline]
19456#[cfg(target_endian = "little")]
19457#[target_feature(enable = "neon")]
19458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19460#[cfg_attr(
19461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19462 assert_instr(ld3)
19463)]
19464#[cfg_attr(
19465 not(target_arch = "arm"),
19466 stable(feature = "neon_intrinsics", since = "1.59.0")
19467)]
19468#[cfg_attr(
19469 target_arch = "arm",
19470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19471)]
19472pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
19473 transmute(vld3_s32(transmute(a)))
19474}
19475#[doc = "Load multiple 3-element structures to three registers"]
19476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
19477#[doc = "## Safety"]
19478#[doc = " * Neon instrinsic unsafe"]
19479#[inline]
19480#[cfg(target_endian = "big")]
19481#[target_feature(enable = "neon")]
19482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19484#[cfg_attr(
19485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19486 assert_instr(ld3)
19487)]
19488#[cfg_attr(
19489 not(target_arch = "arm"),
19490 stable(feature = "neon_intrinsics", since = "1.59.0")
19491)]
19492#[cfg_attr(
19493 target_arch = "arm",
19494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19495)]
19496pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
19497 let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a)));
19498 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
19499 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
19500 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
19501 ret_val
19502}
19503#[doc = "Load multiple 3-element structures to three registers"]
19504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
19505#[doc = "## Safety"]
19506#[doc = " * Neon instrinsic unsafe"]
19507#[inline]
19508#[cfg(target_endian = "little")]
19509#[target_feature(enable = "neon")]
19510#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19511#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19512#[cfg_attr(
19513 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19514 assert_instr(ld3)
19515)]
19516#[cfg_attr(
19517 not(target_arch = "arm"),
19518 stable(feature = "neon_intrinsics", since = "1.59.0")
19519)]
19520#[cfg_attr(
19521 target_arch = "arm",
19522 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19523)]
19524pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
19525 transmute(vld3q_s32(transmute(a)))
19526}
19527#[doc = "Load multiple 3-element structures to three registers"]
19528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
19529#[doc = "## Safety"]
19530#[doc = " * Neon instrinsic unsafe"]
19531#[inline]
19532#[cfg(target_endian = "big")]
19533#[target_feature(enable = "neon")]
19534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19536#[cfg_attr(
19537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19538 assert_instr(ld3)
19539)]
19540#[cfg_attr(
19541 not(target_arch = "arm"),
19542 stable(feature = "neon_intrinsics", since = "1.59.0")
19543)]
19544#[cfg_attr(
19545 target_arch = "arm",
19546 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19547)]
19548pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
19549 let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a)));
19550 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19551 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19552 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19553 ret_val
19554}
19555#[doc = "Load multiple 3-element structures to three registers"]
19556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
19557#[doc = "## Safety"]
19558#[doc = " * Neon instrinsic unsafe"]
19559#[inline]
19560#[cfg(target_endian = "little")]
19561#[target_feature(enable = "neon")]
19562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19564#[cfg_attr(
19565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19566 assert_instr(ld3)
19567)]
19568#[cfg_attr(
19569 not(target_arch = "arm"),
19570 stable(feature = "neon_intrinsics", since = "1.59.0")
19571)]
19572#[cfg_attr(
19573 target_arch = "arm",
19574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19575)]
19576pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
19577 transmute(vld3_s8(transmute(a)))
19578}
19579#[doc = "Load multiple 3-element structures to three registers"]
19580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
19581#[doc = "## Safety"]
19582#[doc = " * Neon instrinsic unsafe"]
19583#[inline]
19584#[cfg(target_endian = "big")]
19585#[target_feature(enable = "neon")]
19586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19588#[cfg_attr(
19589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19590 assert_instr(ld3)
19591)]
19592#[cfg_attr(
19593 not(target_arch = "arm"),
19594 stable(feature = "neon_intrinsics", since = "1.59.0")
19595)]
19596#[cfg_attr(
19597 target_arch = "arm",
19598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19599)]
19600pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
19601 let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a)));
19602 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19603 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19604 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19605 ret_val
19606}
19607#[doc = "Load multiple 3-element structures to three registers"]
19608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
19609#[doc = "## Safety"]
19610#[doc = " * Neon instrinsic unsafe"]
19611#[inline]
19612#[cfg(target_endian = "little")]
19613#[target_feature(enable = "neon")]
19614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19615#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19616#[cfg_attr(
19617 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19618 assert_instr(ld3)
19619)]
19620#[cfg_attr(
19621 not(target_arch = "arm"),
19622 stable(feature = "neon_intrinsics", since = "1.59.0")
19623)]
19624#[cfg_attr(
19625 target_arch = "arm",
19626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19627)]
19628pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
19629 transmute(vld3q_s8(transmute(a)))
19630}
19631#[doc = "Load multiple 3-element structures to three registers"]
19632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
19633#[doc = "## Safety"]
19634#[doc = " * Neon instrinsic unsafe"]
19635#[inline]
19636#[cfg(target_endian = "big")]
19637#[target_feature(enable = "neon")]
19638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19640#[cfg_attr(
19641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19642 assert_instr(ld3)
19643)]
19644#[cfg_attr(
19645 not(target_arch = "arm"),
19646 stable(feature = "neon_intrinsics", since = "1.59.0")
19647)]
19648#[cfg_attr(
19649 target_arch = "arm",
19650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19651)]
19652pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
19653 let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a)));
19654 ret_val.0 = unsafe {
19655 simd_shuffle!(
19656 ret_val.0,
19657 ret_val.0,
19658 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19659 )
19660 };
19661 ret_val.1 = unsafe {
19662 simd_shuffle!(
19663 ret_val.1,
19664 ret_val.1,
19665 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19666 )
19667 };
19668 ret_val.2 = unsafe {
19669 simd_shuffle!(
19670 ret_val.2,
19671 ret_val.2,
19672 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19673 )
19674 };
19675 ret_val
19676}
19677#[doc = "Load multiple 3-element structures to three registers"]
19678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
19679#[doc = "## Safety"]
19680#[doc = " * Neon instrinsic unsafe"]
19681#[inline]
19682#[cfg(target_endian = "little")]
19683#[target_feature(enable = "neon")]
19684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19686#[cfg_attr(
19687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19688 assert_instr(ld3)
19689)]
19690#[cfg_attr(
19691 not(target_arch = "arm"),
19692 stable(feature = "neon_intrinsics", since = "1.59.0")
19693)]
19694#[cfg_attr(
19695 target_arch = "arm",
19696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19697)]
19698pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
19699 transmute(vld3_s16(transmute(a)))
19700}
19701#[doc = "Load multiple 3-element structures to three registers"]
19702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
19703#[doc = "## Safety"]
19704#[doc = " * Neon instrinsic unsafe"]
19705#[inline]
19706#[cfg(target_endian = "big")]
19707#[target_feature(enable = "neon")]
19708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19710#[cfg_attr(
19711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19712 assert_instr(ld3)
19713)]
19714#[cfg_attr(
19715 not(target_arch = "arm"),
19716 stable(feature = "neon_intrinsics", since = "1.59.0")
19717)]
19718#[cfg_attr(
19719 target_arch = "arm",
19720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19721)]
19722pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
19723 let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a)));
19724 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19725 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19726 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19727 ret_val
19728}
19729#[doc = "Load multiple 3-element structures to three registers"]
19730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
19731#[doc = "## Safety"]
19732#[doc = " * Neon instrinsic unsafe"]
19733#[inline]
19734#[cfg(target_endian = "little")]
19735#[target_feature(enable = "neon")]
19736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19738#[cfg_attr(
19739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19740 assert_instr(ld3)
19741)]
19742#[cfg_attr(
19743 not(target_arch = "arm"),
19744 stable(feature = "neon_intrinsics", since = "1.59.0")
19745)]
19746#[cfg_attr(
19747 target_arch = "arm",
19748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19749)]
19750pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
19751 transmute(vld3q_s16(transmute(a)))
19752}
19753#[doc = "Load multiple 3-element structures to three registers"]
19754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
19755#[doc = "## Safety"]
19756#[doc = " * Neon instrinsic unsafe"]
19757#[inline]
19758#[cfg(target_endian = "big")]
19759#[target_feature(enable = "neon")]
19760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
19762#[cfg_attr(
19763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19764 assert_instr(ld3)
19765)]
19766#[cfg_attr(
19767 not(target_arch = "arm"),
19768 stable(feature = "neon_intrinsics", since = "1.59.0")
19769)]
19770#[cfg_attr(
19771 target_arch = "arm",
19772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19773)]
19774pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
19775 let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a)));
19776 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19777 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19778 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19779 ret_val
19780}
19781#[doc = "Load multiple 3-element structures to three registers"]
19782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
19783#[doc = "## Safety"]
19784#[doc = " * Neon instrinsic unsafe"]
19785#[inline]
19786#[cfg(target_arch = "arm")]
19787#[target_feature(enable = "neon,v7")]
19788#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
19789#[rustc_legacy_const_generics(2)]
19790#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19791pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
19792 static_assert_uimm_bits!(LANE, 2);
19793 unsafe extern "unadjusted" {
19794 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
19795 fn _vld3q_lane_f32(
19796 ptr: *const i8,
19797 a: float32x4_t,
19798 b: float32x4_t,
19799 c: float32x4_t,
19800 n: i32,
19801 size: i32,
19802 ) -> float32x4x3_t;
19803 }
19804 _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
19805}
19806#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
19807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
19808#[doc = "## Safety"]
19809#[doc = " * Neon instrinsic unsafe"]
19810#[inline]
19811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19812#[cfg(target_arch = "arm")]
19813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
19814#[target_feature(enable = "neon,fp16")]
19815#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19816pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
19817 unsafe extern "unadjusted" {
19818 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0f16")]
19819 fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
19820 }
19821 _vld4_dup_f16(a as _, 2)
19822}
19823#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
19824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
19825#[doc = "## Safety"]
19826#[doc = " * Neon instrinsic unsafe"]
19827#[inline]
19828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19829#[cfg(target_arch = "arm")]
19830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
19831#[target_feature(enable = "neon,fp16")]
19832#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19833pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
19834 unsafe extern "unadjusted" {
19835 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0f16")]
19836 fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
19837 }
19838 _vld4q_dup_f16(a as _, 2)
19839}
19840#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
19841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
19842#[doc = "## Safety"]
19843#[doc = " * Neon instrinsic unsafe"]
19844#[inline]
19845#[cfg(not(target_arch = "arm"))]
19846#[cfg_attr(
19847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19848 assert_instr(ld4r)
19849)]
19850#[target_feature(enable = "neon,fp16")]
19851#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19852pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
19853 unsafe extern "unadjusted" {
19854 #[cfg_attr(
19855 any(target_arch = "aarch64", target_arch = "arm64ec"),
19856 link_name = "llvm.aarch64.neon.ld4r.v4f16.p0f16"
19857 )]
19858 fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
19859 }
19860 _vld4_dup_f16(a as _)
19861}
19862#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
19863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
19864#[doc = "## Safety"]
19865#[doc = " * Neon instrinsic unsafe"]
19866#[inline]
19867#[cfg(not(target_arch = "arm"))]
19868#[cfg_attr(
19869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19870 assert_instr(ld4r)
19871)]
19872#[target_feature(enable = "neon,fp16")]
19873#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19874pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
19875 unsafe extern "unadjusted" {
19876 #[cfg_attr(
19877 any(target_arch = "aarch64", target_arch = "arm64ec"),
19878 link_name = "llvm.aarch64.neon.ld4r.v8f16.p0f16"
19879 )]
19880 fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
19881 }
19882 _vld4q_dup_f16(a as _)
19883}
19884#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
19886#[doc = "## Safety"]
19887#[doc = " * Neon instrinsic unsafe"]
19888#[inline]
19889#[cfg(target_arch = "arm")]
19890#[target_feature(enable = "neon,v7")]
19891#[cfg_attr(test, assert_instr(vld4))]
19892#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19893pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
19894 unsafe extern "unadjusted" {
19895 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")]
19896 fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
19897 }
19898 _vld4_dup_f32(a as *const i8, 4)
19899}
19900#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
19902#[doc = "## Safety"]
19903#[doc = " * Neon instrinsic unsafe"]
19904#[inline]
19905#[cfg(target_arch = "arm")]
19906#[target_feature(enable = "neon,v7")]
19907#[cfg_attr(test, assert_instr(vld4))]
19908#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19909pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
19910 unsafe extern "unadjusted" {
19911 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")]
19912 fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
19913 }
19914 _vld4q_dup_f32(a as *const i8, 4)
19915}
19916#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
19918#[doc = "## Safety"]
19919#[doc = " * Neon instrinsic unsafe"]
19920#[inline]
19921#[cfg(target_arch = "arm")]
19922#[target_feature(enable = "neon,v7")]
19923#[cfg_attr(test, assert_instr(vld4))]
19924#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19925pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
19926 unsafe extern "unadjusted" {
19927 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")]
19928 fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
19929 }
19930 _vld4_dup_s8(a as *const i8, 1)
19931}
19932#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
19934#[doc = "## Safety"]
19935#[doc = " * Neon instrinsic unsafe"]
19936#[inline]
19937#[cfg(target_arch = "arm")]
19938#[target_feature(enable = "neon,v7")]
19939#[cfg_attr(test, assert_instr(vld4))]
19940#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19941pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
19942 unsafe extern "unadjusted" {
19943 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")]
19944 fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
19945 }
19946 _vld4q_dup_s8(a as *const i8, 1)
19947}
19948#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
19950#[doc = "## Safety"]
19951#[doc = " * Neon instrinsic unsafe"]
19952#[inline]
19953#[cfg(target_arch = "arm")]
19954#[target_feature(enable = "neon,v7")]
19955#[cfg_attr(test, assert_instr(vld4))]
19956#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19957pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
19958 unsafe extern "unadjusted" {
19959 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")]
19960 fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
19961 }
19962 _vld4_dup_s16(a as *const i8, 2)
19963}
19964#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
19966#[doc = "## Safety"]
19967#[doc = " * Neon instrinsic unsafe"]
19968#[inline]
19969#[cfg(target_arch = "arm")]
19970#[target_feature(enable = "neon,v7")]
19971#[cfg_attr(test, assert_instr(vld4))]
19972#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19973pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
19974 unsafe extern "unadjusted" {
19975 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")]
19976 fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
19977 }
19978 _vld4q_dup_s16(a as *const i8, 2)
19979}
19980#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
19982#[doc = "## Safety"]
19983#[doc = " * Neon instrinsic unsafe"]
19984#[inline]
19985#[cfg(target_arch = "arm")]
19986#[target_feature(enable = "neon,v7")]
19987#[cfg_attr(test, assert_instr(vld4))]
19988#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19989pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
19990 unsafe extern "unadjusted" {
19991 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")]
19992 fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
19993 }
19994 _vld4_dup_s32(a as *const i8, 4)
19995}
19996#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
19997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
19998#[doc = "## Safety"]
19999#[doc = " * Neon instrinsic unsafe"]
20000#[inline]
20001#[cfg(target_arch = "arm")]
20002#[target_feature(enable = "neon,v7")]
20003#[cfg_attr(test, assert_instr(vld4))]
20004#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20005pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
20006 unsafe extern "unadjusted" {
20007 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")]
20008 fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
20009 }
20010 _vld4q_dup_s32(a as *const i8, 4)
20011}
20012#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
20014#[doc = "## Safety"]
20015#[doc = " * Neon instrinsic unsafe"]
20016#[inline]
20017#[target_feature(enable = "neon")]
20018#[cfg(not(target_arch = "arm"))]
20019#[cfg_attr(test, assert_instr(ld4r))]
20020#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20021pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
20022 unsafe extern "unadjusted" {
20023 #[cfg_attr(
20024 any(target_arch = "aarch64", target_arch = "arm64ec"),
20025 link_name = "llvm.aarch64.neon.ld4r.v2f32.p0f32.p0"
20026 )]
20027 fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t;
20028 }
20029 _vld4_dup_f32(a as _)
20030}
20031#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
20033#[doc = "## Safety"]
20034#[doc = " * Neon instrinsic unsafe"]
20035#[inline]
20036#[target_feature(enable = "neon")]
20037#[cfg(not(target_arch = "arm"))]
20038#[cfg_attr(test, assert_instr(ld4r))]
20039#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20040pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
20041 unsafe extern "unadjusted" {
20042 #[cfg_attr(
20043 any(target_arch = "aarch64", target_arch = "arm64ec"),
20044 link_name = "llvm.aarch64.neon.ld4r.v4f32.p0f32.p0"
20045 )]
20046 fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t;
20047 }
20048 _vld4q_dup_f32(a as _)
20049}
20050#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
20052#[doc = "## Safety"]
20053#[doc = " * Neon instrinsic unsafe"]
20054#[inline]
20055#[target_feature(enable = "neon")]
20056#[cfg(not(target_arch = "arm"))]
20057#[cfg_attr(test, assert_instr(ld4r))]
20058#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20059pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
20060 unsafe extern "unadjusted" {
20061 #[cfg_attr(
20062 any(target_arch = "aarch64", target_arch = "arm64ec"),
20063 link_name = "llvm.aarch64.neon.ld4r.v8i8.p0i8.p0"
20064 )]
20065 fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t;
20066 }
20067 _vld4_dup_s8(a as _)
20068}
20069#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
20071#[doc = "## Safety"]
20072#[doc = " * Neon instrinsic unsafe"]
20073#[inline]
20074#[target_feature(enable = "neon")]
20075#[cfg(not(target_arch = "arm"))]
20076#[cfg_attr(test, assert_instr(ld4r))]
20077#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20078pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
20079 unsafe extern "unadjusted" {
20080 #[cfg_attr(
20081 any(target_arch = "aarch64", target_arch = "arm64ec"),
20082 link_name = "llvm.aarch64.neon.ld4r.v16i8.p0i8.p0"
20083 )]
20084 fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t;
20085 }
20086 _vld4q_dup_s8(a as _)
20087}
20088#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
20090#[doc = "## Safety"]
20091#[doc = " * Neon instrinsic unsafe"]
20092#[inline]
20093#[target_feature(enable = "neon")]
20094#[cfg(not(target_arch = "arm"))]
20095#[cfg_attr(test, assert_instr(ld4r))]
20096#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20097pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
20098 unsafe extern "unadjusted" {
20099 #[cfg_attr(
20100 any(target_arch = "aarch64", target_arch = "arm64ec"),
20101 link_name = "llvm.aarch64.neon.ld4r.v4i16.p0i16.p0"
20102 )]
20103 fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t;
20104 }
20105 _vld4_dup_s16(a as _)
20106}
20107#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
20109#[doc = "## Safety"]
20110#[doc = " * Neon instrinsic unsafe"]
20111#[inline]
20112#[target_feature(enable = "neon")]
20113#[cfg(not(target_arch = "arm"))]
20114#[cfg_attr(test, assert_instr(ld4r))]
20115#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20116pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
20117 unsafe extern "unadjusted" {
20118 #[cfg_attr(
20119 any(target_arch = "aarch64", target_arch = "arm64ec"),
20120 link_name = "llvm.aarch64.neon.ld4r.v8i16.p0i16.p0"
20121 )]
20122 fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t;
20123 }
20124 _vld4q_dup_s16(a as _)
20125}
20126#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
20128#[doc = "## Safety"]
20129#[doc = " * Neon instrinsic unsafe"]
20130#[inline]
20131#[target_feature(enable = "neon")]
20132#[cfg(not(target_arch = "arm"))]
20133#[cfg_attr(test, assert_instr(ld4r))]
20134#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20135pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
20136 unsafe extern "unadjusted" {
20137 #[cfg_attr(
20138 any(target_arch = "aarch64", target_arch = "arm64ec"),
20139 link_name = "llvm.aarch64.neon.ld4r.v2i32.p0i32.p0"
20140 )]
20141 fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t;
20142 }
20143 _vld4_dup_s32(a as _)
20144}
20145#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
20147#[doc = "## Safety"]
20148#[doc = " * Neon instrinsic unsafe"]
20149#[inline]
20150#[target_feature(enable = "neon")]
20151#[cfg(not(target_arch = "arm"))]
20152#[cfg_attr(test, assert_instr(ld4r))]
20153#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20154pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
20155 unsafe extern "unadjusted" {
20156 #[cfg_attr(
20157 any(target_arch = "aarch64", target_arch = "arm64ec"),
20158 link_name = "llvm.aarch64.neon.ld4r.v4i32.p0i32.p0"
20159 )]
20160 fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t;
20161 }
20162 _vld4q_dup_s32(a as _)
20163}
20164#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
20166#[doc = "## Safety"]
20167#[doc = " * Neon instrinsic unsafe"]
20168#[inline]
20169#[target_feature(enable = "neon")]
20170#[cfg(not(target_arch = "arm"))]
20171#[cfg_attr(test, assert_instr(ld4r))]
20172#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20173pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
20174 unsafe extern "unadjusted" {
20175 #[cfg_attr(
20176 any(target_arch = "aarch64", target_arch = "arm64ec"),
20177 link_name = "llvm.aarch64.neon.ld4r.v1i64.p0i64.p0"
20178 )]
20179 fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t;
20180 }
20181 _vld4_dup_s64(a as _)
20182}
20183#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
20185#[doc = "## Safety"]
20186#[doc = " * Neon instrinsic unsafe"]
20187#[inline]
20188#[target_feature(enable = "neon,aes")]
20189#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20191#[cfg_attr(
20192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20193 assert_instr(ld4r)
20194)]
20195#[cfg_attr(
20196 not(target_arch = "arm"),
20197 stable(feature = "neon_intrinsics", since = "1.59.0")
20198)]
20199#[cfg_attr(
20200 target_arch = "arm",
20201 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20202)]
20203pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
20204 transmute(vld4_dup_s64(transmute(a)))
20205}
20206#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
20208#[doc = "## Safety"]
20209#[doc = " * Neon instrinsic unsafe"]
20210#[inline]
20211#[cfg(target_arch = "arm")]
20212#[target_feature(enable = "neon,v7")]
20213#[cfg_attr(test, assert_instr(nop))]
20214#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20215pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
20216 unsafe extern "unadjusted" {
20217 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")]
20218 fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
20219 }
20220 _vld4_dup_s64(a as *const i8, 8)
20221}
20222#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
20224#[doc = "## Safety"]
20225#[doc = " * Neon instrinsic unsafe"]
20226#[inline]
20227#[target_feature(enable = "neon")]
20228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20230#[cfg_attr(
20231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20232 assert_instr(ld4r)
20233)]
20234#[cfg_attr(
20235 not(target_arch = "arm"),
20236 stable(feature = "neon_intrinsics", since = "1.59.0")
20237)]
20238#[cfg_attr(
20239 target_arch = "arm",
20240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20241)]
20242pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
20243 transmute(vld4_dup_s64(transmute(a)))
20244}
20245#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
20247#[doc = "## Safety"]
20248#[doc = " * Neon instrinsic unsafe"]
20249#[inline]
20250#[cfg(target_endian = "little")]
20251#[target_feature(enable = "neon")]
20252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20254#[cfg_attr(
20255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20256 assert_instr(ld4r)
20257)]
20258#[cfg_attr(
20259 not(target_arch = "arm"),
20260 stable(feature = "neon_intrinsics", since = "1.59.0")
20261)]
20262#[cfg_attr(
20263 target_arch = "arm",
20264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20265)]
20266pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
20267 transmute(vld4_dup_s8(transmute(a)))
20268}
20269#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
20271#[doc = "## Safety"]
20272#[doc = " * Neon instrinsic unsafe"]
20273#[inline]
20274#[cfg(target_endian = "big")]
20275#[target_feature(enable = "neon")]
20276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20278#[cfg_attr(
20279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20280 assert_instr(ld4r)
20281)]
20282#[cfg_attr(
20283 not(target_arch = "arm"),
20284 stable(feature = "neon_intrinsics", since = "1.59.0")
20285)]
20286#[cfg_attr(
20287 target_arch = "arm",
20288 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20289)]
20290pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
20291 let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
20292 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20293 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20294 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
20295 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
20296 ret_val
20297}
20298#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
20300#[doc = "## Safety"]
20301#[doc = " * Neon instrinsic unsafe"]
20302#[inline]
20303#[cfg(target_endian = "little")]
20304#[target_feature(enable = "neon")]
20305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20307#[cfg_attr(
20308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20309 assert_instr(ld4r)
20310)]
20311#[cfg_attr(
20312 not(target_arch = "arm"),
20313 stable(feature = "neon_intrinsics", since = "1.59.0")
20314)]
20315#[cfg_attr(
20316 target_arch = "arm",
20317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20318)]
20319pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
20320 transmute(vld4q_dup_s8(transmute(a)))
20321}
20322#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
20324#[doc = "## Safety"]
20325#[doc = " * Neon instrinsic unsafe"]
20326#[inline]
20327#[cfg(target_endian = "big")]
20328#[target_feature(enable = "neon")]
20329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20331#[cfg_attr(
20332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20333 assert_instr(ld4r)
20334)]
20335#[cfg_attr(
20336 not(target_arch = "arm"),
20337 stable(feature = "neon_intrinsics", since = "1.59.0")
20338)]
20339#[cfg_attr(
20340 target_arch = "arm",
20341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20342)]
20343pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
20344 let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
20345 ret_val.0 = unsafe {
20346 simd_shuffle!(
20347 ret_val.0,
20348 ret_val.0,
20349 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20350 )
20351 };
20352 ret_val.1 = unsafe {
20353 simd_shuffle!(
20354 ret_val.1,
20355 ret_val.1,
20356 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20357 )
20358 };
20359 ret_val.2 = unsafe {
20360 simd_shuffle!(
20361 ret_val.2,
20362 ret_val.2,
20363 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20364 )
20365 };
20366 ret_val.3 = unsafe {
20367 simd_shuffle!(
20368 ret_val.3,
20369 ret_val.3,
20370 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20371 )
20372 };
20373 ret_val
20374}
20375#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
20377#[doc = "## Safety"]
20378#[doc = " * Neon instrinsic unsafe"]
20379#[inline]
20380#[cfg(target_endian = "little")]
20381#[target_feature(enable = "neon")]
20382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20384#[cfg_attr(
20385 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20386 assert_instr(ld4r)
20387)]
20388#[cfg_attr(
20389 not(target_arch = "arm"),
20390 stable(feature = "neon_intrinsics", since = "1.59.0")
20391)]
20392#[cfg_attr(
20393 target_arch = "arm",
20394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20395)]
20396pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
20397 transmute(vld4_dup_s16(transmute(a)))
20398}
20399#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
20401#[doc = "## Safety"]
20402#[doc = " * Neon instrinsic unsafe"]
20403#[inline]
20404#[cfg(target_endian = "big")]
20405#[target_feature(enable = "neon")]
20406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20408#[cfg_attr(
20409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20410 assert_instr(ld4r)
20411)]
20412#[cfg_attr(
20413 not(target_arch = "arm"),
20414 stable(feature = "neon_intrinsics", since = "1.59.0")
20415)]
20416#[cfg_attr(
20417 target_arch = "arm",
20418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20419)]
20420pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
20421 let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
20422 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20423 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20424 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
20425 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
20426 ret_val
20427}
20428#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
20430#[doc = "## Safety"]
20431#[doc = " * Neon instrinsic unsafe"]
20432#[inline]
20433#[cfg(target_endian = "little")]
20434#[target_feature(enable = "neon")]
20435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20437#[cfg_attr(
20438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20439 assert_instr(ld4r)
20440)]
20441#[cfg_attr(
20442 not(target_arch = "arm"),
20443 stable(feature = "neon_intrinsics", since = "1.59.0")
20444)]
20445#[cfg_attr(
20446 target_arch = "arm",
20447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20448)]
20449pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
20450 transmute(vld4q_dup_s16(transmute(a)))
20451}
20452#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
20454#[doc = "## Safety"]
20455#[doc = " * Neon instrinsic unsafe"]
20456#[inline]
20457#[cfg(target_endian = "big")]
20458#[target_feature(enable = "neon")]
20459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20461#[cfg_attr(
20462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20463 assert_instr(ld4r)
20464)]
20465#[cfg_attr(
20466 not(target_arch = "arm"),
20467 stable(feature = "neon_intrinsics", since = "1.59.0")
20468)]
20469#[cfg_attr(
20470 target_arch = "arm",
20471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20472)]
20473pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
20474 let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
20475 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20476 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20477 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
20478 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
20479 ret_val
20480}
20481#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
20483#[doc = "## Safety"]
20484#[doc = " * Neon instrinsic unsafe"]
20485#[inline]
20486#[cfg(target_endian = "little")]
20487#[target_feature(enable = "neon")]
20488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20490#[cfg_attr(
20491 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20492 assert_instr(ld4r)
20493)]
20494#[cfg_attr(
20495 not(target_arch = "arm"),
20496 stable(feature = "neon_intrinsics", since = "1.59.0")
20497)]
20498#[cfg_attr(
20499 target_arch = "arm",
20500 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20501)]
20502pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
20503 transmute(vld4_dup_s32(transmute(a)))
20504}
20505#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
20507#[doc = "## Safety"]
20508#[doc = " * Neon instrinsic unsafe"]
20509#[inline]
20510#[cfg(target_endian = "big")]
20511#[target_feature(enable = "neon")]
20512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20514#[cfg_attr(
20515 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20516 assert_instr(ld4r)
20517)]
20518#[cfg_attr(
20519 not(target_arch = "arm"),
20520 stable(feature = "neon_intrinsics", since = "1.59.0")
20521)]
20522#[cfg_attr(
20523 target_arch = "arm",
20524 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20525)]
20526pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
20527 let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
20528 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
20529 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
20530 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
20531 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
20532 ret_val
20533}
20534#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
20536#[doc = "## Safety"]
20537#[doc = " * Neon instrinsic unsafe"]
20538#[inline]
20539#[cfg(target_endian = "little")]
20540#[target_feature(enable = "neon")]
20541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20543#[cfg_attr(
20544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20545 assert_instr(ld4r)
20546)]
20547#[cfg_attr(
20548 not(target_arch = "arm"),
20549 stable(feature = "neon_intrinsics", since = "1.59.0")
20550)]
20551#[cfg_attr(
20552 target_arch = "arm",
20553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20554)]
20555pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
20556 transmute(vld4q_dup_s32(transmute(a)))
20557}
20558#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
20560#[doc = "## Safety"]
20561#[doc = " * Neon instrinsic unsafe"]
20562#[inline]
20563#[cfg(target_endian = "big")]
20564#[target_feature(enable = "neon")]
20565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20566#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20567#[cfg_attr(
20568 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20569 assert_instr(ld4r)
20570)]
20571#[cfg_attr(
20572 not(target_arch = "arm"),
20573 stable(feature = "neon_intrinsics", since = "1.59.0")
20574)]
20575#[cfg_attr(
20576 target_arch = "arm",
20577 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20578)]
20579pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
20580 let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
20581 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20582 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20583 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
20584 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
20585 ret_val
20586}
20587#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
20589#[doc = "## Safety"]
20590#[doc = " * Neon instrinsic unsafe"]
20591#[inline]
20592#[cfg(target_endian = "little")]
20593#[target_feature(enable = "neon")]
20594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20596#[cfg_attr(
20597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20598 assert_instr(ld4r)
20599)]
20600#[cfg_attr(
20601 not(target_arch = "arm"),
20602 stable(feature = "neon_intrinsics", since = "1.59.0")
20603)]
20604#[cfg_attr(
20605 target_arch = "arm",
20606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20607)]
20608pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
20609 transmute(vld4_dup_s8(transmute(a)))
20610}
20611#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
20613#[doc = "## Safety"]
20614#[doc = " * Neon instrinsic unsafe"]
20615#[inline]
20616#[cfg(target_endian = "big")]
20617#[target_feature(enable = "neon")]
20618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20620#[cfg_attr(
20621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20622 assert_instr(ld4r)
20623)]
20624#[cfg_attr(
20625 not(target_arch = "arm"),
20626 stable(feature = "neon_intrinsics", since = "1.59.0")
20627)]
20628#[cfg_attr(
20629 target_arch = "arm",
20630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20631)]
20632pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
20633 let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
20634 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20635 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20636 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
20637 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
20638 ret_val
20639}
20640#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
20642#[doc = "## Safety"]
20643#[doc = " * Neon instrinsic unsafe"]
20644#[inline]
20645#[cfg(target_endian = "little")]
20646#[target_feature(enable = "neon")]
20647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20649#[cfg_attr(
20650 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20651 assert_instr(ld4r)
20652)]
20653#[cfg_attr(
20654 not(target_arch = "arm"),
20655 stable(feature = "neon_intrinsics", since = "1.59.0")
20656)]
20657#[cfg_attr(
20658 target_arch = "arm",
20659 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20660)]
20661pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
20662 transmute(vld4q_dup_s8(transmute(a)))
20663}
20664#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
20666#[doc = "## Safety"]
20667#[doc = " * Neon instrinsic unsafe"]
20668#[inline]
20669#[cfg(target_endian = "big")]
20670#[target_feature(enable = "neon")]
20671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20673#[cfg_attr(
20674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20675 assert_instr(ld4r)
20676)]
20677#[cfg_attr(
20678 not(target_arch = "arm"),
20679 stable(feature = "neon_intrinsics", since = "1.59.0")
20680)]
20681#[cfg_attr(
20682 target_arch = "arm",
20683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20684)]
20685pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
20686 let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
20687 ret_val.0 = unsafe {
20688 simd_shuffle!(
20689 ret_val.0,
20690 ret_val.0,
20691 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20692 )
20693 };
20694 ret_val.1 = unsafe {
20695 simd_shuffle!(
20696 ret_val.1,
20697 ret_val.1,
20698 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20699 )
20700 };
20701 ret_val.2 = unsafe {
20702 simd_shuffle!(
20703 ret_val.2,
20704 ret_val.2,
20705 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20706 )
20707 };
20708 ret_val.3 = unsafe {
20709 simd_shuffle!(
20710 ret_val.3,
20711 ret_val.3,
20712 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20713 )
20714 };
20715 ret_val
20716}
20717#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
20719#[doc = "## Safety"]
20720#[doc = " * Neon instrinsic unsafe"]
20721#[inline]
20722#[cfg(target_endian = "little")]
20723#[target_feature(enable = "neon")]
20724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20726#[cfg_attr(
20727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20728 assert_instr(ld4r)
20729)]
20730#[cfg_attr(
20731 not(target_arch = "arm"),
20732 stable(feature = "neon_intrinsics", since = "1.59.0")
20733)]
20734#[cfg_attr(
20735 target_arch = "arm",
20736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20737)]
20738pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
20739 transmute(vld4_dup_s16(transmute(a)))
20740}
20741#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
20743#[doc = "## Safety"]
20744#[doc = " * Neon instrinsic unsafe"]
20745#[inline]
20746#[cfg(target_endian = "big")]
20747#[target_feature(enable = "neon")]
20748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20750#[cfg_attr(
20751 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20752 assert_instr(ld4r)
20753)]
20754#[cfg_attr(
20755 not(target_arch = "arm"),
20756 stable(feature = "neon_intrinsics", since = "1.59.0")
20757)]
20758#[cfg_attr(
20759 target_arch = "arm",
20760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20761)]
20762pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
20763 let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
20764 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20765 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20766 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
20767 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
20768 ret_val
20769}
20770#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
20772#[doc = "## Safety"]
20773#[doc = " * Neon instrinsic unsafe"]
20774#[inline]
20775#[cfg(target_endian = "little")]
20776#[target_feature(enable = "neon")]
20777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20779#[cfg_attr(
20780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20781 assert_instr(ld4r)
20782)]
20783#[cfg_attr(
20784 not(target_arch = "arm"),
20785 stable(feature = "neon_intrinsics", since = "1.59.0")
20786)]
20787#[cfg_attr(
20788 target_arch = "arm",
20789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20790)]
20791pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
20792 transmute(vld4q_dup_s16(transmute(a)))
20793}
20794#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
20795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
20796#[doc = "## Safety"]
20797#[doc = " * Neon instrinsic unsafe"]
20798#[inline]
20799#[cfg(target_endian = "big")]
20800#[target_feature(enable = "neon")]
20801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20803#[cfg_attr(
20804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20805 assert_instr(ld4r)
20806)]
20807#[cfg_attr(
20808 not(target_arch = "arm"),
20809 stable(feature = "neon_intrinsics", since = "1.59.0")
20810)]
20811#[cfg_attr(
20812 target_arch = "arm",
20813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20814)]
20815pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
20816 let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
20817 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20818 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20819 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
20820 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
20821 ret_val
20822}
20823#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
20824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
20825#[doc = "## Safety"]
20826#[doc = " * Neon instrinsic unsafe"]
20827#[inline]
20828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20829#[cfg(target_arch = "arm")]
20830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20831#[target_feature(enable = "neon,fp16")]
20832#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20833pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
20834 unsafe extern "unadjusted" {
20835 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0f16")]
20836 fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
20837 }
20838 _vld4_f16(a as _, 2)
20839}
20840#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
20841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
20842#[doc = "## Safety"]
20843#[doc = " * Neon instrinsic unsafe"]
20844#[inline]
20845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20846#[cfg(target_arch = "arm")]
20847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
20848#[target_feature(enable = "neon,fp16")]
20849#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20850pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
20851 unsafe extern "unadjusted" {
20852 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0f16")]
20853 fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
20854 }
20855 _vld4q_f16(a as _, 2)
20856}
20857#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
20858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
20859#[doc = "## Safety"]
20860#[doc = " * Neon instrinsic unsafe"]
20861#[inline]
20862#[cfg(not(target_arch = "arm"))]
20863#[cfg_attr(
20864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20865 assert_instr(ld4)
20866)]
20867#[target_feature(enable = "neon,fp16")]
20868#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20869pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
20870 unsafe extern "unadjusted" {
20871 #[cfg_attr(
20872 any(target_arch = "aarch64", target_arch = "arm64ec"),
20873 link_name = "llvm.aarch64.neon.ld4.v4f16.p0f16"
20874 )]
20875 fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
20876 }
20877 _vld4_f16(a as _)
20878}
20879#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
20880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
20881#[doc = "## Safety"]
20882#[doc = " * Neon instrinsic unsafe"]
20883#[inline]
20884#[cfg(not(target_arch = "arm"))]
20885#[cfg_attr(
20886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20887 assert_instr(ld4)
20888)]
20889#[target_feature(enable = "neon,fp16")]
20890#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20891pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
20892 unsafe extern "unadjusted" {
20893 #[cfg_attr(
20894 any(target_arch = "aarch64", target_arch = "arm64ec"),
20895 link_name = "llvm.aarch64.neon.ld4.v8f16.p0f16"
20896 )]
20897 fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
20898 }
20899 _vld4q_f16(a as _)
20900}
20901#[doc = "Load multiple 4-element structures to four registers"]
20902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
20903#[doc = "## Safety"]
20904#[doc = " * Neon instrinsic unsafe"]
20905#[inline]
20906#[target_feature(enable = "neon")]
20907#[cfg(not(target_arch = "arm"))]
20908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20909#[cfg_attr(test, assert_instr(ld4))]
20910pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
20911 unsafe extern "unadjusted" {
20912 #[cfg_attr(
20913 any(target_arch = "aarch64", target_arch = "arm64ec"),
20914 link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
20915 )]
20916 fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
20917 }
20918 _vld4_f32(a as _)
20919}
20920#[doc = "Load multiple 4-element structures to four registers"]
20921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
20922#[doc = "## Safety"]
20923#[doc = " * Neon instrinsic unsafe"]
20924#[inline]
20925#[target_feature(enable = "neon")]
20926#[cfg(not(target_arch = "arm"))]
20927#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20928#[cfg_attr(test, assert_instr(ld4))]
20929pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
20930 unsafe extern "unadjusted" {
20931 #[cfg_attr(
20932 any(target_arch = "aarch64", target_arch = "arm64ec"),
20933 link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
20934 )]
20935 fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
20936 }
20937 _vld4q_f32(a as _)
20938}
20939#[doc = "Load multiple 4-element structures to four registers"]
20940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
20941#[doc = "## Safety"]
20942#[doc = " * Neon instrinsic unsafe"]
20943#[inline]
20944#[target_feature(enable = "neon")]
20945#[cfg(not(target_arch = "arm"))]
20946#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20947#[cfg_attr(test, assert_instr(ld4))]
20948pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
20949 unsafe extern "unadjusted" {
20950 #[cfg_attr(
20951 any(target_arch = "aarch64", target_arch = "arm64ec"),
20952 link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
20953 )]
20954 fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
20955 }
20956 _vld4_s8(a as _)
20957}
20958#[doc = "Load multiple 4-element structures to four registers"]
20959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
20960#[doc = "## Safety"]
20961#[doc = " * Neon instrinsic unsafe"]
20962#[inline]
20963#[target_feature(enable = "neon")]
20964#[cfg(not(target_arch = "arm"))]
20965#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20966#[cfg_attr(test, assert_instr(ld4))]
20967pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
20968 unsafe extern "unadjusted" {
20969 #[cfg_attr(
20970 any(target_arch = "aarch64", target_arch = "arm64ec"),
20971 link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
20972 )]
20973 fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
20974 }
20975 _vld4q_s8(a as _)
20976}
20977#[doc = "Load multiple 4-element structures to four registers"]
20978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
20979#[doc = "## Safety"]
20980#[doc = " * Neon instrinsic unsafe"]
20981#[inline]
20982#[target_feature(enable = "neon")]
20983#[cfg(not(target_arch = "arm"))]
20984#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20985#[cfg_attr(test, assert_instr(ld4))]
20986pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
20987 unsafe extern "unadjusted" {
20988 #[cfg_attr(
20989 any(target_arch = "aarch64", target_arch = "arm64ec"),
20990 link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
20991 )]
20992 fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
20993 }
20994 _vld4_s16(a as _)
20995}
20996#[doc = "Load multiple 4-element structures to four registers"]
20997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
20998#[doc = "## Safety"]
20999#[doc = " * Neon instrinsic unsafe"]
21000#[inline]
21001#[target_feature(enable = "neon")]
21002#[cfg(not(target_arch = "arm"))]
21003#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21004#[cfg_attr(test, assert_instr(ld4))]
21005pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
21006 unsafe extern "unadjusted" {
21007 #[cfg_attr(
21008 any(target_arch = "aarch64", target_arch = "arm64ec"),
21009 link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
21010 )]
21011 fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
21012 }
21013 _vld4q_s16(a as _)
21014}
21015#[doc = "Load multiple 4-element structures to four registers"]
21016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
21017#[doc = "## Safety"]
21018#[doc = " * Neon instrinsic unsafe"]
21019#[inline]
21020#[target_feature(enable = "neon")]
21021#[cfg(not(target_arch = "arm"))]
21022#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21023#[cfg_attr(test, assert_instr(ld4))]
21024pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
21025 unsafe extern "unadjusted" {
21026 #[cfg_attr(
21027 any(target_arch = "aarch64", target_arch = "arm64ec"),
21028 link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
21029 )]
21030 fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
21031 }
21032 _vld4_s32(a as _)
21033}
21034#[doc = "Load multiple 4-element structures to four registers"]
21035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
21036#[doc = "## Safety"]
21037#[doc = " * Neon instrinsic unsafe"]
21038#[inline]
21039#[target_feature(enable = "neon")]
21040#[cfg(not(target_arch = "arm"))]
21041#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21042#[cfg_attr(test, assert_instr(ld4))]
21043pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
21044 unsafe extern "unadjusted" {
21045 #[cfg_attr(
21046 any(target_arch = "aarch64", target_arch = "arm64ec"),
21047 link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
21048 )]
21049 fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
21050 }
21051 _vld4q_s32(a as _)
21052}
21053#[doc = "Load multiple 4-element structures to four registers"]
21054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
21055#[doc = "## Safety"]
21056#[doc = " * Neon instrinsic unsafe"]
21057#[inline]
21058#[target_feature(enable = "neon,v7")]
21059#[cfg(target_arch = "arm")]
21060#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21061#[cfg_attr(test, assert_instr(vld4))]
21062pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
21063 unsafe extern "unadjusted" {
21064 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")]
21065 fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
21066 }
21067 _vld4_f32(a as *const i8, 4)
21068}
21069#[doc = "Load multiple 4-element structures to four registers"]
21070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
21071#[doc = "## Safety"]
21072#[doc = " * Neon instrinsic unsafe"]
21073#[inline]
21074#[target_feature(enable = "neon,v7")]
21075#[cfg(target_arch = "arm")]
21076#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21077#[cfg_attr(test, assert_instr(vld4))]
21078pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
21079 unsafe extern "unadjusted" {
21080 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")]
21081 fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
21082 }
21083 _vld4q_f32(a as *const i8, 4)
21084}
21085#[doc = "Load multiple 4-element structures to four registers"]
21086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
21087#[doc = "## Safety"]
21088#[doc = " * Neon instrinsic unsafe"]
21089#[inline]
21090#[target_feature(enable = "neon,v7")]
21091#[cfg(target_arch = "arm")]
21092#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21093#[cfg_attr(test, assert_instr(vld4))]
21094pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
21095 unsafe extern "unadjusted" {
21096 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")]
21097 fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
21098 }
21099 _vld4_s8(a as *const i8, 1)
21100}
21101#[doc = "Load multiple 4-element structures to four registers"]
21102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
21103#[doc = "## Safety"]
21104#[doc = " * Neon instrinsic unsafe"]
21105#[inline]
21106#[target_feature(enable = "neon,v7")]
21107#[cfg(target_arch = "arm")]
21108#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21109#[cfg_attr(test, assert_instr(vld4))]
21110pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
21111 unsafe extern "unadjusted" {
21112 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")]
21113 fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
21114 }
21115 _vld4q_s8(a as *const i8, 1)
21116}
21117#[doc = "Load multiple 4-element structures to four registers"]
21118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
21119#[doc = "## Safety"]
21120#[doc = " * Neon instrinsic unsafe"]
21121#[inline]
21122#[target_feature(enable = "neon,v7")]
21123#[cfg(target_arch = "arm")]
21124#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21125#[cfg_attr(test, assert_instr(vld4))]
21126pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
21127 unsafe extern "unadjusted" {
21128 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")]
21129 fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
21130 }
21131 _vld4_s16(a as *const i8, 2)
21132}
21133#[doc = "Load multiple 4-element structures to four registers"]
21134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
21135#[doc = "## Safety"]
21136#[doc = " * Neon instrinsic unsafe"]
21137#[inline]
21138#[target_feature(enable = "neon,v7")]
21139#[cfg(target_arch = "arm")]
21140#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21141#[cfg_attr(test, assert_instr(vld4))]
21142pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
21143 unsafe extern "unadjusted" {
21144 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")]
21145 fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
21146 }
21147 _vld4q_s16(a as *const i8, 2)
21148}
21149#[doc = "Load multiple 4-element structures to four registers"]
21150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
21151#[doc = "## Safety"]
21152#[doc = " * Neon instrinsic unsafe"]
21153#[inline]
21154#[target_feature(enable = "neon,v7")]
21155#[cfg(target_arch = "arm")]
21156#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21157#[cfg_attr(test, assert_instr(vld4))]
21158pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
21159 unsafe extern "unadjusted" {
21160 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")]
21161 fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
21162 }
21163 _vld4_s32(a as *const i8, 4)
21164}
21165#[doc = "Load multiple 4-element structures to four registers"]
21166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
21167#[doc = "## Safety"]
21168#[doc = " * Neon instrinsic unsafe"]
21169#[inline]
21170#[target_feature(enable = "neon,v7")]
21171#[cfg(target_arch = "arm")]
21172#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21173#[cfg_attr(test, assert_instr(vld4))]
21174pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
21175 unsafe extern "unadjusted" {
21176 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")]
21177 fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
21178 }
21179 _vld4q_s32(a as *const i8, 4)
21180}
21181#[doc = "Load multiple 4-element structures to two registers"]
21182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
21183#[doc = "## Safety"]
21184#[doc = " * Neon instrinsic unsafe"]
21185#[inline]
21186#[target_feature(enable = "neon,v7")]
21187#[cfg(target_arch = "arm")]
21188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21189#[rustc_legacy_const_generics(2)]
21190#[target_feature(enable = "neon,fp16")]
21191#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21192pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
21193 static_assert_uimm_bits!(LANE, 2);
21194 unsafe extern "unadjusted" {
21195 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")]
21196 fn _vld4_lane_f16(
21197 ptr: *const f16,
21198 a: float16x4_t,
21199 b: float16x4_t,
21200 c: float16x4_t,
21201 d: float16x4_t,
21202 n: i32,
21203 size: i32,
21204 ) -> float16x4x4_t;
21205 }
21206 _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
21207}
21208#[doc = "Load multiple 4-element structures to two registers"]
21209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
21210#[doc = "## Safety"]
21211#[doc = " * Neon instrinsic unsafe"]
21212#[inline]
21213#[target_feature(enable = "neon,v7")]
21214#[cfg(target_arch = "arm")]
21215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21216#[rustc_legacy_const_generics(2)]
21217#[target_feature(enable = "neon,fp16")]
21218#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21219pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
21220 static_assert_uimm_bits!(LANE, 3);
21221 unsafe extern "unadjusted" {
21222 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")]
21223 fn _vld4q_lane_f16(
21224 ptr: *const f16,
21225 a: float16x8_t,
21226 b: float16x8_t,
21227 c: float16x8_t,
21228 d: float16x8_t,
21229 n: i32,
21230 size: i32,
21231 ) -> float16x8x4_t;
21232 }
21233 _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
21234}
21235#[doc = "Load multiple 4-element structures to two registers"]
21236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
21237#[doc = "## Safety"]
21238#[doc = " * Neon instrinsic unsafe"]
21239#[inline]
21240#[cfg(not(target_arch = "arm"))]
21241#[cfg_attr(
21242 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21243 assert_instr(ld4, LANE = 0)
21244)]
21245#[rustc_legacy_const_generics(2)]
21246#[target_feature(enable = "neon,fp16")]
21247#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21248pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
21249 static_assert_uimm_bits!(LANE, 2);
21250 unsafe extern "unadjusted" {
21251 #[cfg_attr(
21252 any(target_arch = "aarch64", target_arch = "arm64ec"),
21253 link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0"
21254 )]
21255 fn _vld4_lane_f16(
21256 a: float16x4_t,
21257 b: float16x4_t,
21258 c: float16x4_t,
21259 d: float16x4_t,
21260 n: i64,
21261 ptr: *const f16,
21262 ) -> float16x4x4_t;
21263 }
21264 _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21265}
21266#[doc = "Load multiple 4-element structures to two registers"]
21267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
21268#[doc = "## Safety"]
21269#[doc = " * Neon instrinsic unsafe"]
21270#[inline]
21271#[cfg(not(target_arch = "arm"))]
21272#[cfg_attr(
21273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21274 assert_instr(ld4, LANE = 0)
21275)]
21276#[rustc_legacy_const_generics(2)]
21277#[target_feature(enable = "neon,fp16")]
21278#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21279pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
21280 static_assert_uimm_bits!(LANE, 3);
21281 unsafe extern "unadjusted" {
21282 #[cfg_attr(
21283 any(target_arch = "aarch64", target_arch = "arm64ec"),
21284 link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0"
21285 )]
21286 fn _vld4q_lane_f16(
21287 a: float16x8_t,
21288 b: float16x8_t,
21289 c: float16x8_t,
21290 d: float16x8_t,
21291 n: i64,
21292 ptr: *const f16,
21293 ) -> float16x8x4_t;
21294 }
21295 _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21296}
21297#[doc = "Load multiple 4-element structures to four registers"]
21298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
21299#[doc = "## Safety"]
21300#[doc = " * Neon instrinsic unsafe"]
21301#[inline]
21302#[target_feature(enable = "neon")]
21303#[cfg(not(target_arch = "arm"))]
21304#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21305#[rustc_legacy_const_generics(2)]
21306#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21307pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
21308 static_assert_uimm_bits!(LANE, 1);
21309 unsafe extern "unadjusted" {
21310 #[cfg_attr(
21311 any(target_arch = "aarch64", target_arch = "arm64ec"),
21312 link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0"
21313 )]
21314 fn _vld4_lane_f32(
21315 a: float32x2_t,
21316 b: float32x2_t,
21317 c: float32x2_t,
21318 d: float32x2_t,
21319 n: i64,
21320 ptr: *const i8,
21321 ) -> float32x2x4_t;
21322 }
21323 _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21324}
21325#[doc = "Load multiple 4-element structures to four registers"]
21326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
21327#[doc = "## Safety"]
21328#[doc = " * Neon instrinsic unsafe"]
21329#[inline]
21330#[target_feature(enable = "neon")]
21331#[cfg(not(target_arch = "arm"))]
21332#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21333#[rustc_legacy_const_generics(2)]
21334#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21335pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
21336 static_assert_uimm_bits!(LANE, 2);
21337 unsafe extern "unadjusted" {
21338 #[cfg_attr(
21339 any(target_arch = "aarch64", target_arch = "arm64ec"),
21340 link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0"
21341 )]
21342 fn _vld4q_lane_f32(
21343 a: float32x4_t,
21344 b: float32x4_t,
21345 c: float32x4_t,
21346 d: float32x4_t,
21347 n: i64,
21348 ptr: *const i8,
21349 ) -> float32x4x4_t;
21350 }
21351 _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21352}
21353#[doc = "Load multiple 4-element structures to four registers"]
21354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
21355#[doc = "## Safety"]
21356#[doc = " * Neon instrinsic unsafe"]
21357#[inline]
21358#[target_feature(enable = "neon")]
21359#[cfg(not(target_arch = "arm"))]
21360#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21361#[rustc_legacy_const_generics(2)]
21362#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21363pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
21364 static_assert_uimm_bits!(LANE, 3);
21365 unsafe extern "unadjusted" {
21366 #[cfg_attr(
21367 any(target_arch = "aarch64", target_arch = "arm64ec"),
21368 link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0"
21369 )]
21370 fn _vld4_lane_s8(
21371 a: int8x8_t,
21372 b: int8x8_t,
21373 c: int8x8_t,
21374 d: int8x8_t,
21375 n: i64,
21376 ptr: *const i8,
21377 ) -> int8x8x4_t;
21378 }
21379 _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21380}
21381#[doc = "Load multiple 4-element structures to four registers"]
21382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
21383#[doc = "## Safety"]
21384#[doc = " * Neon instrinsic unsafe"]
21385#[inline]
21386#[target_feature(enable = "neon")]
21387#[cfg(not(target_arch = "arm"))]
21388#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21389#[rustc_legacy_const_generics(2)]
21390#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21391pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
21392 static_assert_uimm_bits!(LANE, 2);
21393 unsafe extern "unadjusted" {
21394 #[cfg_attr(
21395 any(target_arch = "aarch64", target_arch = "arm64ec"),
21396 link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0"
21397 )]
21398 fn _vld4_lane_s16(
21399 a: int16x4_t,
21400 b: int16x4_t,
21401 c: int16x4_t,
21402 d: int16x4_t,
21403 n: i64,
21404 ptr: *const i8,
21405 ) -> int16x4x4_t;
21406 }
21407 _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21408}
21409#[doc = "Load multiple 4-element structures to four registers"]
21410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
21411#[doc = "## Safety"]
21412#[doc = " * Neon instrinsic unsafe"]
21413#[inline]
21414#[target_feature(enable = "neon")]
21415#[cfg(not(target_arch = "arm"))]
21416#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21417#[rustc_legacy_const_generics(2)]
21418#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21419pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
21420 static_assert_uimm_bits!(LANE, 3);
21421 unsafe extern "unadjusted" {
21422 #[cfg_attr(
21423 any(target_arch = "aarch64", target_arch = "arm64ec"),
21424 link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0"
21425 )]
21426 fn _vld4q_lane_s16(
21427 a: int16x8_t,
21428 b: int16x8_t,
21429 c: int16x8_t,
21430 d: int16x8_t,
21431 n: i64,
21432 ptr: *const i8,
21433 ) -> int16x8x4_t;
21434 }
21435 _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21436}
21437#[doc = "Load multiple 4-element structures to four registers"]
21438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
21439#[doc = "## Safety"]
21440#[doc = " * Neon instrinsic unsafe"]
21441#[inline]
21442#[target_feature(enable = "neon")]
21443#[cfg(not(target_arch = "arm"))]
21444#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21445#[rustc_legacy_const_generics(2)]
21446#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21447pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
21448 static_assert_uimm_bits!(LANE, 1);
21449 unsafe extern "unadjusted" {
21450 #[cfg_attr(
21451 any(target_arch = "aarch64", target_arch = "arm64ec"),
21452 link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0"
21453 )]
21454 fn _vld4_lane_s32(
21455 a: int32x2_t,
21456 b: int32x2_t,
21457 c: int32x2_t,
21458 d: int32x2_t,
21459 n: i64,
21460 ptr: *const i8,
21461 ) -> int32x2x4_t;
21462 }
21463 _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21464}
21465#[doc = "Load multiple 4-element structures to four registers"]
21466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
21467#[doc = "## Safety"]
21468#[doc = " * Neon instrinsic unsafe"]
21469#[inline]
21470#[target_feature(enable = "neon")]
21471#[cfg(not(target_arch = "arm"))]
21472#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
21473#[rustc_legacy_const_generics(2)]
21474#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21475pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
21476 static_assert_uimm_bits!(LANE, 2);
21477 unsafe extern "unadjusted" {
21478 #[cfg_attr(
21479 any(target_arch = "aarch64", target_arch = "arm64ec"),
21480 link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0"
21481 )]
21482 fn _vld4q_lane_s32(
21483 a: int32x4_t,
21484 b: int32x4_t,
21485 c: int32x4_t,
21486 d: int32x4_t,
21487 n: i64,
21488 ptr: *const i8,
21489 ) -> int32x4x4_t;
21490 }
21491 _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
21492}
21493#[doc = "Load multiple 4-element structures to four registers"]
21494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
21495#[doc = "## Safety"]
21496#[doc = " * Neon instrinsic unsafe"]
21497#[inline]
21498#[target_feature(enable = "neon,v7")]
21499#[cfg(target_arch = "arm")]
21500#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21501#[rustc_legacy_const_generics(2)]
21502#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21503pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
21504 static_assert_uimm_bits!(LANE, 1);
21505 unsafe extern "unadjusted" {
21506 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")]
21507 fn _vld4_lane_f32(
21508 ptr: *const i8,
21509 a: float32x2_t,
21510 b: float32x2_t,
21511 c: float32x2_t,
21512 d: float32x2_t,
21513 n: i32,
21514 size: i32,
21515 ) -> float32x2x4_t;
21516 }
21517 _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
21518}
21519#[doc = "Load multiple 4-element structures to four registers"]
21520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
21521#[doc = "## Safety"]
21522#[doc = " * Neon instrinsic unsafe"]
21523#[inline]
21524#[target_feature(enable = "neon,v7")]
21525#[cfg(target_arch = "arm")]
21526#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21527#[rustc_legacy_const_generics(2)]
21528#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21529pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
21530 static_assert_uimm_bits!(LANE, 2);
21531 unsafe extern "unadjusted" {
21532 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")]
21533 fn _vld4q_lane_f32(
21534 ptr: *const i8,
21535 a: float32x4_t,
21536 b: float32x4_t,
21537 c: float32x4_t,
21538 d: float32x4_t,
21539 n: i32,
21540 size: i32,
21541 ) -> float32x4x4_t;
21542 }
21543 _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
21544}
21545#[doc = "Load multiple 4-element structures to four registers"]
21546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
21547#[doc = "## Safety"]
21548#[doc = " * Neon instrinsic unsafe"]
21549#[inline]
21550#[target_feature(enable = "neon,v7")]
21551#[cfg(target_arch = "arm")]
21552#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21553#[rustc_legacy_const_generics(2)]
21554#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21555pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
21556 static_assert_uimm_bits!(LANE, 3);
21557 unsafe extern "unadjusted" {
21558 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")]
21559 fn _vld4_lane_s8(
21560 ptr: *const i8,
21561 a: int8x8_t,
21562 b: int8x8_t,
21563 c: int8x8_t,
21564 d: int8x8_t,
21565 n: i32,
21566 size: i32,
21567 ) -> int8x8x4_t;
21568 }
21569 _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
21570}
21571#[doc = "Load multiple 4-element structures to four registers"]
21572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
21573#[doc = "## Safety"]
21574#[doc = " * Neon instrinsic unsafe"]
21575#[inline]
21576#[target_feature(enable = "neon,v7")]
21577#[cfg(target_arch = "arm")]
21578#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21579#[rustc_legacy_const_generics(2)]
21580#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21581pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
21582 static_assert_uimm_bits!(LANE, 2);
21583 unsafe extern "unadjusted" {
21584 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")]
21585 fn _vld4_lane_s16(
21586 ptr: *const i8,
21587 a: int16x4_t,
21588 b: int16x4_t,
21589 c: int16x4_t,
21590 d: int16x4_t,
21591 n: i32,
21592 size: i32,
21593 ) -> int16x4x4_t;
21594 }
21595 _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
21596}
21597#[doc = "Load multiple 4-element structures to four registers"]
21598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
21599#[doc = "## Safety"]
21600#[doc = " * Neon instrinsic unsafe"]
21601#[inline]
21602#[target_feature(enable = "neon,v7")]
21603#[cfg(target_arch = "arm")]
21604#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21605#[rustc_legacy_const_generics(2)]
21606#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21607pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
21608 static_assert_uimm_bits!(LANE, 3);
21609 unsafe extern "unadjusted" {
21610 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")]
21611 fn _vld4q_lane_s16(
21612 ptr: *const i8,
21613 a: int16x8_t,
21614 b: int16x8_t,
21615 c: int16x8_t,
21616 d: int16x8_t,
21617 n: i32,
21618 size: i32,
21619 ) -> int16x8x4_t;
21620 }
21621 _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
21622}
21623#[doc = "Load multiple 4-element structures to four registers"]
21624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
21625#[doc = "## Safety"]
21626#[doc = " * Neon instrinsic unsafe"]
21627#[inline]
21628#[target_feature(enable = "neon,v7")]
21629#[cfg(target_arch = "arm")]
21630#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21631#[rustc_legacy_const_generics(2)]
21632#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21633pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
21634 static_assert_uimm_bits!(LANE, 1);
21635 unsafe extern "unadjusted" {
21636 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")]
21637 fn _vld4_lane_s32(
21638 ptr: *const i8,
21639 a: int32x2_t,
21640 b: int32x2_t,
21641 c: int32x2_t,
21642 d: int32x2_t,
21643 n: i32,
21644 size: i32,
21645 ) -> int32x2x4_t;
21646 }
21647 _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
21648}
21649#[doc = "Load multiple 4-element structures to four registers"]
21650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
21651#[doc = "## Safety"]
21652#[doc = " * Neon instrinsic unsafe"]
21653#[inline]
21654#[target_feature(enable = "neon,v7")]
21655#[cfg(target_arch = "arm")]
21656#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
21657#[rustc_legacy_const_generics(2)]
21658#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21659pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
21660 static_assert_uimm_bits!(LANE, 2);
21661 unsafe extern "unadjusted" {
21662 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")]
21663 fn _vld4q_lane_s32(
21664 ptr: *const i8,
21665 a: int32x4_t,
21666 b: int32x4_t,
21667 c: int32x4_t,
21668 d: int32x4_t,
21669 n: i32,
21670 size: i32,
21671 ) -> int32x4x4_t;
21672 }
21673 _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
21674}
21675#[doc = "Load multiple 4-element structures to four registers"]
21676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
21677#[doc = "## Safety"]
21678#[doc = " * Neon instrinsic unsafe"]
21679#[inline]
21680#[target_feature(enable = "neon")]
21681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21683#[cfg_attr(
21684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21685 assert_instr(ld4, LANE = 0)
21686)]
21687#[rustc_legacy_const_generics(2)]
21688#[cfg_attr(
21689 not(target_arch = "arm"),
21690 stable(feature = "neon_intrinsics", since = "1.59.0")
21691)]
21692#[cfg_attr(
21693 target_arch = "arm",
21694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21695)]
21696pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t {
21697 static_assert_uimm_bits!(LANE, 3);
21698 transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
21699}
21700#[doc = "Load multiple 4-element structures to four registers"]
21701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
21702#[doc = "## Safety"]
21703#[doc = " * Neon instrinsic unsafe"]
21704#[inline]
21705#[target_feature(enable = "neon")]
21706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21708#[cfg_attr(
21709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21710 assert_instr(ld4, LANE = 0)
21711)]
21712#[rustc_legacy_const_generics(2)]
21713#[cfg_attr(
21714 not(target_arch = "arm"),
21715 stable(feature = "neon_intrinsics", since = "1.59.0")
21716)]
21717#[cfg_attr(
21718 target_arch = "arm",
21719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21720)]
21721pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t {
21722 static_assert_uimm_bits!(LANE, 2);
21723 transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
21724}
21725#[doc = "Load multiple 4-element structures to four registers"]
21726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
21727#[doc = "## Safety"]
21728#[doc = " * Neon instrinsic unsafe"]
21729#[inline]
21730#[target_feature(enable = "neon")]
21731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21733#[cfg_attr(
21734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21735 assert_instr(ld4, LANE = 0)
21736)]
21737#[rustc_legacy_const_generics(2)]
21738#[cfg_attr(
21739 not(target_arch = "arm"),
21740 stable(feature = "neon_intrinsics", since = "1.59.0")
21741)]
21742#[cfg_attr(
21743 target_arch = "arm",
21744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21745)]
21746pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t {
21747 static_assert_uimm_bits!(LANE, 3);
21748 transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
21749}
21750#[doc = "Load multiple 4-element structures to four registers"]
21751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
21752#[doc = "## Safety"]
21753#[doc = " * Neon instrinsic unsafe"]
21754#[inline]
21755#[target_feature(enable = "neon")]
21756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21758#[cfg_attr(
21759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21760 assert_instr(ld4, LANE = 0)
21761)]
21762#[rustc_legacy_const_generics(2)]
21763#[cfg_attr(
21764 not(target_arch = "arm"),
21765 stable(feature = "neon_intrinsics", since = "1.59.0")
21766)]
21767#[cfg_attr(
21768 target_arch = "arm",
21769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21770)]
21771pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
21772 static_assert_uimm_bits!(LANE, 1);
21773 transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
21774}
21775#[doc = "Load multiple 4-element structures to four registers"]
21776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
21777#[doc = "## Safety"]
21778#[doc = " * Neon instrinsic unsafe"]
21779#[inline]
21780#[target_feature(enable = "neon")]
21781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21783#[cfg_attr(
21784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21785 assert_instr(ld4, LANE = 0)
21786)]
21787#[rustc_legacy_const_generics(2)]
21788#[cfg_attr(
21789 not(target_arch = "arm"),
21790 stable(feature = "neon_intrinsics", since = "1.59.0")
21791)]
21792#[cfg_attr(
21793 target_arch = "arm",
21794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21795)]
21796pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
21797 static_assert_uimm_bits!(LANE, 2);
21798 transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
21799}
21800#[doc = "Load multiple 4-element structures to four registers"]
21801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
21802#[doc = "## Safety"]
21803#[doc = " * Neon instrinsic unsafe"]
21804#[inline]
21805#[target_feature(enable = "neon")]
21806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21807#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21808#[cfg_attr(
21809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21810 assert_instr(ld4, LANE = 0)
21811)]
21812#[rustc_legacy_const_generics(2)]
21813#[cfg_attr(
21814 not(target_arch = "arm"),
21815 stable(feature = "neon_intrinsics", since = "1.59.0")
21816)]
21817#[cfg_attr(
21818 target_arch = "arm",
21819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21820)]
21821pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
21822 static_assert_uimm_bits!(LANE, 3);
21823 transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
21824}
21825#[doc = "Load multiple 4-element structures to four registers"]
21826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
21827#[doc = "## Safety"]
21828#[doc = " * Neon instrinsic unsafe"]
21829#[inline]
21830#[target_feature(enable = "neon")]
21831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21833#[cfg_attr(
21834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21835 assert_instr(ld4, LANE = 0)
21836)]
21837#[rustc_legacy_const_generics(2)]
21838#[cfg_attr(
21839 not(target_arch = "arm"),
21840 stable(feature = "neon_intrinsics", since = "1.59.0")
21841)]
21842#[cfg_attr(
21843 target_arch = "arm",
21844 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21845)]
21846pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
21847 static_assert_uimm_bits!(LANE, 2);
21848 transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
21849}
21850#[doc = "Load multiple 4-element structures to four registers"]
21851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
21852#[doc = "## Safety"]
21853#[doc = " * Neon instrinsic unsafe"]
21854#[inline]
21855#[target_feature(enable = "neon")]
21856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
21858#[cfg_attr(
21859 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21860 assert_instr(ld4, LANE = 0)
21861)]
21862#[rustc_legacy_const_generics(2)]
21863#[cfg_attr(
21864 not(target_arch = "arm"),
21865 stable(feature = "neon_intrinsics", since = "1.59.0")
21866)]
21867#[cfg_attr(
21868 target_arch = "arm",
21869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21870)]
21871pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
21872 static_assert_uimm_bits!(LANE, 3);
21873 transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
21874}
21875#[doc = "Load multiple 4-element structures to four registers"]
21876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
21877#[doc = "## Safety"]
21878#[doc = " * Neon instrinsic unsafe"]
21879#[inline]
21880#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
21881#[target_feature(enable = "neon,aes")]
21882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21883#[cfg_attr(
21884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21885 assert_instr(nop)
21886)]
21887#[cfg_attr(
21888 not(target_arch = "arm"),
21889 stable(feature = "neon_intrinsics", since = "1.59.0")
21890)]
21891#[cfg_attr(
21892 target_arch = "arm",
21893 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21894)]
21895pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
21896 transmute(vld4_s64(transmute(a)))
21897}
21898#[doc = "Load multiple 4-element structures to four registers"]
21899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
21900#[doc = "## Safety"]
21901#[doc = " * Neon instrinsic unsafe"]
21902#[inline]
21903#[target_feature(enable = "neon")]
21904#[cfg(not(target_arch = "arm"))]
21905#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21906#[cfg_attr(test, assert_instr(nop))]
21907pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
21908 unsafe extern "unadjusted" {
21909 #[cfg_attr(
21910 any(target_arch = "aarch64", target_arch = "arm64ec"),
21911 link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
21912 )]
21913 fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
21914 }
21915 _vld4_s64(a as _)
21916}
21917#[doc = "Load multiple 4-element structures to four registers"]
21918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
21919#[doc = "## Safety"]
21920#[doc = " * Neon instrinsic unsafe"]
21921#[inline]
21922#[target_feature(enable = "neon,v7")]
21923#[cfg(target_arch = "arm")]
21924#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21925#[cfg_attr(test, assert_instr(nop))]
21926pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
21927 unsafe extern "unadjusted" {
21928 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
21929 fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
21930 }
21931 _vld4_s64(a as *const i8, 8)
21932}
21933#[doc = "Load multiple 4-element structures to four registers"]
21934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
21935#[doc = "## Safety"]
21936#[doc = " * Neon instrinsic unsafe"]
21937#[inline]
21938#[target_feature(enable = "neon")]
21939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21941#[cfg_attr(
21942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21943 assert_instr(nop)
21944)]
21945#[cfg_attr(
21946 not(target_arch = "arm"),
21947 stable(feature = "neon_intrinsics", since = "1.59.0")
21948)]
21949#[cfg_attr(
21950 target_arch = "arm",
21951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21952)]
21953pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
21954 transmute(vld4_s64(transmute(a)))
21955}
21956#[doc = "Load multiple 4-element structures to four registers"]
21957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
21958#[doc = "## Safety"]
21959#[doc = " * Neon instrinsic unsafe"]
21960#[inline]
21961#[cfg(target_endian = "little")]
21962#[target_feature(enable = "neon")]
21963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
21965#[cfg_attr(
21966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21967 assert_instr(ld4)
21968)]
21969#[cfg_attr(
21970 not(target_arch = "arm"),
21971 stable(feature = "neon_intrinsics", since = "1.59.0")
21972)]
21973#[cfg_attr(
21974 target_arch = "arm",
21975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21976)]
21977pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
21978 transmute(vld4_s8(transmute(a)))
21979}
21980#[doc = "Load multiple 4-element structures to four registers"]
21981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
21982#[doc = "## Safety"]
21983#[doc = " * Neon instrinsic unsafe"]
21984#[inline]
21985#[cfg(target_endian = "big")]
21986#[target_feature(enable = "neon")]
21987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
21989#[cfg_attr(
21990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21991 assert_instr(ld4)
21992)]
21993#[cfg_attr(
21994 not(target_arch = "arm"),
21995 stable(feature = "neon_intrinsics", since = "1.59.0")
21996)]
21997#[cfg_attr(
21998 target_arch = "arm",
21999 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22000)]
22001pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
22002 let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a)));
22003 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22004 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22005 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22006 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
22007 ret_val
22008}
22009#[doc = "Load multiple 4-element structures to four registers"]
22010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
22011#[doc = "## Safety"]
22012#[doc = " * Neon instrinsic unsafe"]
22013#[inline]
22014#[cfg(target_endian = "little")]
22015#[target_feature(enable = "neon")]
22016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22018#[cfg_attr(
22019 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22020 assert_instr(ld4)
22021)]
22022#[cfg_attr(
22023 not(target_arch = "arm"),
22024 stable(feature = "neon_intrinsics", since = "1.59.0")
22025)]
22026#[cfg_attr(
22027 target_arch = "arm",
22028 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22029)]
22030pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
22031 transmute(vld4q_s8(transmute(a)))
22032}
22033#[doc = "Load multiple 4-element structures to four registers"]
22034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
22035#[doc = "## Safety"]
22036#[doc = " * Neon instrinsic unsafe"]
22037#[inline]
22038#[cfg(target_endian = "big")]
22039#[target_feature(enable = "neon")]
22040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22041#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22042#[cfg_attr(
22043 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22044 assert_instr(ld4)
22045)]
22046#[cfg_attr(
22047 not(target_arch = "arm"),
22048 stable(feature = "neon_intrinsics", since = "1.59.0")
22049)]
22050#[cfg_attr(
22051 target_arch = "arm",
22052 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22053)]
22054pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
22055 let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a)));
22056 ret_val.0 = unsafe {
22057 simd_shuffle!(
22058 ret_val.0,
22059 ret_val.0,
22060 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22061 )
22062 };
22063 ret_val.1 = unsafe {
22064 simd_shuffle!(
22065 ret_val.1,
22066 ret_val.1,
22067 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22068 )
22069 };
22070 ret_val.2 = unsafe {
22071 simd_shuffle!(
22072 ret_val.2,
22073 ret_val.2,
22074 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22075 )
22076 };
22077 ret_val.3 = unsafe {
22078 simd_shuffle!(
22079 ret_val.3,
22080 ret_val.3,
22081 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22082 )
22083 };
22084 ret_val
22085}
22086#[doc = "Load multiple 4-element structures to four registers"]
22087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
22088#[doc = "## Safety"]
22089#[doc = " * Neon instrinsic unsafe"]
22090#[inline]
22091#[cfg(target_endian = "little")]
22092#[target_feature(enable = "neon")]
22093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22095#[cfg_attr(
22096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22097 assert_instr(ld4)
22098)]
22099#[cfg_attr(
22100 not(target_arch = "arm"),
22101 stable(feature = "neon_intrinsics", since = "1.59.0")
22102)]
22103#[cfg_attr(
22104 target_arch = "arm",
22105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22106)]
22107pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
22108 transmute(vld4_s16(transmute(a)))
22109}
22110#[doc = "Load multiple 4-element structures to four registers"]
22111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
22112#[doc = "## Safety"]
22113#[doc = " * Neon instrinsic unsafe"]
22114#[inline]
22115#[cfg(target_endian = "big")]
22116#[target_feature(enable = "neon")]
22117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22119#[cfg_attr(
22120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22121 assert_instr(ld4)
22122)]
22123#[cfg_attr(
22124 not(target_arch = "arm"),
22125 stable(feature = "neon_intrinsics", since = "1.59.0")
22126)]
22127#[cfg_attr(
22128 target_arch = "arm",
22129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22130)]
22131pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
22132 let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a)));
22133 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22134 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22135 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22136 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
22137 ret_val
22138}
22139#[doc = "Load multiple 4-element structures to four registers"]
22140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
22141#[doc = "## Safety"]
22142#[doc = " * Neon instrinsic unsafe"]
22143#[inline]
22144#[cfg(target_endian = "little")]
22145#[target_feature(enable = "neon")]
22146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22148#[cfg_attr(
22149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22150 assert_instr(ld4)
22151)]
22152#[cfg_attr(
22153 not(target_arch = "arm"),
22154 stable(feature = "neon_intrinsics", since = "1.59.0")
22155)]
22156#[cfg_attr(
22157 target_arch = "arm",
22158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22159)]
22160pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
22161 transmute(vld4q_s16(transmute(a)))
22162}
22163#[doc = "Load multiple 4-element structures to four registers"]
22164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
22165#[doc = "## Safety"]
22166#[doc = " * Neon instrinsic unsafe"]
22167#[inline]
22168#[cfg(target_endian = "big")]
22169#[target_feature(enable = "neon")]
22170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22171#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22172#[cfg_attr(
22173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22174 assert_instr(ld4)
22175)]
22176#[cfg_attr(
22177 not(target_arch = "arm"),
22178 stable(feature = "neon_intrinsics", since = "1.59.0")
22179)]
22180#[cfg_attr(
22181 target_arch = "arm",
22182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22183)]
22184pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
22185 let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a)));
22186 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22187 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22188 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22189 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
22190 ret_val
22191}
22192#[doc = "Load multiple 4-element structures to four registers"]
22193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
22194#[doc = "## Safety"]
22195#[doc = " * Neon instrinsic unsafe"]
22196#[inline]
22197#[cfg(target_endian = "little")]
22198#[target_feature(enable = "neon")]
22199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22201#[cfg_attr(
22202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22203 assert_instr(ld4)
22204)]
22205#[cfg_attr(
22206 not(target_arch = "arm"),
22207 stable(feature = "neon_intrinsics", since = "1.59.0")
22208)]
22209#[cfg_attr(
22210 target_arch = "arm",
22211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22212)]
22213pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
22214 transmute(vld4_s32(transmute(a)))
22215}
22216#[doc = "Load multiple 4-element structures to four registers"]
22217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
22218#[doc = "## Safety"]
22219#[doc = " * Neon instrinsic unsafe"]
22220#[inline]
22221#[cfg(target_endian = "big")]
22222#[target_feature(enable = "neon")]
22223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22224#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22225#[cfg_attr(
22226 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22227 assert_instr(ld4)
22228)]
22229#[cfg_attr(
22230 not(target_arch = "arm"),
22231 stable(feature = "neon_intrinsics", since = "1.59.0")
22232)]
22233#[cfg_attr(
22234 target_arch = "arm",
22235 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22236)]
22237pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
22238 let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a)));
22239 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
22240 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
22241 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
22242 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
22243 ret_val
22244}
22245#[doc = "Load multiple 4-element structures to four registers"]
22246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
22247#[doc = "## Safety"]
22248#[doc = " * Neon instrinsic unsafe"]
22249#[inline]
22250#[cfg(target_endian = "little")]
22251#[target_feature(enable = "neon")]
22252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22254#[cfg_attr(
22255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22256 assert_instr(ld4)
22257)]
22258#[cfg_attr(
22259 not(target_arch = "arm"),
22260 stable(feature = "neon_intrinsics", since = "1.59.0")
22261)]
22262#[cfg_attr(
22263 target_arch = "arm",
22264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22265)]
22266pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
22267 transmute(vld4q_s32(transmute(a)))
22268}
22269#[doc = "Load multiple 4-element structures to four registers"]
22270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
22271#[doc = "## Safety"]
22272#[doc = " * Neon instrinsic unsafe"]
22273#[inline]
22274#[cfg(target_endian = "big")]
22275#[target_feature(enable = "neon")]
22276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22278#[cfg_attr(
22279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22280 assert_instr(ld4)
22281)]
22282#[cfg_attr(
22283 not(target_arch = "arm"),
22284 stable(feature = "neon_intrinsics", since = "1.59.0")
22285)]
22286#[cfg_attr(
22287 target_arch = "arm",
22288 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22289)]
22290pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
22291 let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a)));
22292 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22293 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22294 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22295 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
22296 ret_val
22297}
22298#[doc = "Load multiple 4-element structures to four registers"]
22299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
22300#[doc = "## Safety"]
22301#[doc = " * Neon instrinsic unsafe"]
22302#[inline]
22303#[cfg(target_endian = "little")]
22304#[target_feature(enable = "neon")]
22305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22307#[cfg_attr(
22308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22309 assert_instr(ld4)
22310)]
22311#[cfg_attr(
22312 not(target_arch = "arm"),
22313 stable(feature = "neon_intrinsics", since = "1.59.0")
22314)]
22315#[cfg_attr(
22316 target_arch = "arm",
22317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22318)]
22319pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
22320 transmute(vld4_s8(transmute(a)))
22321}
22322#[doc = "Load multiple 4-element structures to four registers"]
22323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
22324#[doc = "## Safety"]
22325#[doc = " * Neon instrinsic unsafe"]
22326#[inline]
22327#[cfg(target_endian = "big")]
22328#[target_feature(enable = "neon")]
22329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22331#[cfg_attr(
22332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22333 assert_instr(ld4)
22334)]
22335#[cfg_attr(
22336 not(target_arch = "arm"),
22337 stable(feature = "neon_intrinsics", since = "1.59.0")
22338)]
22339#[cfg_attr(
22340 target_arch = "arm",
22341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22342)]
22343pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
22344 let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a)));
22345 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22346 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22347 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22348 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
22349 ret_val
22350}
22351#[doc = "Load multiple 4-element structures to four registers"]
22352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
22353#[doc = "## Safety"]
22354#[doc = " * Neon instrinsic unsafe"]
22355#[inline]
22356#[cfg(target_endian = "little")]
22357#[target_feature(enable = "neon")]
22358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22360#[cfg_attr(
22361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22362 assert_instr(ld4)
22363)]
22364#[cfg_attr(
22365 not(target_arch = "arm"),
22366 stable(feature = "neon_intrinsics", since = "1.59.0")
22367)]
22368#[cfg_attr(
22369 target_arch = "arm",
22370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22371)]
22372pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
22373 transmute(vld4q_s8(transmute(a)))
22374}
22375#[doc = "Load multiple 4-element structures to four registers"]
22376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
22377#[doc = "## Safety"]
22378#[doc = " * Neon instrinsic unsafe"]
22379#[inline]
22380#[cfg(target_endian = "big")]
22381#[target_feature(enable = "neon")]
22382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22384#[cfg_attr(
22385 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22386 assert_instr(ld4)
22387)]
22388#[cfg_attr(
22389 not(target_arch = "arm"),
22390 stable(feature = "neon_intrinsics", since = "1.59.0")
22391)]
22392#[cfg_attr(
22393 target_arch = "arm",
22394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22395)]
22396pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
22397 let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a)));
22398 ret_val.0 = unsafe {
22399 simd_shuffle!(
22400 ret_val.0,
22401 ret_val.0,
22402 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22403 )
22404 };
22405 ret_val.1 = unsafe {
22406 simd_shuffle!(
22407 ret_val.1,
22408 ret_val.1,
22409 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22410 )
22411 };
22412 ret_val.2 = unsafe {
22413 simd_shuffle!(
22414 ret_val.2,
22415 ret_val.2,
22416 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22417 )
22418 };
22419 ret_val.3 = unsafe {
22420 simd_shuffle!(
22421 ret_val.3,
22422 ret_val.3,
22423 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22424 )
22425 };
22426 ret_val
22427}
22428#[doc = "Load multiple 4-element structures to four registers"]
22429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
22430#[doc = "## Safety"]
22431#[doc = " * Neon instrinsic unsafe"]
22432#[inline]
22433#[cfg(target_endian = "little")]
22434#[target_feature(enable = "neon")]
22435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22437#[cfg_attr(
22438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22439 assert_instr(ld4)
22440)]
22441#[cfg_attr(
22442 not(target_arch = "arm"),
22443 stable(feature = "neon_intrinsics", since = "1.59.0")
22444)]
22445#[cfg_attr(
22446 target_arch = "arm",
22447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22448)]
22449pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
22450 transmute(vld4_s16(transmute(a)))
22451}
22452#[doc = "Load multiple 4-element structures to four registers"]
22453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
22454#[doc = "## Safety"]
22455#[doc = " * Neon instrinsic unsafe"]
22456#[inline]
22457#[cfg(target_endian = "big")]
22458#[target_feature(enable = "neon")]
22459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22461#[cfg_attr(
22462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22463 assert_instr(ld4)
22464)]
22465#[cfg_attr(
22466 not(target_arch = "arm"),
22467 stable(feature = "neon_intrinsics", since = "1.59.0")
22468)]
22469#[cfg_attr(
22470 target_arch = "arm",
22471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22472)]
22473pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
22474 let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a)));
22475 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22476 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22477 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22478 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
22479 ret_val
22480}
22481#[doc = "Load multiple 4-element structures to four registers"]
22482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
22483#[doc = "## Safety"]
22484#[doc = " * Neon instrinsic unsafe"]
22485#[inline]
22486#[cfg(target_endian = "little")]
22487#[target_feature(enable = "neon")]
22488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22490#[cfg_attr(
22491 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22492 assert_instr(ld4)
22493)]
22494#[cfg_attr(
22495 not(target_arch = "arm"),
22496 stable(feature = "neon_intrinsics", since = "1.59.0")
22497)]
22498#[cfg_attr(
22499 target_arch = "arm",
22500 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22501)]
22502pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
22503 transmute(vld4q_s16(transmute(a)))
22504}
22505#[doc = "Load multiple 4-element structures to four registers"]
22506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
22507#[doc = "## Safety"]
22508#[doc = " * Neon instrinsic unsafe"]
22509#[inline]
22510#[cfg(target_endian = "big")]
22511#[target_feature(enable = "neon")]
22512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
22514#[cfg_attr(
22515 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22516 assert_instr(ld4)
22517)]
22518#[cfg_attr(
22519 not(target_arch = "arm"),
22520 stable(feature = "neon_intrinsics", since = "1.59.0")
22521)]
22522#[cfg_attr(
22523 target_arch = "arm",
22524 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22525)]
22526pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
22527 let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a)));
22528 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22529 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22530 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22531 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
22532 ret_val
22533}
22534#[doc = "Maximum (vector)"]
22535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
22536#[inline]
22537#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
22538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22539#[cfg_attr(
22540 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22541 assert_instr(fmax)
22542)]
22543#[target_feature(enable = "neon,fp16")]
22544#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22545pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
22546 unsafe extern "unadjusted" {
22547 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")]
22548 #[cfg_attr(
22549 any(target_arch = "aarch64", target_arch = "arm64ec"),
22550 link_name = "llvm.aarch64.neon.fmax.v4f16"
22551 )]
22552 fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
22553 }
22554 unsafe { _vmax_f16(a, b) }
22555}
22556#[doc = "Maximum (vector)"]
22557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
22558#[inline]
22559#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
22560#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22561#[cfg_attr(
22562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22563 assert_instr(fmax)
22564)]
22565#[target_feature(enable = "neon,fp16")]
22566#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22567pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
22568 unsafe extern "unadjusted" {
22569 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")]
22570 #[cfg_attr(
22571 any(target_arch = "aarch64", target_arch = "arm64ec"),
22572 link_name = "llvm.aarch64.neon.fmax.v8f16"
22573 )]
22574 fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
22575 }
22576 unsafe { _vmaxq_f16(a, b) }
22577}
22578#[doc = "Maximum (vector)"]
22579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
22580#[inline]
22581#[target_feature(enable = "neon")]
22582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22583#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22584#[cfg_attr(
22585 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22586 assert_instr(fmax)
22587)]
22588#[cfg_attr(
22589 not(target_arch = "arm"),
22590 stable(feature = "neon_intrinsics", since = "1.59.0")
22591)]
22592#[cfg_attr(
22593 target_arch = "arm",
22594 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22595)]
22596pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
22597 unsafe extern "unadjusted" {
22598 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")]
22599 #[cfg_attr(
22600 any(target_arch = "aarch64", target_arch = "arm64ec"),
22601 link_name = "llvm.aarch64.neon.fmax.v2f32"
22602 )]
22603 fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
22604 }
22605 unsafe { _vmax_f32(a, b) }
22606}
22607#[doc = "Maximum (vector)"]
22608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
22609#[inline]
22610#[target_feature(enable = "neon")]
22611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22613#[cfg_attr(
22614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22615 assert_instr(fmax)
22616)]
22617#[cfg_attr(
22618 not(target_arch = "arm"),
22619 stable(feature = "neon_intrinsics", since = "1.59.0")
22620)]
22621#[cfg_attr(
22622 target_arch = "arm",
22623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22624)]
22625pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
22626 unsafe extern "unadjusted" {
22627 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")]
22628 #[cfg_attr(
22629 any(target_arch = "aarch64", target_arch = "arm64ec"),
22630 link_name = "llvm.aarch64.neon.fmax.v4f32"
22631 )]
22632 fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
22633 }
22634 unsafe { _vmaxq_f32(a, b) }
22635}
22636#[doc = "Maximum (vector)"]
22637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
22638#[inline]
22639#[target_feature(enable = "neon")]
22640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22642#[cfg_attr(
22643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22644 assert_instr(smax)
22645)]
22646#[cfg_attr(
22647 not(target_arch = "arm"),
22648 stable(feature = "neon_intrinsics", since = "1.59.0")
22649)]
22650#[cfg_attr(
22651 target_arch = "arm",
22652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22653)]
22654pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
22655 unsafe extern "unadjusted" {
22656 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")]
22657 #[cfg_attr(
22658 any(target_arch = "aarch64", target_arch = "arm64ec"),
22659 link_name = "llvm.aarch64.neon.smax.v8i8"
22660 )]
22661 fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
22662 }
22663 unsafe { _vmax_s8(a, b) }
22664}
22665#[doc = "Maximum (vector)"]
22666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
22667#[inline]
22668#[target_feature(enable = "neon")]
22669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22671#[cfg_attr(
22672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22673 assert_instr(smax)
22674)]
22675#[cfg_attr(
22676 not(target_arch = "arm"),
22677 stable(feature = "neon_intrinsics", since = "1.59.0")
22678)]
22679#[cfg_attr(
22680 target_arch = "arm",
22681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22682)]
22683pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
22684 unsafe extern "unadjusted" {
22685 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")]
22686 #[cfg_attr(
22687 any(target_arch = "aarch64", target_arch = "arm64ec"),
22688 link_name = "llvm.aarch64.neon.smax.v16i8"
22689 )]
22690 fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
22691 }
22692 unsafe { _vmaxq_s8(a, b) }
22693}
22694#[doc = "Maximum (vector)"]
22695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
22696#[inline]
22697#[target_feature(enable = "neon")]
22698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22700#[cfg_attr(
22701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22702 assert_instr(smax)
22703)]
22704#[cfg_attr(
22705 not(target_arch = "arm"),
22706 stable(feature = "neon_intrinsics", since = "1.59.0")
22707)]
22708#[cfg_attr(
22709 target_arch = "arm",
22710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22711)]
22712pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
22713 unsafe extern "unadjusted" {
22714 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")]
22715 #[cfg_attr(
22716 any(target_arch = "aarch64", target_arch = "arm64ec"),
22717 link_name = "llvm.aarch64.neon.smax.v4i16"
22718 )]
22719 fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
22720 }
22721 unsafe { _vmax_s16(a, b) }
22722}
22723#[doc = "Maximum (vector)"]
22724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
22725#[inline]
22726#[target_feature(enable = "neon")]
22727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22729#[cfg_attr(
22730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22731 assert_instr(smax)
22732)]
22733#[cfg_attr(
22734 not(target_arch = "arm"),
22735 stable(feature = "neon_intrinsics", since = "1.59.0")
22736)]
22737#[cfg_attr(
22738 target_arch = "arm",
22739 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22740)]
22741pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
22742 unsafe extern "unadjusted" {
22743 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")]
22744 #[cfg_attr(
22745 any(target_arch = "aarch64", target_arch = "arm64ec"),
22746 link_name = "llvm.aarch64.neon.smax.v8i16"
22747 )]
22748 fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
22749 }
22750 unsafe { _vmaxq_s16(a, b) }
22751}
22752#[doc = "Maximum (vector)"]
22753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
22754#[inline]
22755#[target_feature(enable = "neon")]
22756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22758#[cfg_attr(
22759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22760 assert_instr(smax)
22761)]
22762#[cfg_attr(
22763 not(target_arch = "arm"),
22764 stable(feature = "neon_intrinsics", since = "1.59.0")
22765)]
22766#[cfg_attr(
22767 target_arch = "arm",
22768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22769)]
22770pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
22771 unsafe extern "unadjusted" {
22772 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")]
22773 #[cfg_attr(
22774 any(target_arch = "aarch64", target_arch = "arm64ec"),
22775 link_name = "llvm.aarch64.neon.smax.v2i32"
22776 )]
22777 fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
22778 }
22779 unsafe { _vmax_s32(a, b) }
22780}
22781#[doc = "Maximum (vector)"]
22782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
22783#[inline]
22784#[target_feature(enable = "neon")]
22785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22787#[cfg_attr(
22788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22789 assert_instr(smax)
22790)]
22791#[cfg_attr(
22792 not(target_arch = "arm"),
22793 stable(feature = "neon_intrinsics", since = "1.59.0")
22794)]
22795#[cfg_attr(
22796 target_arch = "arm",
22797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22798)]
22799pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
22800 unsafe extern "unadjusted" {
22801 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")]
22802 #[cfg_attr(
22803 any(target_arch = "aarch64", target_arch = "arm64ec"),
22804 link_name = "llvm.aarch64.neon.smax.v4i32"
22805 )]
22806 fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
22807 }
22808 unsafe { _vmaxq_s32(a, b) }
22809}
22810#[doc = "Maximum (vector)"]
22811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
22812#[inline]
22813#[target_feature(enable = "neon")]
22814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22816#[cfg_attr(
22817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22818 assert_instr(umax)
22819)]
22820#[cfg_attr(
22821 not(target_arch = "arm"),
22822 stable(feature = "neon_intrinsics", since = "1.59.0")
22823)]
22824#[cfg_attr(
22825 target_arch = "arm",
22826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22827)]
22828pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
22829 unsafe extern "unadjusted" {
22830 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")]
22831 #[cfg_attr(
22832 any(target_arch = "aarch64", target_arch = "arm64ec"),
22833 link_name = "llvm.aarch64.neon.umax.v8i8"
22834 )]
22835 fn _vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
22836 }
22837 unsafe { _vmax_u8(a, b) }
22838}
22839#[doc = "Maximum (vector)"]
22840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
22841#[inline]
22842#[target_feature(enable = "neon")]
22843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22845#[cfg_attr(
22846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22847 assert_instr(umax)
22848)]
22849#[cfg_attr(
22850 not(target_arch = "arm"),
22851 stable(feature = "neon_intrinsics", since = "1.59.0")
22852)]
22853#[cfg_attr(
22854 target_arch = "arm",
22855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22856)]
22857pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
22858 unsafe extern "unadjusted" {
22859 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")]
22860 #[cfg_attr(
22861 any(target_arch = "aarch64", target_arch = "arm64ec"),
22862 link_name = "llvm.aarch64.neon.umax.v16i8"
22863 )]
22864 fn _vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
22865 }
22866 unsafe { _vmaxq_u8(a, b) }
22867}
22868#[doc = "Maximum (vector)"]
22869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
22870#[inline]
22871#[target_feature(enable = "neon")]
22872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22874#[cfg_attr(
22875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22876 assert_instr(umax)
22877)]
22878#[cfg_attr(
22879 not(target_arch = "arm"),
22880 stable(feature = "neon_intrinsics", since = "1.59.0")
22881)]
22882#[cfg_attr(
22883 target_arch = "arm",
22884 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22885)]
22886pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
22887 unsafe extern "unadjusted" {
22888 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")]
22889 #[cfg_attr(
22890 any(target_arch = "aarch64", target_arch = "arm64ec"),
22891 link_name = "llvm.aarch64.neon.umax.v4i16"
22892 )]
22893 fn _vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
22894 }
22895 unsafe { _vmax_u16(a, b) }
22896}
22897#[doc = "Maximum (vector)"]
22898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
22899#[inline]
22900#[target_feature(enable = "neon")]
22901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22903#[cfg_attr(
22904 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22905 assert_instr(umax)
22906)]
22907#[cfg_attr(
22908 not(target_arch = "arm"),
22909 stable(feature = "neon_intrinsics", since = "1.59.0")
22910)]
22911#[cfg_attr(
22912 target_arch = "arm",
22913 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22914)]
22915pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
22916 unsafe extern "unadjusted" {
22917 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")]
22918 #[cfg_attr(
22919 any(target_arch = "aarch64", target_arch = "arm64ec"),
22920 link_name = "llvm.aarch64.neon.umax.v8i16"
22921 )]
22922 fn _vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
22923 }
22924 unsafe { _vmaxq_u16(a, b) }
22925}
22926#[doc = "Maximum (vector)"]
22927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
22928#[inline]
22929#[target_feature(enable = "neon")]
22930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22932#[cfg_attr(
22933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22934 assert_instr(umax)
22935)]
22936#[cfg_attr(
22937 not(target_arch = "arm"),
22938 stable(feature = "neon_intrinsics", since = "1.59.0")
22939)]
22940#[cfg_attr(
22941 target_arch = "arm",
22942 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22943)]
22944pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
22945 unsafe extern "unadjusted" {
22946 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")]
22947 #[cfg_attr(
22948 any(target_arch = "aarch64", target_arch = "arm64ec"),
22949 link_name = "llvm.aarch64.neon.umax.v2i32"
22950 )]
22951 fn _vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
22952 }
22953 unsafe { _vmax_u32(a, b) }
22954}
22955#[doc = "Maximum (vector)"]
22956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
22957#[inline]
22958#[target_feature(enable = "neon")]
22959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
22961#[cfg_attr(
22962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22963 assert_instr(umax)
22964)]
22965#[cfg_attr(
22966 not(target_arch = "arm"),
22967 stable(feature = "neon_intrinsics", since = "1.59.0")
22968)]
22969#[cfg_attr(
22970 target_arch = "arm",
22971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22972)]
22973pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
22974 unsafe extern "unadjusted" {
22975 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")]
22976 #[cfg_attr(
22977 any(target_arch = "aarch64", target_arch = "arm64ec"),
22978 link_name = "llvm.aarch64.neon.umax.v4i32"
22979 )]
22980 fn _vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
22981 }
22982 unsafe { _vmaxq_u32(a, b) }
22983}
22984#[doc = "Floating-point Maximum Number (vector)"]
22985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
22986#[inline]
22987#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
22988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
22989#[cfg_attr(
22990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22991 assert_instr(fmaxnm)
22992)]
22993#[target_feature(enable = "neon,fp16")]
22994#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22995pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
22996 unsafe extern "unadjusted" {
22997 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")]
22998 #[cfg_attr(
22999 any(target_arch = "aarch64", target_arch = "arm64ec"),
23000 link_name = "llvm.aarch64.neon.fmaxnm.v4f16"
23001 )]
23002 fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
23003 }
23004 unsafe { _vmaxnm_f16(a, b) }
23005}
23006#[doc = "Floating-point Maximum Number (vector)"]
23007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
23008#[inline]
23009#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23010#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
23011#[cfg_attr(
23012 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23013 assert_instr(fmaxnm)
23014)]
23015#[target_feature(enable = "neon,fp16")]
23016#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23017pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
23018 unsafe extern "unadjusted" {
23019 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")]
23020 #[cfg_attr(
23021 any(target_arch = "aarch64", target_arch = "arm64ec"),
23022 link_name = "llvm.aarch64.neon.fmaxnm.v8f16"
23023 )]
23024 fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
23025 }
23026 unsafe { _vmaxnmq_f16(a, b) }
23027}
23028#[doc = "Floating-point Maximum Number (vector)"]
23029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
23030#[inline]
23031#[target_feature(enable = "neon")]
23032#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
23034#[cfg_attr(
23035 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23036 assert_instr(fmaxnm)
23037)]
23038#[cfg_attr(
23039 not(target_arch = "arm"),
23040 stable(feature = "neon_intrinsics", since = "1.59.0")
23041)]
23042#[cfg_attr(
23043 target_arch = "arm",
23044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23045)]
23046pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
23047 unsafe extern "unadjusted" {
23048 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")]
23049 #[cfg_attr(
23050 any(target_arch = "aarch64", target_arch = "arm64ec"),
23051 link_name = "llvm.aarch64.neon.fmaxnm.v2f32"
23052 )]
23053 fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
23054 }
23055 unsafe { _vmaxnm_f32(a, b) }
23056}
23057#[doc = "Floating-point Maximum Number (vector)"]
23058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
23059#[inline]
23060#[target_feature(enable = "neon")]
23061#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
23063#[cfg_attr(
23064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23065 assert_instr(fmaxnm)
23066)]
23067#[cfg_attr(
23068 not(target_arch = "arm"),
23069 stable(feature = "neon_intrinsics", since = "1.59.0")
23070)]
23071#[cfg_attr(
23072 target_arch = "arm",
23073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23074)]
23075pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
23076 unsafe extern "unadjusted" {
23077 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")]
23078 #[cfg_attr(
23079 any(target_arch = "aarch64", target_arch = "arm64ec"),
23080 link_name = "llvm.aarch64.neon.fmaxnm.v4f32"
23081 )]
23082 fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
23083 }
23084 unsafe { _vmaxnmq_f32(a, b) }
23085}
23086#[doc = "Minimum (vector)"]
23087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
23088#[inline]
23089#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
23090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23091#[cfg_attr(
23092 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23093 assert_instr(fmin)
23094)]
23095#[target_feature(enable = "neon,fp16")]
23096#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23097pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
23098 unsafe extern "unadjusted" {
23099 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")]
23100 #[cfg_attr(
23101 any(target_arch = "aarch64", target_arch = "arm64ec"),
23102 link_name = "llvm.aarch64.neon.fmin.v4f16"
23103 )]
23104 fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
23105 }
23106 unsafe { _vmin_f16(a, b) }
23107}
23108#[doc = "Minimum (vector)"]
23109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
23110#[inline]
23111#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
23112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23113#[cfg_attr(
23114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23115 assert_instr(fmin)
23116)]
23117#[target_feature(enable = "neon,fp16")]
23118#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23119pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
23120 unsafe extern "unadjusted" {
23121 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")]
23122 #[cfg_attr(
23123 any(target_arch = "aarch64", target_arch = "arm64ec"),
23124 link_name = "llvm.aarch64.neon.fmin.v8f16"
23125 )]
23126 fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
23127 }
23128 unsafe { _vminq_f16(a, b) }
23129}
23130#[doc = "Minimum (vector)"]
23131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
23132#[inline]
23133#[target_feature(enable = "neon")]
23134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23136#[cfg_attr(
23137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23138 assert_instr(fmin)
23139)]
23140#[cfg_attr(
23141 not(target_arch = "arm"),
23142 stable(feature = "neon_intrinsics", since = "1.59.0")
23143)]
23144#[cfg_attr(
23145 target_arch = "arm",
23146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23147)]
23148pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
23149 unsafe extern "unadjusted" {
23150 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")]
23151 #[cfg_attr(
23152 any(target_arch = "aarch64", target_arch = "arm64ec"),
23153 link_name = "llvm.aarch64.neon.fmin.v2f32"
23154 )]
23155 fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
23156 }
23157 unsafe { _vmin_f32(a, b) }
23158}
23159#[doc = "Minimum (vector)"]
23160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
23161#[inline]
23162#[target_feature(enable = "neon")]
23163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23165#[cfg_attr(
23166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23167 assert_instr(fmin)
23168)]
23169#[cfg_attr(
23170 not(target_arch = "arm"),
23171 stable(feature = "neon_intrinsics", since = "1.59.0")
23172)]
23173#[cfg_attr(
23174 target_arch = "arm",
23175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23176)]
23177pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
23178 unsafe extern "unadjusted" {
23179 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")]
23180 #[cfg_attr(
23181 any(target_arch = "aarch64", target_arch = "arm64ec"),
23182 link_name = "llvm.aarch64.neon.fmin.v4f32"
23183 )]
23184 fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
23185 }
23186 unsafe { _vminq_f32(a, b) }
23187}
23188#[doc = "Minimum (vector)"]
23189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
23190#[inline]
23191#[target_feature(enable = "neon")]
23192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23194#[cfg_attr(
23195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23196 assert_instr(smin)
23197)]
23198#[cfg_attr(
23199 not(target_arch = "arm"),
23200 stable(feature = "neon_intrinsics", since = "1.59.0")
23201)]
23202#[cfg_attr(
23203 target_arch = "arm",
23204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23205)]
23206pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
23207 unsafe extern "unadjusted" {
23208 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")]
23209 #[cfg_attr(
23210 any(target_arch = "aarch64", target_arch = "arm64ec"),
23211 link_name = "llvm.aarch64.neon.smin.v8i8"
23212 )]
23213 fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
23214 }
23215 unsafe { _vmin_s8(a, b) }
23216}
23217#[doc = "Minimum (vector)"]
23218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
23219#[inline]
23220#[target_feature(enable = "neon")]
23221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23223#[cfg_attr(
23224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23225 assert_instr(smin)
23226)]
23227#[cfg_attr(
23228 not(target_arch = "arm"),
23229 stable(feature = "neon_intrinsics", since = "1.59.0")
23230)]
23231#[cfg_attr(
23232 target_arch = "arm",
23233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23234)]
23235pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
23236 unsafe extern "unadjusted" {
23237 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")]
23238 #[cfg_attr(
23239 any(target_arch = "aarch64", target_arch = "arm64ec"),
23240 link_name = "llvm.aarch64.neon.smin.v16i8"
23241 )]
23242 fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
23243 }
23244 unsafe { _vminq_s8(a, b) }
23245}
23246#[doc = "Minimum (vector)"]
23247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
23248#[inline]
23249#[target_feature(enable = "neon")]
23250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23252#[cfg_attr(
23253 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23254 assert_instr(smin)
23255)]
23256#[cfg_attr(
23257 not(target_arch = "arm"),
23258 stable(feature = "neon_intrinsics", since = "1.59.0")
23259)]
23260#[cfg_attr(
23261 target_arch = "arm",
23262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23263)]
23264pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
23265 unsafe extern "unadjusted" {
23266 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")]
23267 #[cfg_attr(
23268 any(target_arch = "aarch64", target_arch = "arm64ec"),
23269 link_name = "llvm.aarch64.neon.smin.v4i16"
23270 )]
23271 fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
23272 }
23273 unsafe { _vmin_s16(a, b) }
23274}
23275#[doc = "Minimum (vector)"]
23276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
23277#[inline]
23278#[target_feature(enable = "neon")]
23279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23281#[cfg_attr(
23282 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23283 assert_instr(smin)
23284)]
23285#[cfg_attr(
23286 not(target_arch = "arm"),
23287 stable(feature = "neon_intrinsics", since = "1.59.0")
23288)]
23289#[cfg_attr(
23290 target_arch = "arm",
23291 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23292)]
23293pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
23294 unsafe extern "unadjusted" {
23295 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")]
23296 #[cfg_attr(
23297 any(target_arch = "aarch64", target_arch = "arm64ec"),
23298 link_name = "llvm.aarch64.neon.smin.v8i16"
23299 )]
23300 fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
23301 }
23302 unsafe { _vminq_s16(a, b) }
23303}
23304#[doc = "Minimum (vector)"]
23305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
23306#[inline]
23307#[target_feature(enable = "neon")]
23308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23310#[cfg_attr(
23311 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23312 assert_instr(smin)
23313)]
23314#[cfg_attr(
23315 not(target_arch = "arm"),
23316 stable(feature = "neon_intrinsics", since = "1.59.0")
23317)]
23318#[cfg_attr(
23319 target_arch = "arm",
23320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23321)]
23322pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
23323 unsafe extern "unadjusted" {
23324 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")]
23325 #[cfg_attr(
23326 any(target_arch = "aarch64", target_arch = "arm64ec"),
23327 link_name = "llvm.aarch64.neon.smin.v2i32"
23328 )]
23329 fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
23330 }
23331 unsafe { _vmin_s32(a, b) }
23332}
23333#[doc = "Minimum (vector)"]
23334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
23335#[inline]
23336#[target_feature(enable = "neon")]
23337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23339#[cfg_attr(
23340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23341 assert_instr(smin)
23342)]
23343#[cfg_attr(
23344 not(target_arch = "arm"),
23345 stable(feature = "neon_intrinsics", since = "1.59.0")
23346)]
23347#[cfg_attr(
23348 target_arch = "arm",
23349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23350)]
23351pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
23352 unsafe extern "unadjusted" {
23353 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")]
23354 #[cfg_attr(
23355 any(target_arch = "aarch64", target_arch = "arm64ec"),
23356 link_name = "llvm.aarch64.neon.smin.v4i32"
23357 )]
23358 fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
23359 }
23360 unsafe { _vminq_s32(a, b) }
23361}
23362#[doc = "Minimum (vector)"]
23363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
23364#[inline]
23365#[target_feature(enable = "neon")]
23366#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23368#[cfg_attr(
23369 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23370 assert_instr(umin)
23371)]
23372#[cfg_attr(
23373 not(target_arch = "arm"),
23374 stable(feature = "neon_intrinsics", since = "1.59.0")
23375)]
23376#[cfg_attr(
23377 target_arch = "arm",
23378 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23379)]
23380pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
23381 unsafe extern "unadjusted" {
23382 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")]
23383 #[cfg_attr(
23384 any(target_arch = "aarch64", target_arch = "arm64ec"),
23385 link_name = "llvm.aarch64.neon.umin.v8i8"
23386 )]
23387 fn _vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
23388 }
23389 unsafe { _vmin_u8(a, b) }
23390}
23391#[doc = "Minimum (vector)"]
23392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
23393#[inline]
23394#[target_feature(enable = "neon")]
23395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23397#[cfg_attr(
23398 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23399 assert_instr(umin)
23400)]
23401#[cfg_attr(
23402 not(target_arch = "arm"),
23403 stable(feature = "neon_intrinsics", since = "1.59.0")
23404)]
23405#[cfg_attr(
23406 target_arch = "arm",
23407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23408)]
23409pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
23410 unsafe extern "unadjusted" {
23411 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")]
23412 #[cfg_attr(
23413 any(target_arch = "aarch64", target_arch = "arm64ec"),
23414 link_name = "llvm.aarch64.neon.umin.v16i8"
23415 )]
23416 fn _vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
23417 }
23418 unsafe { _vminq_u8(a, b) }
23419}
23420#[doc = "Minimum (vector)"]
23421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
23422#[inline]
23423#[target_feature(enable = "neon")]
23424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23426#[cfg_attr(
23427 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23428 assert_instr(umin)
23429)]
23430#[cfg_attr(
23431 not(target_arch = "arm"),
23432 stable(feature = "neon_intrinsics", since = "1.59.0")
23433)]
23434#[cfg_attr(
23435 target_arch = "arm",
23436 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23437)]
23438pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
23439 unsafe extern "unadjusted" {
23440 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")]
23441 #[cfg_attr(
23442 any(target_arch = "aarch64", target_arch = "arm64ec"),
23443 link_name = "llvm.aarch64.neon.umin.v4i16"
23444 )]
23445 fn _vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
23446 }
23447 unsafe { _vmin_u16(a, b) }
23448}
23449#[doc = "Minimum (vector)"]
23450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
23451#[inline]
23452#[target_feature(enable = "neon")]
23453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23454#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23455#[cfg_attr(
23456 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23457 assert_instr(umin)
23458)]
23459#[cfg_attr(
23460 not(target_arch = "arm"),
23461 stable(feature = "neon_intrinsics", since = "1.59.0")
23462)]
23463#[cfg_attr(
23464 target_arch = "arm",
23465 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23466)]
23467pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
23468 unsafe extern "unadjusted" {
23469 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")]
23470 #[cfg_attr(
23471 any(target_arch = "aarch64", target_arch = "arm64ec"),
23472 link_name = "llvm.aarch64.neon.umin.v8i16"
23473 )]
23474 fn _vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
23475 }
23476 unsafe { _vminq_u16(a, b) }
23477}
23478#[doc = "Minimum (vector)"]
23479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
23480#[inline]
23481#[target_feature(enable = "neon")]
23482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23484#[cfg_attr(
23485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23486 assert_instr(umin)
23487)]
23488#[cfg_attr(
23489 not(target_arch = "arm"),
23490 stable(feature = "neon_intrinsics", since = "1.59.0")
23491)]
23492#[cfg_attr(
23493 target_arch = "arm",
23494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23495)]
23496pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
23497 unsafe extern "unadjusted" {
23498 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")]
23499 #[cfg_attr(
23500 any(target_arch = "aarch64", target_arch = "arm64ec"),
23501 link_name = "llvm.aarch64.neon.umin.v2i32"
23502 )]
23503 fn _vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
23504 }
23505 unsafe { _vmin_u32(a, b) }
23506}
23507#[doc = "Minimum (vector)"]
23508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
23509#[inline]
23510#[target_feature(enable = "neon")]
23511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
23513#[cfg_attr(
23514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23515 assert_instr(umin)
23516)]
23517#[cfg_attr(
23518 not(target_arch = "arm"),
23519 stable(feature = "neon_intrinsics", since = "1.59.0")
23520)]
23521#[cfg_attr(
23522 target_arch = "arm",
23523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23524)]
23525pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
23526 unsafe extern "unadjusted" {
23527 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")]
23528 #[cfg_attr(
23529 any(target_arch = "aarch64", target_arch = "arm64ec"),
23530 link_name = "llvm.aarch64.neon.umin.v4i32"
23531 )]
23532 fn _vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
23533 }
23534 unsafe { _vminq_u32(a, b) }
23535}
23536#[doc = "Floating-point Minimum Number (vector)"]
23537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
23538#[inline]
23539#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
23541#[cfg_attr(
23542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23543 assert_instr(fminnm)
23544)]
23545#[target_feature(enable = "neon,fp16")]
23546#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23547pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
23548 unsafe extern "unadjusted" {
23549 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")]
23550 #[cfg_attr(
23551 any(target_arch = "aarch64", target_arch = "arm64ec"),
23552 link_name = "llvm.aarch64.neon.fminnm.v4f16"
23553 )]
23554 fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
23555 }
23556 unsafe { _vminnm_f16(a, b) }
23557}
23558#[doc = "Floating-point Minimum Number (vector)"]
23559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
23560#[inline]
23561#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
23563#[cfg_attr(
23564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23565 assert_instr(fminnm)
23566)]
23567#[target_feature(enable = "neon,fp16")]
23568#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23569pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
23570 unsafe extern "unadjusted" {
23571 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")]
23572 #[cfg_attr(
23573 any(target_arch = "aarch64", target_arch = "arm64ec"),
23574 link_name = "llvm.aarch64.neon.fminnm.v8f16"
23575 )]
23576 fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
23577 }
23578 unsafe { _vminnmq_f16(a, b) }
23579}
23580#[doc = "Floating-point Minimum Number (vector)"]
23581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
23582#[inline]
23583#[target_feature(enable = "neon")]
23584#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
23586#[cfg_attr(
23587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23588 assert_instr(fminnm)
23589)]
23590#[cfg_attr(
23591 not(target_arch = "arm"),
23592 stable(feature = "neon_intrinsics", since = "1.59.0")
23593)]
23594#[cfg_attr(
23595 target_arch = "arm",
23596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23597)]
23598pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
23599 unsafe extern "unadjusted" {
23600 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")]
23601 #[cfg_attr(
23602 any(target_arch = "aarch64", target_arch = "arm64ec"),
23603 link_name = "llvm.aarch64.neon.fminnm.v2f32"
23604 )]
23605 fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
23606 }
23607 unsafe { _vminnm_f32(a, b) }
23608}
23609#[doc = "Floating-point Minimum Number (vector)"]
23610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
23611#[inline]
23612#[target_feature(enable = "neon")]
23613#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
23614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
23615#[cfg_attr(
23616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23617 assert_instr(fminnm)
23618)]
23619#[cfg_attr(
23620 not(target_arch = "arm"),
23621 stable(feature = "neon_intrinsics", since = "1.59.0")
23622)]
23623#[cfg_attr(
23624 target_arch = "arm",
23625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23626)]
23627pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
23628 unsafe extern "unadjusted" {
23629 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")]
23630 #[cfg_attr(
23631 any(target_arch = "aarch64", target_arch = "arm64ec"),
23632 link_name = "llvm.aarch64.neon.fminnm.v4f32"
23633 )]
23634 fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
23635 }
23636 unsafe { _vminnmq_f32(a, b) }
23637}
23638#[doc = "Floating-point multiply-add to accumulator"]
23639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
23640#[inline]
23641#[target_feature(enable = "neon")]
23642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
23644#[cfg_attr(
23645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23646 assert_instr(fmul)
23647)]
23648#[cfg_attr(
23649 not(target_arch = "arm"),
23650 stable(feature = "neon_intrinsics", since = "1.59.0")
23651)]
23652#[cfg_attr(
23653 target_arch = "arm",
23654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23655)]
23656pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
23657 unsafe { simd_add(a, simd_mul(b, c)) }
23658}
23659#[doc = "Floating-point multiply-add to accumulator"]
23660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
23661#[inline]
23662#[target_feature(enable = "neon")]
23663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
23665#[cfg_attr(
23666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23667 assert_instr(fmul)
23668)]
23669#[cfg_attr(
23670 not(target_arch = "arm"),
23671 stable(feature = "neon_intrinsics", since = "1.59.0")
23672)]
23673#[cfg_attr(
23674 target_arch = "arm",
23675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23676)]
23677pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
23678 unsafe { simd_add(a, simd_mul(b, c)) }
23679}
23680#[doc = "Vector multiply accumulate with scalar"]
23681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
23682#[inline]
23683#[target_feature(enable = "neon")]
23684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
23686#[cfg_attr(
23687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23688 assert_instr(fmul, LANE = 1)
23689)]
23690#[rustc_legacy_const_generics(3)]
23691#[cfg_attr(
23692 not(target_arch = "arm"),
23693 stable(feature = "neon_intrinsics", since = "1.59.0")
23694)]
23695#[cfg_attr(
23696 target_arch = "arm",
23697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23698)]
23699pub fn vmla_lane_f32<const LANE: i32>(
23700 a: float32x2_t,
23701 b: float32x2_t,
23702 c: float32x2_t,
23703) -> float32x2_t {
23704 static_assert_uimm_bits!(LANE, 1);
23705 unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
23706}
23707#[doc = "Vector multiply accumulate with scalar"]
23708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
23709#[inline]
23710#[target_feature(enable = "neon")]
23711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23712#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
23713#[cfg_attr(
23714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23715 assert_instr(fmul, LANE = 1)
23716)]
23717#[rustc_legacy_const_generics(3)]
23718#[cfg_attr(
23719 not(target_arch = "arm"),
23720 stable(feature = "neon_intrinsics", since = "1.59.0")
23721)]
23722#[cfg_attr(
23723 target_arch = "arm",
23724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23725)]
23726pub fn vmla_laneq_f32<const LANE: i32>(
23727 a: float32x2_t,
23728 b: float32x2_t,
23729 c: float32x4_t,
23730) -> float32x2_t {
23731 static_assert_uimm_bits!(LANE, 2);
23732 unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
23733}
23734#[doc = "Vector multiply accumulate with scalar"]
23735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
23736#[inline]
23737#[target_feature(enable = "neon")]
23738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23739#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
23740#[cfg_attr(
23741 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23742 assert_instr(fmul, LANE = 1)
23743)]
23744#[rustc_legacy_const_generics(3)]
23745#[cfg_attr(
23746 not(target_arch = "arm"),
23747 stable(feature = "neon_intrinsics", since = "1.59.0")
23748)]
23749#[cfg_attr(
23750 target_arch = "arm",
23751 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23752)]
23753pub fn vmlaq_lane_f32<const LANE: i32>(
23754 a: float32x4_t,
23755 b: float32x4_t,
23756 c: float32x2_t,
23757) -> float32x4_t {
23758 static_assert_uimm_bits!(LANE, 1);
23759 unsafe {
23760 vmlaq_f32(
23761 a,
23762 b,
23763 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
23764 )
23765 }
23766}
23767#[doc = "Vector multiply accumulate with scalar"]
23768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
23769#[inline]
23770#[target_feature(enable = "neon")]
23771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23772#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
23773#[cfg_attr(
23774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23775 assert_instr(fmul, LANE = 1)
23776)]
23777#[rustc_legacy_const_generics(3)]
23778#[cfg_attr(
23779 not(target_arch = "arm"),
23780 stable(feature = "neon_intrinsics", since = "1.59.0")
23781)]
23782#[cfg_attr(
23783 target_arch = "arm",
23784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23785)]
23786pub fn vmlaq_laneq_f32<const LANE: i32>(
23787 a: float32x4_t,
23788 b: float32x4_t,
23789 c: float32x4_t,
23790) -> float32x4_t {
23791 static_assert_uimm_bits!(LANE, 2);
23792 unsafe {
23793 vmlaq_f32(
23794 a,
23795 b,
23796 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
23797 )
23798 }
23799}
23800#[doc = "Vector multiply accumulate with scalar"]
23801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
23802#[inline]
23803#[target_feature(enable = "neon")]
23804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23805#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
23806#[cfg_attr(
23807 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23808 assert_instr(mla, LANE = 1)
23809)]
23810#[rustc_legacy_const_generics(3)]
23811#[cfg_attr(
23812 not(target_arch = "arm"),
23813 stable(feature = "neon_intrinsics", since = "1.59.0")
23814)]
23815#[cfg_attr(
23816 target_arch = "arm",
23817 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23818)]
23819pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
23820 static_assert_uimm_bits!(LANE, 2);
23821 unsafe {
23822 vmla_s16(
23823 a,
23824 b,
23825 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
23826 )
23827 }
23828}
23829#[doc = "Vector multiply accumulate with scalar"]
23830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
23831#[inline]
23832#[target_feature(enable = "neon")]
23833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23834#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
23835#[cfg_attr(
23836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23837 assert_instr(mla, LANE = 1)
23838)]
23839#[rustc_legacy_const_generics(3)]
23840#[cfg_attr(
23841 not(target_arch = "arm"),
23842 stable(feature = "neon_intrinsics", since = "1.59.0")
23843)]
23844#[cfg_attr(
23845 target_arch = "arm",
23846 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23847)]
23848pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
23849 static_assert_uimm_bits!(LANE, 2);
23850 unsafe {
23851 vmla_u16(
23852 a,
23853 b,
23854 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
23855 )
23856 }
23857}
23858#[doc = "Vector multiply accumulate with scalar"]
23859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
23860#[inline]
23861#[target_feature(enable = "neon")]
23862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
23864#[cfg_attr(
23865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23866 assert_instr(mla, LANE = 1)
23867)]
23868#[rustc_legacy_const_generics(3)]
23869#[cfg_attr(
23870 not(target_arch = "arm"),
23871 stable(feature = "neon_intrinsics", since = "1.59.0")
23872)]
23873#[cfg_attr(
23874 target_arch = "arm",
23875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23876)]
23877pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
23878 static_assert_uimm_bits!(LANE, 3);
23879 unsafe {
23880 vmla_s16(
23881 a,
23882 b,
23883 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
23884 )
23885 }
23886}
23887#[doc = "Vector multiply accumulate with scalar"]
23888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
23889#[inline]
23890#[target_feature(enable = "neon")]
23891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
23893#[cfg_attr(
23894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23895 assert_instr(mla, LANE = 1)
23896)]
23897#[rustc_legacy_const_generics(3)]
23898#[cfg_attr(
23899 not(target_arch = "arm"),
23900 stable(feature = "neon_intrinsics", since = "1.59.0")
23901)]
23902#[cfg_attr(
23903 target_arch = "arm",
23904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23905)]
23906pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
23907 static_assert_uimm_bits!(LANE, 3);
23908 unsafe {
23909 vmla_u16(
23910 a,
23911 b,
23912 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
23913 )
23914 }
23915}
23916#[doc = "Vector multiply accumulate with scalar"]
23917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
23918#[inline]
23919#[target_feature(enable = "neon")]
23920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23921#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
23922#[cfg_attr(
23923 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23924 assert_instr(mla, LANE = 1)
23925)]
23926#[rustc_legacy_const_generics(3)]
23927#[cfg_attr(
23928 not(target_arch = "arm"),
23929 stable(feature = "neon_intrinsics", since = "1.59.0")
23930)]
23931#[cfg_attr(
23932 target_arch = "arm",
23933 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23934)]
23935pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
23936 static_assert_uimm_bits!(LANE, 2);
23937 unsafe {
23938 vmlaq_s16(
23939 a,
23940 b,
23941 simd_shuffle!(
23942 c,
23943 c,
23944 [
23945 LANE as u32,
23946 LANE as u32,
23947 LANE as u32,
23948 LANE as u32,
23949 LANE as u32,
23950 LANE as u32,
23951 LANE as u32,
23952 LANE as u32
23953 ]
23954 ),
23955 )
23956 }
23957}
23958#[doc = "Vector multiply accumulate with scalar"]
23959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
23960#[inline]
23961#[target_feature(enable = "neon")]
23962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23963#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
23964#[cfg_attr(
23965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23966 assert_instr(mla, LANE = 1)
23967)]
23968#[rustc_legacy_const_generics(3)]
23969#[cfg_attr(
23970 not(target_arch = "arm"),
23971 stable(feature = "neon_intrinsics", since = "1.59.0")
23972)]
23973#[cfg_attr(
23974 target_arch = "arm",
23975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23976)]
23977pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
23978 static_assert_uimm_bits!(LANE, 2);
23979 unsafe {
23980 vmlaq_u16(
23981 a,
23982 b,
23983 simd_shuffle!(
23984 c,
23985 c,
23986 [
23987 LANE as u32,
23988 LANE as u32,
23989 LANE as u32,
23990 LANE as u32,
23991 LANE as u32,
23992 LANE as u32,
23993 LANE as u32,
23994 LANE as u32
23995 ]
23996 ),
23997 )
23998 }
23999}
24000#[doc = "Vector multiply accumulate with scalar"]
24001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
24002#[inline]
24003#[target_feature(enable = "neon")]
24004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24005#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
24006#[cfg_attr(
24007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24008 assert_instr(mla, LANE = 1)
24009)]
24010#[rustc_legacy_const_generics(3)]
24011#[cfg_attr(
24012 not(target_arch = "arm"),
24013 stable(feature = "neon_intrinsics", since = "1.59.0")
24014)]
24015#[cfg_attr(
24016 target_arch = "arm",
24017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24018)]
24019pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
24020 static_assert_uimm_bits!(LANE, 3);
24021 unsafe {
24022 vmlaq_s16(
24023 a,
24024 b,
24025 simd_shuffle!(
24026 c,
24027 c,
24028 [
24029 LANE as u32,
24030 LANE as u32,
24031 LANE as u32,
24032 LANE as u32,
24033 LANE as u32,
24034 LANE as u32,
24035 LANE as u32,
24036 LANE as u32
24037 ]
24038 ),
24039 )
24040 }
24041}
24042#[doc = "Vector multiply accumulate with scalar"]
24043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
24044#[inline]
24045#[target_feature(enable = "neon")]
24046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24047#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
24048#[cfg_attr(
24049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24050 assert_instr(mla, LANE = 1)
24051)]
24052#[rustc_legacy_const_generics(3)]
24053#[cfg_attr(
24054 not(target_arch = "arm"),
24055 stable(feature = "neon_intrinsics", since = "1.59.0")
24056)]
24057#[cfg_attr(
24058 target_arch = "arm",
24059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24060)]
24061pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
24062 static_assert_uimm_bits!(LANE, 3);
24063 unsafe {
24064 vmlaq_u16(
24065 a,
24066 b,
24067 simd_shuffle!(
24068 c,
24069 c,
24070 [
24071 LANE as u32,
24072 LANE as u32,
24073 LANE as u32,
24074 LANE as u32,
24075 LANE as u32,
24076 LANE as u32,
24077 LANE as u32,
24078 LANE as u32
24079 ]
24080 ),
24081 )
24082 }
24083}
24084#[doc = "Vector multiply accumulate with scalar"]
24085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
24086#[inline]
24087#[target_feature(enable = "neon")]
24088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24089#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24090#[cfg_attr(
24091 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24092 assert_instr(mla, LANE = 1)
24093)]
24094#[rustc_legacy_const_generics(3)]
24095#[cfg_attr(
24096 not(target_arch = "arm"),
24097 stable(feature = "neon_intrinsics", since = "1.59.0")
24098)]
24099#[cfg_attr(
24100 target_arch = "arm",
24101 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24102)]
24103pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
24104 static_assert_uimm_bits!(LANE, 1);
24105 unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24106}
24107#[doc = "Vector multiply accumulate with scalar"]
24108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
24109#[inline]
24110#[target_feature(enable = "neon")]
24111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24112#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24113#[cfg_attr(
24114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24115 assert_instr(mla, LANE = 1)
24116)]
24117#[rustc_legacy_const_generics(3)]
24118#[cfg_attr(
24119 not(target_arch = "arm"),
24120 stable(feature = "neon_intrinsics", since = "1.59.0")
24121)]
24122#[cfg_attr(
24123 target_arch = "arm",
24124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24125)]
24126pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
24127 static_assert_uimm_bits!(LANE, 1);
24128 unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24129}
24130#[doc = "Vector multiply accumulate with scalar"]
24131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
24132#[inline]
24133#[target_feature(enable = "neon")]
24134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24135#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24136#[cfg_attr(
24137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24138 assert_instr(mla, LANE = 1)
24139)]
24140#[rustc_legacy_const_generics(3)]
24141#[cfg_attr(
24142 not(target_arch = "arm"),
24143 stable(feature = "neon_intrinsics", since = "1.59.0")
24144)]
24145#[cfg_attr(
24146 target_arch = "arm",
24147 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24148)]
24149pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
24150 static_assert_uimm_bits!(LANE, 2);
24151 unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24152}
24153#[doc = "Vector multiply accumulate with scalar"]
24154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
24155#[inline]
24156#[target_feature(enable = "neon")]
24157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24159#[cfg_attr(
24160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24161 assert_instr(mla, LANE = 1)
24162)]
24163#[rustc_legacy_const_generics(3)]
24164#[cfg_attr(
24165 not(target_arch = "arm"),
24166 stable(feature = "neon_intrinsics", since = "1.59.0")
24167)]
24168#[cfg_attr(
24169 target_arch = "arm",
24170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24171)]
24172pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
24173 static_assert_uimm_bits!(LANE, 2);
24174 unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24175}
24176#[doc = "Vector multiply accumulate with scalar"]
24177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
24178#[inline]
24179#[target_feature(enable = "neon")]
24180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24181#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24182#[cfg_attr(
24183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24184 assert_instr(mla, LANE = 1)
24185)]
24186#[rustc_legacy_const_generics(3)]
24187#[cfg_attr(
24188 not(target_arch = "arm"),
24189 stable(feature = "neon_intrinsics", since = "1.59.0")
24190)]
24191#[cfg_attr(
24192 target_arch = "arm",
24193 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24194)]
24195pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
24196 static_assert_uimm_bits!(LANE, 1);
24197 unsafe {
24198 vmlaq_s32(
24199 a,
24200 b,
24201 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24202 )
24203 }
24204}
24205#[doc = "Vector multiply accumulate with scalar"]
24206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
24207#[inline]
24208#[target_feature(enable = "neon")]
24209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24210#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24211#[cfg_attr(
24212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24213 assert_instr(mla, LANE = 1)
24214)]
24215#[rustc_legacy_const_generics(3)]
24216#[cfg_attr(
24217 not(target_arch = "arm"),
24218 stable(feature = "neon_intrinsics", since = "1.59.0")
24219)]
24220#[cfg_attr(
24221 target_arch = "arm",
24222 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24223)]
24224pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
24225 static_assert_uimm_bits!(LANE, 1);
24226 unsafe {
24227 vmlaq_u32(
24228 a,
24229 b,
24230 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24231 )
24232 }
24233}
24234#[doc = "Vector multiply accumulate with scalar"]
24235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
24236#[inline]
24237#[target_feature(enable = "neon")]
24238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24240#[cfg_attr(
24241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24242 assert_instr(mla, LANE = 1)
24243)]
24244#[rustc_legacy_const_generics(3)]
24245#[cfg_attr(
24246 not(target_arch = "arm"),
24247 stable(feature = "neon_intrinsics", since = "1.59.0")
24248)]
24249#[cfg_attr(
24250 target_arch = "arm",
24251 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24252)]
24253pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
24254 static_assert_uimm_bits!(LANE, 2);
24255 unsafe {
24256 vmlaq_s32(
24257 a,
24258 b,
24259 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24260 )
24261 }
24262}
24263#[doc = "Vector multiply accumulate with scalar"]
24264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
24265#[inline]
24266#[target_feature(enable = "neon")]
24267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
24269#[cfg_attr(
24270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24271 assert_instr(mla, LANE = 1)
24272)]
24273#[rustc_legacy_const_generics(3)]
24274#[cfg_attr(
24275 not(target_arch = "arm"),
24276 stable(feature = "neon_intrinsics", since = "1.59.0")
24277)]
24278#[cfg_attr(
24279 target_arch = "arm",
24280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24281)]
24282pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
24283 static_assert_uimm_bits!(LANE, 2);
24284 unsafe {
24285 vmlaq_u32(
24286 a,
24287 b,
24288 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24289 )
24290 }
24291}
24292#[doc = "Vector multiply accumulate with scalar"]
24293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
24294#[inline]
24295#[target_feature(enable = "neon")]
24296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
24298#[cfg_attr(
24299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24300 assert_instr(fmul)
24301)]
24302#[cfg_attr(
24303 not(target_arch = "arm"),
24304 stable(feature = "neon_intrinsics", since = "1.59.0")
24305)]
24306#[cfg_attr(
24307 target_arch = "arm",
24308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24309)]
24310pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
24311 vmla_f32(a, b, vdup_n_f32(c))
24312}
24313#[doc = "Vector multiply accumulate with scalar"]
24314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
24315#[inline]
24316#[target_feature(enable = "neon")]
24317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24318#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
24319#[cfg_attr(
24320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24321 assert_instr(fmul)
24322)]
24323#[cfg_attr(
24324 not(target_arch = "arm"),
24325 stable(feature = "neon_intrinsics", since = "1.59.0")
24326)]
24327#[cfg_attr(
24328 target_arch = "arm",
24329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24330)]
24331pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
24332 vmlaq_f32(a, b, vdupq_n_f32(c))
24333}
24334#[doc = "Vector multiply accumulate with scalar"]
24335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
24336#[inline]
24337#[target_feature(enable = "neon")]
24338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24339#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24340#[cfg_attr(
24341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24342 assert_instr(mla)
24343)]
24344#[cfg_attr(
24345 not(target_arch = "arm"),
24346 stable(feature = "neon_intrinsics", since = "1.59.0")
24347)]
24348#[cfg_attr(
24349 target_arch = "arm",
24350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24351)]
24352pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
24353 vmla_s16(a, b, vdup_n_s16(c))
24354}
24355#[doc = "Vector multiply accumulate with scalar"]
24356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
24357#[inline]
24358#[target_feature(enable = "neon")]
24359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24360#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24361#[cfg_attr(
24362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24363 assert_instr(mla)
24364)]
24365#[cfg_attr(
24366 not(target_arch = "arm"),
24367 stable(feature = "neon_intrinsics", since = "1.59.0")
24368)]
24369#[cfg_attr(
24370 target_arch = "arm",
24371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24372)]
24373pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
24374 vmlaq_s16(a, b, vdupq_n_s16(c))
24375}
24376#[doc = "Vector multiply accumulate with scalar"]
24377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
24378#[inline]
24379#[target_feature(enable = "neon")]
24380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24381#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24382#[cfg_attr(
24383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24384 assert_instr(mla)
24385)]
24386#[cfg_attr(
24387 not(target_arch = "arm"),
24388 stable(feature = "neon_intrinsics", since = "1.59.0")
24389)]
24390#[cfg_attr(
24391 target_arch = "arm",
24392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24393)]
24394pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
24395 vmla_u16(a, b, vdup_n_u16(c))
24396}
24397#[doc = "Vector multiply accumulate with scalar"]
24398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
24399#[inline]
24400#[target_feature(enable = "neon")]
24401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24403#[cfg_attr(
24404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24405 assert_instr(mla)
24406)]
24407#[cfg_attr(
24408 not(target_arch = "arm"),
24409 stable(feature = "neon_intrinsics", since = "1.59.0")
24410)]
24411#[cfg_attr(
24412 target_arch = "arm",
24413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24414)]
24415pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
24416 vmlaq_u16(a, b, vdupq_n_u16(c))
24417}
24418#[doc = "Vector multiply accumulate with scalar"]
24419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
24420#[inline]
24421#[target_feature(enable = "neon")]
24422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24423#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24424#[cfg_attr(
24425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24426 assert_instr(mla)
24427)]
24428#[cfg_attr(
24429 not(target_arch = "arm"),
24430 stable(feature = "neon_intrinsics", since = "1.59.0")
24431)]
24432#[cfg_attr(
24433 target_arch = "arm",
24434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24435)]
24436pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
24437 vmla_s32(a, b, vdup_n_s32(c))
24438}
24439#[doc = "Vector multiply accumulate with scalar"]
24440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
24441#[inline]
24442#[target_feature(enable = "neon")]
24443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24444#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24445#[cfg_attr(
24446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24447 assert_instr(mla)
24448)]
24449#[cfg_attr(
24450 not(target_arch = "arm"),
24451 stable(feature = "neon_intrinsics", since = "1.59.0")
24452)]
24453#[cfg_attr(
24454 target_arch = "arm",
24455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24456)]
24457pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
24458 vmlaq_s32(a, b, vdupq_n_s32(c))
24459}
24460#[doc = "Vector multiply accumulate with scalar"]
24461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
24462#[inline]
24463#[target_feature(enable = "neon")]
24464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24465#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24466#[cfg_attr(
24467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24468 assert_instr(mla)
24469)]
24470#[cfg_attr(
24471 not(target_arch = "arm"),
24472 stable(feature = "neon_intrinsics", since = "1.59.0")
24473)]
24474#[cfg_attr(
24475 target_arch = "arm",
24476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24477)]
24478pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
24479 vmla_u32(a, b, vdup_n_u32(c))
24480}
24481#[doc = "Vector multiply accumulate with scalar"]
24482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
24483#[inline]
24484#[target_feature(enable = "neon")]
24485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24486#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24487#[cfg_attr(
24488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24489 assert_instr(mla)
24490)]
24491#[cfg_attr(
24492 not(target_arch = "arm"),
24493 stable(feature = "neon_intrinsics", since = "1.59.0")
24494)]
24495#[cfg_attr(
24496 target_arch = "arm",
24497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24498)]
24499pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
24500 vmlaq_u32(a, b, vdupq_n_u32(c))
24501}
24502#[doc = "Multiply-add to accumulator"]
24503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
24504#[inline]
24505#[target_feature(enable = "neon")]
24506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24507#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
24508#[cfg_attr(
24509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24510 assert_instr(mla)
24511)]
24512#[cfg_attr(
24513 not(target_arch = "arm"),
24514 stable(feature = "neon_intrinsics", since = "1.59.0")
24515)]
24516#[cfg_attr(
24517 target_arch = "arm",
24518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24519)]
24520pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
24521 unsafe { simd_add(a, simd_mul(b, c)) }
24522}
24523#[doc = "Multiply-add to accumulator"]
24524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
24525#[inline]
24526#[target_feature(enable = "neon")]
24527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24528#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
24529#[cfg_attr(
24530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24531 assert_instr(mla)
24532)]
24533#[cfg_attr(
24534 not(target_arch = "arm"),
24535 stable(feature = "neon_intrinsics", since = "1.59.0")
24536)]
24537#[cfg_attr(
24538 target_arch = "arm",
24539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24540)]
24541pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
24542 unsafe { simd_add(a, simd_mul(b, c)) }
24543}
24544#[doc = "Multiply-add to accumulator"]
24545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
24546#[inline]
24547#[target_feature(enable = "neon")]
24548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24549#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24550#[cfg_attr(
24551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24552 assert_instr(mla)
24553)]
24554#[cfg_attr(
24555 not(target_arch = "arm"),
24556 stable(feature = "neon_intrinsics", since = "1.59.0")
24557)]
24558#[cfg_attr(
24559 target_arch = "arm",
24560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24561)]
24562pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
24563 unsafe { simd_add(a, simd_mul(b, c)) }
24564}
24565#[doc = "Multiply-add to accumulator"]
24566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
24567#[inline]
24568#[target_feature(enable = "neon")]
24569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24570#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24571#[cfg_attr(
24572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24573 assert_instr(mla)
24574)]
24575#[cfg_attr(
24576 not(target_arch = "arm"),
24577 stable(feature = "neon_intrinsics", since = "1.59.0")
24578)]
24579#[cfg_attr(
24580 target_arch = "arm",
24581 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24582)]
24583pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
24584 unsafe { simd_add(a, simd_mul(b, c)) }
24585}
24586#[doc = "Multiply-add to accumulator"]
24587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
24588#[inline]
24589#[target_feature(enable = "neon")]
24590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24592#[cfg_attr(
24593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24594 assert_instr(mla)
24595)]
24596#[cfg_attr(
24597 not(target_arch = "arm"),
24598 stable(feature = "neon_intrinsics", since = "1.59.0")
24599)]
24600#[cfg_attr(
24601 target_arch = "arm",
24602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24603)]
24604pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
24605 unsafe { simd_add(a, simd_mul(b, c)) }
24606}
24607#[doc = "Multiply-add to accumulator"]
24608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
24609#[inline]
24610#[target_feature(enable = "neon")]
24611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24613#[cfg_attr(
24614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24615 assert_instr(mla)
24616)]
24617#[cfg_attr(
24618 not(target_arch = "arm"),
24619 stable(feature = "neon_intrinsics", since = "1.59.0")
24620)]
24621#[cfg_attr(
24622 target_arch = "arm",
24623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24624)]
24625pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
24626 unsafe { simd_add(a, simd_mul(b, c)) }
24627}
24628#[doc = "Multiply-add to accumulator"]
24629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
24630#[inline]
24631#[target_feature(enable = "neon")]
24632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24633#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
24634#[cfg_attr(
24635 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24636 assert_instr(mla)
24637)]
24638#[cfg_attr(
24639 not(target_arch = "arm"),
24640 stable(feature = "neon_intrinsics", since = "1.59.0")
24641)]
24642#[cfg_attr(
24643 target_arch = "arm",
24644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24645)]
24646pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
24647 unsafe { simd_add(a, simd_mul(b, c)) }
24648}
24649#[doc = "Multiply-add to accumulator"]
24650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
24651#[inline]
24652#[target_feature(enable = "neon")]
24653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24654#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
24655#[cfg_attr(
24656 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24657 assert_instr(mla)
24658)]
24659#[cfg_attr(
24660 not(target_arch = "arm"),
24661 stable(feature = "neon_intrinsics", since = "1.59.0")
24662)]
24663#[cfg_attr(
24664 target_arch = "arm",
24665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24666)]
24667pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
24668 unsafe { simd_add(a, simd_mul(b, c)) }
24669}
24670#[doc = "Multiply-add to accumulator"]
24671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
24672#[inline]
24673#[target_feature(enable = "neon")]
24674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24676#[cfg_attr(
24677 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24678 assert_instr(mla)
24679)]
24680#[cfg_attr(
24681 not(target_arch = "arm"),
24682 stable(feature = "neon_intrinsics", since = "1.59.0")
24683)]
24684#[cfg_attr(
24685 target_arch = "arm",
24686 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24687)]
24688pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
24689 unsafe { simd_add(a, simd_mul(b, c)) }
24690}
24691#[doc = "Multiply-add to accumulator"]
24692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
24693#[inline]
24694#[target_feature(enable = "neon")]
24695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24696#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
24697#[cfg_attr(
24698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24699 assert_instr(mla)
24700)]
24701#[cfg_attr(
24702 not(target_arch = "arm"),
24703 stable(feature = "neon_intrinsics", since = "1.59.0")
24704)]
24705#[cfg_attr(
24706 target_arch = "arm",
24707 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24708)]
24709pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
24710 unsafe { simd_add(a, simd_mul(b, c)) }
24711}
24712#[doc = "Multiply-add to accumulator"]
24713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
24714#[inline]
24715#[target_feature(enable = "neon")]
24716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24717#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24718#[cfg_attr(
24719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24720 assert_instr(mla)
24721)]
24722#[cfg_attr(
24723 not(target_arch = "arm"),
24724 stable(feature = "neon_intrinsics", since = "1.59.0")
24725)]
24726#[cfg_attr(
24727 target_arch = "arm",
24728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24729)]
24730pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
24731 unsafe { simd_add(a, simd_mul(b, c)) }
24732}
24733#[doc = "Multiply-add to accumulator"]
24734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
24735#[inline]
24736#[target_feature(enable = "neon")]
24737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
24739#[cfg_attr(
24740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24741 assert_instr(mla)
24742)]
24743#[cfg_attr(
24744 not(target_arch = "arm"),
24745 stable(feature = "neon_intrinsics", since = "1.59.0")
24746)]
24747#[cfg_attr(
24748 target_arch = "arm",
24749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24750)]
24751pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
24752 unsafe { simd_add(a, simd_mul(b, c)) }
24753}
24754#[doc = "Vector widening multiply accumulate with scalar"]
24755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
24756#[inline]
24757#[target_feature(enable = "neon")]
24758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24759#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
24760#[cfg_attr(
24761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24762 assert_instr(smlal, LANE = 1)
24763)]
24764#[rustc_legacy_const_generics(3)]
24765#[cfg_attr(
24766 not(target_arch = "arm"),
24767 stable(feature = "neon_intrinsics", since = "1.59.0")
24768)]
24769#[cfg_attr(
24770 target_arch = "arm",
24771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24772)]
24773pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
24774 static_assert_uimm_bits!(LANE, 2);
24775 unsafe {
24776 vmlal_s16(
24777 a,
24778 b,
24779 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24780 )
24781 }
24782}
24783#[doc = "Vector widening multiply accumulate with scalar"]
24784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
24785#[inline]
24786#[target_feature(enable = "neon")]
24787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24788#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
24789#[cfg_attr(
24790 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24791 assert_instr(smlal, LANE = 1)
24792)]
24793#[rustc_legacy_const_generics(3)]
24794#[cfg_attr(
24795 not(target_arch = "arm"),
24796 stable(feature = "neon_intrinsics", since = "1.59.0")
24797)]
24798#[cfg_attr(
24799 target_arch = "arm",
24800 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24801)]
24802pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
24803 static_assert_uimm_bits!(LANE, 3);
24804 unsafe {
24805 vmlal_s16(
24806 a,
24807 b,
24808 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24809 )
24810 }
24811}
24812#[doc = "Vector widening multiply accumulate with scalar"]
24813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
24814#[inline]
24815#[target_feature(enable = "neon")]
24816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24817#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
24818#[cfg_attr(
24819 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24820 assert_instr(smlal, LANE = 1)
24821)]
24822#[rustc_legacy_const_generics(3)]
24823#[cfg_attr(
24824 not(target_arch = "arm"),
24825 stable(feature = "neon_intrinsics", since = "1.59.0")
24826)]
24827#[cfg_attr(
24828 target_arch = "arm",
24829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24830)]
24831pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
24832 static_assert_uimm_bits!(LANE, 1);
24833 unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24834}
24835#[doc = "Vector widening multiply accumulate with scalar"]
24836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
24837#[inline]
24838#[target_feature(enable = "neon")]
24839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
24841#[cfg_attr(
24842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24843 assert_instr(smlal, LANE = 1)
24844)]
24845#[rustc_legacy_const_generics(3)]
24846#[cfg_attr(
24847 not(target_arch = "arm"),
24848 stable(feature = "neon_intrinsics", since = "1.59.0")
24849)]
24850#[cfg_attr(
24851 target_arch = "arm",
24852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24853)]
24854pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
24855 static_assert_uimm_bits!(LANE, 2);
24856 unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24857}
24858#[doc = "Vector widening multiply accumulate with scalar"]
24859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
24860#[inline]
24861#[target_feature(enable = "neon")]
24862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
24864#[cfg_attr(
24865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24866 assert_instr(umlal, LANE = 1)
24867)]
24868#[rustc_legacy_const_generics(3)]
24869#[cfg_attr(
24870 not(target_arch = "arm"),
24871 stable(feature = "neon_intrinsics", since = "1.59.0")
24872)]
24873#[cfg_attr(
24874 target_arch = "arm",
24875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24876)]
24877pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
24878 static_assert_uimm_bits!(LANE, 2);
24879 unsafe {
24880 vmlal_u16(
24881 a,
24882 b,
24883 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24884 )
24885 }
24886}
24887#[doc = "Vector widening multiply accumulate with scalar"]
24888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
24889#[inline]
24890#[target_feature(enable = "neon")]
24891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
24893#[cfg_attr(
24894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24895 assert_instr(umlal, LANE = 1)
24896)]
24897#[rustc_legacy_const_generics(3)]
24898#[cfg_attr(
24899 not(target_arch = "arm"),
24900 stable(feature = "neon_intrinsics", since = "1.59.0")
24901)]
24902#[cfg_attr(
24903 target_arch = "arm",
24904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24905)]
24906pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
24907 static_assert_uimm_bits!(LANE, 3);
24908 unsafe {
24909 vmlal_u16(
24910 a,
24911 b,
24912 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
24913 )
24914 }
24915}
24916#[doc = "Vector widening multiply accumulate with scalar"]
24917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
24918#[inline]
24919#[target_feature(enable = "neon")]
24920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24921#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
24922#[cfg_attr(
24923 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24924 assert_instr(umlal, LANE = 1)
24925)]
24926#[rustc_legacy_const_generics(3)]
24927#[cfg_attr(
24928 not(target_arch = "arm"),
24929 stable(feature = "neon_intrinsics", since = "1.59.0")
24930)]
24931#[cfg_attr(
24932 target_arch = "arm",
24933 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24934)]
24935pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
24936 static_assert_uimm_bits!(LANE, 1);
24937 unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24938}
24939#[doc = "Vector widening multiply accumulate with scalar"]
24940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
24941#[inline]
24942#[target_feature(enable = "neon")]
24943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24944#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
24945#[cfg_attr(
24946 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24947 assert_instr(umlal, LANE = 1)
24948)]
24949#[rustc_legacy_const_generics(3)]
24950#[cfg_attr(
24951 not(target_arch = "arm"),
24952 stable(feature = "neon_intrinsics", since = "1.59.0")
24953)]
24954#[cfg_attr(
24955 target_arch = "arm",
24956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24957)]
24958pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
24959 static_assert_uimm_bits!(LANE, 2);
24960 unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
24961}
24962#[doc = "Vector widening multiply accumulate with scalar"]
24963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
24964#[inline]
24965#[target_feature(enable = "neon")]
24966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24967#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
24968#[cfg_attr(
24969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24970 assert_instr(smlal)
24971)]
24972#[cfg_attr(
24973 not(target_arch = "arm"),
24974 stable(feature = "neon_intrinsics", since = "1.59.0")
24975)]
24976#[cfg_attr(
24977 target_arch = "arm",
24978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24979)]
24980pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
24981 vmlal_s16(a, b, vdup_n_s16(c))
24982}
24983#[doc = "Vector widening multiply accumulate with scalar"]
24984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
24985#[inline]
24986#[target_feature(enable = "neon")]
24987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
24989#[cfg_attr(
24990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24991 assert_instr(smlal)
24992)]
24993#[cfg_attr(
24994 not(target_arch = "arm"),
24995 stable(feature = "neon_intrinsics", since = "1.59.0")
24996)]
24997#[cfg_attr(
24998 target_arch = "arm",
24999 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25000)]
25001pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
25002 vmlal_s32(a, b, vdup_n_s32(c))
25003}
25004#[doc = "Vector widening multiply accumulate with scalar"]
25005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
25006#[inline]
25007#[target_feature(enable = "neon")]
25008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
25010#[cfg_attr(
25011 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25012 assert_instr(umlal)
25013)]
25014#[cfg_attr(
25015 not(target_arch = "arm"),
25016 stable(feature = "neon_intrinsics", since = "1.59.0")
25017)]
25018#[cfg_attr(
25019 target_arch = "arm",
25020 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25021)]
25022pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
25023 vmlal_u16(a, b, vdup_n_u16(c))
25024}
25025#[doc = "Vector widening multiply accumulate with scalar"]
25026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
25027#[inline]
25028#[target_feature(enable = "neon")]
25029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25030#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
25031#[cfg_attr(
25032 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25033 assert_instr(umlal)
25034)]
25035#[cfg_attr(
25036 not(target_arch = "arm"),
25037 stable(feature = "neon_intrinsics", since = "1.59.0")
25038)]
25039#[cfg_attr(
25040 target_arch = "arm",
25041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25042)]
25043pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
25044 vmlal_u32(a, b, vdup_n_u32(c))
25045}
25046#[doc = "Signed multiply-add long"]
25047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
25048#[inline]
25049#[target_feature(enable = "neon")]
25050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25051#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
25052#[cfg_attr(
25053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25054 assert_instr(smlal)
25055)]
25056#[cfg_attr(
25057 not(target_arch = "arm"),
25058 stable(feature = "neon_intrinsics", since = "1.59.0")
25059)]
25060#[cfg_attr(
25061 target_arch = "arm",
25062 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25063)]
25064pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
25065 unsafe { simd_add(a, vmull_s8(b, c)) }
25066}
25067#[doc = "Signed multiply-add long"]
25068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
25069#[inline]
25070#[target_feature(enable = "neon")]
25071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
25073#[cfg_attr(
25074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25075 assert_instr(smlal)
25076)]
25077#[cfg_attr(
25078 not(target_arch = "arm"),
25079 stable(feature = "neon_intrinsics", since = "1.59.0")
25080)]
25081#[cfg_attr(
25082 target_arch = "arm",
25083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25084)]
25085pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
25086 unsafe { simd_add(a, vmull_s16(b, c)) }
25087}
25088#[doc = "Signed multiply-add long"]
25089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
25090#[inline]
25091#[target_feature(enable = "neon")]
25092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25093#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
25094#[cfg_attr(
25095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25096 assert_instr(smlal)
25097)]
25098#[cfg_attr(
25099 not(target_arch = "arm"),
25100 stable(feature = "neon_intrinsics", since = "1.59.0")
25101)]
25102#[cfg_attr(
25103 target_arch = "arm",
25104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25105)]
25106pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
25107 unsafe { simd_add(a, vmull_s32(b, c)) }
25108}
25109#[doc = "Unsigned multiply-add long"]
25110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
25111#[inline]
25112#[target_feature(enable = "neon")]
25113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25114#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
25115#[cfg_attr(
25116 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25117 assert_instr(umlal)
25118)]
25119#[cfg_attr(
25120 not(target_arch = "arm"),
25121 stable(feature = "neon_intrinsics", since = "1.59.0")
25122)]
25123#[cfg_attr(
25124 target_arch = "arm",
25125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25126)]
25127pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
25128 unsafe { simd_add(a, vmull_u8(b, c)) }
25129}
25130#[doc = "Unsigned multiply-add long"]
25131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
25132#[inline]
25133#[target_feature(enable = "neon")]
25134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25135#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
25136#[cfg_attr(
25137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25138 assert_instr(umlal)
25139)]
25140#[cfg_attr(
25141 not(target_arch = "arm"),
25142 stable(feature = "neon_intrinsics", since = "1.59.0")
25143)]
25144#[cfg_attr(
25145 target_arch = "arm",
25146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25147)]
25148pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
25149 unsafe { simd_add(a, vmull_u16(b, c)) }
25150}
25151#[doc = "Unsigned multiply-add long"]
25152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
25153#[inline]
25154#[target_feature(enable = "neon")]
25155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
25157#[cfg_attr(
25158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25159 assert_instr(umlal)
25160)]
25161#[cfg_attr(
25162 not(target_arch = "arm"),
25163 stable(feature = "neon_intrinsics", since = "1.59.0")
25164)]
25165#[cfg_attr(
25166 target_arch = "arm",
25167 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25168)]
25169pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
25170 unsafe { simd_add(a, vmull_u32(b, c)) }
25171}
25172#[doc = "Floating-point multiply-subtract from accumulator"]
25173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
25174#[inline]
25175#[target_feature(enable = "neon")]
25176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25177#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
25178#[cfg_attr(
25179 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25180 assert_instr(fmul)
25181)]
25182#[cfg_attr(
25183 not(target_arch = "arm"),
25184 stable(feature = "neon_intrinsics", since = "1.59.0")
25185)]
25186#[cfg_attr(
25187 target_arch = "arm",
25188 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25189)]
25190pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
25191 unsafe { simd_sub(a, simd_mul(b, c)) }
25192}
25193#[doc = "Floating-point multiply-subtract from accumulator"]
25194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
25195#[inline]
25196#[target_feature(enable = "neon")]
25197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25198#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
25199#[cfg_attr(
25200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25201 assert_instr(fmul)
25202)]
25203#[cfg_attr(
25204 not(target_arch = "arm"),
25205 stable(feature = "neon_intrinsics", since = "1.59.0")
25206)]
25207#[cfg_attr(
25208 target_arch = "arm",
25209 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25210)]
25211pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
25212 unsafe { simd_sub(a, simd_mul(b, c)) }
25213}
25214#[doc = "Vector multiply subtract with scalar"]
25215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
25216#[inline]
25217#[target_feature(enable = "neon")]
25218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25219#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
25220#[cfg_attr(
25221 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25222 assert_instr(fmul, LANE = 1)
25223)]
25224#[rustc_legacy_const_generics(3)]
25225#[cfg_attr(
25226 not(target_arch = "arm"),
25227 stable(feature = "neon_intrinsics", since = "1.59.0")
25228)]
25229#[cfg_attr(
25230 target_arch = "arm",
25231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25232)]
25233pub fn vmls_lane_f32<const LANE: i32>(
25234 a: float32x2_t,
25235 b: float32x2_t,
25236 c: float32x2_t,
25237) -> float32x2_t {
25238 static_assert_uimm_bits!(LANE, 1);
25239 unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
25240}
25241#[doc = "Vector multiply subtract with scalar"]
25242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
25243#[inline]
25244#[target_feature(enable = "neon")]
25245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25246#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
25247#[cfg_attr(
25248 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25249 assert_instr(fmul, LANE = 1)
25250)]
25251#[rustc_legacy_const_generics(3)]
25252#[cfg_attr(
25253 not(target_arch = "arm"),
25254 stable(feature = "neon_intrinsics", since = "1.59.0")
25255)]
25256#[cfg_attr(
25257 target_arch = "arm",
25258 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25259)]
25260pub fn vmls_laneq_f32<const LANE: i32>(
25261 a: float32x2_t,
25262 b: float32x2_t,
25263 c: float32x4_t,
25264) -> float32x2_t {
25265 static_assert_uimm_bits!(LANE, 2);
25266 unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
25267}
25268#[doc = "Vector multiply subtract with scalar"]
25269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
25270#[inline]
25271#[target_feature(enable = "neon")]
25272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25273#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
25274#[cfg_attr(
25275 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25276 assert_instr(fmul, LANE = 1)
25277)]
25278#[rustc_legacy_const_generics(3)]
25279#[cfg_attr(
25280 not(target_arch = "arm"),
25281 stable(feature = "neon_intrinsics", since = "1.59.0")
25282)]
25283#[cfg_attr(
25284 target_arch = "arm",
25285 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25286)]
25287pub fn vmlsq_lane_f32<const LANE: i32>(
25288 a: float32x4_t,
25289 b: float32x4_t,
25290 c: float32x2_t,
25291) -> float32x4_t {
25292 static_assert_uimm_bits!(LANE, 1);
25293 unsafe {
25294 vmlsq_f32(
25295 a,
25296 b,
25297 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25298 )
25299 }
25300}
25301#[doc = "Vector multiply subtract with scalar"]
25302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
25303#[inline]
25304#[target_feature(enable = "neon")]
25305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25306#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
25307#[cfg_attr(
25308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25309 assert_instr(fmul, LANE = 1)
25310)]
25311#[rustc_legacy_const_generics(3)]
25312#[cfg_attr(
25313 not(target_arch = "arm"),
25314 stable(feature = "neon_intrinsics", since = "1.59.0")
25315)]
25316#[cfg_attr(
25317 target_arch = "arm",
25318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25319)]
25320pub fn vmlsq_laneq_f32<const LANE: i32>(
25321 a: float32x4_t,
25322 b: float32x4_t,
25323 c: float32x4_t,
25324) -> float32x4_t {
25325 static_assert_uimm_bits!(LANE, 2);
25326 unsafe {
25327 vmlsq_f32(
25328 a,
25329 b,
25330 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25331 )
25332 }
25333}
25334#[doc = "Vector multiply subtract with scalar"]
25335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
25336#[inline]
25337#[target_feature(enable = "neon")]
25338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25339#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25340#[cfg_attr(
25341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25342 assert_instr(mls, LANE = 1)
25343)]
25344#[rustc_legacy_const_generics(3)]
25345#[cfg_attr(
25346 not(target_arch = "arm"),
25347 stable(feature = "neon_intrinsics", since = "1.59.0")
25348)]
25349#[cfg_attr(
25350 target_arch = "arm",
25351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25352)]
25353pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
25354 static_assert_uimm_bits!(LANE, 2);
25355 unsafe {
25356 vmls_s16(
25357 a,
25358 b,
25359 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25360 )
25361 }
25362}
25363#[doc = "Vector multiply subtract with scalar"]
25364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
25365#[inline]
25366#[target_feature(enable = "neon")]
25367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25368#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25369#[cfg_attr(
25370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25371 assert_instr(mls, LANE = 1)
25372)]
25373#[rustc_legacy_const_generics(3)]
25374#[cfg_attr(
25375 not(target_arch = "arm"),
25376 stable(feature = "neon_intrinsics", since = "1.59.0")
25377)]
25378#[cfg_attr(
25379 target_arch = "arm",
25380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25381)]
25382pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
25383 static_assert_uimm_bits!(LANE, 2);
25384 unsafe {
25385 vmls_u16(
25386 a,
25387 b,
25388 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25389 )
25390 }
25391}
25392#[doc = "Vector multiply subtract with scalar"]
25393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
25394#[inline]
25395#[target_feature(enable = "neon")]
25396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25397#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25398#[cfg_attr(
25399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25400 assert_instr(mls, LANE = 1)
25401)]
25402#[rustc_legacy_const_generics(3)]
25403#[cfg_attr(
25404 not(target_arch = "arm"),
25405 stable(feature = "neon_intrinsics", since = "1.59.0")
25406)]
25407#[cfg_attr(
25408 target_arch = "arm",
25409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25410)]
25411pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
25412 static_assert_uimm_bits!(LANE, 3);
25413 unsafe {
25414 vmls_s16(
25415 a,
25416 b,
25417 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25418 )
25419 }
25420}
25421#[doc = "Vector multiply subtract with scalar"]
25422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
25423#[inline]
25424#[target_feature(enable = "neon")]
25425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25426#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25427#[cfg_attr(
25428 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25429 assert_instr(mls, LANE = 1)
25430)]
25431#[rustc_legacy_const_generics(3)]
25432#[cfg_attr(
25433 not(target_arch = "arm"),
25434 stable(feature = "neon_intrinsics", since = "1.59.0")
25435)]
25436#[cfg_attr(
25437 target_arch = "arm",
25438 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25439)]
25440pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
25441 static_assert_uimm_bits!(LANE, 3);
25442 unsafe {
25443 vmls_u16(
25444 a,
25445 b,
25446 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25447 )
25448 }
25449}
25450#[doc = "Vector multiply subtract with scalar"]
25451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
25452#[inline]
25453#[target_feature(enable = "neon")]
25454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25456#[cfg_attr(
25457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25458 assert_instr(mls, LANE = 1)
25459)]
25460#[rustc_legacy_const_generics(3)]
25461#[cfg_attr(
25462 not(target_arch = "arm"),
25463 stable(feature = "neon_intrinsics", since = "1.59.0")
25464)]
25465#[cfg_attr(
25466 target_arch = "arm",
25467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25468)]
25469pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
25470 static_assert_uimm_bits!(LANE, 2);
25471 unsafe {
25472 vmlsq_s16(
25473 a,
25474 b,
25475 simd_shuffle!(
25476 c,
25477 c,
25478 [
25479 LANE as u32,
25480 LANE as u32,
25481 LANE as u32,
25482 LANE as u32,
25483 LANE as u32,
25484 LANE as u32,
25485 LANE as u32,
25486 LANE as u32
25487 ]
25488 ),
25489 )
25490 }
25491}
25492#[doc = "Vector multiply subtract with scalar"]
25493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
25494#[inline]
25495#[target_feature(enable = "neon")]
25496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25497#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25498#[cfg_attr(
25499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25500 assert_instr(mls, LANE = 1)
25501)]
25502#[rustc_legacy_const_generics(3)]
25503#[cfg_attr(
25504 not(target_arch = "arm"),
25505 stable(feature = "neon_intrinsics", since = "1.59.0")
25506)]
25507#[cfg_attr(
25508 target_arch = "arm",
25509 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25510)]
25511pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
25512 static_assert_uimm_bits!(LANE, 2);
25513 unsafe {
25514 vmlsq_u16(
25515 a,
25516 b,
25517 simd_shuffle!(
25518 c,
25519 c,
25520 [
25521 LANE as u32,
25522 LANE as u32,
25523 LANE as u32,
25524 LANE as u32,
25525 LANE as u32,
25526 LANE as u32,
25527 LANE as u32,
25528 LANE as u32
25529 ]
25530 ),
25531 )
25532 }
25533}
25534#[doc = "Vector multiply subtract with scalar"]
25535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
25536#[inline]
25537#[target_feature(enable = "neon")]
25538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25540#[cfg_attr(
25541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25542 assert_instr(mls, LANE = 1)
25543)]
25544#[rustc_legacy_const_generics(3)]
25545#[cfg_attr(
25546 not(target_arch = "arm"),
25547 stable(feature = "neon_intrinsics", since = "1.59.0")
25548)]
25549#[cfg_attr(
25550 target_arch = "arm",
25551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25552)]
25553pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
25554 static_assert_uimm_bits!(LANE, 3);
25555 unsafe {
25556 vmlsq_s16(
25557 a,
25558 b,
25559 simd_shuffle!(
25560 c,
25561 c,
25562 [
25563 LANE as u32,
25564 LANE as u32,
25565 LANE as u32,
25566 LANE as u32,
25567 LANE as u32,
25568 LANE as u32,
25569 LANE as u32,
25570 LANE as u32
25571 ]
25572 ),
25573 )
25574 }
25575}
25576#[doc = "Vector multiply subtract with scalar"]
25577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
25578#[inline]
25579#[target_feature(enable = "neon")]
25580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25581#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
25582#[cfg_attr(
25583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25584 assert_instr(mls, LANE = 1)
25585)]
25586#[rustc_legacy_const_generics(3)]
25587#[cfg_attr(
25588 not(target_arch = "arm"),
25589 stable(feature = "neon_intrinsics", since = "1.59.0")
25590)]
25591#[cfg_attr(
25592 target_arch = "arm",
25593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25594)]
25595pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
25596 static_assert_uimm_bits!(LANE, 3);
25597 unsafe {
25598 vmlsq_u16(
25599 a,
25600 b,
25601 simd_shuffle!(
25602 c,
25603 c,
25604 [
25605 LANE as u32,
25606 LANE as u32,
25607 LANE as u32,
25608 LANE as u32,
25609 LANE as u32,
25610 LANE as u32,
25611 LANE as u32,
25612 LANE as u32
25613 ]
25614 ),
25615 )
25616 }
25617}
25618#[doc = "Vector multiply subtract with scalar"]
25619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
25620#[inline]
25621#[target_feature(enable = "neon")]
25622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25623#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25624#[cfg_attr(
25625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25626 assert_instr(mls, LANE = 1)
25627)]
25628#[rustc_legacy_const_generics(3)]
25629#[cfg_attr(
25630 not(target_arch = "arm"),
25631 stable(feature = "neon_intrinsics", since = "1.59.0")
25632)]
25633#[cfg_attr(
25634 target_arch = "arm",
25635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25636)]
25637pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
25638 static_assert_uimm_bits!(LANE, 1);
25639 unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
25640}
25641#[doc = "Vector multiply subtract with scalar"]
25642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
25643#[inline]
25644#[target_feature(enable = "neon")]
25645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25646#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25647#[cfg_attr(
25648 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25649 assert_instr(mls, LANE = 1)
25650)]
25651#[rustc_legacy_const_generics(3)]
25652#[cfg_attr(
25653 not(target_arch = "arm"),
25654 stable(feature = "neon_intrinsics", since = "1.59.0")
25655)]
25656#[cfg_attr(
25657 target_arch = "arm",
25658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25659)]
25660pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
25661 static_assert_uimm_bits!(LANE, 1);
25662 unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
25663}
25664#[doc = "Vector multiply subtract with scalar"]
25665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
25666#[inline]
25667#[target_feature(enable = "neon")]
25668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25670#[cfg_attr(
25671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25672 assert_instr(mls, LANE = 1)
25673)]
25674#[rustc_legacy_const_generics(3)]
25675#[cfg_attr(
25676 not(target_arch = "arm"),
25677 stable(feature = "neon_intrinsics", since = "1.59.0")
25678)]
25679#[cfg_attr(
25680 target_arch = "arm",
25681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25682)]
25683pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
25684 static_assert_uimm_bits!(LANE, 2);
25685 unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
25686}
25687#[doc = "Vector multiply subtract with scalar"]
25688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
25689#[inline]
25690#[target_feature(enable = "neon")]
25691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25692#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25693#[cfg_attr(
25694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25695 assert_instr(mls, LANE = 1)
25696)]
25697#[rustc_legacy_const_generics(3)]
25698#[cfg_attr(
25699 not(target_arch = "arm"),
25700 stable(feature = "neon_intrinsics", since = "1.59.0")
25701)]
25702#[cfg_attr(
25703 target_arch = "arm",
25704 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25705)]
25706pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
25707 static_assert_uimm_bits!(LANE, 2);
25708 unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
25709}
25710#[doc = "Vector multiply subtract with scalar"]
25711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
25712#[inline]
25713#[target_feature(enable = "neon")]
25714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25715#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25716#[cfg_attr(
25717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25718 assert_instr(mls, LANE = 1)
25719)]
25720#[rustc_legacy_const_generics(3)]
25721#[cfg_attr(
25722 not(target_arch = "arm"),
25723 stable(feature = "neon_intrinsics", since = "1.59.0")
25724)]
25725#[cfg_attr(
25726 target_arch = "arm",
25727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25728)]
25729pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
25730 static_assert_uimm_bits!(LANE, 1);
25731 unsafe {
25732 vmlsq_s32(
25733 a,
25734 b,
25735 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25736 )
25737 }
25738}
25739#[doc = "Vector multiply subtract with scalar"]
25740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
25741#[inline]
25742#[target_feature(enable = "neon")]
25743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25745#[cfg_attr(
25746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25747 assert_instr(mls, LANE = 1)
25748)]
25749#[rustc_legacy_const_generics(3)]
25750#[cfg_attr(
25751 not(target_arch = "arm"),
25752 stable(feature = "neon_intrinsics", since = "1.59.0")
25753)]
25754#[cfg_attr(
25755 target_arch = "arm",
25756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25757)]
25758pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
25759 static_assert_uimm_bits!(LANE, 1);
25760 unsafe {
25761 vmlsq_u32(
25762 a,
25763 b,
25764 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25765 )
25766 }
25767}
25768#[doc = "Vector multiply subtract with scalar"]
25769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
25770#[inline]
25771#[target_feature(enable = "neon")]
25772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25773#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25774#[cfg_attr(
25775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25776 assert_instr(mls, LANE = 1)
25777)]
25778#[rustc_legacy_const_generics(3)]
25779#[cfg_attr(
25780 not(target_arch = "arm"),
25781 stable(feature = "neon_intrinsics", since = "1.59.0")
25782)]
25783#[cfg_attr(
25784 target_arch = "arm",
25785 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25786)]
25787pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
25788 static_assert_uimm_bits!(LANE, 2);
25789 unsafe {
25790 vmlsq_s32(
25791 a,
25792 b,
25793 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25794 )
25795 }
25796}
25797#[doc = "Vector multiply subtract with scalar"]
25798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
25799#[inline]
25800#[target_feature(enable = "neon")]
25801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
25803#[cfg_attr(
25804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25805 assert_instr(mls, LANE = 1)
25806)]
25807#[rustc_legacy_const_generics(3)]
25808#[cfg_attr(
25809 not(target_arch = "arm"),
25810 stable(feature = "neon_intrinsics", since = "1.59.0")
25811)]
25812#[cfg_attr(
25813 target_arch = "arm",
25814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25815)]
25816pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
25817 static_assert_uimm_bits!(LANE, 2);
25818 unsafe {
25819 vmlsq_u32(
25820 a,
25821 b,
25822 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
25823 )
25824 }
25825}
25826#[doc = "Vector multiply subtract with scalar"]
25827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
25828#[inline]
25829#[target_feature(enable = "neon")]
25830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25831#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
25832#[cfg_attr(
25833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25834 assert_instr(fmul)
25835)]
25836#[cfg_attr(
25837 not(target_arch = "arm"),
25838 stable(feature = "neon_intrinsics", since = "1.59.0")
25839)]
25840#[cfg_attr(
25841 target_arch = "arm",
25842 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25843)]
25844pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
25845 vmls_f32(a, b, vdup_n_f32(c))
25846}
25847#[doc = "Vector multiply subtract with scalar"]
25848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
25849#[inline]
25850#[target_feature(enable = "neon")]
25851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
25853#[cfg_attr(
25854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25855 assert_instr(fmul)
25856)]
25857#[cfg_attr(
25858 not(target_arch = "arm"),
25859 stable(feature = "neon_intrinsics", since = "1.59.0")
25860)]
25861#[cfg_attr(
25862 target_arch = "arm",
25863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25864)]
25865pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
25866 vmlsq_f32(a, b, vdupq_n_f32(c))
25867}
25868#[doc = "Vector multiply subtract with scalar"]
25869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
25870#[inline]
25871#[target_feature(enable = "neon")]
25872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25873#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
25874#[cfg_attr(
25875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25876 assert_instr(mls)
25877)]
25878#[cfg_attr(
25879 not(target_arch = "arm"),
25880 stable(feature = "neon_intrinsics", since = "1.59.0")
25881)]
25882#[cfg_attr(
25883 target_arch = "arm",
25884 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25885)]
25886pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
25887 vmls_s16(a, b, vdup_n_s16(c))
25888}
25889#[doc = "Vector multiply subtract with scalar"]
25890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
25891#[inline]
25892#[target_feature(enable = "neon")]
25893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
25895#[cfg_attr(
25896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25897 assert_instr(mls)
25898)]
25899#[cfg_attr(
25900 not(target_arch = "arm"),
25901 stable(feature = "neon_intrinsics", since = "1.59.0")
25902)]
25903#[cfg_attr(
25904 target_arch = "arm",
25905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25906)]
25907pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
25908 vmlsq_s16(a, b, vdupq_n_s16(c))
25909}
25910#[doc = "Vector multiply subtract with scalar"]
25911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
25912#[inline]
25913#[target_feature(enable = "neon")]
25914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25915#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
25916#[cfg_attr(
25917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25918 assert_instr(mls)
25919)]
25920#[cfg_attr(
25921 not(target_arch = "arm"),
25922 stable(feature = "neon_intrinsics", since = "1.59.0")
25923)]
25924#[cfg_attr(
25925 target_arch = "arm",
25926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25927)]
25928pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
25929 vmls_u16(a, b, vdup_n_u16(c))
25930}
25931#[doc = "Vector multiply subtract with scalar"]
25932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
25933#[inline]
25934#[target_feature(enable = "neon")]
25935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
25937#[cfg_attr(
25938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25939 assert_instr(mls)
25940)]
25941#[cfg_attr(
25942 not(target_arch = "arm"),
25943 stable(feature = "neon_intrinsics", since = "1.59.0")
25944)]
25945#[cfg_attr(
25946 target_arch = "arm",
25947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25948)]
25949pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
25950 vmlsq_u16(a, b, vdupq_n_u16(c))
25951}
25952#[doc = "Vector multiply subtract with scalar"]
25953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
25954#[inline]
25955#[target_feature(enable = "neon")]
25956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25957#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
25958#[cfg_attr(
25959 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25960 assert_instr(mls)
25961)]
25962#[cfg_attr(
25963 not(target_arch = "arm"),
25964 stable(feature = "neon_intrinsics", since = "1.59.0")
25965)]
25966#[cfg_attr(
25967 target_arch = "arm",
25968 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25969)]
25970pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
25971 vmls_s32(a, b, vdup_n_s32(c))
25972}
25973#[doc = "Vector multiply subtract with scalar"]
25974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
25975#[inline]
25976#[target_feature(enable = "neon")]
25977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25978#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
25979#[cfg_attr(
25980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25981 assert_instr(mls)
25982)]
25983#[cfg_attr(
25984 not(target_arch = "arm"),
25985 stable(feature = "neon_intrinsics", since = "1.59.0")
25986)]
25987#[cfg_attr(
25988 target_arch = "arm",
25989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25990)]
25991pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
25992 vmlsq_s32(a, b, vdupq_n_s32(c))
25993}
25994#[doc = "Vector multiply subtract with scalar"]
25995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
25996#[inline]
25997#[target_feature(enable = "neon")]
25998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25999#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
26000#[cfg_attr(
26001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26002 assert_instr(mls)
26003)]
26004#[cfg_attr(
26005 not(target_arch = "arm"),
26006 stable(feature = "neon_intrinsics", since = "1.59.0")
26007)]
26008#[cfg_attr(
26009 target_arch = "arm",
26010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26011)]
26012pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
26013 vmls_u32(a, b, vdup_n_u32(c))
26014}
26015#[doc = "Vector multiply subtract with scalar"]
26016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
26017#[inline]
26018#[target_feature(enable = "neon")]
26019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26020#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
26021#[cfg_attr(
26022 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26023 assert_instr(mls)
26024)]
26025#[cfg_attr(
26026 not(target_arch = "arm"),
26027 stable(feature = "neon_intrinsics", since = "1.59.0")
26028)]
26029#[cfg_attr(
26030 target_arch = "arm",
26031 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26032)]
26033pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
26034 vmlsq_u32(a, b, vdupq_n_u32(c))
26035}
26036#[doc = "Multiply-subtract from accumulator"]
26037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
26038#[inline]
26039#[target_feature(enable = "neon")]
26040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26041#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
26042#[cfg_attr(
26043 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26044 assert_instr(mls)
26045)]
26046#[cfg_attr(
26047 not(target_arch = "arm"),
26048 stable(feature = "neon_intrinsics", since = "1.59.0")
26049)]
26050#[cfg_attr(
26051 target_arch = "arm",
26052 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26053)]
26054pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
26055 unsafe { simd_sub(a, simd_mul(b, c)) }
26056}
26057#[doc = "Multiply-subtract from accumulator"]
26058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
26059#[inline]
26060#[target_feature(enable = "neon")]
26061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
26063#[cfg_attr(
26064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26065 assert_instr(mls)
26066)]
26067#[cfg_attr(
26068 not(target_arch = "arm"),
26069 stable(feature = "neon_intrinsics", since = "1.59.0")
26070)]
26071#[cfg_attr(
26072 target_arch = "arm",
26073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26074)]
26075pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
26076 unsafe { simd_sub(a, simd_mul(b, c)) }
26077}
26078#[doc = "Multiply-subtract from accumulator"]
26079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
26080#[inline]
26081#[target_feature(enable = "neon")]
26082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26083#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
26084#[cfg_attr(
26085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26086 assert_instr(mls)
26087)]
26088#[cfg_attr(
26089 not(target_arch = "arm"),
26090 stable(feature = "neon_intrinsics", since = "1.59.0")
26091)]
26092#[cfg_attr(
26093 target_arch = "arm",
26094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26095)]
26096pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
26097 unsafe { simd_sub(a, simd_mul(b, c)) }
26098}
26099#[doc = "Multiply-subtract from accumulator"]
26100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
26101#[inline]
26102#[target_feature(enable = "neon")]
26103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26104#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
26105#[cfg_attr(
26106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26107 assert_instr(mls)
26108)]
26109#[cfg_attr(
26110 not(target_arch = "arm"),
26111 stable(feature = "neon_intrinsics", since = "1.59.0")
26112)]
26113#[cfg_attr(
26114 target_arch = "arm",
26115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26116)]
26117pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
26118 unsafe { simd_sub(a, simd_mul(b, c)) }
26119}
26120#[doc = "Multiply-subtract from accumulator"]
26121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
26122#[inline]
26123#[target_feature(enable = "neon")]
26124#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26125#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
26126#[cfg_attr(
26127 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26128 assert_instr(mls)
26129)]
26130#[cfg_attr(
26131 not(target_arch = "arm"),
26132 stable(feature = "neon_intrinsics", since = "1.59.0")
26133)]
26134#[cfg_attr(
26135 target_arch = "arm",
26136 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26137)]
26138pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
26139 unsafe { simd_sub(a, simd_mul(b, c)) }
26140}
26141#[doc = "Multiply-subtract from accumulator"]
26142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
26143#[inline]
26144#[target_feature(enable = "neon")]
26145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26146#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
26147#[cfg_attr(
26148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26149 assert_instr(mls)
26150)]
26151#[cfg_attr(
26152 not(target_arch = "arm"),
26153 stable(feature = "neon_intrinsics", since = "1.59.0")
26154)]
26155#[cfg_attr(
26156 target_arch = "arm",
26157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26158)]
26159pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
26160 unsafe { simd_sub(a, simd_mul(b, c)) }
26161}
26162#[doc = "Multiply-subtract from accumulator"]
26163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
26164#[inline]
26165#[target_feature(enable = "neon")]
26166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26167#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
26168#[cfg_attr(
26169 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26170 assert_instr(mls)
26171)]
26172#[cfg_attr(
26173 not(target_arch = "arm"),
26174 stable(feature = "neon_intrinsics", since = "1.59.0")
26175)]
26176#[cfg_attr(
26177 target_arch = "arm",
26178 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26179)]
26180pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
26181 unsafe { simd_sub(a, simd_mul(b, c)) }
26182}
26183#[doc = "Multiply-subtract from accumulator"]
26184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
26185#[inline]
26186#[target_feature(enable = "neon")]
26187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26188#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
26189#[cfg_attr(
26190 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26191 assert_instr(mls)
26192)]
26193#[cfg_attr(
26194 not(target_arch = "arm"),
26195 stable(feature = "neon_intrinsics", since = "1.59.0")
26196)]
26197#[cfg_attr(
26198 target_arch = "arm",
26199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26200)]
26201pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
26202 unsafe { simd_sub(a, simd_mul(b, c)) }
26203}
26204#[doc = "Multiply-subtract from accumulator"]
26205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
26206#[inline]
26207#[target_feature(enable = "neon")]
26208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
26210#[cfg_attr(
26211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26212 assert_instr(mls)
26213)]
26214#[cfg_attr(
26215 not(target_arch = "arm"),
26216 stable(feature = "neon_intrinsics", since = "1.59.0")
26217)]
26218#[cfg_attr(
26219 target_arch = "arm",
26220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26221)]
26222pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
26223 unsafe { simd_sub(a, simd_mul(b, c)) }
26224}
26225#[doc = "Multiply-subtract from accumulator"]
26226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
26227#[inline]
26228#[target_feature(enable = "neon")]
26229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26230#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
26231#[cfg_attr(
26232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26233 assert_instr(mls)
26234)]
26235#[cfg_attr(
26236 not(target_arch = "arm"),
26237 stable(feature = "neon_intrinsics", since = "1.59.0")
26238)]
26239#[cfg_attr(
26240 target_arch = "arm",
26241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26242)]
26243pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
26244 unsafe { simd_sub(a, simd_mul(b, c)) }
26245}
26246#[doc = "Multiply-subtract from accumulator"]
26247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
26248#[inline]
26249#[target_feature(enable = "neon")]
26250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26251#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
26252#[cfg_attr(
26253 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26254 assert_instr(mls)
26255)]
26256#[cfg_attr(
26257 not(target_arch = "arm"),
26258 stable(feature = "neon_intrinsics", since = "1.59.0")
26259)]
26260#[cfg_attr(
26261 target_arch = "arm",
26262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26263)]
26264pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
26265 unsafe { simd_sub(a, simd_mul(b, c)) }
26266}
26267#[doc = "Multiply-subtract from accumulator"]
26268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
26269#[inline]
26270#[target_feature(enable = "neon")]
26271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26272#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
26273#[cfg_attr(
26274 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26275 assert_instr(mls)
26276)]
26277#[cfg_attr(
26278 not(target_arch = "arm"),
26279 stable(feature = "neon_intrinsics", since = "1.59.0")
26280)]
26281#[cfg_attr(
26282 target_arch = "arm",
26283 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26284)]
26285pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
26286 unsafe { simd_sub(a, simd_mul(b, c)) }
26287}
26288#[doc = "Vector widening multiply subtract with scalar"]
26289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
26290#[inline]
26291#[target_feature(enable = "neon")]
26292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26293#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
26294#[cfg_attr(
26295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26296 assert_instr(smlsl, LANE = 1)
26297)]
26298#[rustc_legacy_const_generics(3)]
26299#[cfg_attr(
26300 not(target_arch = "arm"),
26301 stable(feature = "neon_intrinsics", since = "1.59.0")
26302)]
26303#[cfg_attr(
26304 target_arch = "arm",
26305 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26306)]
26307pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
26308 static_assert_uimm_bits!(LANE, 2);
26309 unsafe {
26310 vmlsl_s16(
26311 a,
26312 b,
26313 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
26314 )
26315 }
26316}
26317#[doc = "Vector widening multiply subtract with scalar"]
26318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
26319#[inline]
26320#[target_feature(enable = "neon")]
26321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26322#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
26323#[cfg_attr(
26324 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26325 assert_instr(smlsl, LANE = 1)
26326)]
26327#[rustc_legacy_const_generics(3)]
26328#[cfg_attr(
26329 not(target_arch = "arm"),
26330 stable(feature = "neon_intrinsics", since = "1.59.0")
26331)]
26332#[cfg_attr(
26333 target_arch = "arm",
26334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26335)]
26336pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
26337 static_assert_uimm_bits!(LANE, 3);
26338 unsafe {
26339 vmlsl_s16(
26340 a,
26341 b,
26342 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
26343 )
26344 }
26345}
26346#[doc = "Vector widening multiply subtract with scalar"]
26347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
26348#[inline]
26349#[target_feature(enable = "neon")]
26350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26351#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
26352#[cfg_attr(
26353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26354 assert_instr(smlsl, LANE = 1)
26355)]
26356#[rustc_legacy_const_generics(3)]
26357#[cfg_attr(
26358 not(target_arch = "arm"),
26359 stable(feature = "neon_intrinsics", since = "1.59.0")
26360)]
26361#[cfg_attr(
26362 target_arch = "arm",
26363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26364)]
26365pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
26366 static_assert_uimm_bits!(LANE, 1);
26367 unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
26368}
26369#[doc = "Vector widening multiply subtract with scalar"]
26370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
26371#[inline]
26372#[target_feature(enable = "neon")]
26373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26374#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
26375#[cfg_attr(
26376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26377 assert_instr(smlsl, LANE = 1)
26378)]
26379#[rustc_legacy_const_generics(3)]
26380#[cfg_attr(
26381 not(target_arch = "arm"),
26382 stable(feature = "neon_intrinsics", since = "1.59.0")
26383)]
26384#[cfg_attr(
26385 target_arch = "arm",
26386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26387)]
26388pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
26389 static_assert_uimm_bits!(LANE, 2);
26390 unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
26391}
26392#[doc = "Vector widening multiply subtract with scalar"]
26393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
26394#[inline]
26395#[target_feature(enable = "neon")]
26396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26397#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
26398#[cfg_attr(
26399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26400 assert_instr(umlsl, LANE = 1)
26401)]
26402#[rustc_legacy_const_generics(3)]
26403#[cfg_attr(
26404 not(target_arch = "arm"),
26405 stable(feature = "neon_intrinsics", since = "1.59.0")
26406)]
26407#[cfg_attr(
26408 target_arch = "arm",
26409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26410)]
26411pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
26412 static_assert_uimm_bits!(LANE, 2);
26413 unsafe {
26414 vmlsl_u16(
26415 a,
26416 b,
26417 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
26418 )
26419 }
26420}
26421#[doc = "Vector widening multiply subtract with scalar"]
26422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
26423#[inline]
26424#[target_feature(enable = "neon")]
26425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26426#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
26427#[cfg_attr(
26428 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26429 assert_instr(umlsl, LANE = 1)
26430)]
26431#[rustc_legacy_const_generics(3)]
26432#[cfg_attr(
26433 not(target_arch = "arm"),
26434 stable(feature = "neon_intrinsics", since = "1.59.0")
26435)]
26436#[cfg_attr(
26437 target_arch = "arm",
26438 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26439)]
26440pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
26441 static_assert_uimm_bits!(LANE, 3);
26442 unsafe {
26443 vmlsl_u16(
26444 a,
26445 b,
26446 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
26447 )
26448 }
26449}
26450#[doc = "Vector widening multiply subtract with scalar"]
26451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
26452#[inline]
26453#[target_feature(enable = "neon")]
26454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
26456#[cfg_attr(
26457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26458 assert_instr(umlsl, LANE = 1)
26459)]
26460#[rustc_legacy_const_generics(3)]
26461#[cfg_attr(
26462 not(target_arch = "arm"),
26463 stable(feature = "neon_intrinsics", since = "1.59.0")
26464)]
26465#[cfg_attr(
26466 target_arch = "arm",
26467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26468)]
26469pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
26470 static_assert_uimm_bits!(LANE, 1);
26471 unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
26472}
26473#[doc = "Vector widening multiply subtract with scalar"]
26474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
26475#[inline]
26476#[target_feature(enable = "neon")]
26477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26478#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
26479#[cfg_attr(
26480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26481 assert_instr(umlsl, LANE = 1)
26482)]
26483#[rustc_legacy_const_generics(3)]
26484#[cfg_attr(
26485 not(target_arch = "arm"),
26486 stable(feature = "neon_intrinsics", since = "1.59.0")
26487)]
26488#[cfg_attr(
26489 target_arch = "arm",
26490 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26491)]
26492pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
26493 static_assert_uimm_bits!(LANE, 2);
26494 unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
26495}
26496#[doc = "Vector widening multiply subtract with scalar"]
26497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
26498#[inline]
26499#[target_feature(enable = "neon")]
26500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26501#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
26502#[cfg_attr(
26503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26504 assert_instr(smlsl)
26505)]
26506#[cfg_attr(
26507 not(target_arch = "arm"),
26508 stable(feature = "neon_intrinsics", since = "1.59.0")
26509)]
26510#[cfg_attr(
26511 target_arch = "arm",
26512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26513)]
26514pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
26515 vmlsl_s16(a, b, vdup_n_s16(c))
26516}
26517#[doc = "Vector widening multiply subtract with scalar"]
26518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
26519#[inline]
26520#[target_feature(enable = "neon")]
26521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26522#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
26523#[cfg_attr(
26524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26525 assert_instr(smlsl)
26526)]
26527#[cfg_attr(
26528 not(target_arch = "arm"),
26529 stable(feature = "neon_intrinsics", since = "1.59.0")
26530)]
26531#[cfg_attr(
26532 target_arch = "arm",
26533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26534)]
26535pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
26536 vmlsl_s32(a, b, vdup_n_s32(c))
26537}
26538#[doc = "Vector widening multiply subtract with scalar"]
26539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
26540#[inline]
26541#[target_feature(enable = "neon")]
26542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
26544#[cfg_attr(
26545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26546 assert_instr(umlsl)
26547)]
26548#[cfg_attr(
26549 not(target_arch = "arm"),
26550 stable(feature = "neon_intrinsics", since = "1.59.0")
26551)]
26552#[cfg_attr(
26553 target_arch = "arm",
26554 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26555)]
26556pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
26557 vmlsl_u16(a, b, vdup_n_u16(c))
26558}
26559#[doc = "Vector widening multiply subtract with scalar"]
26560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
26561#[inline]
26562#[target_feature(enable = "neon")]
26563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26564#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
26565#[cfg_attr(
26566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26567 assert_instr(umlsl)
26568)]
26569#[cfg_attr(
26570 not(target_arch = "arm"),
26571 stable(feature = "neon_intrinsics", since = "1.59.0")
26572)]
26573#[cfg_attr(
26574 target_arch = "arm",
26575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26576)]
26577pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
26578 vmlsl_u32(a, b, vdup_n_u32(c))
26579}
26580#[doc = "Signed multiply-subtract long"]
26581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
26582#[inline]
26583#[target_feature(enable = "neon")]
26584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26585#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
26586#[cfg_attr(
26587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26588 assert_instr(smlsl)
26589)]
26590#[cfg_attr(
26591 not(target_arch = "arm"),
26592 stable(feature = "neon_intrinsics", since = "1.59.0")
26593)]
26594#[cfg_attr(
26595 target_arch = "arm",
26596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26597)]
26598pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
26599 unsafe { simd_sub(a, vmull_s8(b, c)) }
26600}
26601#[doc = "Signed multiply-subtract long"]
26602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
26603#[inline]
26604#[target_feature(enable = "neon")]
26605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26606#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
26607#[cfg_attr(
26608 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26609 assert_instr(smlsl)
26610)]
26611#[cfg_attr(
26612 not(target_arch = "arm"),
26613 stable(feature = "neon_intrinsics", since = "1.59.0")
26614)]
26615#[cfg_attr(
26616 target_arch = "arm",
26617 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26618)]
26619pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
26620 unsafe { simd_sub(a, vmull_s16(b, c)) }
26621}
26622#[doc = "Signed multiply-subtract long"]
26623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
26624#[inline]
26625#[target_feature(enable = "neon")]
26626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
26628#[cfg_attr(
26629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26630 assert_instr(smlsl)
26631)]
26632#[cfg_attr(
26633 not(target_arch = "arm"),
26634 stable(feature = "neon_intrinsics", since = "1.59.0")
26635)]
26636#[cfg_attr(
26637 target_arch = "arm",
26638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26639)]
26640pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
26641 unsafe { simd_sub(a, vmull_s32(b, c)) }
26642}
26643#[doc = "Unsigned multiply-subtract long"]
26644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
26645#[inline]
26646#[target_feature(enable = "neon")]
26647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26648#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
26649#[cfg_attr(
26650 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26651 assert_instr(umlsl)
26652)]
26653#[cfg_attr(
26654 not(target_arch = "arm"),
26655 stable(feature = "neon_intrinsics", since = "1.59.0")
26656)]
26657#[cfg_attr(
26658 target_arch = "arm",
26659 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26660)]
26661pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
26662 unsafe { simd_sub(a, vmull_u8(b, c)) }
26663}
26664#[doc = "Unsigned multiply-subtract long"]
26665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
26666#[inline]
26667#[target_feature(enable = "neon")]
26668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
26670#[cfg_attr(
26671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26672 assert_instr(umlsl)
26673)]
26674#[cfg_attr(
26675 not(target_arch = "arm"),
26676 stable(feature = "neon_intrinsics", since = "1.59.0")
26677)]
26678#[cfg_attr(
26679 target_arch = "arm",
26680 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26681)]
26682pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
26683 unsafe { simd_sub(a, vmull_u16(b, c)) }
26684}
26685#[doc = "Unsigned multiply-subtract long"]
26686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
26687#[inline]
26688#[target_feature(enable = "neon")]
26689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26690#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
26691#[cfg_attr(
26692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26693 assert_instr(umlsl)
26694)]
26695#[cfg_attr(
26696 not(target_arch = "arm"),
26697 stable(feature = "neon_intrinsics", since = "1.59.0")
26698)]
26699#[cfg_attr(
26700 target_arch = "arm",
26701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26702)]
26703pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
26704 unsafe { simd_sub(a, vmull_u32(b, c)) }
26705}
26706#[doc = "8-bit integer matrix multiply-accumulate"]
26707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
26708#[inline]
26709#[target_feature(enable = "neon,i8mm")]
26710#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26712#[cfg_attr(
26713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26714 assert_instr(smmla)
26715)]
26716#[cfg_attr(
26717 not(target_arch = "arm"),
26718 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
26719)]
26720#[cfg_attr(
26721 target_arch = "arm",
26722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26723)]
26724pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
26725 unsafe extern "unadjusted" {
26726 #[cfg_attr(
26727 any(target_arch = "aarch64", target_arch = "arm64ec"),
26728 link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8"
26729 )]
26730 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")]
26731 fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
26732 }
26733 unsafe { _vmmlaq_s32(a, b, c) }
26734}
26735#[doc = "8-bit integer matrix multiply-accumulate"]
26736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
26737#[inline]
26738#[target_feature(enable = "neon,i8mm")]
26739#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26741#[cfg_attr(
26742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26743 assert_instr(ummla)
26744)]
26745#[cfg_attr(
26746 not(target_arch = "arm"),
26747 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
26748)]
26749#[cfg_attr(
26750 target_arch = "arm",
26751 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26752)]
26753pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
26754 unsafe extern "unadjusted" {
26755 #[cfg_attr(
26756 any(target_arch = "aarch64", target_arch = "arm64ec"),
26757 link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8"
26758 )]
26759 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")]
26760 fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
26761 }
26762 unsafe { _vmmlaq_u32(a, b, c) }
26763}
26764#[doc = "Duplicate element to vector"]
26765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
26766#[inline]
26767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26768#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
26769#[cfg_attr(
26770 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26771 assert_instr(dup)
26772)]
26773#[target_feature(enable = "neon,fp16")]
26774#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26775pub fn vmov_n_f16(a: f16) -> float16x4_t {
26776 vdup_n_f16(a)
26777}
26778#[doc = "Duplicate element to vector"]
26779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
26780#[inline]
26781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26782#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
26783#[cfg_attr(
26784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26785 assert_instr(dup)
26786)]
26787#[target_feature(enable = "neon,fp16")]
26788#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26789pub fn vmovq_n_f16(a: f16) -> float16x8_t {
26790 vdupq_n_f16(a)
26791}
26792#[doc = "Multiply"]
26793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
26794#[inline]
26795#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26796#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
26797#[cfg_attr(
26798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26799 assert_instr(fmul)
26800)]
26801#[target_feature(enable = "neon,fp16")]
26802#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26803pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
26804 unsafe { simd_mul(a, b) }
26805}
26806#[doc = "Multiply"]
26807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
26808#[inline]
26809#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26810#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
26811#[cfg_attr(
26812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26813 assert_instr(fmul)
26814)]
26815#[target_feature(enable = "neon,fp16")]
26816#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26817pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
26818 unsafe { simd_mul(a, b) }
26819}
26820#[doc = "Multiply"]
26821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
26822#[inline]
26823#[target_feature(enable = "neon")]
26824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26825#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
26826#[cfg_attr(
26827 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26828 assert_instr(fmul)
26829)]
26830#[cfg_attr(
26831 not(target_arch = "arm"),
26832 stable(feature = "neon_intrinsics", since = "1.59.0")
26833)]
26834#[cfg_attr(
26835 target_arch = "arm",
26836 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26837)]
26838pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
26839 unsafe { simd_mul(a, b) }
26840}
26841#[doc = "Multiply"]
26842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
26843#[inline]
26844#[target_feature(enable = "neon")]
26845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
26847#[cfg_attr(
26848 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26849 assert_instr(fmul)
26850)]
26851#[cfg_attr(
26852 not(target_arch = "arm"),
26853 stable(feature = "neon_intrinsics", since = "1.59.0")
26854)]
26855#[cfg_attr(
26856 target_arch = "arm",
26857 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26858)]
26859pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
26860 unsafe { simd_mul(a, b) }
26861}
26862#[doc = "Multiply"]
26863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
26864#[inline]
26865#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
26867#[cfg_attr(
26868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26869 assert_instr(fmul, LANE = 1)
26870)]
26871#[rustc_legacy_const_generics(2)]
26872#[target_feature(enable = "neon,fp16")]
26873#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26874pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
26875 static_assert_uimm_bits!(LANE, 2);
26876 unsafe {
26877 simd_mul(
26878 a,
26879 simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
26880 )
26881 }
26882}
26883#[doc = "Multiply"]
26884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
26885#[inline]
26886#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
26888#[cfg_attr(
26889 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26890 assert_instr(fmul, LANE = 1)
26891)]
26892#[rustc_legacy_const_generics(2)]
26893#[target_feature(enable = "neon,fp16")]
26894#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26895pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
26896 static_assert_uimm_bits!(LANE, 2);
26897 unsafe {
26898 simd_mul(
26899 a,
26900 simd_shuffle!(
26901 v,
26902 v,
26903 [
26904 LANE as u32,
26905 LANE as u32,
26906 LANE as u32,
26907 LANE as u32,
26908 LANE as u32,
26909 LANE as u32,
26910 LANE as u32,
26911 LANE as u32
26912 ]
26913 ),
26914 )
26915 }
26916}
26917#[doc = "Floating-point multiply"]
26918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
26919#[inline]
26920#[target_feature(enable = "neon")]
26921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
26923#[cfg_attr(
26924 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26925 assert_instr(fmul, LANE = 0)
26926)]
26927#[rustc_legacy_const_generics(2)]
26928#[cfg_attr(
26929 not(target_arch = "arm"),
26930 stable(feature = "neon_intrinsics", since = "1.59.0")
26931)]
26932#[cfg_attr(
26933 target_arch = "arm",
26934 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26935)]
26936pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
26937 static_assert_uimm_bits!(LANE, 1);
26938 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
26939}
26940#[doc = "Floating-point multiply"]
26941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
26942#[inline]
26943#[target_feature(enable = "neon")]
26944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
26946#[cfg_attr(
26947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26948 assert_instr(fmul, LANE = 0)
26949)]
26950#[rustc_legacy_const_generics(2)]
26951#[cfg_attr(
26952 not(target_arch = "arm"),
26953 stable(feature = "neon_intrinsics", since = "1.59.0")
26954)]
26955#[cfg_attr(
26956 target_arch = "arm",
26957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26958)]
26959pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
26960 static_assert_uimm_bits!(LANE, 2);
26961 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
26962}
26963#[doc = "Floating-point multiply"]
26964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
26965#[inline]
26966#[target_feature(enable = "neon")]
26967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
26969#[cfg_attr(
26970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26971 assert_instr(fmul, LANE = 0)
26972)]
26973#[rustc_legacy_const_generics(2)]
26974#[cfg_attr(
26975 not(target_arch = "arm"),
26976 stable(feature = "neon_intrinsics", since = "1.59.0")
26977)]
26978#[cfg_attr(
26979 target_arch = "arm",
26980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26981)]
26982pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
26983 static_assert_uimm_bits!(LANE, 1);
26984 unsafe {
26985 simd_mul(
26986 a,
26987 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
26988 )
26989 }
26990}
26991#[doc = "Floating-point multiply"]
26992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
26993#[inline]
26994#[target_feature(enable = "neon")]
26995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
26997#[cfg_attr(
26998 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26999 assert_instr(fmul, LANE = 0)
27000)]
27001#[rustc_legacy_const_generics(2)]
27002#[cfg_attr(
27003 not(target_arch = "arm"),
27004 stable(feature = "neon_intrinsics", since = "1.59.0")
27005)]
27006#[cfg_attr(
27007 target_arch = "arm",
27008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27009)]
27010pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27011 static_assert_uimm_bits!(LANE, 2);
27012 unsafe {
27013 simd_mul(
27014 a,
27015 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27016 )
27017 }
27018}
27019#[doc = "Multiply"]
27020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
27021#[inline]
27022#[target_feature(enable = "neon")]
27023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27025#[cfg_attr(
27026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27027 assert_instr(mul, LANE = 1)
27028)]
27029#[rustc_legacy_const_generics(2)]
27030#[cfg_attr(
27031 not(target_arch = "arm"),
27032 stable(feature = "neon_intrinsics", since = "1.59.0")
27033)]
27034#[cfg_attr(
27035 target_arch = "arm",
27036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27037)]
27038pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27039 static_assert_uimm_bits!(LANE, 2);
27040 unsafe {
27041 simd_mul(
27042 a,
27043 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27044 )
27045 }
27046}
27047#[doc = "Multiply"]
27048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
27049#[inline]
27050#[target_feature(enable = "neon")]
27051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27053#[cfg_attr(
27054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27055 assert_instr(mul, LANE = 1)
27056)]
27057#[rustc_legacy_const_generics(2)]
27058#[cfg_attr(
27059 not(target_arch = "arm"),
27060 stable(feature = "neon_intrinsics", since = "1.59.0")
27061)]
27062#[cfg_attr(
27063 target_arch = "arm",
27064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27065)]
27066pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
27067 static_assert_uimm_bits!(LANE, 2);
27068 unsafe {
27069 simd_mul(
27070 a,
27071 simd_shuffle!(
27072 b,
27073 b,
27074 [
27075 LANE as u32,
27076 LANE as u32,
27077 LANE as u32,
27078 LANE as u32,
27079 LANE as u32,
27080 LANE as u32,
27081 LANE as u32,
27082 LANE as u32
27083 ]
27084 ),
27085 )
27086 }
27087}
27088#[doc = "Multiply"]
27089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
27090#[inline]
27091#[target_feature(enable = "neon")]
27092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27094#[cfg_attr(
27095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27096 assert_instr(mul, LANE = 1)
27097)]
27098#[rustc_legacy_const_generics(2)]
27099#[cfg_attr(
27100 not(target_arch = "arm"),
27101 stable(feature = "neon_intrinsics", since = "1.59.0")
27102)]
27103#[cfg_attr(
27104 target_arch = "arm",
27105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27106)]
27107pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27108 static_assert_uimm_bits!(LANE, 1);
27109 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
27110}
27111#[doc = "Multiply"]
27112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
27113#[inline]
27114#[target_feature(enable = "neon")]
27115#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27116#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27117#[cfg_attr(
27118 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27119 assert_instr(mul, LANE = 1)
27120)]
27121#[rustc_legacy_const_generics(2)]
27122#[cfg_attr(
27123 not(target_arch = "arm"),
27124 stable(feature = "neon_intrinsics", since = "1.59.0")
27125)]
27126#[cfg_attr(
27127 target_arch = "arm",
27128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27129)]
27130pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
27131 static_assert_uimm_bits!(LANE, 1);
27132 unsafe {
27133 simd_mul(
27134 a,
27135 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27136 )
27137 }
27138}
27139#[doc = "Multiply"]
27140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
27141#[inline]
27142#[target_feature(enable = "neon")]
27143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27145#[cfg_attr(
27146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27147 assert_instr(mul, LANE = 1)
27148)]
27149#[rustc_legacy_const_generics(2)]
27150#[cfg_attr(
27151 not(target_arch = "arm"),
27152 stable(feature = "neon_intrinsics", since = "1.59.0")
27153)]
27154#[cfg_attr(
27155 target_arch = "arm",
27156 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27157)]
27158pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27159 static_assert_uimm_bits!(LANE, 2);
27160 unsafe {
27161 simd_mul(
27162 a,
27163 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27164 )
27165 }
27166}
27167#[doc = "Multiply"]
27168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
27169#[inline]
27170#[target_feature(enable = "neon")]
27171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27173#[cfg_attr(
27174 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27175 assert_instr(mul, LANE = 1)
27176)]
27177#[rustc_legacy_const_generics(2)]
27178#[cfg_attr(
27179 not(target_arch = "arm"),
27180 stable(feature = "neon_intrinsics", since = "1.59.0")
27181)]
27182#[cfg_attr(
27183 target_arch = "arm",
27184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27185)]
27186pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
27187 static_assert_uimm_bits!(LANE, 2);
27188 unsafe {
27189 simd_mul(
27190 a,
27191 simd_shuffle!(
27192 b,
27193 b,
27194 [
27195 LANE as u32,
27196 LANE as u32,
27197 LANE as u32,
27198 LANE as u32,
27199 LANE as u32,
27200 LANE as u32,
27201 LANE as u32,
27202 LANE as u32
27203 ]
27204 ),
27205 )
27206 }
27207}
27208#[doc = "Multiply"]
27209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
27210#[inline]
27211#[target_feature(enable = "neon")]
27212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27214#[cfg_attr(
27215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27216 assert_instr(mul, LANE = 1)
27217)]
27218#[rustc_legacy_const_generics(2)]
27219#[cfg_attr(
27220 not(target_arch = "arm"),
27221 stable(feature = "neon_intrinsics", since = "1.59.0")
27222)]
27223#[cfg_attr(
27224 target_arch = "arm",
27225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27226)]
27227pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
27228 static_assert_uimm_bits!(LANE, 1);
27229 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
27230}
27231#[doc = "Multiply"]
27232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
27233#[inline]
27234#[target_feature(enable = "neon")]
27235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27237#[cfg_attr(
27238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27239 assert_instr(mul, LANE = 1)
27240)]
27241#[rustc_legacy_const_generics(2)]
27242#[cfg_attr(
27243 not(target_arch = "arm"),
27244 stable(feature = "neon_intrinsics", since = "1.59.0")
27245)]
27246#[cfg_attr(
27247 target_arch = "arm",
27248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27249)]
27250pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
27251 static_assert_uimm_bits!(LANE, 1);
27252 unsafe {
27253 simd_mul(
27254 a,
27255 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27256 )
27257 }
27258}
27259#[doc = "Multiply"]
27260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
27261#[inline]
27262#[target_feature(enable = "neon")]
27263#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27264#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27265#[cfg_attr(
27266 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27267 assert_instr(mul, LANE = 1)
27268)]
27269#[rustc_legacy_const_generics(2)]
27270#[cfg_attr(
27271 not(target_arch = "arm"),
27272 stable(feature = "neon_intrinsics", since = "1.59.0")
27273)]
27274#[cfg_attr(
27275 target_arch = "arm",
27276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27277)]
27278pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
27279 static_assert_uimm_bits!(LANE, 3);
27280 unsafe {
27281 simd_mul(
27282 a,
27283 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27284 )
27285 }
27286}
27287#[doc = "Multiply"]
27288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
27289#[inline]
27290#[target_feature(enable = "neon")]
27291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27293#[cfg_attr(
27294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27295 assert_instr(mul, LANE = 1)
27296)]
27297#[rustc_legacy_const_generics(2)]
27298#[cfg_attr(
27299 not(target_arch = "arm"),
27300 stable(feature = "neon_intrinsics", since = "1.59.0")
27301)]
27302#[cfg_attr(
27303 target_arch = "arm",
27304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27305)]
27306pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27307 static_assert_uimm_bits!(LANE, 3);
27308 unsafe {
27309 simd_mul(
27310 a,
27311 simd_shuffle!(
27312 b,
27313 b,
27314 [
27315 LANE as u32,
27316 LANE as u32,
27317 LANE as u32,
27318 LANE as u32,
27319 LANE as u32,
27320 LANE as u32,
27321 LANE as u32,
27322 LANE as u32
27323 ]
27324 ),
27325 )
27326 }
27327}
27328#[doc = "Multiply"]
27329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
27330#[inline]
27331#[target_feature(enable = "neon")]
27332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27334#[cfg_attr(
27335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27336 assert_instr(mul, LANE = 1)
27337)]
27338#[rustc_legacy_const_generics(2)]
27339#[cfg_attr(
27340 not(target_arch = "arm"),
27341 stable(feature = "neon_intrinsics", since = "1.59.0")
27342)]
27343#[cfg_attr(
27344 target_arch = "arm",
27345 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27346)]
27347pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
27348 static_assert_uimm_bits!(LANE, 2);
27349 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
27350}
27351#[doc = "Multiply"]
27352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
27353#[inline]
27354#[target_feature(enable = "neon")]
27355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27356#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27357#[cfg_attr(
27358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27359 assert_instr(mul, LANE = 1)
27360)]
27361#[rustc_legacy_const_generics(2)]
27362#[cfg_attr(
27363 not(target_arch = "arm"),
27364 stable(feature = "neon_intrinsics", since = "1.59.0")
27365)]
27366#[cfg_attr(
27367 target_arch = "arm",
27368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27369)]
27370pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27371 static_assert_uimm_bits!(LANE, 2);
27372 unsafe {
27373 simd_mul(
27374 a,
27375 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27376 )
27377 }
27378}
27379#[doc = "Multiply"]
27380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
27381#[inline]
27382#[target_feature(enable = "neon")]
27383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27385#[cfg_attr(
27386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27387 assert_instr(mul, LANE = 1)
27388)]
27389#[rustc_legacy_const_generics(2)]
27390#[cfg_attr(
27391 not(target_arch = "arm"),
27392 stable(feature = "neon_intrinsics", since = "1.59.0")
27393)]
27394#[cfg_attr(
27395 target_arch = "arm",
27396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27397)]
27398pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
27399 static_assert_uimm_bits!(LANE, 3);
27400 unsafe {
27401 simd_mul(
27402 a,
27403 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27404 )
27405 }
27406}
27407#[doc = "Multiply"]
27408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
27409#[inline]
27410#[target_feature(enable = "neon")]
27411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27413#[cfg_attr(
27414 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27415 assert_instr(mul, LANE = 1)
27416)]
27417#[rustc_legacy_const_generics(2)]
27418#[cfg_attr(
27419 not(target_arch = "arm"),
27420 stable(feature = "neon_intrinsics", since = "1.59.0")
27421)]
27422#[cfg_attr(
27423 target_arch = "arm",
27424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27425)]
27426pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27427 static_assert_uimm_bits!(LANE, 3);
27428 unsafe {
27429 simd_mul(
27430 a,
27431 simd_shuffle!(
27432 b,
27433 b,
27434 [
27435 LANE as u32,
27436 LANE as u32,
27437 LANE as u32,
27438 LANE as u32,
27439 LANE as u32,
27440 LANE as u32,
27441 LANE as u32,
27442 LANE as u32
27443 ]
27444 ),
27445 )
27446 }
27447}
27448#[doc = "Multiply"]
27449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
27450#[inline]
27451#[target_feature(enable = "neon")]
27452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27454#[cfg_attr(
27455 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27456 assert_instr(mul, LANE = 1)
27457)]
27458#[rustc_legacy_const_generics(2)]
27459#[cfg_attr(
27460 not(target_arch = "arm"),
27461 stable(feature = "neon_intrinsics", since = "1.59.0")
27462)]
27463#[cfg_attr(
27464 target_arch = "arm",
27465 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27466)]
27467pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
27468 static_assert_uimm_bits!(LANE, 2);
27469 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
27470}
27471#[doc = "Multiply"]
27472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
27473#[inline]
27474#[target_feature(enable = "neon")]
27475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
27477#[cfg_attr(
27478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27479 assert_instr(mul, LANE = 1)
27480)]
27481#[rustc_legacy_const_generics(2)]
27482#[cfg_attr(
27483 not(target_arch = "arm"),
27484 stable(feature = "neon_intrinsics", since = "1.59.0")
27485)]
27486#[cfg_attr(
27487 target_arch = "arm",
27488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27489)]
27490pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27491 static_assert_uimm_bits!(LANE, 2);
27492 unsafe {
27493 simd_mul(
27494 a,
27495 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
27496 )
27497 }
27498}
27499#[doc = "Vector multiply by scalar"]
27500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
27501#[inline]
27502#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27504#[cfg_attr(
27505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27506 assert_instr(fmul)
27507)]
27508#[target_feature(enable = "neon,fp16")]
27509#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27510pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
27511 unsafe { simd_mul(a, vdup_n_f16(b)) }
27512}
27513#[doc = "Vector multiply by scalar"]
27514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
27515#[inline]
27516#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27518#[cfg_attr(
27519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27520 assert_instr(fmul)
27521)]
27522#[target_feature(enable = "neon,fp16")]
27523#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27524pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
27525 unsafe { simd_mul(a, vdupq_n_f16(b)) }
27526}
27527#[doc = "Vector multiply by scalar"]
27528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
27529#[inline]
27530#[target_feature(enable = "neon")]
27531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27533#[cfg_attr(
27534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27535 assert_instr(fmul)
27536)]
27537#[cfg_attr(
27538 not(target_arch = "arm"),
27539 stable(feature = "neon_intrinsics", since = "1.59.0")
27540)]
27541#[cfg_attr(
27542 target_arch = "arm",
27543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27544)]
27545pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
27546 unsafe { simd_mul(a, vdup_n_f32(b)) }
27547}
27548#[doc = "Vector multiply by scalar"]
27549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
27550#[inline]
27551#[target_feature(enable = "neon")]
27552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27553#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27554#[cfg_attr(
27555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27556 assert_instr(fmul)
27557)]
27558#[cfg_attr(
27559 not(target_arch = "arm"),
27560 stable(feature = "neon_intrinsics", since = "1.59.0")
27561)]
27562#[cfg_attr(
27563 target_arch = "arm",
27564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27565)]
27566pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
27567 unsafe { simd_mul(a, vdupq_n_f32(b)) }
27568}
27569#[doc = "Vector multiply by scalar"]
27570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
27571#[inline]
27572#[target_feature(enable = "neon")]
27573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27575#[cfg_attr(
27576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27577 assert_instr(mul)
27578)]
27579#[cfg_attr(
27580 not(target_arch = "arm"),
27581 stable(feature = "neon_intrinsics", since = "1.59.0")
27582)]
27583#[cfg_attr(
27584 target_arch = "arm",
27585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27586)]
27587pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
27588 unsafe { simd_mul(a, vdup_n_s16(b)) }
27589}
27590#[doc = "Vector multiply by scalar"]
27591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
27592#[inline]
27593#[target_feature(enable = "neon")]
27594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27596#[cfg_attr(
27597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27598 assert_instr(mul)
27599)]
27600#[cfg_attr(
27601 not(target_arch = "arm"),
27602 stable(feature = "neon_intrinsics", since = "1.59.0")
27603)]
27604#[cfg_attr(
27605 target_arch = "arm",
27606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27607)]
27608pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
27609 unsafe { simd_mul(a, vdupq_n_s16(b)) }
27610}
27611#[doc = "Vector multiply by scalar"]
27612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
27613#[inline]
27614#[target_feature(enable = "neon")]
27615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27617#[cfg_attr(
27618 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27619 assert_instr(mul)
27620)]
27621#[cfg_attr(
27622 not(target_arch = "arm"),
27623 stable(feature = "neon_intrinsics", since = "1.59.0")
27624)]
27625#[cfg_attr(
27626 target_arch = "arm",
27627 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27628)]
27629pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
27630 unsafe { simd_mul(a, vdup_n_s32(b)) }
27631}
27632#[doc = "Vector multiply by scalar"]
27633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
27634#[inline]
27635#[target_feature(enable = "neon")]
27636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27638#[cfg_attr(
27639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27640 assert_instr(mul)
27641)]
27642#[cfg_attr(
27643 not(target_arch = "arm"),
27644 stable(feature = "neon_intrinsics", since = "1.59.0")
27645)]
27646#[cfg_attr(
27647 target_arch = "arm",
27648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27649)]
27650pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
27651 unsafe { simd_mul(a, vdupq_n_s32(b)) }
27652}
27653#[doc = "Vector multiply by scalar"]
27654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
27655#[inline]
27656#[target_feature(enable = "neon")]
27657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27659#[cfg_attr(
27660 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27661 assert_instr(mul)
27662)]
27663#[cfg_attr(
27664 not(target_arch = "arm"),
27665 stable(feature = "neon_intrinsics", since = "1.59.0")
27666)]
27667#[cfg_attr(
27668 target_arch = "arm",
27669 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27670)]
27671pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
27672 unsafe { simd_mul(a, vdup_n_u16(b)) }
27673}
27674#[doc = "Vector multiply by scalar"]
27675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
27676#[inline]
27677#[target_feature(enable = "neon")]
27678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27680#[cfg_attr(
27681 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27682 assert_instr(mul)
27683)]
27684#[cfg_attr(
27685 not(target_arch = "arm"),
27686 stable(feature = "neon_intrinsics", since = "1.59.0")
27687)]
27688#[cfg_attr(
27689 target_arch = "arm",
27690 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27691)]
27692pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
27693 unsafe { simd_mul(a, vdupq_n_u16(b)) }
27694}
27695#[doc = "Vector multiply by scalar"]
27696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
27697#[inline]
27698#[target_feature(enable = "neon")]
27699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27701#[cfg_attr(
27702 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27703 assert_instr(mul)
27704)]
27705#[cfg_attr(
27706 not(target_arch = "arm"),
27707 stable(feature = "neon_intrinsics", since = "1.59.0")
27708)]
27709#[cfg_attr(
27710 target_arch = "arm",
27711 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27712)]
27713pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
27714 unsafe { simd_mul(a, vdup_n_u32(b)) }
27715}
27716#[doc = "Vector multiply by scalar"]
27717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
27718#[inline]
27719#[target_feature(enable = "neon")]
27720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27721#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27722#[cfg_attr(
27723 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27724 assert_instr(mul)
27725)]
27726#[cfg_attr(
27727 not(target_arch = "arm"),
27728 stable(feature = "neon_intrinsics", since = "1.59.0")
27729)]
27730#[cfg_attr(
27731 target_arch = "arm",
27732 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27733)]
27734pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
27735 unsafe { simd_mul(a, vdupq_n_u32(b)) }
27736}
27737#[doc = "Polynomial multiply"]
27738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
27739#[inline]
27740#[target_feature(enable = "neon")]
27741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27743#[cfg_attr(
27744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27745 assert_instr(pmul)
27746)]
27747#[cfg_attr(
27748 not(target_arch = "arm"),
27749 stable(feature = "neon_intrinsics", since = "1.59.0")
27750)]
27751#[cfg_attr(
27752 target_arch = "arm",
27753 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27754)]
27755pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
27756 unsafe extern "unadjusted" {
27757 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")]
27758 #[cfg_attr(
27759 any(target_arch = "aarch64", target_arch = "arm64ec"),
27760 link_name = "llvm.aarch64.neon.pmul.v8i8"
27761 )]
27762 fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t;
27763 }
27764 unsafe { _vmul_p8(a, b) }
27765}
27766#[doc = "Polynomial multiply"]
27767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
27768#[inline]
27769#[target_feature(enable = "neon")]
27770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
27772#[cfg_attr(
27773 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27774 assert_instr(pmul)
27775)]
27776#[cfg_attr(
27777 not(target_arch = "arm"),
27778 stable(feature = "neon_intrinsics", since = "1.59.0")
27779)]
27780#[cfg_attr(
27781 target_arch = "arm",
27782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27783)]
27784pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
27785 unsafe extern "unadjusted" {
27786 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")]
27787 #[cfg_attr(
27788 any(target_arch = "aarch64", target_arch = "arm64ec"),
27789 link_name = "llvm.aarch64.neon.pmul.v16i8"
27790 )]
27791 fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t;
27792 }
27793 unsafe { _vmulq_p8(a, b) }
27794}
27795#[doc = "Multiply"]
27796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
27797#[inline]
27798#[target_feature(enable = "neon")]
27799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27800#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
27801#[cfg_attr(
27802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27803 assert_instr(mul)
27804)]
27805#[cfg_attr(
27806 not(target_arch = "arm"),
27807 stable(feature = "neon_intrinsics", since = "1.59.0")
27808)]
27809#[cfg_attr(
27810 target_arch = "arm",
27811 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27812)]
27813pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27814 unsafe { simd_mul(a, b) }
27815}
27816#[doc = "Multiply"]
27817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
27818#[inline]
27819#[target_feature(enable = "neon")]
27820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27821#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
27822#[cfg_attr(
27823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27824 assert_instr(mul)
27825)]
27826#[cfg_attr(
27827 not(target_arch = "arm"),
27828 stable(feature = "neon_intrinsics", since = "1.59.0")
27829)]
27830#[cfg_attr(
27831 target_arch = "arm",
27832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27833)]
27834pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27835 unsafe { simd_mul(a, b) }
27836}
27837#[doc = "Multiply"]
27838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
27839#[inline]
27840#[target_feature(enable = "neon")]
27841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27842#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
27843#[cfg_attr(
27844 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27845 assert_instr(mul)
27846)]
27847#[cfg_attr(
27848 not(target_arch = "arm"),
27849 stable(feature = "neon_intrinsics", since = "1.59.0")
27850)]
27851#[cfg_attr(
27852 target_arch = "arm",
27853 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27854)]
27855pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27856 unsafe { simd_mul(a, b) }
27857}
27858#[doc = "Multiply"]
27859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
27860#[inline]
27861#[target_feature(enable = "neon")]
27862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
27864#[cfg_attr(
27865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27866 assert_instr(mul)
27867)]
27868#[cfg_attr(
27869 not(target_arch = "arm"),
27870 stable(feature = "neon_intrinsics", since = "1.59.0")
27871)]
27872#[cfg_attr(
27873 target_arch = "arm",
27874 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27875)]
27876pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27877 unsafe { simd_mul(a, b) }
27878}
27879#[doc = "Multiply"]
27880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
27881#[inline]
27882#[target_feature(enable = "neon")]
27883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
27885#[cfg_attr(
27886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27887 assert_instr(mul)
27888)]
27889#[cfg_attr(
27890 not(target_arch = "arm"),
27891 stable(feature = "neon_intrinsics", since = "1.59.0")
27892)]
27893#[cfg_attr(
27894 target_arch = "arm",
27895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27896)]
27897pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27898 unsafe { simd_mul(a, b) }
27899}
27900#[doc = "Multiply"]
27901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
27902#[inline]
27903#[target_feature(enable = "neon")]
27904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27905#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
27906#[cfg_attr(
27907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27908 assert_instr(mul)
27909)]
27910#[cfg_attr(
27911 not(target_arch = "arm"),
27912 stable(feature = "neon_intrinsics", since = "1.59.0")
27913)]
27914#[cfg_attr(
27915 target_arch = "arm",
27916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27917)]
27918pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27919 unsafe { simd_mul(a, b) }
27920}
27921#[doc = "Multiply"]
27922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
27923#[inline]
27924#[target_feature(enable = "neon")]
27925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27926#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
27927#[cfg_attr(
27928 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27929 assert_instr(mul)
27930)]
27931#[cfg_attr(
27932 not(target_arch = "arm"),
27933 stable(feature = "neon_intrinsics", since = "1.59.0")
27934)]
27935#[cfg_attr(
27936 target_arch = "arm",
27937 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27938)]
27939pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
27940 unsafe { simd_mul(a, b) }
27941}
27942#[doc = "Multiply"]
27943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
27944#[inline]
27945#[target_feature(enable = "neon")]
27946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
27948#[cfg_attr(
27949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27950 assert_instr(mul)
27951)]
27952#[cfg_attr(
27953 not(target_arch = "arm"),
27954 stable(feature = "neon_intrinsics", since = "1.59.0")
27955)]
27956#[cfg_attr(
27957 target_arch = "arm",
27958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27959)]
27960pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27961 unsafe { simd_mul(a, b) }
27962}
27963#[doc = "Multiply"]
27964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
27965#[inline]
27966#[target_feature(enable = "neon")]
27967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27968#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
27969#[cfg_attr(
27970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27971 assert_instr(mul)
27972)]
27973#[cfg_attr(
27974 not(target_arch = "arm"),
27975 stable(feature = "neon_intrinsics", since = "1.59.0")
27976)]
27977#[cfg_attr(
27978 target_arch = "arm",
27979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27980)]
27981pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27982 unsafe { simd_mul(a, b) }
27983}
27984#[doc = "Multiply"]
27985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
27986#[inline]
27987#[target_feature(enable = "neon")]
27988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27989#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
27990#[cfg_attr(
27991 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27992 assert_instr(mul)
27993)]
27994#[cfg_attr(
27995 not(target_arch = "arm"),
27996 stable(feature = "neon_intrinsics", since = "1.59.0")
27997)]
27998#[cfg_attr(
27999 target_arch = "arm",
28000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28001)]
28002pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28003 unsafe { simd_mul(a, b) }
28004}
28005#[doc = "Multiply"]
28006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
28007#[inline]
28008#[target_feature(enable = "neon")]
28009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28010#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
28011#[cfg_attr(
28012 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28013 assert_instr(mul)
28014)]
28015#[cfg_attr(
28016 not(target_arch = "arm"),
28017 stable(feature = "neon_intrinsics", since = "1.59.0")
28018)]
28019#[cfg_attr(
28020 target_arch = "arm",
28021 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28022)]
28023pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28024 unsafe { simd_mul(a, b) }
28025}
28026#[doc = "Multiply"]
28027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
28028#[inline]
28029#[target_feature(enable = "neon")]
28030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28031#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
28032#[cfg_attr(
28033 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28034 assert_instr(mul)
28035)]
28036#[cfg_attr(
28037 not(target_arch = "arm"),
28038 stable(feature = "neon_intrinsics", since = "1.59.0")
28039)]
28040#[cfg_attr(
28041 target_arch = "arm",
28042 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28043)]
28044pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28045 unsafe { simd_mul(a, b) }
28046}
28047#[doc = "Vector long multiply by scalar"]
28048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
28049#[inline]
28050#[target_feature(enable = "neon")]
28051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28053#[cfg_attr(
28054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28055 assert_instr(smull, LANE = 1)
28056)]
28057#[rustc_legacy_const_generics(2)]
28058#[cfg_attr(
28059 not(target_arch = "arm"),
28060 stable(feature = "neon_intrinsics", since = "1.59.0")
28061)]
28062#[cfg_attr(
28063 target_arch = "arm",
28064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28065)]
28066pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
28067 static_assert_uimm_bits!(LANE, 2);
28068 unsafe {
28069 vmull_s16(
28070 a,
28071 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28072 )
28073 }
28074}
28075#[doc = "Vector long multiply by scalar"]
28076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
28077#[inline]
28078#[target_feature(enable = "neon")]
28079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28081#[cfg_attr(
28082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28083 assert_instr(smull, LANE = 1)
28084)]
28085#[rustc_legacy_const_generics(2)]
28086#[cfg_attr(
28087 not(target_arch = "arm"),
28088 stable(feature = "neon_intrinsics", since = "1.59.0")
28089)]
28090#[cfg_attr(
28091 target_arch = "arm",
28092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28093)]
28094pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
28095 static_assert_uimm_bits!(LANE, 3);
28096 unsafe {
28097 vmull_s16(
28098 a,
28099 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28100 )
28101 }
28102}
28103#[doc = "Vector long multiply by scalar"]
28104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
28105#[inline]
28106#[target_feature(enable = "neon")]
28107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28109#[cfg_attr(
28110 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28111 assert_instr(smull, LANE = 1)
28112)]
28113#[rustc_legacy_const_generics(2)]
28114#[cfg_attr(
28115 not(target_arch = "arm"),
28116 stable(feature = "neon_intrinsics", since = "1.59.0")
28117)]
28118#[cfg_attr(
28119 target_arch = "arm",
28120 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28121)]
28122pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
28123 static_assert_uimm_bits!(LANE, 1);
28124 unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
28125}
28126#[doc = "Vector long multiply by scalar"]
28127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
28128#[inline]
28129#[target_feature(enable = "neon")]
28130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28132#[cfg_attr(
28133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28134 assert_instr(smull, LANE = 1)
28135)]
28136#[rustc_legacy_const_generics(2)]
28137#[cfg_attr(
28138 not(target_arch = "arm"),
28139 stable(feature = "neon_intrinsics", since = "1.59.0")
28140)]
28141#[cfg_attr(
28142 target_arch = "arm",
28143 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28144)]
28145pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
28146 static_assert_uimm_bits!(LANE, 2);
28147 unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
28148}
28149#[doc = "Vector long multiply by scalar"]
28150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
28151#[inline]
28152#[target_feature(enable = "neon")]
28153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28154#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28155#[cfg_attr(
28156 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28157 assert_instr(umull, LANE = 1)
28158)]
28159#[rustc_legacy_const_generics(2)]
28160#[cfg_attr(
28161 not(target_arch = "arm"),
28162 stable(feature = "neon_intrinsics", since = "1.59.0")
28163)]
28164#[cfg_attr(
28165 target_arch = "arm",
28166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28167)]
28168pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
28169 static_assert_uimm_bits!(LANE, 2);
28170 unsafe {
28171 vmull_u16(
28172 a,
28173 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28174 )
28175 }
28176}
28177#[doc = "Vector long multiply by scalar"]
28178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
28179#[inline]
28180#[target_feature(enable = "neon")]
28181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28183#[cfg_attr(
28184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28185 assert_instr(umull, LANE = 1)
28186)]
28187#[rustc_legacy_const_generics(2)]
28188#[cfg_attr(
28189 not(target_arch = "arm"),
28190 stable(feature = "neon_intrinsics", since = "1.59.0")
28191)]
28192#[cfg_attr(
28193 target_arch = "arm",
28194 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28195)]
28196pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t {
28197 static_assert_uimm_bits!(LANE, 3);
28198 unsafe {
28199 vmull_u16(
28200 a,
28201 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28202 )
28203 }
28204}
28205#[doc = "Vector long multiply by scalar"]
28206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
28207#[inline]
28208#[target_feature(enable = "neon")]
28209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28211#[cfg_attr(
28212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28213 assert_instr(umull, LANE = 1)
28214)]
28215#[rustc_legacy_const_generics(2)]
28216#[cfg_attr(
28217 not(target_arch = "arm"),
28218 stable(feature = "neon_intrinsics", since = "1.59.0")
28219)]
28220#[cfg_attr(
28221 target_arch = "arm",
28222 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28223)]
28224pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
28225 static_assert_uimm_bits!(LANE, 1);
28226 unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
28227}
28228#[doc = "Vector long multiply by scalar"]
28229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
28230#[inline]
28231#[target_feature(enable = "neon")]
28232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
28234#[cfg_attr(
28235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28236 assert_instr(umull, LANE = 1)
28237)]
28238#[rustc_legacy_const_generics(2)]
28239#[cfg_attr(
28240 not(target_arch = "arm"),
28241 stable(feature = "neon_intrinsics", since = "1.59.0")
28242)]
28243#[cfg_attr(
28244 target_arch = "arm",
28245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28246)]
28247pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t {
28248 static_assert_uimm_bits!(LANE, 2);
28249 unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
28250}
28251#[doc = "Vector long multiply with scalar"]
28252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
28253#[inline]
28254#[target_feature(enable = "neon")]
28255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
28257#[cfg_attr(
28258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28259 assert_instr(smull)
28260)]
28261#[cfg_attr(
28262 not(target_arch = "arm"),
28263 stable(feature = "neon_intrinsics", since = "1.59.0")
28264)]
28265#[cfg_attr(
28266 target_arch = "arm",
28267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28268)]
28269pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
28270 vmull_s16(a, vdup_n_s16(b))
28271}
28272#[doc = "Vector long multiply with scalar"]
28273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
28274#[inline]
28275#[target_feature(enable = "neon")]
28276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
28278#[cfg_attr(
28279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28280 assert_instr(smull)
28281)]
28282#[cfg_attr(
28283 not(target_arch = "arm"),
28284 stable(feature = "neon_intrinsics", since = "1.59.0")
28285)]
28286#[cfg_attr(
28287 target_arch = "arm",
28288 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28289)]
28290pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
28291 vmull_s32(a, vdup_n_s32(b))
28292}
28293#[doc = "Vector long multiply with scalar"]
28294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
28295#[inline]
28296#[target_feature(enable = "neon")]
28297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
28299#[cfg_attr(
28300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28301 assert_instr(umull)
28302)]
28303#[cfg_attr(
28304 not(target_arch = "arm"),
28305 stable(feature = "neon_intrinsics", since = "1.59.0")
28306)]
28307#[cfg_attr(
28308 target_arch = "arm",
28309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28310)]
28311pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
28312 vmull_u16(a, vdup_n_u16(b))
28313}
28314#[doc = "Vector long multiply with scalar"]
28315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
28316#[inline]
28317#[target_feature(enable = "neon")]
28318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
28320#[cfg_attr(
28321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28322 assert_instr(umull)
28323)]
28324#[cfg_attr(
28325 not(target_arch = "arm"),
28326 stable(feature = "neon_intrinsics", since = "1.59.0")
28327)]
28328#[cfg_attr(
28329 target_arch = "arm",
28330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28331)]
28332pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
28333 vmull_u32(a, vdup_n_u32(b))
28334}
28335#[doc = "Polynomial multiply long"]
28336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
28337#[inline]
28338#[target_feature(enable = "neon")]
28339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
28341#[cfg_attr(
28342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28343 assert_instr(pmull)
28344)]
28345#[cfg_attr(
28346 not(target_arch = "arm"),
28347 stable(feature = "neon_intrinsics", since = "1.59.0")
28348)]
28349#[cfg_attr(
28350 target_arch = "arm",
28351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28352)]
28353pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
28354 unsafe extern "unadjusted" {
28355 #[cfg_attr(
28356 any(target_arch = "aarch64", target_arch = "arm64ec"),
28357 link_name = "llvm.aarch64.neon.pmull.v8i16"
28358 )]
28359 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")]
28360 fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t;
28361 }
28362 unsafe { _vmull_p8(a, b) }
28363}
28364#[doc = "Signed multiply long"]
28365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
28366#[inline]
28367#[target_feature(enable = "neon")]
28368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
28370#[cfg_attr(
28371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28372 assert_instr(smull)
28373)]
28374#[cfg_attr(
28375 not(target_arch = "arm"),
28376 stable(feature = "neon_intrinsics", since = "1.59.0")
28377)]
28378#[cfg_attr(
28379 target_arch = "arm",
28380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28381)]
28382pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
28383 unsafe extern "unadjusted" {
28384 #[cfg_attr(
28385 any(target_arch = "aarch64", target_arch = "arm64ec"),
28386 link_name = "llvm.aarch64.neon.smull.v4i16"
28387 )]
28388 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i16")]
28389 fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
28390 }
28391 unsafe { _vmull_s16(a, b) }
28392}
28393#[doc = "Signed multiply long"]
28394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
28395#[inline]
28396#[target_feature(enable = "neon")]
28397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28398#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
28399#[cfg_attr(
28400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28401 assert_instr(smull)
28402)]
28403#[cfg_attr(
28404 not(target_arch = "arm"),
28405 stable(feature = "neon_intrinsics", since = "1.59.0")
28406)]
28407#[cfg_attr(
28408 target_arch = "arm",
28409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28410)]
28411pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
28412 unsafe extern "unadjusted" {
28413 #[cfg_attr(
28414 any(target_arch = "aarch64", target_arch = "arm64ec"),
28415 link_name = "llvm.aarch64.neon.smull.v2i32"
28416 )]
28417 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i32")]
28418 fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
28419 }
28420 unsafe { _vmull_s32(a, b) }
28421}
28422#[doc = "Signed multiply long"]
28423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
28424#[inline]
28425#[target_feature(enable = "neon")]
28426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28427#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
28428#[cfg_attr(
28429 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28430 assert_instr(smull)
28431)]
28432#[cfg_attr(
28433 not(target_arch = "arm"),
28434 stable(feature = "neon_intrinsics", since = "1.59.0")
28435)]
28436#[cfg_attr(
28437 target_arch = "arm",
28438 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28439)]
28440pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
28441 unsafe extern "unadjusted" {
28442 #[cfg_attr(
28443 any(target_arch = "aarch64", target_arch = "arm64ec"),
28444 link_name = "llvm.aarch64.neon.smull.v8i8"
28445 )]
28446 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i8")]
28447 fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t;
28448 }
28449 unsafe { _vmull_s8(a, b) }
28450}
28451#[doc = "Unsigned multiply long"]
28452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
28453#[inline]
28454#[target_feature(enable = "neon")]
28455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28456#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
28457#[cfg_attr(
28458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28459 assert_instr(umull)
28460)]
28461#[cfg_attr(
28462 not(target_arch = "arm"),
28463 stable(feature = "neon_intrinsics", since = "1.59.0")
28464)]
28465#[cfg_attr(
28466 target_arch = "arm",
28467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28468)]
28469pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
28470 unsafe extern "unadjusted" {
28471 #[cfg_attr(
28472 any(target_arch = "aarch64", target_arch = "arm64ec"),
28473 link_name = "llvm.aarch64.neon.umull.v8i8"
28474 )]
28475 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i8")]
28476 fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t;
28477 }
28478 unsafe { _vmull_u8(a, b) }
28479}
28480#[doc = "Unsigned multiply long"]
28481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
28482#[inline]
28483#[target_feature(enable = "neon")]
28484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
28486#[cfg_attr(
28487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28488 assert_instr(umull)
28489)]
28490#[cfg_attr(
28491 not(target_arch = "arm"),
28492 stable(feature = "neon_intrinsics", since = "1.59.0")
28493)]
28494#[cfg_attr(
28495 target_arch = "arm",
28496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28497)]
28498pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
28499 unsafe extern "unadjusted" {
28500 #[cfg_attr(
28501 any(target_arch = "aarch64", target_arch = "arm64ec"),
28502 link_name = "llvm.aarch64.neon.umull.v4i16"
28503 )]
28504 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i16")]
28505 fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t;
28506 }
28507 unsafe { _vmull_u16(a, b) }
28508}
28509#[doc = "Unsigned multiply long"]
28510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
28511#[inline]
28512#[target_feature(enable = "neon")]
28513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28514#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
28515#[cfg_attr(
28516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28517 assert_instr(umull)
28518)]
28519#[cfg_attr(
28520 not(target_arch = "arm"),
28521 stable(feature = "neon_intrinsics", since = "1.59.0")
28522)]
28523#[cfg_attr(
28524 target_arch = "arm",
28525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28526)]
28527pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
28528 unsafe extern "unadjusted" {
28529 #[cfg_attr(
28530 any(target_arch = "aarch64", target_arch = "arm64ec"),
28531 link_name = "llvm.aarch64.neon.umull.v2i32"
28532 )]
28533 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i32")]
28534 fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t;
28535 }
28536 unsafe { _vmull_u32(a, b) }
28537}
28538#[doc = "Negate"]
28539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
28540#[inline]
28541#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28542#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
28543#[cfg_attr(
28544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28545 assert_instr(fneg)
28546)]
28547#[target_feature(enable = "neon,fp16")]
28548#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28549pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
28550 unsafe { simd_neg(a) }
28551}
28552#[doc = "Negate"]
28553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
28554#[inline]
28555#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
28557#[cfg_attr(
28558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28559 assert_instr(fneg)
28560)]
28561#[target_feature(enable = "neon,fp16")]
28562#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28563pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
28564 unsafe { simd_neg(a) }
28565}
28566#[doc = "Negate"]
28567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
28568#[inline]
28569#[target_feature(enable = "neon")]
28570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28571#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
28572#[cfg_attr(
28573 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28574 assert_instr(fneg)
28575)]
28576#[cfg_attr(
28577 not(target_arch = "arm"),
28578 stable(feature = "neon_intrinsics", since = "1.59.0")
28579)]
28580#[cfg_attr(
28581 target_arch = "arm",
28582 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28583)]
28584pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
28585 unsafe { simd_neg(a) }
28586}
28587#[doc = "Negate"]
28588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
28589#[inline]
28590#[target_feature(enable = "neon")]
28591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28592#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
28593#[cfg_attr(
28594 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28595 assert_instr(fneg)
28596)]
28597#[cfg_attr(
28598 not(target_arch = "arm"),
28599 stable(feature = "neon_intrinsics", since = "1.59.0")
28600)]
28601#[cfg_attr(
28602 target_arch = "arm",
28603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28604)]
28605pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
28606 unsafe { simd_neg(a) }
28607}
28608#[doc = "Negate"]
28609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
28610#[inline]
28611#[target_feature(enable = "neon")]
28612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
28614#[cfg_attr(
28615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28616 assert_instr(neg)
28617)]
28618#[cfg_attr(
28619 not(target_arch = "arm"),
28620 stable(feature = "neon_intrinsics", since = "1.59.0")
28621)]
28622#[cfg_attr(
28623 target_arch = "arm",
28624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28625)]
28626pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
28627 unsafe { simd_neg(a) }
28628}
28629#[doc = "Negate"]
28630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
28631#[inline]
28632#[target_feature(enable = "neon")]
28633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
28635#[cfg_attr(
28636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28637 assert_instr(neg)
28638)]
28639#[cfg_attr(
28640 not(target_arch = "arm"),
28641 stable(feature = "neon_intrinsics", since = "1.59.0")
28642)]
28643#[cfg_attr(
28644 target_arch = "arm",
28645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28646)]
28647pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
28648 unsafe { simd_neg(a) }
28649}
28650#[doc = "Negate"]
28651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
28652#[inline]
28653#[target_feature(enable = "neon")]
28654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
28656#[cfg_attr(
28657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28658 assert_instr(neg)
28659)]
28660#[cfg_attr(
28661 not(target_arch = "arm"),
28662 stable(feature = "neon_intrinsics", since = "1.59.0")
28663)]
28664#[cfg_attr(
28665 target_arch = "arm",
28666 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28667)]
28668pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
28669 unsafe { simd_neg(a) }
28670}
28671#[doc = "Negate"]
28672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
28673#[inline]
28674#[target_feature(enable = "neon")]
28675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
28677#[cfg_attr(
28678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28679 assert_instr(neg)
28680)]
28681#[cfg_attr(
28682 not(target_arch = "arm"),
28683 stable(feature = "neon_intrinsics", since = "1.59.0")
28684)]
28685#[cfg_attr(
28686 target_arch = "arm",
28687 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28688)]
28689pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
28690 unsafe { simd_neg(a) }
28691}
28692#[doc = "Negate"]
28693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
28694#[inline]
28695#[target_feature(enable = "neon")]
28696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28697#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
28698#[cfg_attr(
28699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28700 assert_instr(neg)
28701)]
28702#[cfg_attr(
28703 not(target_arch = "arm"),
28704 stable(feature = "neon_intrinsics", since = "1.59.0")
28705)]
28706#[cfg_attr(
28707 target_arch = "arm",
28708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28709)]
28710pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
28711 unsafe { simd_neg(a) }
28712}
28713#[doc = "Negate"]
28714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
28715#[inline]
28716#[target_feature(enable = "neon")]
28717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28718#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
28719#[cfg_attr(
28720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28721 assert_instr(neg)
28722)]
28723#[cfg_attr(
28724 not(target_arch = "arm"),
28725 stable(feature = "neon_intrinsics", since = "1.59.0")
28726)]
28727#[cfg_attr(
28728 target_arch = "arm",
28729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28730)]
28731pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
28732 unsafe { simd_neg(a) }
28733}
28734#[doc = "Vector bitwise or (immediate, inclusive)"]
28735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
28736#[inline]
28737#[target_feature(enable = "neon")]
28738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28740#[cfg_attr(
28741 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28742 assert_instr(orr)
28743)]
28744#[cfg_attr(
28745 not(target_arch = "arm"),
28746 stable(feature = "neon_intrinsics", since = "1.59.0")
28747)]
28748#[cfg_attr(
28749 target_arch = "arm",
28750 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28751)]
28752pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28753 unsafe { simd_or(a, b) }
28754}
28755#[doc = "Vector bitwise or (immediate, inclusive)"]
28756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
28757#[inline]
28758#[target_feature(enable = "neon")]
28759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28761#[cfg_attr(
28762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28763 assert_instr(orr)
28764)]
28765#[cfg_attr(
28766 not(target_arch = "arm"),
28767 stable(feature = "neon_intrinsics", since = "1.59.0")
28768)]
28769#[cfg_attr(
28770 target_arch = "arm",
28771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28772)]
28773pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28774 unsafe { simd_or(a, b) }
28775}
28776#[doc = "Vector bitwise or (immediate, inclusive)"]
28777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
28778#[inline]
28779#[target_feature(enable = "neon")]
28780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28782#[cfg_attr(
28783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28784 assert_instr(orr)
28785)]
28786#[cfg_attr(
28787 not(target_arch = "arm"),
28788 stable(feature = "neon_intrinsics", since = "1.59.0")
28789)]
28790#[cfg_attr(
28791 target_arch = "arm",
28792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28793)]
28794pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28795 unsafe { simd_or(a, b) }
28796}
28797#[doc = "Vector bitwise or (immediate, inclusive)"]
28798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
28799#[inline]
28800#[target_feature(enable = "neon")]
28801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28803#[cfg_attr(
28804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28805 assert_instr(orr)
28806)]
28807#[cfg_attr(
28808 not(target_arch = "arm"),
28809 stable(feature = "neon_intrinsics", since = "1.59.0")
28810)]
28811#[cfg_attr(
28812 target_arch = "arm",
28813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28814)]
28815pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28816 unsafe { simd_or(a, b) }
28817}
28818#[doc = "Vector bitwise or (immediate, inclusive)"]
28819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
28820#[inline]
28821#[target_feature(enable = "neon")]
28822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28824#[cfg_attr(
28825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28826 assert_instr(orr)
28827)]
28828#[cfg_attr(
28829 not(target_arch = "arm"),
28830 stable(feature = "neon_intrinsics", since = "1.59.0")
28831)]
28832#[cfg_attr(
28833 target_arch = "arm",
28834 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28835)]
28836pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28837 unsafe { simd_or(a, b) }
28838}
28839#[doc = "Vector bitwise or (immediate, inclusive)"]
28840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
28841#[inline]
28842#[target_feature(enable = "neon")]
28843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28845#[cfg_attr(
28846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28847 assert_instr(orr)
28848)]
28849#[cfg_attr(
28850 not(target_arch = "arm"),
28851 stable(feature = "neon_intrinsics", since = "1.59.0")
28852)]
28853#[cfg_attr(
28854 target_arch = "arm",
28855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28856)]
28857pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28858 unsafe { simd_or(a, b) }
28859}
28860#[doc = "Vector bitwise or (immediate, inclusive)"]
28861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
28862#[inline]
28863#[target_feature(enable = "neon")]
28864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28866#[cfg_attr(
28867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28868 assert_instr(orr)
28869)]
28870#[cfg_attr(
28871 not(target_arch = "arm"),
28872 stable(feature = "neon_intrinsics", since = "1.59.0")
28873)]
28874#[cfg_attr(
28875 target_arch = "arm",
28876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28877)]
28878pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
28879 unsafe { simd_or(a, b) }
28880}
28881#[doc = "Vector bitwise or (immediate, inclusive)"]
28882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
28883#[inline]
28884#[target_feature(enable = "neon")]
28885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28887#[cfg_attr(
28888 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28889 assert_instr(orr)
28890)]
28891#[cfg_attr(
28892 not(target_arch = "arm"),
28893 stable(feature = "neon_intrinsics", since = "1.59.0")
28894)]
28895#[cfg_attr(
28896 target_arch = "arm",
28897 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28898)]
28899pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
28900 unsafe { simd_or(a, b) }
28901}
28902#[doc = "Vector bitwise or (immediate, inclusive)"]
28903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
28904#[inline]
28905#[target_feature(enable = "neon")]
28906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28908#[cfg_attr(
28909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28910 assert_instr(orr)
28911)]
28912#[cfg_attr(
28913 not(target_arch = "arm"),
28914 stable(feature = "neon_intrinsics", since = "1.59.0")
28915)]
28916#[cfg_attr(
28917 target_arch = "arm",
28918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28919)]
28920pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28921 unsafe { simd_or(a, b) }
28922}
28923#[doc = "Vector bitwise or (immediate, inclusive)"]
28924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
28925#[inline]
28926#[target_feature(enable = "neon")]
28927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28929#[cfg_attr(
28930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28931 assert_instr(orr)
28932)]
28933#[cfg_attr(
28934 not(target_arch = "arm"),
28935 stable(feature = "neon_intrinsics", since = "1.59.0")
28936)]
28937#[cfg_attr(
28938 target_arch = "arm",
28939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28940)]
28941pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28942 unsafe { simd_or(a, b) }
28943}
28944#[doc = "Vector bitwise or (immediate, inclusive)"]
28945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
28946#[inline]
28947#[target_feature(enable = "neon")]
28948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28950#[cfg_attr(
28951 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28952 assert_instr(orr)
28953)]
28954#[cfg_attr(
28955 not(target_arch = "arm"),
28956 stable(feature = "neon_intrinsics", since = "1.59.0")
28957)]
28958#[cfg_attr(
28959 target_arch = "arm",
28960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28961)]
28962pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28963 unsafe { simd_or(a, b) }
28964}
28965#[doc = "Vector bitwise or (immediate, inclusive)"]
28966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
28967#[inline]
28968#[target_feature(enable = "neon")]
28969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28971#[cfg_attr(
28972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28973 assert_instr(orr)
28974)]
28975#[cfg_attr(
28976 not(target_arch = "arm"),
28977 stable(feature = "neon_intrinsics", since = "1.59.0")
28978)]
28979#[cfg_attr(
28980 target_arch = "arm",
28981 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28982)]
28983pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28984 unsafe { simd_or(a, b) }
28985}
28986#[doc = "Vector bitwise or (immediate, inclusive)"]
28987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
28988#[inline]
28989#[target_feature(enable = "neon")]
28990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28991#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
28992#[cfg_attr(
28993 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28994 assert_instr(orr)
28995)]
28996#[cfg_attr(
28997 not(target_arch = "arm"),
28998 stable(feature = "neon_intrinsics", since = "1.59.0")
28999)]
29000#[cfg_attr(
29001 target_arch = "arm",
29002 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29003)]
29004pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
29005 unsafe { simd_or(a, b) }
29006}
29007#[doc = "Vector bitwise or (immediate, inclusive)"]
29008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
29009#[inline]
29010#[target_feature(enable = "neon")]
29011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
29013#[cfg_attr(
29014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29015 assert_instr(orr)
29016)]
29017#[cfg_attr(
29018 not(target_arch = "arm"),
29019 stable(feature = "neon_intrinsics", since = "1.59.0")
29020)]
29021#[cfg_attr(
29022 target_arch = "arm",
29023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29024)]
29025pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
29026 unsafe { simd_or(a, b) }
29027}
29028#[doc = "Vector bitwise or (immediate, inclusive)"]
29029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
29030#[inline]
29031#[target_feature(enable = "neon")]
29032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
29034#[cfg_attr(
29035 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29036 assert_instr(orr)
29037)]
29038#[cfg_attr(
29039 not(target_arch = "arm"),
29040 stable(feature = "neon_intrinsics", since = "1.59.0")
29041)]
29042#[cfg_attr(
29043 target_arch = "arm",
29044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29045)]
29046pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
29047 unsafe { simd_or(a, b) }
29048}
29049#[doc = "Vector bitwise or (immediate, inclusive)"]
29050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
29051#[inline]
29052#[target_feature(enable = "neon")]
29053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
29055#[cfg_attr(
29056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29057 assert_instr(orr)
29058)]
29059#[cfg_attr(
29060 not(target_arch = "arm"),
29061 stable(feature = "neon_intrinsics", since = "1.59.0")
29062)]
29063#[cfg_attr(
29064 target_arch = "arm",
29065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29066)]
29067pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
29068 unsafe { simd_or(a, b) }
29069}
29070#[doc = "Signed Add and Accumulate Long Pairwise."]
29071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
29072#[inline]
29073#[target_feature(enable = "neon")]
29074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29075#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
29076#[cfg_attr(
29077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29078 assert_instr(sadalp)
29079)]
29080#[cfg_attr(
29081 not(target_arch = "arm"),
29082 stable(feature = "neon_intrinsics", since = "1.59.0")
29083)]
29084#[cfg_attr(
29085 target_arch = "arm",
29086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29087)]
29088pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
29089 let x: int16x4_t;
29090 #[cfg(target_arch = "arm")]
29091 {
29092 x = priv_vpadal_s8(a, b);
29093 }
29094 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29095 unsafe {
29096 x = simd_add(vpaddl_s8(b), a);
29097 };
29098 x
29099}
29100#[doc = "Signed Add and Accumulate Long Pairwise."]
29101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
29102#[inline]
29103#[target_feature(enable = "neon")]
29104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29105#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
29106#[cfg_attr(
29107 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29108 assert_instr(sadalp)
29109)]
29110#[cfg_attr(
29111 not(target_arch = "arm"),
29112 stable(feature = "neon_intrinsics", since = "1.59.0")
29113)]
29114#[cfg_attr(
29115 target_arch = "arm",
29116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29117)]
29118pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
29119 let x: int16x8_t;
29120 #[cfg(target_arch = "arm")]
29121 {
29122 x = priv_vpadalq_s8(a, b);
29123 }
29124 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29125 unsafe {
29126 x = simd_add(vpaddlq_s8(b), a);
29127 };
29128 x
29129}
29130#[doc = "Signed Add and Accumulate Long Pairwise."]
29131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
29132#[inline]
29133#[target_feature(enable = "neon")]
29134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29135#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
29136#[cfg_attr(
29137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29138 assert_instr(sadalp)
29139)]
29140#[cfg_attr(
29141 not(target_arch = "arm"),
29142 stable(feature = "neon_intrinsics", since = "1.59.0")
29143)]
29144#[cfg_attr(
29145 target_arch = "arm",
29146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29147)]
29148pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
29149 let x: int32x2_t;
29150 #[cfg(target_arch = "arm")]
29151 {
29152 x = priv_vpadal_s16(a, b);
29153 }
29154 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29155 unsafe {
29156 x = simd_add(vpaddl_s16(b), a);
29157 };
29158 x
29159}
29160#[doc = "Signed Add and Accumulate Long Pairwise."]
29161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
29162#[inline]
29163#[target_feature(enable = "neon")]
29164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29165#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
29166#[cfg_attr(
29167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29168 assert_instr(sadalp)
29169)]
29170#[cfg_attr(
29171 not(target_arch = "arm"),
29172 stable(feature = "neon_intrinsics", since = "1.59.0")
29173)]
29174#[cfg_attr(
29175 target_arch = "arm",
29176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29177)]
29178pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
29179 let x: int32x4_t;
29180 #[cfg(target_arch = "arm")]
29181 {
29182 x = priv_vpadalq_s16(a, b);
29183 }
29184 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29185 unsafe {
29186 x = simd_add(vpaddlq_s16(b), a);
29187 };
29188 x
29189}
29190#[doc = "Signed Add and Accumulate Long Pairwise."]
29191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
29192#[inline]
29193#[target_feature(enable = "neon")]
29194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29195#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
29196#[cfg_attr(
29197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29198 assert_instr(sadalp)
29199)]
29200#[cfg_attr(
29201 not(target_arch = "arm"),
29202 stable(feature = "neon_intrinsics", since = "1.59.0")
29203)]
29204#[cfg_attr(
29205 target_arch = "arm",
29206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29207)]
29208pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
29209 let x: int64x1_t;
29210 #[cfg(target_arch = "arm")]
29211 {
29212 x = priv_vpadal_s32(a, b);
29213 }
29214 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29215 unsafe {
29216 x = simd_add(vpaddl_s32(b), a);
29217 };
29218 x
29219}
29220#[doc = "Signed Add and Accumulate Long Pairwise."]
29221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
29222#[inline]
29223#[target_feature(enable = "neon")]
29224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29225#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
29226#[cfg_attr(
29227 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29228 assert_instr(sadalp)
29229)]
29230#[cfg_attr(
29231 not(target_arch = "arm"),
29232 stable(feature = "neon_intrinsics", since = "1.59.0")
29233)]
29234#[cfg_attr(
29235 target_arch = "arm",
29236 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29237)]
29238pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
29239 let x: int64x2_t;
29240 #[cfg(target_arch = "arm")]
29241 {
29242 x = priv_vpadalq_s32(a, b);
29243 }
29244 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29245 unsafe {
29246 x = simd_add(vpaddlq_s32(b), a);
29247 };
29248 x
29249}
29250#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
29252#[inline]
29253#[target_feature(enable = "neon")]
29254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29255#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
29256#[cfg_attr(
29257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29258 assert_instr(uadalp)
29259)]
29260#[cfg_attr(
29261 not(target_arch = "arm"),
29262 stable(feature = "neon_intrinsics", since = "1.59.0")
29263)]
29264#[cfg_attr(
29265 target_arch = "arm",
29266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29267)]
29268pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
29269 let x: uint16x4_t;
29270 #[cfg(target_arch = "arm")]
29271 {
29272 x = priv_vpadal_u8(a, b);
29273 }
29274 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29275 unsafe {
29276 x = simd_add(vpaddl_u8(b), a);
29277 };
29278 x
29279}
29280#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
29282#[inline]
29283#[target_feature(enable = "neon")]
29284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29285#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
29286#[cfg_attr(
29287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29288 assert_instr(uadalp)
29289)]
29290#[cfg_attr(
29291 not(target_arch = "arm"),
29292 stable(feature = "neon_intrinsics", since = "1.59.0")
29293)]
29294#[cfg_attr(
29295 target_arch = "arm",
29296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29297)]
29298pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
29299 let x: uint16x8_t;
29300 #[cfg(target_arch = "arm")]
29301 {
29302 x = priv_vpadalq_u8(a, b);
29303 }
29304 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29305 unsafe {
29306 x = simd_add(vpaddlq_u8(b), a);
29307 };
29308 x
29309}
29310#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
29312#[inline]
29313#[target_feature(enable = "neon")]
29314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
29316#[cfg_attr(
29317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29318 assert_instr(uadalp)
29319)]
29320#[cfg_attr(
29321 not(target_arch = "arm"),
29322 stable(feature = "neon_intrinsics", since = "1.59.0")
29323)]
29324#[cfg_attr(
29325 target_arch = "arm",
29326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29327)]
29328pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
29329 let x: uint32x2_t;
29330 #[cfg(target_arch = "arm")]
29331 {
29332 x = priv_vpadal_u16(a, b);
29333 }
29334 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29335 unsafe {
29336 x = simd_add(vpaddl_u16(b), a);
29337 };
29338 x
29339}
29340#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
29342#[inline]
29343#[target_feature(enable = "neon")]
29344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29345#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
29346#[cfg_attr(
29347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29348 assert_instr(uadalp)
29349)]
29350#[cfg_attr(
29351 not(target_arch = "arm"),
29352 stable(feature = "neon_intrinsics", since = "1.59.0")
29353)]
29354#[cfg_attr(
29355 target_arch = "arm",
29356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29357)]
29358pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
29359 let x: uint32x4_t;
29360 #[cfg(target_arch = "arm")]
29361 {
29362 x = priv_vpadalq_u16(a, b);
29363 }
29364 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29365 unsafe {
29366 x = simd_add(vpaddlq_u16(b), a);
29367 };
29368 x
29369}
29370#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
29372#[inline]
29373#[target_feature(enable = "neon")]
29374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29375#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
29376#[cfg_attr(
29377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29378 assert_instr(uadalp)
29379)]
29380#[cfg_attr(
29381 not(target_arch = "arm"),
29382 stable(feature = "neon_intrinsics", since = "1.59.0")
29383)]
29384#[cfg_attr(
29385 target_arch = "arm",
29386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29387)]
29388pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
29389 let x: uint64x1_t;
29390 #[cfg(target_arch = "arm")]
29391 {
29392 x = priv_vpadal_u32(a, b);
29393 }
29394 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29395 unsafe {
29396 x = simd_add(vpaddl_u32(b), a);
29397 };
29398 x
29399}
29400#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
29402#[inline]
29403#[target_feature(enable = "neon")]
29404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29405#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
29406#[cfg_attr(
29407 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29408 assert_instr(uadalp)
29409)]
29410#[cfg_attr(
29411 not(target_arch = "arm"),
29412 stable(feature = "neon_intrinsics", since = "1.59.0")
29413)]
29414#[cfg_attr(
29415 target_arch = "arm",
29416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29417)]
29418pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
29419 let x: uint64x2_t;
29420 #[cfg(target_arch = "arm")]
29421 {
29422 x = priv_vpadalq_u32(a, b);
29423 }
29424 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
29425 unsafe {
29426 x = simd_add(vpaddlq_u32(b), a);
29427 };
29428 x
29429}
29430#[doc = "Floating-point add pairwise"]
29431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
29432#[inline]
29433#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
29434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29435#[cfg_attr(
29436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29437 assert_instr(faddp)
29438)]
29439#[target_feature(enable = "neon,fp16")]
29440#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
29441pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
29442 unsafe extern "unadjusted" {
29443 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")]
29444 #[cfg_attr(
29445 any(target_arch = "aarch64", target_arch = "arm64ec"),
29446 link_name = "llvm.aarch64.neon.faddp.v4f16"
29447 )]
29448 fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
29449 }
29450 unsafe { _vpadd_f16(a, b) }
29451}
29452#[doc = "Floating-point add pairwise"]
29453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
29454#[inline]
29455#[target_feature(enable = "neon")]
29456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29458#[cfg_attr(
29459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29460 assert_instr(faddp)
29461)]
29462#[cfg_attr(
29463 not(target_arch = "arm"),
29464 stable(feature = "neon_intrinsics", since = "1.59.0")
29465)]
29466#[cfg_attr(
29467 target_arch = "arm",
29468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29469)]
29470pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
29471 unsafe extern "unadjusted" {
29472 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")]
29473 #[cfg_attr(
29474 any(target_arch = "aarch64", target_arch = "arm64ec"),
29475 link_name = "llvm.aarch64.neon.faddp.v2f32"
29476 )]
29477 fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
29478 }
29479 unsafe { _vpadd_f32(a, b) }
29480}
29481#[doc = "Add pairwise."]
29482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
29483#[inline]
29484#[target_feature(enable = "neon")]
29485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29487#[cfg_attr(
29488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29489 assert_instr(addp)
29490)]
29491#[cfg_attr(
29492 not(target_arch = "arm"),
29493 stable(feature = "neon_intrinsics", since = "1.59.0")
29494)]
29495#[cfg_attr(
29496 target_arch = "arm",
29497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29498)]
29499pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
29500 unsafe extern "unadjusted" {
29501 #[cfg_attr(
29502 any(target_arch = "aarch64", target_arch = "arm64ec"),
29503 link_name = "llvm.aarch64.neon.addp.v8i8"
29504 )]
29505 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")]
29506 fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
29507 }
29508 unsafe { _vpadd_s8(a, b) }
29509}
29510#[doc = "Add pairwise."]
29511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
29512#[inline]
29513#[target_feature(enable = "neon")]
29514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29516#[cfg_attr(
29517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29518 assert_instr(addp)
29519)]
29520#[cfg_attr(
29521 not(target_arch = "arm"),
29522 stable(feature = "neon_intrinsics", since = "1.59.0")
29523)]
29524#[cfg_attr(
29525 target_arch = "arm",
29526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29527)]
29528pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
29529 unsafe extern "unadjusted" {
29530 #[cfg_attr(
29531 any(target_arch = "aarch64", target_arch = "arm64ec"),
29532 link_name = "llvm.aarch64.neon.addp.v4i16"
29533 )]
29534 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")]
29535 fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
29536 }
29537 unsafe { _vpadd_s16(a, b) }
29538}
29539#[doc = "Add pairwise."]
29540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
29541#[inline]
29542#[target_feature(enable = "neon")]
29543#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29544#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29545#[cfg_attr(
29546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29547 assert_instr(addp)
29548)]
29549#[cfg_attr(
29550 not(target_arch = "arm"),
29551 stable(feature = "neon_intrinsics", since = "1.59.0")
29552)]
29553#[cfg_attr(
29554 target_arch = "arm",
29555 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29556)]
29557pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
29558 unsafe extern "unadjusted" {
29559 #[cfg_attr(
29560 any(target_arch = "aarch64", target_arch = "arm64ec"),
29561 link_name = "llvm.aarch64.neon.addp.v2i32"
29562 )]
29563 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")]
29564 fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
29565 }
29566 unsafe { _vpadd_s32(a, b) }
29567}
29568#[doc = "Add pairwise."]
29569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
29570#[inline]
29571#[cfg(target_endian = "little")]
29572#[target_feature(enable = "neon")]
29573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29575#[cfg_attr(
29576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29577 assert_instr(addp)
29578)]
29579#[cfg_attr(
29580 not(target_arch = "arm"),
29581 stable(feature = "neon_intrinsics", since = "1.59.0")
29582)]
29583#[cfg_attr(
29584 target_arch = "arm",
29585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29586)]
29587pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
29588 unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) }
29589}
29590#[doc = "Add pairwise."]
29591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
29592#[inline]
29593#[cfg(target_endian = "big")]
29594#[target_feature(enable = "neon")]
29595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29597#[cfg_attr(
29598 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29599 assert_instr(addp)
29600)]
29601#[cfg_attr(
29602 not(target_arch = "arm"),
29603 stable(feature = "neon_intrinsics", since = "1.59.0")
29604)]
29605#[cfg_attr(
29606 target_arch = "arm",
29607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29608)]
29609pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
29610 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
29611 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
29612 unsafe {
29613 let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b)));
29614 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29615 }
29616}
29617#[doc = "Add pairwise."]
29618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
29619#[inline]
29620#[cfg(target_endian = "little")]
29621#[target_feature(enable = "neon")]
29622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29624#[cfg_attr(
29625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29626 assert_instr(addp)
29627)]
29628#[cfg_attr(
29629 not(target_arch = "arm"),
29630 stable(feature = "neon_intrinsics", since = "1.59.0")
29631)]
29632#[cfg_attr(
29633 target_arch = "arm",
29634 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29635)]
29636pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
29637 unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) }
29638}
29639#[doc = "Add pairwise."]
29640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
29641#[inline]
29642#[cfg(target_endian = "big")]
29643#[target_feature(enable = "neon")]
29644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29646#[cfg_attr(
29647 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29648 assert_instr(addp)
29649)]
29650#[cfg_attr(
29651 not(target_arch = "arm"),
29652 stable(feature = "neon_intrinsics", since = "1.59.0")
29653)]
29654#[cfg_attr(
29655 target_arch = "arm",
29656 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29657)]
29658pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
29659 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
29660 let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
29661 unsafe {
29662 let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b)));
29663 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29664 }
29665}
29666#[doc = "Add pairwise."]
29667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
29668#[inline]
29669#[cfg(target_endian = "little")]
29670#[target_feature(enable = "neon")]
29671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29673#[cfg_attr(
29674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29675 assert_instr(addp)
29676)]
29677#[cfg_attr(
29678 not(target_arch = "arm"),
29679 stable(feature = "neon_intrinsics", since = "1.59.0")
29680)]
29681#[cfg_attr(
29682 target_arch = "arm",
29683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29684)]
29685pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
29686 unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) }
29687}
29688#[doc = "Add pairwise."]
29689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
29690#[inline]
29691#[cfg(target_endian = "big")]
29692#[target_feature(enable = "neon")]
29693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
29695#[cfg_attr(
29696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29697 assert_instr(addp)
29698)]
29699#[cfg_attr(
29700 not(target_arch = "arm"),
29701 stable(feature = "neon_intrinsics", since = "1.59.0")
29702)]
29703#[cfg_attr(
29704 target_arch = "arm",
29705 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29706)]
29707pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
29708 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
29709 let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
29710 unsafe {
29711 let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b)));
29712 simd_shuffle!(ret_val, ret_val, [1, 0])
29713 }
29714}
29715#[doc = "Signed Add and Accumulate Long Pairwise."]
29716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
29717#[inline]
29718#[target_feature(enable = "neon")]
29719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29720#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
29721#[cfg_attr(
29722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29723 assert_instr(saddlp)
29724)]
29725#[cfg_attr(
29726 not(target_arch = "arm"),
29727 stable(feature = "neon_intrinsics", since = "1.59.0")
29728)]
29729#[cfg_attr(
29730 target_arch = "arm",
29731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29732)]
29733pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
29734 unsafe extern "unadjusted" {
29735 #[cfg_attr(
29736 any(target_arch = "aarch64", target_arch = "arm64ec"),
29737 link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8"
29738 )]
29739 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")]
29740 fn _vpaddl_s8(a: int8x8_t) -> int16x4_t;
29741 }
29742 unsafe { _vpaddl_s8(a) }
29743}
29744#[doc = "Signed Add and Accumulate Long Pairwise."]
29745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
29746#[inline]
29747#[target_feature(enable = "neon")]
29748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29749#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
29750#[cfg_attr(
29751 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29752 assert_instr(saddlp)
29753)]
29754#[cfg_attr(
29755 not(target_arch = "arm"),
29756 stable(feature = "neon_intrinsics", since = "1.59.0")
29757)]
29758#[cfg_attr(
29759 target_arch = "arm",
29760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29761)]
29762pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
29763 unsafe extern "unadjusted" {
29764 #[cfg_attr(
29765 any(target_arch = "aarch64", target_arch = "arm64ec"),
29766 link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8"
29767 )]
29768 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")]
29769 fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t;
29770 }
29771 unsafe { _vpaddlq_s8(a) }
29772}
29773#[doc = "Signed Add and Accumulate Long Pairwise."]
29774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
29775#[inline]
29776#[target_feature(enable = "neon")]
29777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
29779#[cfg_attr(
29780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29781 assert_instr(saddlp)
29782)]
29783#[cfg_attr(
29784 not(target_arch = "arm"),
29785 stable(feature = "neon_intrinsics", since = "1.59.0")
29786)]
29787#[cfg_attr(
29788 target_arch = "arm",
29789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29790)]
29791pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
29792 unsafe extern "unadjusted" {
29793 #[cfg_attr(
29794 any(target_arch = "aarch64", target_arch = "arm64ec"),
29795 link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16"
29796 )]
29797 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")]
29798 fn _vpaddl_s16(a: int16x4_t) -> int32x2_t;
29799 }
29800 unsafe { _vpaddl_s16(a) }
29801}
29802#[doc = "Signed Add and Accumulate Long Pairwise."]
29803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
29804#[inline]
29805#[target_feature(enable = "neon")]
29806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29807#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
29808#[cfg_attr(
29809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29810 assert_instr(saddlp)
29811)]
29812#[cfg_attr(
29813 not(target_arch = "arm"),
29814 stable(feature = "neon_intrinsics", since = "1.59.0")
29815)]
29816#[cfg_attr(
29817 target_arch = "arm",
29818 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29819)]
29820pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
29821 unsafe extern "unadjusted" {
29822 #[cfg_attr(
29823 any(target_arch = "aarch64", target_arch = "arm64ec"),
29824 link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16"
29825 )]
29826 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")]
29827 fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t;
29828 }
29829 unsafe { _vpaddlq_s16(a) }
29830}
29831#[doc = "Signed Add and Accumulate Long Pairwise."]
29832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
29833#[inline]
29834#[target_feature(enable = "neon")]
29835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29836#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
29837#[cfg_attr(
29838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29839 assert_instr(saddlp)
29840)]
29841#[cfg_attr(
29842 not(target_arch = "arm"),
29843 stable(feature = "neon_intrinsics", since = "1.59.0")
29844)]
29845#[cfg_attr(
29846 target_arch = "arm",
29847 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29848)]
29849pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
29850 unsafe extern "unadjusted" {
29851 #[cfg_attr(
29852 any(target_arch = "aarch64", target_arch = "arm64ec"),
29853 link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32"
29854 )]
29855 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")]
29856 fn _vpaddl_s32(a: int32x2_t) -> int64x1_t;
29857 }
29858 unsafe { _vpaddl_s32(a) }
29859}
29860#[doc = "Signed Add and Accumulate Long Pairwise."]
29861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
29862#[inline]
29863#[target_feature(enable = "neon")]
29864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29865#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
29866#[cfg_attr(
29867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29868 assert_instr(saddlp)
29869)]
29870#[cfg_attr(
29871 not(target_arch = "arm"),
29872 stable(feature = "neon_intrinsics", since = "1.59.0")
29873)]
29874#[cfg_attr(
29875 target_arch = "arm",
29876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29877)]
29878pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
29879 unsafe extern "unadjusted" {
29880 #[cfg_attr(
29881 any(target_arch = "aarch64", target_arch = "arm64ec"),
29882 link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32"
29883 )]
29884 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")]
29885 fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t;
29886 }
29887 unsafe { _vpaddlq_s32(a) }
29888}
29889#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
29891#[inline]
29892#[target_feature(enable = "neon")]
29893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
29895#[cfg_attr(
29896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29897 assert_instr(uaddlp)
29898)]
29899#[cfg_attr(
29900 not(target_arch = "arm"),
29901 stable(feature = "neon_intrinsics", since = "1.59.0")
29902)]
29903#[cfg_attr(
29904 target_arch = "arm",
29905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29906)]
29907pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
29908 unsafe extern "unadjusted" {
29909 #[cfg_attr(
29910 any(target_arch = "aarch64", target_arch = "arm64ec"),
29911 link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8"
29912 )]
29913 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")]
29914 fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t;
29915 }
29916 unsafe { _vpaddl_u8(a) }
29917}
29918#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
29920#[inline]
29921#[target_feature(enable = "neon")]
29922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29923#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
29924#[cfg_attr(
29925 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29926 assert_instr(uaddlp)
29927)]
29928#[cfg_attr(
29929 not(target_arch = "arm"),
29930 stable(feature = "neon_intrinsics", since = "1.59.0")
29931)]
29932#[cfg_attr(
29933 target_arch = "arm",
29934 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29935)]
29936pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
29937 unsafe extern "unadjusted" {
29938 #[cfg_attr(
29939 any(target_arch = "aarch64", target_arch = "arm64ec"),
29940 link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8"
29941 )]
29942 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")]
29943 fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t;
29944 }
29945 unsafe { _vpaddlq_u8(a) }
29946}
29947#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
29949#[inline]
29950#[target_feature(enable = "neon")]
29951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29952#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
29953#[cfg_attr(
29954 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29955 assert_instr(uaddlp)
29956)]
29957#[cfg_attr(
29958 not(target_arch = "arm"),
29959 stable(feature = "neon_intrinsics", since = "1.59.0")
29960)]
29961#[cfg_attr(
29962 target_arch = "arm",
29963 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29964)]
29965pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
29966 unsafe extern "unadjusted" {
29967 #[cfg_attr(
29968 any(target_arch = "aarch64", target_arch = "arm64ec"),
29969 link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16"
29970 )]
29971 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")]
29972 fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t;
29973 }
29974 unsafe { _vpaddl_u16(a) }
29975}
29976#[doc = "Unsigned Add and Accumulate Long Pairwise."]
29977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
29978#[inline]
29979#[target_feature(enable = "neon")]
29980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29981#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
29982#[cfg_attr(
29983 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29984 assert_instr(uaddlp)
29985)]
29986#[cfg_attr(
29987 not(target_arch = "arm"),
29988 stable(feature = "neon_intrinsics", since = "1.59.0")
29989)]
29990#[cfg_attr(
29991 target_arch = "arm",
29992 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29993)]
29994pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
29995 unsafe extern "unadjusted" {
29996 #[cfg_attr(
29997 any(target_arch = "aarch64", target_arch = "arm64ec"),
29998 link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16"
29999 )]
30000 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")]
30001 fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t;
30002 }
30003 unsafe { _vpaddlq_u16(a) }
30004}
30005#[doc = "Unsigned Add and Accumulate Long Pairwise."]
30006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
30007#[inline]
30008#[target_feature(enable = "neon")]
30009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30010#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
30011#[cfg_attr(
30012 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30013 assert_instr(uaddlp)
30014)]
30015#[cfg_attr(
30016 not(target_arch = "arm"),
30017 stable(feature = "neon_intrinsics", since = "1.59.0")
30018)]
30019#[cfg_attr(
30020 target_arch = "arm",
30021 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30022)]
30023pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
30024 unsafe extern "unadjusted" {
30025 #[cfg_attr(
30026 any(target_arch = "aarch64", target_arch = "arm64ec"),
30027 link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32"
30028 )]
30029 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")]
30030 fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t;
30031 }
30032 unsafe { _vpaddl_u32(a) }
30033}
30034#[doc = "Unsigned Add and Accumulate Long Pairwise."]
30035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
30036#[inline]
30037#[target_feature(enable = "neon")]
30038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30039#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
30040#[cfg_attr(
30041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30042 assert_instr(uaddlp)
30043)]
30044#[cfg_attr(
30045 not(target_arch = "arm"),
30046 stable(feature = "neon_intrinsics", since = "1.59.0")
30047)]
30048#[cfg_attr(
30049 target_arch = "arm",
30050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30051)]
30052pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
30053 unsafe extern "unadjusted" {
30054 #[cfg_attr(
30055 any(target_arch = "aarch64", target_arch = "arm64ec"),
30056 link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32"
30057 )]
30058 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")]
30059 fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t;
30060 }
30061 unsafe { _vpaddlq_u32(a) }
30062}
30063#[doc = "Folding maximum of adjacent pairs"]
30064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
30065#[inline]
30066#[target_feature(enable = "neon")]
30067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30069#[cfg_attr(
30070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30071 assert_instr(fmaxp)
30072)]
30073#[cfg_attr(
30074 not(target_arch = "arm"),
30075 stable(feature = "neon_intrinsics", since = "1.59.0")
30076)]
30077#[cfg_attr(
30078 target_arch = "arm",
30079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30080)]
30081pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
30082 unsafe extern "unadjusted" {
30083 #[cfg_attr(
30084 any(target_arch = "aarch64", target_arch = "arm64ec"),
30085 link_name = "llvm.aarch64.neon.fmaxp.v2f32"
30086 )]
30087 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
30088 fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
30089 }
30090 unsafe { _vpmax_f32(a, b) }
30091}
30092#[doc = "Folding maximum of adjacent pairs"]
30093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
30094#[inline]
30095#[target_feature(enable = "neon")]
30096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30098#[cfg_attr(
30099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30100 assert_instr(smaxp)
30101)]
30102#[cfg_attr(
30103 not(target_arch = "arm"),
30104 stable(feature = "neon_intrinsics", since = "1.59.0")
30105)]
30106#[cfg_attr(
30107 target_arch = "arm",
30108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30109)]
30110pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30111 unsafe extern "unadjusted" {
30112 #[cfg_attr(
30113 any(target_arch = "aarch64", target_arch = "arm64ec"),
30114 link_name = "llvm.aarch64.neon.smaxp.v8i8"
30115 )]
30116 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
30117 fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
30118 }
30119 unsafe { _vpmax_s8(a, b) }
30120}
30121#[doc = "Folding maximum of adjacent pairs"]
30122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
30123#[inline]
30124#[target_feature(enable = "neon")]
30125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30127#[cfg_attr(
30128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30129 assert_instr(smaxp)
30130)]
30131#[cfg_attr(
30132 not(target_arch = "arm"),
30133 stable(feature = "neon_intrinsics", since = "1.59.0")
30134)]
30135#[cfg_attr(
30136 target_arch = "arm",
30137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30138)]
30139pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30140 unsafe extern "unadjusted" {
30141 #[cfg_attr(
30142 any(target_arch = "aarch64", target_arch = "arm64ec"),
30143 link_name = "llvm.aarch64.neon.smaxp.v4i16"
30144 )]
30145 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
30146 fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
30147 }
30148 unsafe { _vpmax_s16(a, b) }
30149}
30150#[doc = "Folding maximum of adjacent pairs"]
30151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
30152#[inline]
30153#[target_feature(enable = "neon")]
30154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30156#[cfg_attr(
30157 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30158 assert_instr(smaxp)
30159)]
30160#[cfg_attr(
30161 not(target_arch = "arm"),
30162 stable(feature = "neon_intrinsics", since = "1.59.0")
30163)]
30164#[cfg_attr(
30165 target_arch = "arm",
30166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30167)]
30168pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
30169 unsafe extern "unadjusted" {
30170 #[cfg_attr(
30171 any(target_arch = "aarch64", target_arch = "arm64ec"),
30172 link_name = "llvm.aarch64.neon.smaxp.v2i32"
30173 )]
30174 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
30175 fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
30176 }
30177 unsafe { _vpmax_s32(a, b) }
30178}
30179#[doc = "Folding maximum of adjacent pairs"]
30180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
30181#[inline]
30182#[target_feature(enable = "neon")]
30183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30185#[cfg_attr(
30186 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30187 assert_instr(umaxp)
30188)]
30189#[cfg_attr(
30190 not(target_arch = "arm"),
30191 stable(feature = "neon_intrinsics", since = "1.59.0")
30192)]
30193#[cfg_attr(
30194 target_arch = "arm",
30195 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30196)]
30197pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
30198 unsafe extern "unadjusted" {
30199 #[cfg_attr(
30200 any(target_arch = "aarch64", target_arch = "arm64ec"),
30201 link_name = "llvm.aarch64.neon.umaxp.v8i8"
30202 )]
30203 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
30204 fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
30205 }
30206 unsafe { _vpmax_u8(a, b) }
30207}
30208#[doc = "Folding maximum of adjacent pairs"]
30209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
30210#[inline]
30211#[target_feature(enable = "neon")]
30212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30214#[cfg_attr(
30215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30216 assert_instr(umaxp)
30217)]
30218#[cfg_attr(
30219 not(target_arch = "arm"),
30220 stable(feature = "neon_intrinsics", since = "1.59.0")
30221)]
30222#[cfg_attr(
30223 target_arch = "arm",
30224 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30225)]
30226pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
30227 unsafe extern "unadjusted" {
30228 #[cfg_attr(
30229 any(target_arch = "aarch64", target_arch = "arm64ec"),
30230 link_name = "llvm.aarch64.neon.umaxp.v4i16"
30231 )]
30232 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
30233 fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
30234 }
30235 unsafe { _vpmax_u16(a, b) }
30236}
30237#[doc = "Folding maximum of adjacent pairs"]
30238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
30239#[inline]
30240#[target_feature(enable = "neon")]
30241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
30243#[cfg_attr(
30244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30245 assert_instr(umaxp)
30246)]
30247#[cfg_attr(
30248 not(target_arch = "arm"),
30249 stable(feature = "neon_intrinsics", since = "1.59.0")
30250)]
30251#[cfg_attr(
30252 target_arch = "arm",
30253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30254)]
30255pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
30256 unsafe extern "unadjusted" {
30257 #[cfg_attr(
30258 any(target_arch = "aarch64", target_arch = "arm64ec"),
30259 link_name = "llvm.aarch64.neon.umaxp.v2i32"
30260 )]
30261 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
30262 fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
30263 }
30264 unsafe { _vpmax_u32(a, b) }
30265}
30266#[doc = "Folding minimum of adjacent pairs"]
30267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
30268#[inline]
30269#[target_feature(enable = "neon")]
30270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30272#[cfg_attr(
30273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30274 assert_instr(fminp)
30275)]
30276#[cfg_attr(
30277 not(target_arch = "arm"),
30278 stable(feature = "neon_intrinsics", since = "1.59.0")
30279)]
30280#[cfg_attr(
30281 target_arch = "arm",
30282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30283)]
30284pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
30285 unsafe extern "unadjusted" {
30286 #[cfg_attr(
30287 any(target_arch = "aarch64", target_arch = "arm64ec"),
30288 link_name = "llvm.aarch64.neon.fminp.v2f32"
30289 )]
30290 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
30291 fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
30292 }
30293 unsafe { _vpmin_f32(a, b) }
30294}
30295#[doc = "Folding minimum of adjacent pairs"]
30296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
30297#[inline]
30298#[target_feature(enable = "neon")]
30299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30301#[cfg_attr(
30302 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30303 assert_instr(sminp)
30304)]
30305#[cfg_attr(
30306 not(target_arch = "arm"),
30307 stable(feature = "neon_intrinsics", since = "1.59.0")
30308)]
30309#[cfg_attr(
30310 target_arch = "arm",
30311 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30312)]
30313pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30314 unsafe extern "unadjusted" {
30315 #[cfg_attr(
30316 any(target_arch = "aarch64", target_arch = "arm64ec"),
30317 link_name = "llvm.aarch64.neon.sminp.v8i8"
30318 )]
30319 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
30320 fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
30321 }
30322 unsafe { _vpmin_s8(a, b) }
30323}
30324#[doc = "Folding minimum of adjacent pairs"]
30325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
30326#[inline]
30327#[target_feature(enable = "neon")]
30328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30330#[cfg_attr(
30331 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30332 assert_instr(sminp)
30333)]
30334#[cfg_attr(
30335 not(target_arch = "arm"),
30336 stable(feature = "neon_intrinsics", since = "1.59.0")
30337)]
30338#[cfg_attr(
30339 target_arch = "arm",
30340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30341)]
30342pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30343 unsafe extern "unadjusted" {
30344 #[cfg_attr(
30345 any(target_arch = "aarch64", target_arch = "arm64ec"),
30346 link_name = "llvm.aarch64.neon.sminp.v4i16"
30347 )]
30348 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
30349 fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
30350 }
30351 unsafe { _vpmin_s16(a, b) }
30352}
30353#[doc = "Folding minimum of adjacent pairs"]
30354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
30355#[inline]
30356#[target_feature(enable = "neon")]
30357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30359#[cfg_attr(
30360 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30361 assert_instr(sminp)
30362)]
30363#[cfg_attr(
30364 not(target_arch = "arm"),
30365 stable(feature = "neon_intrinsics", since = "1.59.0")
30366)]
30367#[cfg_attr(
30368 target_arch = "arm",
30369 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30370)]
30371pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
30372 unsafe extern "unadjusted" {
30373 #[cfg_attr(
30374 any(target_arch = "aarch64", target_arch = "arm64ec"),
30375 link_name = "llvm.aarch64.neon.sminp.v2i32"
30376 )]
30377 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
30378 fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
30379 }
30380 unsafe { _vpmin_s32(a, b) }
30381}
30382#[doc = "Folding minimum of adjacent pairs"]
30383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
30384#[inline]
30385#[target_feature(enable = "neon")]
30386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30388#[cfg_attr(
30389 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30390 assert_instr(uminp)
30391)]
30392#[cfg_attr(
30393 not(target_arch = "arm"),
30394 stable(feature = "neon_intrinsics", since = "1.59.0")
30395)]
30396#[cfg_attr(
30397 target_arch = "arm",
30398 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30399)]
30400pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
30401 unsafe extern "unadjusted" {
30402 #[cfg_attr(
30403 any(target_arch = "aarch64", target_arch = "arm64ec"),
30404 link_name = "llvm.aarch64.neon.uminp.v8i8"
30405 )]
30406 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
30407 fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
30408 }
30409 unsafe { _vpmin_u8(a, b) }
30410}
30411#[doc = "Folding minimum of adjacent pairs"]
30412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
30413#[inline]
30414#[target_feature(enable = "neon")]
30415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30417#[cfg_attr(
30418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30419 assert_instr(uminp)
30420)]
30421#[cfg_attr(
30422 not(target_arch = "arm"),
30423 stable(feature = "neon_intrinsics", since = "1.59.0")
30424)]
30425#[cfg_attr(
30426 target_arch = "arm",
30427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30428)]
30429pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
30430 unsafe extern "unadjusted" {
30431 #[cfg_attr(
30432 any(target_arch = "aarch64", target_arch = "arm64ec"),
30433 link_name = "llvm.aarch64.neon.uminp.v4i16"
30434 )]
30435 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
30436 fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
30437 }
30438 unsafe { _vpmin_u16(a, b) }
30439}
30440#[doc = "Folding minimum of adjacent pairs"]
30441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
30442#[inline]
30443#[target_feature(enable = "neon")]
30444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
30446#[cfg_attr(
30447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30448 assert_instr(uminp)
30449)]
30450#[cfg_attr(
30451 not(target_arch = "arm"),
30452 stable(feature = "neon_intrinsics", since = "1.59.0")
30453)]
30454#[cfg_attr(
30455 target_arch = "arm",
30456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30457)]
30458pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
30459 unsafe extern "unadjusted" {
30460 #[cfg_attr(
30461 any(target_arch = "aarch64", target_arch = "arm64ec"),
30462 link_name = "llvm.aarch64.neon.uminp.v2i32"
30463 )]
30464 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
30465 fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
30466 }
30467 unsafe { _vpmin_u32(a, b) }
30468}
30469#[doc = "Signed saturating Absolute value"]
30470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
30471#[inline]
30472#[target_feature(enable = "neon")]
30473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30474#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
30475#[cfg_attr(
30476 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30477 assert_instr(sqabs)
30478)]
30479#[cfg_attr(
30480 not(target_arch = "arm"),
30481 stable(feature = "neon_intrinsics", since = "1.59.0")
30482)]
30483#[cfg_attr(
30484 target_arch = "arm",
30485 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30486)]
30487pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
30488 unsafe extern "unadjusted" {
30489 #[cfg_attr(
30490 any(target_arch = "aarch64", target_arch = "arm64ec"),
30491 link_name = "llvm.aarch64.neon.sqabs.v8i8"
30492 )]
30493 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")]
30494 fn _vqabs_s8(a: int8x8_t) -> int8x8_t;
30495 }
30496 unsafe { _vqabs_s8(a) }
30497}
30498#[doc = "Signed saturating Absolute value"]
30499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
30500#[inline]
30501#[target_feature(enable = "neon")]
30502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
30504#[cfg_attr(
30505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30506 assert_instr(sqabs)
30507)]
30508#[cfg_attr(
30509 not(target_arch = "arm"),
30510 stable(feature = "neon_intrinsics", since = "1.59.0")
30511)]
30512#[cfg_attr(
30513 target_arch = "arm",
30514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30515)]
30516pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
30517 unsafe extern "unadjusted" {
30518 #[cfg_attr(
30519 any(target_arch = "aarch64", target_arch = "arm64ec"),
30520 link_name = "llvm.aarch64.neon.sqabs.v16i8"
30521 )]
30522 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")]
30523 fn _vqabsq_s8(a: int8x16_t) -> int8x16_t;
30524 }
30525 unsafe { _vqabsq_s8(a) }
30526}
30527#[doc = "Signed saturating Absolute value"]
30528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
30529#[inline]
30530#[target_feature(enable = "neon")]
30531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30532#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
30533#[cfg_attr(
30534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30535 assert_instr(sqabs)
30536)]
30537#[cfg_attr(
30538 not(target_arch = "arm"),
30539 stable(feature = "neon_intrinsics", since = "1.59.0")
30540)]
30541#[cfg_attr(
30542 target_arch = "arm",
30543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30544)]
30545pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
30546 unsafe extern "unadjusted" {
30547 #[cfg_attr(
30548 any(target_arch = "aarch64", target_arch = "arm64ec"),
30549 link_name = "llvm.aarch64.neon.sqabs.v4i16"
30550 )]
30551 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")]
30552 fn _vqabs_s16(a: int16x4_t) -> int16x4_t;
30553 }
30554 unsafe { _vqabs_s16(a) }
30555}
30556#[doc = "Signed saturating Absolute value"]
30557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
30558#[inline]
30559#[target_feature(enable = "neon")]
30560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30561#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
30562#[cfg_attr(
30563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30564 assert_instr(sqabs)
30565)]
30566#[cfg_attr(
30567 not(target_arch = "arm"),
30568 stable(feature = "neon_intrinsics", since = "1.59.0")
30569)]
30570#[cfg_attr(
30571 target_arch = "arm",
30572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30573)]
30574pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
30575 unsafe extern "unadjusted" {
30576 #[cfg_attr(
30577 any(target_arch = "aarch64", target_arch = "arm64ec"),
30578 link_name = "llvm.aarch64.neon.sqabs.v8i16"
30579 )]
30580 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")]
30581 fn _vqabsq_s16(a: int16x8_t) -> int16x8_t;
30582 }
30583 unsafe { _vqabsq_s16(a) }
30584}
30585#[doc = "Signed saturating Absolute value"]
30586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
30587#[inline]
30588#[target_feature(enable = "neon")]
30589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30590#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
30591#[cfg_attr(
30592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30593 assert_instr(sqabs)
30594)]
30595#[cfg_attr(
30596 not(target_arch = "arm"),
30597 stable(feature = "neon_intrinsics", since = "1.59.0")
30598)]
30599#[cfg_attr(
30600 target_arch = "arm",
30601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30602)]
30603pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
30604 unsafe extern "unadjusted" {
30605 #[cfg_attr(
30606 any(target_arch = "aarch64", target_arch = "arm64ec"),
30607 link_name = "llvm.aarch64.neon.sqabs.v2i32"
30608 )]
30609 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")]
30610 fn _vqabs_s32(a: int32x2_t) -> int32x2_t;
30611 }
30612 unsafe { _vqabs_s32(a) }
30613}
30614#[doc = "Signed saturating Absolute value"]
30615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
30616#[inline]
30617#[target_feature(enable = "neon")]
30618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30619#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
30620#[cfg_attr(
30621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30622 assert_instr(sqabs)
30623)]
30624#[cfg_attr(
30625 not(target_arch = "arm"),
30626 stable(feature = "neon_intrinsics", since = "1.59.0")
30627)]
30628#[cfg_attr(
30629 target_arch = "arm",
30630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30631)]
30632pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
30633 unsafe extern "unadjusted" {
30634 #[cfg_attr(
30635 any(target_arch = "aarch64", target_arch = "arm64ec"),
30636 link_name = "llvm.aarch64.neon.sqabs.v4i32"
30637 )]
30638 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")]
30639 fn _vqabsq_s32(a: int32x4_t) -> int32x4_t;
30640 }
30641 unsafe { _vqabsq_s32(a) }
30642}
30643#[doc = "Saturating add"]
30644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
30645#[inline]
30646#[target_feature(enable = "neon")]
30647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30648#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
30649#[cfg_attr(
30650 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30651 assert_instr(sqadd)
30652)]
30653#[cfg_attr(
30654 not(target_arch = "arm"),
30655 stable(feature = "neon_intrinsics", since = "1.59.0")
30656)]
30657#[cfg_attr(
30658 target_arch = "arm",
30659 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30660)]
30661pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30662 unsafe extern "unadjusted" {
30663 #[cfg_attr(
30664 any(target_arch = "aarch64", target_arch = "arm64ec"),
30665 link_name = "llvm.aarch64.neon.sqadd.v8i8"
30666 )]
30667 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")]
30668 fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
30669 }
30670 unsafe { _vqadd_s8(a, b) }
30671}
30672#[doc = "Saturating add"]
30673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
30674#[inline]
30675#[target_feature(enable = "neon")]
30676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30677#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
30678#[cfg_attr(
30679 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30680 assert_instr(sqadd)
30681)]
30682#[cfg_attr(
30683 not(target_arch = "arm"),
30684 stable(feature = "neon_intrinsics", since = "1.59.0")
30685)]
30686#[cfg_attr(
30687 target_arch = "arm",
30688 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30689)]
30690pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
30691 unsafe extern "unadjusted" {
30692 #[cfg_attr(
30693 any(target_arch = "aarch64", target_arch = "arm64ec"),
30694 link_name = "llvm.aarch64.neon.sqadd.v16i8"
30695 )]
30696 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")]
30697 fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
30698 }
30699 unsafe { _vqaddq_s8(a, b) }
30700}
30701#[doc = "Saturating add"]
30702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
30703#[inline]
30704#[target_feature(enable = "neon")]
30705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
30707#[cfg_attr(
30708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30709 assert_instr(sqadd)
30710)]
30711#[cfg_attr(
30712 not(target_arch = "arm"),
30713 stable(feature = "neon_intrinsics", since = "1.59.0")
30714)]
30715#[cfg_attr(
30716 target_arch = "arm",
30717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30718)]
30719pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30720 unsafe extern "unadjusted" {
30721 #[cfg_attr(
30722 any(target_arch = "aarch64", target_arch = "arm64ec"),
30723 link_name = "llvm.aarch64.neon.sqadd.v4i16"
30724 )]
30725 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")]
30726 fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
30727 }
30728 unsafe { _vqadd_s16(a, b) }
30729}
30730#[doc = "Saturating add"]
30731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
30732#[inline]
30733#[target_feature(enable = "neon")]
30734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30735#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
30736#[cfg_attr(
30737 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30738 assert_instr(sqadd)
30739)]
30740#[cfg_attr(
30741 not(target_arch = "arm"),
30742 stable(feature = "neon_intrinsics", since = "1.59.0")
30743)]
30744#[cfg_attr(
30745 target_arch = "arm",
30746 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30747)]
30748pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
30749 unsafe extern "unadjusted" {
30750 #[cfg_attr(
30751 any(target_arch = "aarch64", target_arch = "arm64ec"),
30752 link_name = "llvm.aarch64.neon.sqadd.v8i16"
30753 )]
30754 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")]
30755 fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
30756 }
30757 unsafe { _vqaddq_s16(a, b) }
30758}
30759#[doc = "Saturating add"]
30760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
30761#[inline]
30762#[target_feature(enable = "neon")]
30763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30764#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
30765#[cfg_attr(
30766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30767 assert_instr(sqadd)
30768)]
30769#[cfg_attr(
30770 not(target_arch = "arm"),
30771 stable(feature = "neon_intrinsics", since = "1.59.0")
30772)]
30773#[cfg_attr(
30774 target_arch = "arm",
30775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30776)]
30777pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
30778 unsafe extern "unadjusted" {
30779 #[cfg_attr(
30780 any(target_arch = "aarch64", target_arch = "arm64ec"),
30781 link_name = "llvm.aarch64.neon.sqadd.v2i32"
30782 )]
30783 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")]
30784 fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
30785 }
30786 unsafe { _vqadd_s32(a, b) }
30787}
30788#[doc = "Saturating add"]
30789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
30790#[inline]
30791#[target_feature(enable = "neon")]
30792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30793#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
30794#[cfg_attr(
30795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30796 assert_instr(sqadd)
30797)]
30798#[cfg_attr(
30799 not(target_arch = "arm"),
30800 stable(feature = "neon_intrinsics", since = "1.59.0")
30801)]
30802#[cfg_attr(
30803 target_arch = "arm",
30804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30805)]
30806pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
30807 unsafe extern "unadjusted" {
30808 #[cfg_attr(
30809 any(target_arch = "aarch64", target_arch = "arm64ec"),
30810 link_name = "llvm.aarch64.neon.sqadd.v4i32"
30811 )]
30812 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")]
30813 fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
30814 }
30815 unsafe { _vqaddq_s32(a, b) }
30816}
30817#[doc = "Saturating add"]
30818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
30819#[inline]
30820#[target_feature(enable = "neon")]
30821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30822#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
30823#[cfg_attr(
30824 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30825 assert_instr(sqadd)
30826)]
30827#[cfg_attr(
30828 not(target_arch = "arm"),
30829 stable(feature = "neon_intrinsics", since = "1.59.0")
30830)]
30831#[cfg_attr(
30832 target_arch = "arm",
30833 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30834)]
30835pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
30836 unsafe extern "unadjusted" {
30837 #[cfg_attr(
30838 any(target_arch = "aarch64", target_arch = "arm64ec"),
30839 link_name = "llvm.aarch64.neon.sqadd.v1i64"
30840 )]
30841 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")]
30842 fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
30843 }
30844 unsafe { _vqadd_s64(a, b) }
30845}
30846#[doc = "Saturating add"]
30847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
30848#[inline]
30849#[target_feature(enable = "neon")]
30850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30851#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
30852#[cfg_attr(
30853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30854 assert_instr(sqadd)
30855)]
30856#[cfg_attr(
30857 not(target_arch = "arm"),
30858 stable(feature = "neon_intrinsics", since = "1.59.0")
30859)]
30860#[cfg_attr(
30861 target_arch = "arm",
30862 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30863)]
30864pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
30865 unsafe extern "unadjusted" {
30866 #[cfg_attr(
30867 any(target_arch = "aarch64", target_arch = "arm64ec"),
30868 link_name = "llvm.aarch64.neon.sqadd.v2i64"
30869 )]
30870 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")]
30871 fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
30872 }
30873 unsafe { _vqaddq_s64(a, b) }
30874}
30875#[doc = "Saturating add"]
30876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
30877#[inline]
30878#[target_feature(enable = "neon")]
30879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30880#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
30881#[cfg_attr(
30882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30883 assert_instr(uqadd)
30884)]
30885#[cfg_attr(
30886 not(target_arch = "arm"),
30887 stable(feature = "neon_intrinsics", since = "1.59.0")
30888)]
30889#[cfg_attr(
30890 target_arch = "arm",
30891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30892)]
30893pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
30894 unsafe extern "unadjusted" {
30895 #[cfg_attr(
30896 any(target_arch = "aarch64", target_arch = "arm64ec"),
30897 link_name = "llvm.aarch64.neon.uqadd.v8i8"
30898 )]
30899 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")]
30900 fn _vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
30901 }
30902 unsafe { _vqadd_u8(a, b) }
30903}
30904#[doc = "Saturating add"]
30905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
30906#[inline]
30907#[target_feature(enable = "neon")]
30908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30909#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
30910#[cfg_attr(
30911 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30912 assert_instr(uqadd)
30913)]
30914#[cfg_attr(
30915 not(target_arch = "arm"),
30916 stable(feature = "neon_intrinsics", since = "1.59.0")
30917)]
30918#[cfg_attr(
30919 target_arch = "arm",
30920 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30921)]
30922pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
30923 unsafe extern "unadjusted" {
30924 #[cfg_attr(
30925 any(target_arch = "aarch64", target_arch = "arm64ec"),
30926 link_name = "llvm.aarch64.neon.uqadd.v16i8"
30927 )]
30928 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")]
30929 fn _vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
30930 }
30931 unsafe { _vqaddq_u8(a, b) }
30932}
30933#[doc = "Saturating add"]
30934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
30935#[inline]
30936#[target_feature(enable = "neon")]
30937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30938#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
30939#[cfg_attr(
30940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30941 assert_instr(uqadd)
30942)]
30943#[cfg_attr(
30944 not(target_arch = "arm"),
30945 stable(feature = "neon_intrinsics", since = "1.59.0")
30946)]
30947#[cfg_attr(
30948 target_arch = "arm",
30949 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30950)]
30951pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
30952 unsafe extern "unadjusted" {
30953 #[cfg_attr(
30954 any(target_arch = "aarch64", target_arch = "arm64ec"),
30955 link_name = "llvm.aarch64.neon.uqadd.v4i16"
30956 )]
30957 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")]
30958 fn _vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
30959 }
30960 unsafe { _vqadd_u16(a, b) }
30961}
30962#[doc = "Saturating add"]
30963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
30964#[inline]
30965#[target_feature(enable = "neon")]
30966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30967#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
30968#[cfg_attr(
30969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30970 assert_instr(uqadd)
30971)]
30972#[cfg_attr(
30973 not(target_arch = "arm"),
30974 stable(feature = "neon_intrinsics", since = "1.59.0")
30975)]
30976#[cfg_attr(
30977 target_arch = "arm",
30978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30979)]
30980pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
30981 unsafe extern "unadjusted" {
30982 #[cfg_attr(
30983 any(target_arch = "aarch64", target_arch = "arm64ec"),
30984 link_name = "llvm.aarch64.neon.uqadd.v8i16"
30985 )]
30986 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")]
30987 fn _vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
30988 }
30989 unsafe { _vqaddq_u16(a, b) }
30990}
30991#[doc = "Saturating add"]
30992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
30993#[inline]
30994#[target_feature(enable = "neon")]
30995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30996#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
30997#[cfg_attr(
30998 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30999 assert_instr(uqadd)
31000)]
31001#[cfg_attr(
31002 not(target_arch = "arm"),
31003 stable(feature = "neon_intrinsics", since = "1.59.0")
31004)]
31005#[cfg_attr(
31006 target_arch = "arm",
31007 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31008)]
31009pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
31010 unsafe extern "unadjusted" {
31011 #[cfg_attr(
31012 any(target_arch = "aarch64", target_arch = "arm64ec"),
31013 link_name = "llvm.aarch64.neon.uqadd.v2i32"
31014 )]
31015 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")]
31016 fn _vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
31017 }
31018 unsafe { _vqadd_u32(a, b) }
31019}
31020#[doc = "Saturating add"]
31021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
31022#[inline]
31023#[target_feature(enable = "neon")]
31024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31025#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
31026#[cfg_attr(
31027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31028 assert_instr(uqadd)
31029)]
31030#[cfg_attr(
31031 not(target_arch = "arm"),
31032 stable(feature = "neon_intrinsics", since = "1.59.0")
31033)]
31034#[cfg_attr(
31035 target_arch = "arm",
31036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31037)]
31038pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
31039 unsafe extern "unadjusted" {
31040 #[cfg_attr(
31041 any(target_arch = "aarch64", target_arch = "arm64ec"),
31042 link_name = "llvm.aarch64.neon.uqadd.v4i32"
31043 )]
31044 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")]
31045 fn _vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
31046 }
31047 unsafe { _vqaddq_u32(a, b) }
31048}
31049#[doc = "Saturating add"]
31050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
31051#[inline]
31052#[target_feature(enable = "neon")]
31053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31054#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
31055#[cfg_attr(
31056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31057 assert_instr(uqadd)
31058)]
31059#[cfg_attr(
31060 not(target_arch = "arm"),
31061 stable(feature = "neon_intrinsics", since = "1.59.0")
31062)]
31063#[cfg_attr(
31064 target_arch = "arm",
31065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31066)]
31067pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
31068 unsafe extern "unadjusted" {
31069 #[cfg_attr(
31070 any(target_arch = "aarch64", target_arch = "arm64ec"),
31071 link_name = "llvm.aarch64.neon.uqadd.v1i64"
31072 )]
31073 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")]
31074 fn _vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
31075 }
31076 unsafe { _vqadd_u64(a, b) }
31077}
31078#[doc = "Saturating add"]
31079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
31080#[inline]
31081#[target_feature(enable = "neon")]
31082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31083#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
31084#[cfg_attr(
31085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31086 assert_instr(uqadd)
31087)]
31088#[cfg_attr(
31089 not(target_arch = "arm"),
31090 stable(feature = "neon_intrinsics", since = "1.59.0")
31091)]
31092#[cfg_attr(
31093 target_arch = "arm",
31094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31095)]
31096pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
31097 unsafe extern "unadjusted" {
31098 #[cfg_attr(
31099 any(target_arch = "aarch64", target_arch = "arm64ec"),
31100 link_name = "llvm.aarch64.neon.uqadd.v2i64"
31101 )]
31102 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")]
31103 fn _vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
31104 }
31105 unsafe { _vqaddq_u64(a, b) }
31106}
31107#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
31108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
31109#[inline]
31110#[target_feature(enable = "neon")]
31111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
31113#[cfg_attr(
31114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31115 assert_instr(sqdmlal, N = 2)
31116)]
31117#[rustc_legacy_const_generics(3)]
31118#[cfg_attr(
31119 not(target_arch = "arm"),
31120 stable(feature = "neon_intrinsics", since = "1.59.0")
31121)]
31122#[cfg_attr(
31123 target_arch = "arm",
31124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31125)]
31126pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31127 static_assert_uimm_bits!(N, 2);
31128 vqaddq_s32(a, vqdmull_lane_s16::<N>(b, c))
31129}
31130#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
31131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
31132#[inline]
31133#[target_feature(enable = "neon")]
31134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
31136#[cfg_attr(
31137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31138 assert_instr(sqdmlal, N = 1)
31139)]
31140#[rustc_legacy_const_generics(3)]
31141#[cfg_attr(
31142 not(target_arch = "arm"),
31143 stable(feature = "neon_intrinsics", since = "1.59.0")
31144)]
31145#[cfg_attr(
31146 target_arch = "arm",
31147 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31148)]
31149pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31150 static_assert_uimm_bits!(N, 1);
31151 vqaddq_s64(a, vqdmull_lane_s32::<N>(b, c))
31152}
31153#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
31154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
31155#[inline]
31156#[target_feature(enable = "neon")]
31157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
31159#[cfg_attr(
31160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31161 assert_instr(sqdmlal)
31162)]
31163#[cfg_attr(
31164 not(target_arch = "arm"),
31165 stable(feature = "neon_intrinsics", since = "1.59.0")
31166)]
31167#[cfg_attr(
31168 target_arch = "arm",
31169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31170)]
31171pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
31172 vqaddq_s32(a, vqdmull_n_s16(b, c))
31173}
31174#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
31175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
31176#[inline]
31177#[target_feature(enable = "neon")]
31178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
31180#[cfg_attr(
31181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31182 assert_instr(sqdmlal)
31183)]
31184#[cfg_attr(
31185 not(target_arch = "arm"),
31186 stable(feature = "neon_intrinsics", since = "1.59.0")
31187)]
31188#[cfg_attr(
31189 target_arch = "arm",
31190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31191)]
31192pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
31193 vqaddq_s64(a, vqdmull_n_s32(b, c))
31194}
31195#[doc = "Signed saturating doubling multiply-add long"]
31196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
31197#[inline]
31198#[target_feature(enable = "neon")]
31199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
31201#[cfg_attr(
31202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31203 assert_instr(sqdmlal)
31204)]
31205#[cfg_attr(
31206 not(target_arch = "arm"),
31207 stable(feature = "neon_intrinsics", since = "1.59.0")
31208)]
31209#[cfg_attr(
31210 target_arch = "arm",
31211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31212)]
31213pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31214 vqaddq_s32(a, vqdmull_s16(b, c))
31215}
31216#[doc = "Signed saturating doubling multiply-add long"]
31217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
31218#[inline]
31219#[target_feature(enable = "neon")]
31220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
31222#[cfg_attr(
31223 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31224 assert_instr(sqdmlal)
31225)]
31226#[cfg_attr(
31227 not(target_arch = "arm"),
31228 stable(feature = "neon_intrinsics", since = "1.59.0")
31229)]
31230#[cfg_attr(
31231 target_arch = "arm",
31232 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31233)]
31234pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31235 vqaddq_s64(a, vqdmull_s32(b, c))
31236}
31237#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
31238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
31239#[inline]
31240#[target_feature(enable = "neon")]
31241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
31243#[cfg_attr(
31244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31245 assert_instr(sqdmlsl, N = 2)
31246)]
31247#[rustc_legacy_const_generics(3)]
31248#[cfg_attr(
31249 not(target_arch = "arm"),
31250 stable(feature = "neon_intrinsics", since = "1.59.0")
31251)]
31252#[cfg_attr(
31253 target_arch = "arm",
31254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31255)]
31256pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31257 static_assert_uimm_bits!(N, 2);
31258 vqsubq_s32(a, vqdmull_lane_s16::<N>(b, c))
31259}
31260#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
31261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
31262#[inline]
31263#[target_feature(enable = "neon")]
31264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
31266#[cfg_attr(
31267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31268 assert_instr(sqdmlsl, N = 1)
31269)]
31270#[rustc_legacy_const_generics(3)]
31271#[cfg_attr(
31272 not(target_arch = "arm"),
31273 stable(feature = "neon_intrinsics", since = "1.59.0")
31274)]
31275#[cfg_attr(
31276 target_arch = "arm",
31277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31278)]
31279pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31280 static_assert_uimm_bits!(N, 1);
31281 vqsubq_s64(a, vqdmull_lane_s32::<N>(b, c))
31282}
31283#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
31284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
31285#[inline]
31286#[target_feature(enable = "neon")]
31287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
31289#[cfg_attr(
31290 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31291 assert_instr(sqdmlsl)
31292)]
31293#[cfg_attr(
31294 not(target_arch = "arm"),
31295 stable(feature = "neon_intrinsics", since = "1.59.0")
31296)]
31297#[cfg_attr(
31298 target_arch = "arm",
31299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31300)]
31301pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
31302 vqsubq_s32(a, vqdmull_n_s16(b, c))
31303}
31304#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
31305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
31306#[inline]
31307#[target_feature(enable = "neon")]
31308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
31310#[cfg_attr(
31311 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31312 assert_instr(sqdmlsl)
31313)]
31314#[cfg_attr(
31315 not(target_arch = "arm"),
31316 stable(feature = "neon_intrinsics", since = "1.59.0")
31317)]
31318#[cfg_attr(
31319 target_arch = "arm",
31320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31321)]
31322pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
31323 vqsubq_s64(a, vqdmull_n_s32(b, c))
31324}
31325#[doc = "Signed saturating doubling multiply-subtract long"]
31326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
31327#[inline]
31328#[target_feature(enable = "neon")]
31329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
31331#[cfg_attr(
31332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31333 assert_instr(sqdmlsl)
31334)]
31335#[cfg_attr(
31336 not(target_arch = "arm"),
31337 stable(feature = "neon_intrinsics", since = "1.59.0")
31338)]
31339#[cfg_attr(
31340 target_arch = "arm",
31341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31342)]
31343pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31344 vqsubq_s32(a, vqdmull_s16(b, c))
31345}
31346#[doc = "Signed saturating doubling multiply-subtract long"]
31347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
31348#[inline]
31349#[target_feature(enable = "neon")]
31350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
31352#[cfg_attr(
31353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31354 assert_instr(sqdmlsl)
31355)]
31356#[cfg_attr(
31357 not(target_arch = "arm"),
31358 stable(feature = "neon_intrinsics", since = "1.59.0")
31359)]
31360#[cfg_attr(
31361 target_arch = "arm",
31362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31363)]
31364pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31365 vqsubq_s64(a, vqdmull_s32(b, c))
31366}
31367#[doc = "Vector saturating doubling multiply high by scalar"]
31368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
31369#[inline]
31370#[target_feature(enable = "neon")]
31371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
31373#[cfg_attr(
31374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31375 assert_instr(sqdmulh, LANE = 0)
31376)]
31377#[rustc_legacy_const_generics(2)]
31378#[cfg_attr(
31379 not(target_arch = "arm"),
31380 stable(feature = "neon_intrinsics", since = "1.59.0")
31381)]
31382#[cfg_attr(
31383 target_arch = "arm",
31384 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31385)]
31386pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
31387 static_assert_uimm_bits!(LANE, 3);
31388 unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
31389}
31390#[doc = "Vector saturating doubling multiply high by scalar"]
31391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
31392#[inline]
31393#[target_feature(enable = "neon")]
31394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
31396#[cfg_attr(
31397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31398 assert_instr(sqdmulh, LANE = 0)
31399)]
31400#[rustc_legacy_const_generics(2)]
31401#[cfg_attr(
31402 not(target_arch = "arm"),
31403 stable(feature = "neon_intrinsics", since = "1.59.0")
31404)]
31405#[cfg_attr(
31406 target_arch = "arm",
31407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31408)]
31409pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
31410 static_assert_uimm_bits!(LANE, 3);
31411 unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
31412}
31413#[doc = "Vector saturating doubling multiply high by scalar"]
31414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
31415#[inline]
31416#[target_feature(enable = "neon")]
31417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
31419#[cfg_attr(
31420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31421 assert_instr(sqdmulh, LANE = 0)
31422)]
31423#[rustc_legacy_const_generics(2)]
31424#[cfg_attr(
31425 not(target_arch = "arm"),
31426 stable(feature = "neon_intrinsics", since = "1.59.0")
31427)]
31428#[cfg_attr(
31429 target_arch = "arm",
31430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31431)]
31432pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
31433 static_assert_uimm_bits!(LANE, 2);
31434 unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
31435}
31436#[doc = "Vector saturating doubling multiply high by scalar"]
31437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
31438#[inline]
31439#[target_feature(enable = "neon")]
31440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31441#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
31442#[cfg_attr(
31443 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31444 assert_instr(sqdmulh, LANE = 0)
31445)]
31446#[rustc_legacy_const_generics(2)]
31447#[cfg_attr(
31448 not(target_arch = "arm"),
31449 stable(feature = "neon_intrinsics", since = "1.59.0")
31450)]
31451#[cfg_attr(
31452 target_arch = "arm",
31453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31454)]
31455pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
31456 static_assert_uimm_bits!(LANE, 2);
31457 unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
31458}
31459#[doc = "Vector saturating doubling multiply high with scalar"]
31460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
31461#[inline]
31462#[target_feature(enable = "neon")]
31463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31465#[cfg_attr(
31466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31467 assert_instr(sqdmulh)
31468)]
31469#[cfg_attr(
31470 not(target_arch = "arm"),
31471 stable(feature = "neon_intrinsics", since = "1.59.0")
31472)]
31473#[cfg_attr(
31474 target_arch = "arm",
31475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31476)]
31477pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
31478 let b: int16x4_t = vdup_n_s16(b);
31479 vqdmulh_s16(a, b)
31480}
31481#[doc = "Vector saturating doubling multiply high with scalar"]
31482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
31483#[inline]
31484#[target_feature(enable = "neon")]
31485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31487#[cfg_attr(
31488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31489 assert_instr(sqdmulh)
31490)]
31491#[cfg_attr(
31492 not(target_arch = "arm"),
31493 stable(feature = "neon_intrinsics", since = "1.59.0")
31494)]
31495#[cfg_attr(
31496 target_arch = "arm",
31497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31498)]
31499pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
31500 let b: int16x8_t = vdupq_n_s16(b);
31501 vqdmulhq_s16(a, b)
31502}
31503#[doc = "Vector saturating doubling multiply high with scalar"]
31504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
31505#[inline]
31506#[target_feature(enable = "neon")]
31507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31509#[cfg_attr(
31510 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31511 assert_instr(sqdmulh)
31512)]
31513#[cfg_attr(
31514 not(target_arch = "arm"),
31515 stable(feature = "neon_intrinsics", since = "1.59.0")
31516)]
31517#[cfg_attr(
31518 target_arch = "arm",
31519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31520)]
31521pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
31522 let b: int32x2_t = vdup_n_s32(b);
31523 vqdmulh_s32(a, b)
31524}
31525#[doc = "Vector saturating doubling multiply high with scalar"]
31526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
31527#[inline]
31528#[target_feature(enable = "neon")]
31529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31531#[cfg_attr(
31532 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31533 assert_instr(sqdmulh)
31534)]
31535#[cfg_attr(
31536 not(target_arch = "arm"),
31537 stable(feature = "neon_intrinsics", since = "1.59.0")
31538)]
31539#[cfg_attr(
31540 target_arch = "arm",
31541 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31542)]
31543pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
31544 let b: int32x4_t = vdupq_n_s32(b);
31545 vqdmulhq_s32(a, b)
31546}
31547#[doc = "Signed saturating doubling multiply returning high half"]
31548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
31549#[inline]
31550#[target_feature(enable = "neon")]
31551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31553#[cfg_attr(
31554 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31555 assert_instr(sqdmulh)
31556)]
31557#[cfg_attr(
31558 not(target_arch = "arm"),
31559 stable(feature = "neon_intrinsics", since = "1.59.0")
31560)]
31561#[cfg_attr(
31562 target_arch = "arm",
31563 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31564)]
31565pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
31566 unsafe extern "unadjusted" {
31567 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")]
31568 #[cfg_attr(
31569 any(target_arch = "aarch64", target_arch = "arm64ec"),
31570 link_name = "llvm.aarch64.neon.sqdmulh.v4i16"
31571 )]
31572 fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
31573 }
31574 unsafe { _vqdmulh_s16(a, b) }
31575}
31576#[doc = "Signed saturating doubling multiply returning high half"]
31577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
31578#[inline]
31579#[target_feature(enable = "neon")]
31580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31582#[cfg_attr(
31583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31584 assert_instr(sqdmulh)
31585)]
31586#[cfg_attr(
31587 not(target_arch = "arm"),
31588 stable(feature = "neon_intrinsics", since = "1.59.0")
31589)]
31590#[cfg_attr(
31591 target_arch = "arm",
31592 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31593)]
31594pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
31595 unsafe extern "unadjusted" {
31596 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")]
31597 #[cfg_attr(
31598 any(target_arch = "aarch64", target_arch = "arm64ec"),
31599 link_name = "llvm.aarch64.neon.sqdmulh.v8i16"
31600 )]
31601 fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
31602 }
31603 unsafe { _vqdmulhq_s16(a, b) }
31604}
31605#[doc = "Signed saturating doubling multiply returning high half"]
31606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
31607#[inline]
31608#[target_feature(enable = "neon")]
31609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31611#[cfg_attr(
31612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31613 assert_instr(sqdmulh)
31614)]
31615#[cfg_attr(
31616 not(target_arch = "arm"),
31617 stable(feature = "neon_intrinsics", since = "1.59.0")
31618)]
31619#[cfg_attr(
31620 target_arch = "arm",
31621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31622)]
31623pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
31624 unsafe extern "unadjusted" {
31625 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")]
31626 #[cfg_attr(
31627 any(target_arch = "aarch64", target_arch = "arm64ec"),
31628 link_name = "llvm.aarch64.neon.sqdmulh.v2i32"
31629 )]
31630 fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
31631 }
31632 unsafe { _vqdmulh_s32(a, b) }
31633}
31634#[doc = "Signed saturating doubling multiply returning high half"]
31635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
31636#[inline]
31637#[target_feature(enable = "neon")]
31638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
31640#[cfg_attr(
31641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31642 assert_instr(sqdmulh)
31643)]
31644#[cfg_attr(
31645 not(target_arch = "arm"),
31646 stable(feature = "neon_intrinsics", since = "1.59.0")
31647)]
31648#[cfg_attr(
31649 target_arch = "arm",
31650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31651)]
31652pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
31653 unsafe extern "unadjusted" {
31654 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")]
31655 #[cfg_attr(
31656 any(target_arch = "aarch64", target_arch = "arm64ec"),
31657 link_name = "llvm.aarch64.neon.sqdmulh.v4i32"
31658 )]
31659 fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
31660 }
31661 unsafe { _vqdmulhq_s32(a, b) }
31662}
31663#[doc = "Vector saturating doubling long multiply by scalar"]
31664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
31665#[inline]
31666#[target_feature(enable = "neon")]
31667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
31669#[cfg_attr(
31670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31671 assert_instr(sqdmull, N = 2)
31672)]
31673#[rustc_legacy_const_generics(2)]
31674#[cfg_attr(
31675 not(target_arch = "arm"),
31676 stable(feature = "neon_intrinsics", since = "1.59.0")
31677)]
31678#[cfg_attr(
31679 target_arch = "arm",
31680 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31681)]
31682pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
31683 static_assert_uimm_bits!(N, 2);
31684 unsafe {
31685 let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
31686 vqdmull_s16(a, b)
31687 }
31688}
31689#[doc = "Vector saturating doubling long multiply by scalar"]
31690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
31691#[inline]
31692#[target_feature(enable = "neon")]
31693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
31695#[cfg_attr(
31696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31697 assert_instr(sqdmull, N = 1)
31698)]
31699#[rustc_legacy_const_generics(2)]
31700#[cfg_attr(
31701 not(target_arch = "arm"),
31702 stable(feature = "neon_intrinsics", since = "1.59.0")
31703)]
31704#[cfg_attr(
31705 target_arch = "arm",
31706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31707)]
31708pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
31709 static_assert_uimm_bits!(N, 1);
31710 unsafe {
31711 let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
31712 vqdmull_s32(a, b)
31713 }
31714}
31715#[doc = "Vector saturating doubling long multiply with scalar"]
31716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
31717#[inline]
31718#[target_feature(enable = "neon")]
31719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
31721#[cfg_attr(
31722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31723 assert_instr(sqdmull)
31724)]
31725#[cfg_attr(
31726 not(target_arch = "arm"),
31727 stable(feature = "neon_intrinsics", since = "1.59.0")
31728)]
31729#[cfg_attr(
31730 target_arch = "arm",
31731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31732)]
31733pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
31734 vqdmull_s16(a, vdup_n_s16(b))
31735}
31736#[doc = "Vector saturating doubling long multiply with scalar"]
31737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
31738#[inline]
31739#[target_feature(enable = "neon")]
31740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31741#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
31742#[cfg_attr(
31743 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31744 assert_instr(sqdmull)
31745)]
31746#[cfg_attr(
31747 not(target_arch = "arm"),
31748 stable(feature = "neon_intrinsics", since = "1.59.0")
31749)]
31750#[cfg_attr(
31751 target_arch = "arm",
31752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31753)]
31754pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
31755 vqdmull_s32(a, vdup_n_s32(b))
31756}
31757#[doc = "Signed saturating doubling multiply long"]
31758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
31759#[inline]
31760#[target_feature(enable = "neon")]
31761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31762#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
31763#[cfg_attr(
31764 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31765 assert_instr(sqdmull)
31766)]
31767#[cfg_attr(
31768 not(target_arch = "arm"),
31769 stable(feature = "neon_intrinsics", since = "1.59.0")
31770)]
31771#[cfg_attr(
31772 target_arch = "arm",
31773 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31774)]
31775pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
31776 unsafe extern "unadjusted" {
31777 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")]
31778 #[cfg_attr(
31779 any(target_arch = "aarch64", target_arch = "arm64ec"),
31780 link_name = "llvm.aarch64.neon.sqdmull.v4i32"
31781 )]
31782 fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
31783 }
31784 unsafe { _vqdmull_s16(a, b) }
31785}
31786#[doc = "Signed saturating doubling multiply long"]
31787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
31788#[inline]
31789#[target_feature(enable = "neon")]
31790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
31792#[cfg_attr(
31793 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31794 assert_instr(sqdmull)
31795)]
31796#[cfg_attr(
31797 not(target_arch = "arm"),
31798 stable(feature = "neon_intrinsics", since = "1.59.0")
31799)]
31800#[cfg_attr(
31801 target_arch = "arm",
31802 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31803)]
31804pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
31805 unsafe extern "unadjusted" {
31806 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")]
31807 #[cfg_attr(
31808 any(target_arch = "aarch64", target_arch = "arm64ec"),
31809 link_name = "llvm.aarch64.neon.sqdmull.v2i64"
31810 )]
31811 fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
31812 }
31813 unsafe { _vqdmull_s32(a, b) }
31814}
31815#[doc = "Signed saturating extract narrow"]
31816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
31817#[inline]
31818#[target_feature(enable = "neon")]
31819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
31821#[cfg_attr(
31822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31823 assert_instr(sqxtn)
31824)]
31825#[cfg_attr(
31826 not(target_arch = "arm"),
31827 stable(feature = "neon_intrinsics", since = "1.59.0")
31828)]
31829#[cfg_attr(
31830 target_arch = "arm",
31831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31832)]
31833pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
31834 unsafe extern "unadjusted" {
31835 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")]
31836 #[cfg_attr(
31837 any(target_arch = "aarch64", target_arch = "arm64ec"),
31838 link_name = "llvm.aarch64.neon.sqxtn.v8i8"
31839 )]
31840 fn _vqmovn_s16(a: int16x8_t) -> int8x8_t;
31841 }
31842 unsafe { _vqmovn_s16(a) }
31843}
31844#[doc = "Signed saturating extract narrow"]
31845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
31846#[inline]
31847#[target_feature(enable = "neon")]
31848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
31850#[cfg_attr(
31851 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31852 assert_instr(sqxtn)
31853)]
31854#[cfg_attr(
31855 not(target_arch = "arm"),
31856 stable(feature = "neon_intrinsics", since = "1.59.0")
31857)]
31858#[cfg_attr(
31859 target_arch = "arm",
31860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31861)]
31862pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
31863 unsafe extern "unadjusted" {
31864 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")]
31865 #[cfg_attr(
31866 any(target_arch = "aarch64", target_arch = "arm64ec"),
31867 link_name = "llvm.aarch64.neon.sqxtn.v4i16"
31868 )]
31869 fn _vqmovn_s32(a: int32x4_t) -> int16x4_t;
31870 }
31871 unsafe { _vqmovn_s32(a) }
31872}
31873#[doc = "Signed saturating extract narrow"]
31874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
31875#[inline]
31876#[target_feature(enable = "neon")]
31877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
31879#[cfg_attr(
31880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31881 assert_instr(sqxtn)
31882)]
31883#[cfg_attr(
31884 not(target_arch = "arm"),
31885 stable(feature = "neon_intrinsics", since = "1.59.0")
31886)]
31887#[cfg_attr(
31888 target_arch = "arm",
31889 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31890)]
31891pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
31892 unsafe extern "unadjusted" {
31893 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")]
31894 #[cfg_attr(
31895 any(target_arch = "aarch64", target_arch = "arm64ec"),
31896 link_name = "llvm.aarch64.neon.sqxtn.v2i32"
31897 )]
31898 fn _vqmovn_s64(a: int64x2_t) -> int32x2_t;
31899 }
31900 unsafe { _vqmovn_s64(a) }
31901}
31902#[doc = "Unsigned saturating extract narrow"]
31903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
31904#[inline]
31905#[target_feature(enable = "neon")]
31906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
31908#[cfg_attr(
31909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31910 assert_instr(uqxtn)
31911)]
31912#[cfg_attr(
31913 not(target_arch = "arm"),
31914 stable(feature = "neon_intrinsics", since = "1.59.0")
31915)]
31916#[cfg_attr(
31917 target_arch = "arm",
31918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31919)]
31920pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
31921 unsafe extern "unadjusted" {
31922 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")]
31923 #[cfg_attr(
31924 any(target_arch = "aarch64", target_arch = "arm64ec"),
31925 link_name = "llvm.aarch64.neon.uqxtn.v8i8"
31926 )]
31927 fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t;
31928 }
31929 unsafe { _vqmovn_u16(a) }
31930}
31931#[doc = "Unsigned saturating extract narrow"]
31932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
31933#[inline]
31934#[target_feature(enable = "neon")]
31935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
31937#[cfg_attr(
31938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31939 assert_instr(uqxtn)
31940)]
31941#[cfg_attr(
31942 not(target_arch = "arm"),
31943 stable(feature = "neon_intrinsics", since = "1.59.0")
31944)]
31945#[cfg_attr(
31946 target_arch = "arm",
31947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31948)]
31949pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
31950 unsafe extern "unadjusted" {
31951 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")]
31952 #[cfg_attr(
31953 any(target_arch = "aarch64", target_arch = "arm64ec"),
31954 link_name = "llvm.aarch64.neon.uqxtn.v4i16"
31955 )]
31956 fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t;
31957 }
31958 unsafe { _vqmovn_u32(a) }
31959}
31960#[doc = "Unsigned saturating extract narrow"]
31961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
31962#[inline]
31963#[target_feature(enable = "neon")]
31964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31965#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
31966#[cfg_attr(
31967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31968 assert_instr(uqxtn)
31969)]
31970#[cfg_attr(
31971 not(target_arch = "arm"),
31972 stable(feature = "neon_intrinsics", since = "1.59.0")
31973)]
31974#[cfg_attr(
31975 target_arch = "arm",
31976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31977)]
31978pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
31979 unsafe extern "unadjusted" {
31980 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")]
31981 #[cfg_attr(
31982 any(target_arch = "aarch64", target_arch = "arm64ec"),
31983 link_name = "llvm.aarch64.neon.uqxtn.v2i32"
31984 )]
31985 fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t;
31986 }
31987 unsafe { _vqmovn_u64(a) }
31988}
31989#[doc = "Signed saturating extract unsigned narrow"]
31990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
31991#[inline]
31992#[target_feature(enable = "neon")]
31993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
31995#[cfg_attr(
31996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31997 assert_instr(sqxtun)
31998)]
31999#[cfg_attr(
32000 not(target_arch = "arm"),
32001 stable(feature = "neon_intrinsics", since = "1.59.0")
32002)]
32003#[cfg_attr(
32004 target_arch = "arm",
32005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32006)]
32007pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
32008 unsafe extern "unadjusted" {
32009 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")]
32010 #[cfg_attr(
32011 any(target_arch = "aarch64", target_arch = "arm64ec"),
32012 link_name = "llvm.aarch64.neon.sqxtun.v8i8"
32013 )]
32014 fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t;
32015 }
32016 unsafe { _vqmovun_s16(a) }
32017}
32018#[doc = "Signed saturating extract unsigned narrow"]
32019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
32020#[inline]
32021#[target_feature(enable = "neon")]
32022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
32024#[cfg_attr(
32025 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32026 assert_instr(sqxtun)
32027)]
32028#[cfg_attr(
32029 not(target_arch = "arm"),
32030 stable(feature = "neon_intrinsics", since = "1.59.0")
32031)]
32032#[cfg_attr(
32033 target_arch = "arm",
32034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32035)]
32036pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
32037 unsafe extern "unadjusted" {
32038 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")]
32039 #[cfg_attr(
32040 any(target_arch = "aarch64", target_arch = "arm64ec"),
32041 link_name = "llvm.aarch64.neon.sqxtun.v4i16"
32042 )]
32043 fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t;
32044 }
32045 unsafe { _vqmovun_s32(a) }
32046}
32047#[doc = "Signed saturating extract unsigned narrow"]
32048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
32049#[inline]
32050#[target_feature(enable = "neon")]
32051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
32053#[cfg_attr(
32054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32055 assert_instr(sqxtun)
32056)]
32057#[cfg_attr(
32058 not(target_arch = "arm"),
32059 stable(feature = "neon_intrinsics", since = "1.59.0")
32060)]
32061#[cfg_attr(
32062 target_arch = "arm",
32063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32064)]
32065pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
32066 unsafe extern "unadjusted" {
32067 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")]
32068 #[cfg_attr(
32069 any(target_arch = "aarch64", target_arch = "arm64ec"),
32070 link_name = "llvm.aarch64.neon.sqxtun.v2i32"
32071 )]
32072 fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t;
32073 }
32074 unsafe { _vqmovun_s64(a) }
32075}
32076#[doc = "Signed saturating negate"]
32077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
32078#[inline]
32079#[target_feature(enable = "neon")]
32080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32081#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
32082#[cfg_attr(
32083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32084 assert_instr(sqneg)
32085)]
32086#[cfg_attr(
32087 not(target_arch = "arm"),
32088 stable(feature = "neon_intrinsics", since = "1.59.0")
32089)]
32090#[cfg_attr(
32091 target_arch = "arm",
32092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32093)]
32094pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
32095 unsafe extern "unadjusted" {
32096 #[cfg_attr(
32097 any(target_arch = "aarch64", target_arch = "arm64ec"),
32098 link_name = "llvm.aarch64.neon.sqneg.v8i8"
32099 )]
32100 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")]
32101 fn _vqneg_s8(a: int8x8_t) -> int8x8_t;
32102 }
32103 unsafe { _vqneg_s8(a) }
32104}
32105#[doc = "Signed saturating negate"]
32106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
32107#[inline]
32108#[target_feature(enable = "neon")]
32109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
32111#[cfg_attr(
32112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32113 assert_instr(sqneg)
32114)]
32115#[cfg_attr(
32116 not(target_arch = "arm"),
32117 stable(feature = "neon_intrinsics", since = "1.59.0")
32118)]
32119#[cfg_attr(
32120 target_arch = "arm",
32121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32122)]
32123pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
32124 unsafe extern "unadjusted" {
32125 #[cfg_attr(
32126 any(target_arch = "aarch64", target_arch = "arm64ec"),
32127 link_name = "llvm.aarch64.neon.sqneg.v16i8"
32128 )]
32129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")]
32130 fn _vqnegq_s8(a: int8x16_t) -> int8x16_t;
32131 }
32132 unsafe { _vqnegq_s8(a) }
32133}
32134#[doc = "Signed saturating negate"]
32135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
32136#[inline]
32137#[target_feature(enable = "neon")]
32138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32139#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
32140#[cfg_attr(
32141 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32142 assert_instr(sqneg)
32143)]
32144#[cfg_attr(
32145 not(target_arch = "arm"),
32146 stable(feature = "neon_intrinsics", since = "1.59.0")
32147)]
32148#[cfg_attr(
32149 target_arch = "arm",
32150 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32151)]
32152pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
32153 unsafe extern "unadjusted" {
32154 #[cfg_attr(
32155 any(target_arch = "aarch64", target_arch = "arm64ec"),
32156 link_name = "llvm.aarch64.neon.sqneg.v4i16"
32157 )]
32158 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")]
32159 fn _vqneg_s16(a: int16x4_t) -> int16x4_t;
32160 }
32161 unsafe { _vqneg_s16(a) }
32162}
32163#[doc = "Signed saturating negate"]
32164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
32165#[inline]
32166#[target_feature(enable = "neon")]
32167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
32169#[cfg_attr(
32170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32171 assert_instr(sqneg)
32172)]
32173#[cfg_attr(
32174 not(target_arch = "arm"),
32175 stable(feature = "neon_intrinsics", since = "1.59.0")
32176)]
32177#[cfg_attr(
32178 target_arch = "arm",
32179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32180)]
32181pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
32182 unsafe extern "unadjusted" {
32183 #[cfg_attr(
32184 any(target_arch = "aarch64", target_arch = "arm64ec"),
32185 link_name = "llvm.aarch64.neon.sqneg.v8i16"
32186 )]
32187 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")]
32188 fn _vqnegq_s16(a: int16x8_t) -> int16x8_t;
32189 }
32190 unsafe { _vqnegq_s16(a) }
32191}
32192#[doc = "Signed saturating negate"]
32193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
32194#[inline]
32195#[target_feature(enable = "neon")]
32196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32197#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
32198#[cfg_attr(
32199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32200 assert_instr(sqneg)
32201)]
32202#[cfg_attr(
32203 not(target_arch = "arm"),
32204 stable(feature = "neon_intrinsics", since = "1.59.0")
32205)]
32206#[cfg_attr(
32207 target_arch = "arm",
32208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32209)]
32210pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
32211 unsafe extern "unadjusted" {
32212 #[cfg_attr(
32213 any(target_arch = "aarch64", target_arch = "arm64ec"),
32214 link_name = "llvm.aarch64.neon.sqneg.v2i32"
32215 )]
32216 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")]
32217 fn _vqneg_s32(a: int32x2_t) -> int32x2_t;
32218 }
32219 unsafe { _vqneg_s32(a) }
32220}
32221#[doc = "Signed saturating negate"]
32222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
32223#[inline]
32224#[target_feature(enable = "neon")]
32225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
32227#[cfg_attr(
32228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32229 assert_instr(sqneg)
32230)]
32231#[cfg_attr(
32232 not(target_arch = "arm"),
32233 stable(feature = "neon_intrinsics", since = "1.59.0")
32234)]
32235#[cfg_attr(
32236 target_arch = "arm",
32237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32238)]
32239pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
32240 unsafe extern "unadjusted" {
32241 #[cfg_attr(
32242 any(target_arch = "aarch64", target_arch = "arm64ec"),
32243 link_name = "llvm.aarch64.neon.sqneg.v4i32"
32244 )]
32245 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")]
32246 fn _vqnegq_s32(a: int32x4_t) -> int32x4_t;
32247 }
32248 unsafe { _vqnegq_s32(a) }
32249}
32250#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
32252#[inline]
32253#[target_feature(enable = "neon")]
32254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32256#[cfg_attr(
32257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32258 assert_instr(sqrdmulh, LANE = 1)
32259)]
32260#[rustc_legacy_const_generics(2)]
32261#[cfg_attr(
32262 not(target_arch = "arm"),
32263 stable(feature = "neon_intrinsics", since = "1.59.0")
32264)]
32265#[cfg_attr(
32266 target_arch = "arm",
32267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32268)]
32269pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32270 static_assert_uimm_bits!(LANE, 2);
32271 unsafe {
32272 let b: int16x4_t =
32273 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
32274 vqrdmulh_s16(a, b)
32275 }
32276}
32277#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
32279#[inline]
32280#[target_feature(enable = "neon")]
32281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32283#[cfg_attr(
32284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32285 assert_instr(sqrdmulh, LANE = 1)
32286)]
32287#[rustc_legacy_const_generics(2)]
32288#[cfg_attr(
32289 not(target_arch = "arm"),
32290 stable(feature = "neon_intrinsics", since = "1.59.0")
32291)]
32292#[cfg_attr(
32293 target_arch = "arm",
32294 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32295)]
32296pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32297 static_assert_uimm_bits!(LANE, 1);
32298 unsafe {
32299 let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
32300 vqrdmulh_s32(a, b)
32301 }
32302}
32303#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
32305#[inline]
32306#[target_feature(enable = "neon")]
32307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32309#[cfg_attr(
32310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32311 assert_instr(sqrdmulh, LANE = 1)
32312)]
32313#[rustc_legacy_const_generics(2)]
32314#[cfg_attr(
32315 not(target_arch = "arm"),
32316 stable(feature = "neon_intrinsics", since = "1.59.0")
32317)]
32318#[cfg_attr(
32319 target_arch = "arm",
32320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32321)]
32322pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
32323 static_assert_uimm_bits!(LANE, 3);
32324 unsafe {
32325 let b: int16x4_t =
32326 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
32327 vqrdmulh_s16(a, b)
32328 }
32329}
32330#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
32332#[inline]
32333#[target_feature(enable = "neon")]
32334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32336#[cfg_attr(
32337 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32338 assert_instr(sqrdmulh, LANE = 1)
32339)]
32340#[rustc_legacy_const_generics(2)]
32341#[cfg_attr(
32342 not(target_arch = "arm"),
32343 stable(feature = "neon_intrinsics", since = "1.59.0")
32344)]
32345#[cfg_attr(
32346 target_arch = "arm",
32347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32348)]
32349pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
32350 static_assert_uimm_bits!(LANE, 2);
32351 unsafe {
32352 let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
32353 vqrdmulh_s32(a, b)
32354 }
32355}
32356#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
32358#[inline]
32359#[target_feature(enable = "neon")]
32360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32362#[cfg_attr(
32363 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32364 assert_instr(sqrdmulh, LANE = 1)
32365)]
32366#[rustc_legacy_const_generics(2)]
32367#[cfg_attr(
32368 not(target_arch = "arm"),
32369 stable(feature = "neon_intrinsics", since = "1.59.0")
32370)]
32371#[cfg_attr(
32372 target_arch = "arm",
32373 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32374)]
32375pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
32376 static_assert_uimm_bits!(LANE, 2);
32377 unsafe {
32378 let b: int16x8_t = simd_shuffle!(
32379 b,
32380 b,
32381 [
32382 LANE as u32,
32383 LANE as u32,
32384 LANE as u32,
32385 LANE as u32,
32386 LANE as u32,
32387 LANE as u32,
32388 LANE as u32,
32389 LANE as u32
32390 ]
32391 );
32392 vqrdmulhq_s16(a, b)
32393 }
32394}
32395#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
32397#[inline]
32398#[target_feature(enable = "neon")]
32399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32400#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32401#[cfg_attr(
32402 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32403 assert_instr(sqrdmulh, LANE = 1)
32404)]
32405#[rustc_legacy_const_generics(2)]
32406#[cfg_attr(
32407 not(target_arch = "arm"),
32408 stable(feature = "neon_intrinsics", since = "1.59.0")
32409)]
32410#[cfg_attr(
32411 target_arch = "arm",
32412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32413)]
32414pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
32415 static_assert_uimm_bits!(LANE, 1);
32416 unsafe {
32417 let b: int32x4_t =
32418 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
32419 vqrdmulhq_s32(a, b)
32420 }
32421}
32422#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
32424#[inline]
32425#[target_feature(enable = "neon")]
32426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32427#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32428#[cfg_attr(
32429 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32430 assert_instr(sqrdmulh, LANE = 1)
32431)]
32432#[rustc_legacy_const_generics(2)]
32433#[cfg_attr(
32434 not(target_arch = "arm"),
32435 stable(feature = "neon_intrinsics", since = "1.59.0")
32436)]
32437#[cfg_attr(
32438 target_arch = "arm",
32439 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32440)]
32441pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
32442 static_assert_uimm_bits!(LANE, 3);
32443 unsafe {
32444 let b: int16x8_t = simd_shuffle!(
32445 b,
32446 b,
32447 [
32448 LANE as u32,
32449 LANE as u32,
32450 LANE as u32,
32451 LANE as u32,
32452 LANE as u32,
32453 LANE as u32,
32454 LANE as u32,
32455 LANE as u32
32456 ]
32457 );
32458 vqrdmulhq_s16(a, b)
32459 }
32460}
32461#[doc = "Vector rounding saturating doubling multiply high by scalar"]
32462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
32463#[inline]
32464#[target_feature(enable = "neon")]
32465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
32467#[cfg_attr(
32468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32469 assert_instr(sqrdmulh, LANE = 1)
32470)]
32471#[rustc_legacy_const_generics(2)]
32472#[cfg_attr(
32473 not(target_arch = "arm"),
32474 stable(feature = "neon_intrinsics", since = "1.59.0")
32475)]
32476#[cfg_attr(
32477 target_arch = "arm",
32478 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32479)]
32480pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
32481 static_assert_uimm_bits!(LANE, 2);
32482 unsafe {
32483 let b: int32x4_t =
32484 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
32485 vqrdmulhq_s32(a, b)
32486 }
32487}
32488#[doc = "Vector saturating rounding doubling multiply high with scalar"]
32489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
32490#[inline]
32491#[target_feature(enable = "neon")]
32492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32493#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32494#[cfg_attr(
32495 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32496 assert_instr(sqrdmulh)
32497)]
32498#[cfg_attr(
32499 not(target_arch = "arm"),
32500 stable(feature = "neon_intrinsics", since = "1.59.0")
32501)]
32502#[cfg_attr(
32503 target_arch = "arm",
32504 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32505)]
32506pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
32507 vqrdmulh_s16(a, vdup_n_s16(b))
32508}
32509#[doc = "Vector saturating rounding doubling multiply high with scalar"]
32510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
32511#[inline]
32512#[target_feature(enable = "neon")]
32513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32515#[cfg_attr(
32516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32517 assert_instr(sqrdmulh)
32518)]
32519#[cfg_attr(
32520 not(target_arch = "arm"),
32521 stable(feature = "neon_intrinsics", since = "1.59.0")
32522)]
32523#[cfg_attr(
32524 target_arch = "arm",
32525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32526)]
32527pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
32528 vqrdmulhq_s16(a, vdupq_n_s16(b))
32529}
32530#[doc = "Vector saturating rounding doubling multiply high with scalar"]
32531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
32532#[inline]
32533#[target_feature(enable = "neon")]
32534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32536#[cfg_attr(
32537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32538 assert_instr(sqrdmulh)
32539)]
32540#[cfg_attr(
32541 not(target_arch = "arm"),
32542 stable(feature = "neon_intrinsics", since = "1.59.0")
32543)]
32544#[cfg_attr(
32545 target_arch = "arm",
32546 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32547)]
32548pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
32549 vqrdmulh_s32(a, vdup_n_s32(b))
32550}
32551#[doc = "Vector saturating rounding doubling multiply high with scalar"]
32552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
32553#[inline]
32554#[target_feature(enable = "neon")]
32555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32557#[cfg_attr(
32558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32559 assert_instr(sqrdmulh)
32560)]
32561#[cfg_attr(
32562 not(target_arch = "arm"),
32563 stable(feature = "neon_intrinsics", since = "1.59.0")
32564)]
32565#[cfg_attr(
32566 target_arch = "arm",
32567 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32568)]
32569pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
32570 vqrdmulhq_s32(a, vdupq_n_s32(b))
32571}
32572#[doc = "Signed saturating rounding doubling multiply returning high half"]
32573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
32574#[inline]
32575#[target_feature(enable = "neon")]
32576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32578#[cfg_attr(
32579 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32580 assert_instr(sqrdmulh)
32581)]
32582#[cfg_attr(
32583 not(target_arch = "arm"),
32584 stable(feature = "neon_intrinsics", since = "1.59.0")
32585)]
32586#[cfg_attr(
32587 target_arch = "arm",
32588 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32589)]
32590pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32591 unsafe extern "unadjusted" {
32592 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")]
32593 #[cfg_attr(
32594 any(target_arch = "aarch64", target_arch = "arm64ec"),
32595 link_name = "llvm.aarch64.neon.sqrdmulh.v4i16"
32596 )]
32597 fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
32598 }
32599 unsafe { _vqrdmulh_s16(a, b) }
32600}
32601#[doc = "Signed saturating rounding doubling multiply returning high half"]
32602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
32603#[inline]
32604#[target_feature(enable = "neon")]
32605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32607#[cfg_attr(
32608 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32609 assert_instr(sqrdmulh)
32610)]
32611#[cfg_attr(
32612 not(target_arch = "arm"),
32613 stable(feature = "neon_intrinsics", since = "1.59.0")
32614)]
32615#[cfg_attr(
32616 target_arch = "arm",
32617 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32618)]
32619pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
32620 unsafe extern "unadjusted" {
32621 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")]
32622 #[cfg_attr(
32623 any(target_arch = "aarch64", target_arch = "arm64ec"),
32624 link_name = "llvm.aarch64.neon.sqrdmulh.v8i16"
32625 )]
32626 fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
32627 }
32628 unsafe { _vqrdmulhq_s16(a, b) }
32629}
32630#[doc = "Signed saturating rounding doubling multiply returning high half"]
32631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
32632#[inline]
32633#[target_feature(enable = "neon")]
32634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32636#[cfg_attr(
32637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32638 assert_instr(sqrdmulh)
32639)]
32640#[cfg_attr(
32641 not(target_arch = "arm"),
32642 stable(feature = "neon_intrinsics", since = "1.59.0")
32643)]
32644#[cfg_attr(
32645 target_arch = "arm",
32646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32647)]
32648pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32649 unsafe extern "unadjusted" {
32650 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")]
32651 #[cfg_attr(
32652 any(target_arch = "aarch64", target_arch = "arm64ec"),
32653 link_name = "llvm.aarch64.neon.sqrdmulh.v2i32"
32654 )]
32655 fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
32656 }
32657 unsafe { _vqrdmulh_s32(a, b) }
32658}
32659#[doc = "Signed saturating rounding doubling multiply returning high half"]
32660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
32661#[inline]
32662#[target_feature(enable = "neon")]
32663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32664#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
32665#[cfg_attr(
32666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32667 assert_instr(sqrdmulh)
32668)]
32669#[cfg_attr(
32670 not(target_arch = "arm"),
32671 stable(feature = "neon_intrinsics", since = "1.59.0")
32672)]
32673#[cfg_attr(
32674 target_arch = "arm",
32675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32676)]
32677pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
32678 unsafe extern "unadjusted" {
32679 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")]
32680 #[cfg_attr(
32681 any(target_arch = "aarch64", target_arch = "arm64ec"),
32682 link_name = "llvm.aarch64.neon.sqrdmulh.v4i32"
32683 )]
32684 fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
32685 }
32686 unsafe { _vqrdmulhq_s32(a, b) }
32687}
32688#[doc = "Signed saturating rounding shift left"]
32689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
32690#[inline]
32691#[target_feature(enable = "neon")]
32692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32694#[cfg_attr(
32695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32696 assert_instr(sqrshl)
32697)]
32698#[cfg_attr(
32699 not(target_arch = "arm"),
32700 stable(feature = "neon_intrinsics", since = "1.59.0")
32701)]
32702#[cfg_attr(
32703 target_arch = "arm",
32704 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32705)]
32706pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
32707 unsafe extern "unadjusted" {
32708 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")]
32709 #[cfg_attr(
32710 any(target_arch = "aarch64", target_arch = "arm64ec"),
32711 link_name = "llvm.aarch64.neon.sqrshl.v8i8"
32712 )]
32713 fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
32714 }
32715 unsafe { _vqrshl_s8(a, b) }
32716}
32717#[doc = "Signed saturating rounding shift left"]
32718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
32719#[inline]
32720#[target_feature(enable = "neon")]
32721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32723#[cfg_attr(
32724 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32725 assert_instr(sqrshl)
32726)]
32727#[cfg_attr(
32728 not(target_arch = "arm"),
32729 stable(feature = "neon_intrinsics", since = "1.59.0")
32730)]
32731#[cfg_attr(
32732 target_arch = "arm",
32733 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32734)]
32735pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
32736 unsafe extern "unadjusted" {
32737 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")]
32738 #[cfg_attr(
32739 any(target_arch = "aarch64", target_arch = "arm64ec"),
32740 link_name = "llvm.aarch64.neon.sqrshl.v16i8"
32741 )]
32742 fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
32743 }
32744 unsafe { _vqrshlq_s8(a, b) }
32745}
32746#[doc = "Signed saturating rounding shift left"]
32747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
32748#[inline]
32749#[target_feature(enable = "neon")]
32750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32752#[cfg_attr(
32753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32754 assert_instr(sqrshl)
32755)]
32756#[cfg_attr(
32757 not(target_arch = "arm"),
32758 stable(feature = "neon_intrinsics", since = "1.59.0")
32759)]
32760#[cfg_attr(
32761 target_arch = "arm",
32762 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32763)]
32764pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32765 unsafe extern "unadjusted" {
32766 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")]
32767 #[cfg_attr(
32768 any(target_arch = "aarch64", target_arch = "arm64ec"),
32769 link_name = "llvm.aarch64.neon.sqrshl.v4i16"
32770 )]
32771 fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
32772 }
32773 unsafe { _vqrshl_s16(a, b) }
32774}
32775#[doc = "Signed saturating rounding shift left"]
32776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
32777#[inline]
32778#[target_feature(enable = "neon")]
32779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32781#[cfg_attr(
32782 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32783 assert_instr(sqrshl)
32784)]
32785#[cfg_attr(
32786 not(target_arch = "arm"),
32787 stable(feature = "neon_intrinsics", since = "1.59.0")
32788)]
32789#[cfg_attr(
32790 target_arch = "arm",
32791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32792)]
32793pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
32794 unsafe extern "unadjusted" {
32795 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")]
32796 #[cfg_attr(
32797 any(target_arch = "aarch64", target_arch = "arm64ec"),
32798 link_name = "llvm.aarch64.neon.sqrshl.v8i16"
32799 )]
32800 fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
32801 }
32802 unsafe { _vqrshlq_s16(a, b) }
32803}
32804#[doc = "Signed saturating rounding shift left"]
32805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
32806#[inline]
32807#[target_feature(enable = "neon")]
32808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32810#[cfg_attr(
32811 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32812 assert_instr(sqrshl)
32813)]
32814#[cfg_attr(
32815 not(target_arch = "arm"),
32816 stable(feature = "neon_intrinsics", since = "1.59.0")
32817)]
32818#[cfg_attr(
32819 target_arch = "arm",
32820 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32821)]
32822pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32823 unsafe extern "unadjusted" {
32824 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")]
32825 #[cfg_attr(
32826 any(target_arch = "aarch64", target_arch = "arm64ec"),
32827 link_name = "llvm.aarch64.neon.sqrshl.v2i32"
32828 )]
32829 fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
32830 }
32831 unsafe { _vqrshl_s32(a, b) }
32832}
32833#[doc = "Signed saturating rounding shift left"]
32834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
32835#[inline]
32836#[target_feature(enable = "neon")]
32837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32839#[cfg_attr(
32840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32841 assert_instr(sqrshl)
32842)]
32843#[cfg_attr(
32844 not(target_arch = "arm"),
32845 stable(feature = "neon_intrinsics", since = "1.59.0")
32846)]
32847#[cfg_attr(
32848 target_arch = "arm",
32849 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32850)]
32851pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
32852 unsafe extern "unadjusted" {
32853 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")]
32854 #[cfg_attr(
32855 any(target_arch = "aarch64", target_arch = "arm64ec"),
32856 link_name = "llvm.aarch64.neon.sqrshl.v4i32"
32857 )]
32858 fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
32859 }
32860 unsafe { _vqrshlq_s32(a, b) }
32861}
32862#[doc = "Signed saturating rounding shift left"]
32863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
32864#[inline]
32865#[target_feature(enable = "neon")]
32866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32868#[cfg_attr(
32869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32870 assert_instr(sqrshl)
32871)]
32872#[cfg_attr(
32873 not(target_arch = "arm"),
32874 stable(feature = "neon_intrinsics", since = "1.59.0")
32875)]
32876#[cfg_attr(
32877 target_arch = "arm",
32878 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32879)]
32880pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
32881 unsafe extern "unadjusted" {
32882 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")]
32883 #[cfg_attr(
32884 any(target_arch = "aarch64", target_arch = "arm64ec"),
32885 link_name = "llvm.aarch64.neon.sqrshl.v1i64"
32886 )]
32887 fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
32888 }
32889 unsafe { _vqrshl_s64(a, b) }
32890}
32891#[doc = "Signed saturating rounding shift left"]
32892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
32893#[inline]
32894#[target_feature(enable = "neon")]
32895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32897#[cfg_attr(
32898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32899 assert_instr(sqrshl)
32900)]
32901#[cfg_attr(
32902 not(target_arch = "arm"),
32903 stable(feature = "neon_intrinsics", since = "1.59.0")
32904)]
32905#[cfg_attr(
32906 target_arch = "arm",
32907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32908)]
32909pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
32910 unsafe extern "unadjusted" {
32911 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")]
32912 #[cfg_attr(
32913 any(target_arch = "aarch64", target_arch = "arm64ec"),
32914 link_name = "llvm.aarch64.neon.sqrshl.v2i64"
32915 )]
32916 fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
32917 }
32918 unsafe { _vqrshlq_s64(a, b) }
32919}
32920#[doc = "Unsigned signed saturating rounding shift left"]
32921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
32922#[inline]
32923#[target_feature(enable = "neon")]
32924#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32926#[cfg_attr(
32927 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32928 assert_instr(uqrshl)
32929)]
32930#[cfg_attr(
32931 not(target_arch = "arm"),
32932 stable(feature = "neon_intrinsics", since = "1.59.0")
32933)]
32934#[cfg_attr(
32935 target_arch = "arm",
32936 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32937)]
32938pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
32939 unsafe extern "unadjusted" {
32940 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")]
32941 #[cfg_attr(
32942 any(target_arch = "aarch64", target_arch = "arm64ec"),
32943 link_name = "llvm.aarch64.neon.uqrshl.v8i8"
32944 )]
32945 fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
32946 }
32947 unsafe { _vqrshl_u8(a, b) }
32948}
32949#[doc = "Unsigned signed saturating rounding shift left"]
32950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
32951#[inline]
32952#[target_feature(enable = "neon")]
32953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32955#[cfg_attr(
32956 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32957 assert_instr(uqrshl)
32958)]
32959#[cfg_attr(
32960 not(target_arch = "arm"),
32961 stable(feature = "neon_intrinsics", since = "1.59.0")
32962)]
32963#[cfg_attr(
32964 target_arch = "arm",
32965 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32966)]
32967pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
32968 unsafe extern "unadjusted" {
32969 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")]
32970 #[cfg_attr(
32971 any(target_arch = "aarch64", target_arch = "arm64ec"),
32972 link_name = "llvm.aarch64.neon.uqrshl.v16i8"
32973 )]
32974 fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
32975 }
32976 unsafe { _vqrshlq_u8(a, b) }
32977}
32978#[doc = "Unsigned signed saturating rounding shift left"]
32979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
32980#[inline]
32981#[target_feature(enable = "neon")]
32982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
32984#[cfg_attr(
32985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32986 assert_instr(uqrshl)
32987)]
32988#[cfg_attr(
32989 not(target_arch = "arm"),
32990 stable(feature = "neon_intrinsics", since = "1.59.0")
32991)]
32992#[cfg_attr(
32993 target_arch = "arm",
32994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32995)]
32996pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
32997 unsafe extern "unadjusted" {
32998 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")]
32999 #[cfg_attr(
33000 any(target_arch = "aarch64", target_arch = "arm64ec"),
33001 link_name = "llvm.aarch64.neon.uqrshl.v4i16"
33002 )]
33003 fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
33004 }
33005 unsafe { _vqrshl_u16(a, b) }
33006}
33007#[doc = "Unsigned signed saturating rounding shift left"]
33008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
33009#[inline]
33010#[target_feature(enable = "neon")]
33011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
33013#[cfg_attr(
33014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33015 assert_instr(uqrshl)
33016)]
33017#[cfg_attr(
33018 not(target_arch = "arm"),
33019 stable(feature = "neon_intrinsics", since = "1.59.0")
33020)]
33021#[cfg_attr(
33022 target_arch = "arm",
33023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33024)]
33025pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
33026 unsafe extern "unadjusted" {
33027 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")]
33028 #[cfg_attr(
33029 any(target_arch = "aarch64", target_arch = "arm64ec"),
33030 link_name = "llvm.aarch64.neon.uqrshl.v8i16"
33031 )]
33032 fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
33033 }
33034 unsafe { _vqrshlq_u16(a, b) }
33035}
33036#[doc = "Unsigned signed saturating rounding shift left"]
33037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
33038#[inline]
33039#[target_feature(enable = "neon")]
33040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33041#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
33042#[cfg_attr(
33043 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33044 assert_instr(uqrshl)
33045)]
33046#[cfg_attr(
33047 not(target_arch = "arm"),
33048 stable(feature = "neon_intrinsics", since = "1.59.0")
33049)]
33050#[cfg_attr(
33051 target_arch = "arm",
33052 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33053)]
33054pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
33055 unsafe extern "unadjusted" {
33056 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")]
33057 #[cfg_attr(
33058 any(target_arch = "aarch64", target_arch = "arm64ec"),
33059 link_name = "llvm.aarch64.neon.uqrshl.v2i32"
33060 )]
33061 fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
33062 }
33063 unsafe { _vqrshl_u32(a, b) }
33064}
33065#[doc = "Unsigned signed saturating rounding shift left"]
33066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
33067#[inline]
33068#[target_feature(enable = "neon")]
33069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33070#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
33071#[cfg_attr(
33072 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33073 assert_instr(uqrshl)
33074)]
33075#[cfg_attr(
33076 not(target_arch = "arm"),
33077 stable(feature = "neon_intrinsics", since = "1.59.0")
33078)]
33079#[cfg_attr(
33080 target_arch = "arm",
33081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33082)]
33083pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
33084 unsafe extern "unadjusted" {
33085 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")]
33086 #[cfg_attr(
33087 any(target_arch = "aarch64", target_arch = "arm64ec"),
33088 link_name = "llvm.aarch64.neon.uqrshl.v4i32"
33089 )]
33090 fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
33091 }
33092 unsafe { _vqrshlq_u32(a, b) }
33093}
33094#[doc = "Unsigned signed saturating rounding shift left"]
33095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
33096#[inline]
33097#[target_feature(enable = "neon")]
33098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
33100#[cfg_attr(
33101 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33102 assert_instr(uqrshl)
33103)]
33104#[cfg_attr(
33105 not(target_arch = "arm"),
33106 stable(feature = "neon_intrinsics", since = "1.59.0")
33107)]
33108#[cfg_attr(
33109 target_arch = "arm",
33110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33111)]
33112pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
33113 unsafe extern "unadjusted" {
33114 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")]
33115 #[cfg_attr(
33116 any(target_arch = "aarch64", target_arch = "arm64ec"),
33117 link_name = "llvm.aarch64.neon.uqrshl.v1i64"
33118 )]
33119 fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
33120 }
33121 unsafe { _vqrshl_u64(a, b) }
33122}
33123#[doc = "Unsigned signed saturating rounding shift left"]
33124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
33125#[inline]
33126#[target_feature(enable = "neon")]
33127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
33129#[cfg_attr(
33130 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33131 assert_instr(uqrshl)
33132)]
33133#[cfg_attr(
33134 not(target_arch = "arm"),
33135 stable(feature = "neon_intrinsics", since = "1.59.0")
33136)]
33137#[cfg_attr(
33138 target_arch = "arm",
33139 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33140)]
33141pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
33142 unsafe extern "unadjusted" {
33143 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")]
33144 #[cfg_attr(
33145 any(target_arch = "aarch64", target_arch = "arm64ec"),
33146 link_name = "llvm.aarch64.neon.uqrshl.v2i64"
33147 )]
33148 fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
33149 }
33150 unsafe { _vqrshlq_u64(a, b) }
33151}
33152#[doc = "Signed saturating rounded shift right narrow"]
33153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
33154#[inline]
33155#[cfg(target_arch = "arm")]
33156#[target_feature(enable = "neon,v7")]
33157#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
33158#[rustc_legacy_const_generics(1)]
33159#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33160pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
33161 static_assert!(N >= 1 && N <= 8);
33162 unsafe extern "unadjusted" {
33163 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")]
33164 fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
33165 }
33166 unsafe {
33167 _vqrshrn_n_s16(
33168 a,
33169 const {
33170 int16x8_t([
33171 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
33172 -N as i16,
33173 ])
33174 },
33175 )
33176 }
33177}
33178#[doc = "Signed saturating rounded shift right narrow"]
33179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
33180#[inline]
33181#[cfg(target_arch = "arm")]
33182#[target_feature(enable = "neon,v7")]
33183#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
33184#[rustc_legacy_const_generics(1)]
33185#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33186pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
33187 static_assert!(N >= 1 && N <= 16);
33188 unsafe extern "unadjusted" {
33189 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")]
33190 fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
33191 }
33192 unsafe {
33193 _vqrshrn_n_s32(
33194 a,
33195 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
33196 )
33197 }
33198}
33199#[doc = "Signed saturating rounded shift right narrow"]
33200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
33201#[inline]
33202#[cfg(target_arch = "arm")]
33203#[target_feature(enable = "neon,v7")]
33204#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
33205#[rustc_legacy_const_generics(1)]
33206#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33207pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
33208 static_assert!(N >= 1 && N <= 32);
33209 unsafe extern "unadjusted" {
33210 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
33211 fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
33212 }
33213 unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
33214}
33215#[doc = "Signed saturating rounded shift right narrow"]
33216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
33217#[inline]
33218#[target_feature(enable = "neon")]
33219#[cfg(not(target_arch = "arm"))]
33220#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
33221#[rustc_legacy_const_generics(1)]
33222#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33223pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
33224 static_assert!(N >= 1 && N <= 8);
33225 unsafe extern "unadjusted" {
33226 #[cfg_attr(
33227 any(target_arch = "aarch64", target_arch = "arm64ec"),
33228 link_name = "llvm.aarch64.neon.sqrshrn.v8i8"
33229 )]
33230 fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
33231 }
33232 unsafe { _vqrshrn_n_s16(a, N) }
33233}
33234#[doc = "Signed saturating rounded shift right narrow"]
33235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
33236#[inline]
33237#[target_feature(enable = "neon")]
33238#[cfg(not(target_arch = "arm"))]
33239#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
33240#[rustc_legacy_const_generics(1)]
33241#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33242pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
33243 static_assert!(N >= 1 && N <= 16);
33244 unsafe extern "unadjusted" {
33245 #[cfg_attr(
33246 any(target_arch = "aarch64", target_arch = "arm64ec"),
33247 link_name = "llvm.aarch64.neon.sqrshrn.v4i16"
33248 )]
33249 fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
33250 }
33251 unsafe { _vqrshrn_n_s32(a, N) }
33252}
33253#[doc = "Signed saturating rounded shift right narrow"]
33254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
33255#[inline]
33256#[target_feature(enable = "neon")]
33257#[cfg(not(target_arch = "arm"))]
33258#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
33259#[rustc_legacy_const_generics(1)]
33260#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33261pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
33262 static_assert!(N >= 1 && N <= 32);
33263 unsafe extern "unadjusted" {
33264 #[cfg_attr(
33265 any(target_arch = "aarch64", target_arch = "arm64ec"),
33266 link_name = "llvm.aarch64.neon.sqrshrn.v2i32"
33267 )]
33268 fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
33269 }
33270 unsafe { _vqrshrn_n_s64(a, N) }
33271}
33272#[doc = "Unsigned signed saturating rounded shift right narrow"]
33273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
33274#[inline]
33275#[cfg(target_arch = "arm")]
33276#[target_feature(enable = "neon,v7")]
33277#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
33278#[rustc_legacy_const_generics(1)]
33279#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33280pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
33281 static_assert!(N >= 1 && N <= 8);
33282 unsafe extern "unadjusted" {
33283 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
33284 fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
33285 }
33286 unsafe {
33287 _vqrshrn_n_u16(
33288 a,
33289 const {
33290 uint16x8_t([
33291 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
33292 -N as u16,
33293 ])
33294 },
33295 )
33296 }
33297}
33298#[doc = "Unsigned signed saturating rounded shift right narrow"]
33299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
33300#[inline]
33301#[cfg(target_arch = "arm")]
33302#[target_feature(enable = "neon,v7")]
33303#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
33304#[rustc_legacy_const_generics(1)]
33305#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33306pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
33307 static_assert!(N >= 1 && N <= 16);
33308 unsafe extern "unadjusted" {
33309 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
33310 fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
33311 }
33312 unsafe {
33313 _vqrshrn_n_u32(
33314 a,
33315 const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
33316 )
33317 }
33318}
33319#[doc = "Unsigned signed saturating rounded shift right narrow"]
33320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
33321#[inline]
33322#[cfg(target_arch = "arm")]
33323#[target_feature(enable = "neon,v7")]
33324#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
33325#[rustc_legacy_const_generics(1)]
33326#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33327pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
33328 static_assert!(N >= 1 && N <= 32);
33329 unsafe extern "unadjusted" {
33330 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
33331 fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
33332 }
33333 unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
33334}
33335#[doc = "Unsigned signed saturating rounded shift right narrow"]
33336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
33337#[inline]
33338#[target_feature(enable = "neon")]
33339#[cfg(not(target_arch = "arm"))]
33340#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
33341#[rustc_legacy_const_generics(1)]
33342#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33343pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
33344 static_assert!(N >= 1 && N <= 8);
33345 unsafe extern "unadjusted" {
33346 #[cfg_attr(
33347 any(target_arch = "aarch64", target_arch = "arm64ec"),
33348 link_name = "llvm.aarch64.neon.uqrshrn.v8i8"
33349 )]
33350 fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
33351 }
33352 unsafe { _vqrshrn_n_u16(a, N) }
33353}
33354#[doc = "Unsigned signed saturating rounded shift right narrow"]
33355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
33356#[inline]
33357#[target_feature(enable = "neon")]
33358#[cfg(not(target_arch = "arm"))]
33359#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
33360#[rustc_legacy_const_generics(1)]
33361#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33362pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
33363 static_assert!(N >= 1 && N <= 16);
33364 unsafe extern "unadjusted" {
33365 #[cfg_attr(
33366 any(target_arch = "aarch64", target_arch = "arm64ec"),
33367 link_name = "llvm.aarch64.neon.uqrshrn.v4i16"
33368 )]
33369 fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
33370 }
33371 unsafe { _vqrshrn_n_u32(a, N) }
33372}
33373#[doc = "Unsigned signed saturating rounded shift right narrow"]
33374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
33375#[inline]
33376#[target_feature(enable = "neon")]
33377#[cfg(not(target_arch = "arm"))]
33378#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
33379#[rustc_legacy_const_generics(1)]
33380#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33381pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
33382 static_assert!(N >= 1 && N <= 32);
33383 unsafe extern "unadjusted" {
33384 #[cfg_attr(
33385 any(target_arch = "aarch64", target_arch = "arm64ec"),
33386 link_name = "llvm.aarch64.neon.uqrshrn.v2i32"
33387 )]
33388 fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
33389 }
33390 unsafe { _vqrshrn_n_u64(a, N) }
33391}
33392#[doc = "Signed saturating rounded shift right unsigned narrow"]
33393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
33394#[inline]
33395#[cfg(target_arch = "arm")]
33396#[target_feature(enable = "neon,v7")]
33397#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
33398#[rustc_legacy_const_generics(1)]
33399#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33400pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
33401 static_assert!(N >= 1 && N <= 8);
33402 unsafe extern "unadjusted" {
33403 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
33404 fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
33405 }
33406 unsafe {
33407 _vqrshrun_n_s16(
33408 a,
33409 const {
33410 int16x8_t([
33411 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
33412 -N as i16,
33413 ])
33414 },
33415 )
33416 }
33417}
33418#[doc = "Signed saturating rounded shift right unsigned narrow"]
33419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
33420#[inline]
33421#[cfg(target_arch = "arm")]
33422#[target_feature(enable = "neon,v7")]
33423#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
33424#[rustc_legacy_const_generics(1)]
33425#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33426pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
33427 static_assert!(N >= 1 && N <= 16);
33428 unsafe extern "unadjusted" {
33429 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
33430 fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
33431 }
33432 unsafe {
33433 _vqrshrun_n_s32(
33434 a,
33435 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
33436 )
33437 }
33438}
33439#[doc = "Signed saturating rounded shift right unsigned narrow"]
33440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
33441#[inline]
33442#[cfg(target_arch = "arm")]
33443#[target_feature(enable = "neon,v7")]
33444#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
33445#[rustc_legacy_const_generics(1)]
33446#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
33447pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
33448 static_assert!(N >= 1 && N <= 32);
33449 unsafe extern "unadjusted" {
33450 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
33451 fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
33452 }
33453 unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
33454}
33455#[doc = "Signed saturating rounded shift right unsigned narrow"]
33456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
33457#[inline]
33458#[target_feature(enable = "neon")]
33459#[cfg(not(target_arch = "arm"))]
33460#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
33461#[rustc_legacy_const_generics(1)]
33462#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33463pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
33464 static_assert!(N >= 1 && N <= 8);
33465 unsafe extern "unadjusted" {
33466 #[cfg_attr(
33467 any(target_arch = "aarch64", target_arch = "arm64ec"),
33468 link_name = "llvm.aarch64.neon.sqrshrun.v8i8"
33469 )]
33470 fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
33471 }
33472 unsafe { _vqrshrun_n_s16(a, N) }
33473}
33474#[doc = "Signed saturating rounded shift right unsigned narrow"]
33475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
33476#[inline]
33477#[target_feature(enable = "neon")]
33478#[cfg(not(target_arch = "arm"))]
33479#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
33480#[rustc_legacy_const_generics(1)]
33481#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33482pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
33483 static_assert!(N >= 1 && N <= 16);
33484 unsafe extern "unadjusted" {
33485 #[cfg_attr(
33486 any(target_arch = "aarch64", target_arch = "arm64ec"),
33487 link_name = "llvm.aarch64.neon.sqrshrun.v4i16"
33488 )]
33489 fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
33490 }
33491 unsafe { _vqrshrun_n_s32(a, N) }
33492}
33493#[doc = "Signed saturating rounded shift right unsigned narrow"]
33494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
33495#[inline]
33496#[target_feature(enable = "neon")]
33497#[cfg(not(target_arch = "arm"))]
33498#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
33499#[rustc_legacy_const_generics(1)]
33500#[stable(feature = "neon_intrinsics", since = "1.59.0")]
33501pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
33502 static_assert!(N >= 1 && N <= 32);
33503 unsafe extern "unadjusted" {
33504 #[cfg_attr(
33505 any(target_arch = "aarch64", target_arch = "arm64ec"),
33506 link_name = "llvm.aarch64.neon.sqrshrun.v2i32"
33507 )]
33508 fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
33509 }
33510 unsafe { _vqrshrun_n_s64(a, N) }
33511}
33512#[doc = "Signed saturating shift left"]
33513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
33514#[inline]
33515#[target_feature(enable = "neon")]
33516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33518#[cfg_attr(
33519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33520 assert_instr(sqshl, N = 2)
33521)]
33522#[rustc_legacy_const_generics(1)]
33523#[cfg_attr(
33524 not(target_arch = "arm"),
33525 stable(feature = "neon_intrinsics", since = "1.59.0")
33526)]
33527#[cfg_attr(
33528 target_arch = "arm",
33529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33530)]
33531pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
33532 static_assert_uimm_bits!(N, 3);
33533 vqshl_s8(a, vdup_n_s8(N as _))
33534}
33535#[doc = "Signed saturating shift left"]
33536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
33537#[inline]
33538#[target_feature(enable = "neon")]
33539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33541#[cfg_attr(
33542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33543 assert_instr(sqshl, N = 2)
33544)]
33545#[rustc_legacy_const_generics(1)]
33546#[cfg_attr(
33547 not(target_arch = "arm"),
33548 stable(feature = "neon_intrinsics", since = "1.59.0")
33549)]
33550#[cfg_attr(
33551 target_arch = "arm",
33552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33553)]
33554pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
33555 static_assert_uimm_bits!(N, 3);
33556 vqshlq_s8(a, vdupq_n_s8(N as _))
33557}
33558#[doc = "Signed saturating shift left"]
33559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
33560#[inline]
33561#[target_feature(enable = "neon")]
33562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33564#[cfg_attr(
33565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33566 assert_instr(sqshl, N = 2)
33567)]
33568#[rustc_legacy_const_generics(1)]
33569#[cfg_attr(
33570 not(target_arch = "arm"),
33571 stable(feature = "neon_intrinsics", since = "1.59.0")
33572)]
33573#[cfg_attr(
33574 target_arch = "arm",
33575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33576)]
33577pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
33578 static_assert_uimm_bits!(N, 4);
33579 vqshl_s16(a, vdup_n_s16(N as _))
33580}
33581#[doc = "Signed saturating shift left"]
33582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
33583#[inline]
33584#[target_feature(enable = "neon")]
33585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33587#[cfg_attr(
33588 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33589 assert_instr(sqshl, N = 2)
33590)]
33591#[rustc_legacy_const_generics(1)]
33592#[cfg_attr(
33593 not(target_arch = "arm"),
33594 stable(feature = "neon_intrinsics", since = "1.59.0")
33595)]
33596#[cfg_attr(
33597 target_arch = "arm",
33598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33599)]
33600pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
33601 static_assert_uimm_bits!(N, 4);
33602 vqshlq_s16(a, vdupq_n_s16(N as _))
33603}
33604#[doc = "Signed saturating shift left"]
33605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
33606#[inline]
33607#[target_feature(enable = "neon")]
33608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33610#[cfg_attr(
33611 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33612 assert_instr(sqshl, N = 2)
33613)]
33614#[rustc_legacy_const_generics(1)]
33615#[cfg_attr(
33616 not(target_arch = "arm"),
33617 stable(feature = "neon_intrinsics", since = "1.59.0")
33618)]
33619#[cfg_attr(
33620 target_arch = "arm",
33621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33622)]
33623pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
33624 static_assert_uimm_bits!(N, 5);
33625 vqshl_s32(a, vdup_n_s32(N as _))
33626}
33627#[doc = "Signed saturating shift left"]
33628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
33629#[inline]
33630#[target_feature(enable = "neon")]
33631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33633#[cfg_attr(
33634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33635 assert_instr(sqshl, N = 2)
33636)]
33637#[rustc_legacy_const_generics(1)]
33638#[cfg_attr(
33639 not(target_arch = "arm"),
33640 stable(feature = "neon_intrinsics", since = "1.59.0")
33641)]
33642#[cfg_attr(
33643 target_arch = "arm",
33644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33645)]
33646pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
33647 static_assert_uimm_bits!(N, 5);
33648 vqshlq_s32(a, vdupq_n_s32(N as _))
33649}
33650#[doc = "Signed saturating shift left"]
33651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
33652#[inline]
33653#[target_feature(enable = "neon")]
33654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33656#[cfg_attr(
33657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33658 assert_instr(sqshl, N = 2)
33659)]
33660#[rustc_legacy_const_generics(1)]
33661#[cfg_attr(
33662 not(target_arch = "arm"),
33663 stable(feature = "neon_intrinsics", since = "1.59.0")
33664)]
33665#[cfg_attr(
33666 target_arch = "arm",
33667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33668)]
33669pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
33670 static_assert_uimm_bits!(N, 6);
33671 vqshl_s64(a, vdup_n_s64(N as _))
33672}
33673#[doc = "Signed saturating shift left"]
33674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
33675#[inline]
33676#[target_feature(enable = "neon")]
33677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33679#[cfg_attr(
33680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33681 assert_instr(sqshl, N = 2)
33682)]
33683#[rustc_legacy_const_generics(1)]
33684#[cfg_attr(
33685 not(target_arch = "arm"),
33686 stable(feature = "neon_intrinsics", since = "1.59.0")
33687)]
33688#[cfg_attr(
33689 target_arch = "arm",
33690 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33691)]
33692pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
33693 static_assert_uimm_bits!(N, 6);
33694 vqshlq_s64(a, vdupq_n_s64(N as _))
33695}
33696#[doc = "Unsigned saturating shift left"]
33697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
33698#[inline]
33699#[target_feature(enable = "neon")]
33700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33702#[cfg_attr(
33703 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33704 assert_instr(uqshl, N = 2)
33705)]
33706#[rustc_legacy_const_generics(1)]
33707#[cfg_attr(
33708 not(target_arch = "arm"),
33709 stable(feature = "neon_intrinsics", since = "1.59.0")
33710)]
33711#[cfg_attr(
33712 target_arch = "arm",
33713 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33714)]
33715pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
33716 static_assert_uimm_bits!(N, 3);
33717 vqshl_u8(a, vdup_n_s8(N as _))
33718}
33719#[doc = "Unsigned saturating shift left"]
33720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
33721#[inline]
33722#[target_feature(enable = "neon")]
33723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33725#[cfg_attr(
33726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33727 assert_instr(uqshl, N = 2)
33728)]
33729#[rustc_legacy_const_generics(1)]
33730#[cfg_attr(
33731 not(target_arch = "arm"),
33732 stable(feature = "neon_intrinsics", since = "1.59.0")
33733)]
33734#[cfg_attr(
33735 target_arch = "arm",
33736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33737)]
33738pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
33739 static_assert_uimm_bits!(N, 3);
33740 vqshlq_u8(a, vdupq_n_s8(N as _))
33741}
33742#[doc = "Unsigned saturating shift left"]
33743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
33744#[inline]
33745#[target_feature(enable = "neon")]
33746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33748#[cfg_attr(
33749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33750 assert_instr(uqshl, N = 2)
33751)]
33752#[rustc_legacy_const_generics(1)]
33753#[cfg_attr(
33754 not(target_arch = "arm"),
33755 stable(feature = "neon_intrinsics", since = "1.59.0")
33756)]
33757#[cfg_attr(
33758 target_arch = "arm",
33759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33760)]
33761pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
33762 static_assert_uimm_bits!(N, 4);
33763 vqshl_u16(a, vdup_n_s16(N as _))
33764}
33765#[doc = "Unsigned saturating shift left"]
33766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
33767#[inline]
33768#[target_feature(enable = "neon")]
33769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33771#[cfg_attr(
33772 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33773 assert_instr(uqshl, N = 2)
33774)]
33775#[rustc_legacy_const_generics(1)]
33776#[cfg_attr(
33777 not(target_arch = "arm"),
33778 stable(feature = "neon_intrinsics", since = "1.59.0")
33779)]
33780#[cfg_attr(
33781 target_arch = "arm",
33782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33783)]
33784pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
33785 static_assert_uimm_bits!(N, 4);
33786 vqshlq_u16(a, vdupq_n_s16(N as _))
33787}
33788#[doc = "Unsigned saturating shift left"]
33789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
33790#[inline]
33791#[target_feature(enable = "neon")]
33792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33794#[cfg_attr(
33795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33796 assert_instr(uqshl, N = 2)
33797)]
33798#[rustc_legacy_const_generics(1)]
33799#[cfg_attr(
33800 not(target_arch = "arm"),
33801 stable(feature = "neon_intrinsics", since = "1.59.0")
33802)]
33803#[cfg_attr(
33804 target_arch = "arm",
33805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33806)]
33807pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
33808 static_assert_uimm_bits!(N, 5);
33809 vqshl_u32(a, vdup_n_s32(N as _))
33810}
33811#[doc = "Unsigned saturating shift left"]
33812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
33813#[inline]
33814#[target_feature(enable = "neon")]
33815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33817#[cfg_attr(
33818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33819 assert_instr(uqshl, N = 2)
33820)]
33821#[rustc_legacy_const_generics(1)]
33822#[cfg_attr(
33823 not(target_arch = "arm"),
33824 stable(feature = "neon_intrinsics", since = "1.59.0")
33825)]
33826#[cfg_attr(
33827 target_arch = "arm",
33828 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33829)]
33830pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
33831 static_assert_uimm_bits!(N, 5);
33832 vqshlq_u32(a, vdupq_n_s32(N as _))
33833}
33834#[doc = "Unsigned saturating shift left"]
33835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
33836#[inline]
33837#[target_feature(enable = "neon")]
33838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33840#[cfg_attr(
33841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33842 assert_instr(uqshl, N = 2)
33843)]
33844#[rustc_legacy_const_generics(1)]
33845#[cfg_attr(
33846 not(target_arch = "arm"),
33847 stable(feature = "neon_intrinsics", since = "1.59.0")
33848)]
33849#[cfg_attr(
33850 target_arch = "arm",
33851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33852)]
33853pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
33854 static_assert_uimm_bits!(N, 6);
33855 vqshl_u64(a, vdup_n_s64(N as _))
33856}
33857#[doc = "Unsigned saturating shift left"]
33858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
33859#[inline]
33860#[target_feature(enable = "neon")]
33861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33862#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
33863#[cfg_attr(
33864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33865 assert_instr(uqshl, N = 2)
33866)]
33867#[rustc_legacy_const_generics(1)]
33868#[cfg_attr(
33869 not(target_arch = "arm"),
33870 stable(feature = "neon_intrinsics", since = "1.59.0")
33871)]
33872#[cfg_attr(
33873 target_arch = "arm",
33874 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33875)]
33876pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
33877 static_assert_uimm_bits!(N, 6);
33878 vqshlq_u64(a, vdupq_n_s64(N as _))
33879}
33880#[doc = "Signed saturating shift left"]
33881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
33882#[inline]
33883#[target_feature(enable = "neon")]
33884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33885#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
33886#[cfg_attr(
33887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33888 assert_instr(sqshl)
33889)]
33890#[cfg_attr(
33891 not(target_arch = "arm"),
33892 stable(feature = "neon_intrinsics", since = "1.59.0")
33893)]
33894#[cfg_attr(
33895 target_arch = "arm",
33896 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33897)]
33898pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
33899 unsafe extern "unadjusted" {
33900 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")]
33901 #[cfg_attr(
33902 any(target_arch = "aarch64", target_arch = "arm64ec"),
33903 link_name = "llvm.aarch64.neon.sqshl.v8i8"
33904 )]
33905 fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
33906 }
33907 unsafe { _vqshl_s8(a, b) }
33908}
33909#[doc = "Signed saturating shift left"]
33910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
33911#[inline]
33912#[target_feature(enable = "neon")]
33913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
33915#[cfg_attr(
33916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33917 assert_instr(sqshl)
33918)]
33919#[cfg_attr(
33920 not(target_arch = "arm"),
33921 stable(feature = "neon_intrinsics", since = "1.59.0")
33922)]
33923#[cfg_attr(
33924 target_arch = "arm",
33925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33926)]
33927pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
33928 unsafe extern "unadjusted" {
33929 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")]
33930 #[cfg_attr(
33931 any(target_arch = "aarch64", target_arch = "arm64ec"),
33932 link_name = "llvm.aarch64.neon.sqshl.v16i8"
33933 )]
33934 fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
33935 }
33936 unsafe { _vqshlq_s8(a, b) }
33937}
33938#[doc = "Signed saturating shift left"]
33939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
33940#[inline]
33941#[target_feature(enable = "neon")]
33942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
33944#[cfg_attr(
33945 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33946 assert_instr(sqshl)
33947)]
33948#[cfg_attr(
33949 not(target_arch = "arm"),
33950 stable(feature = "neon_intrinsics", since = "1.59.0")
33951)]
33952#[cfg_attr(
33953 target_arch = "arm",
33954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33955)]
33956pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
33957 unsafe extern "unadjusted" {
33958 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")]
33959 #[cfg_attr(
33960 any(target_arch = "aarch64", target_arch = "arm64ec"),
33961 link_name = "llvm.aarch64.neon.sqshl.v4i16"
33962 )]
33963 fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
33964 }
33965 unsafe { _vqshl_s16(a, b) }
33966}
33967#[doc = "Signed saturating shift left"]
33968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
33969#[inline]
33970#[target_feature(enable = "neon")]
33971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
33973#[cfg_attr(
33974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33975 assert_instr(sqshl)
33976)]
33977#[cfg_attr(
33978 not(target_arch = "arm"),
33979 stable(feature = "neon_intrinsics", since = "1.59.0")
33980)]
33981#[cfg_attr(
33982 target_arch = "arm",
33983 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33984)]
33985pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33986 unsafe extern "unadjusted" {
33987 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")]
33988 #[cfg_attr(
33989 any(target_arch = "aarch64", target_arch = "arm64ec"),
33990 link_name = "llvm.aarch64.neon.sqshl.v8i16"
33991 )]
33992 fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
33993 }
33994 unsafe { _vqshlq_s16(a, b) }
33995}
33996#[doc = "Signed saturating shift left"]
33997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
33998#[inline]
33999#[target_feature(enable = "neon")]
34000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34002#[cfg_attr(
34003 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34004 assert_instr(sqshl)
34005)]
34006#[cfg_attr(
34007 not(target_arch = "arm"),
34008 stable(feature = "neon_intrinsics", since = "1.59.0")
34009)]
34010#[cfg_attr(
34011 target_arch = "arm",
34012 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34013)]
34014pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
34015 unsafe extern "unadjusted" {
34016 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")]
34017 #[cfg_attr(
34018 any(target_arch = "aarch64", target_arch = "arm64ec"),
34019 link_name = "llvm.aarch64.neon.sqshl.v2i32"
34020 )]
34021 fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
34022 }
34023 unsafe { _vqshl_s32(a, b) }
34024}
34025#[doc = "Signed saturating shift left"]
34026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
34027#[inline]
34028#[target_feature(enable = "neon")]
34029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34030#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34031#[cfg_attr(
34032 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34033 assert_instr(sqshl)
34034)]
34035#[cfg_attr(
34036 not(target_arch = "arm"),
34037 stable(feature = "neon_intrinsics", since = "1.59.0")
34038)]
34039#[cfg_attr(
34040 target_arch = "arm",
34041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34042)]
34043pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
34044 unsafe extern "unadjusted" {
34045 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")]
34046 #[cfg_attr(
34047 any(target_arch = "aarch64", target_arch = "arm64ec"),
34048 link_name = "llvm.aarch64.neon.sqshl.v4i32"
34049 )]
34050 fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
34051 }
34052 unsafe { _vqshlq_s32(a, b) }
34053}
34054#[doc = "Signed saturating shift left"]
34055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
34056#[inline]
34057#[target_feature(enable = "neon")]
34058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34060#[cfg_attr(
34061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34062 assert_instr(sqshl)
34063)]
34064#[cfg_attr(
34065 not(target_arch = "arm"),
34066 stable(feature = "neon_intrinsics", since = "1.59.0")
34067)]
34068#[cfg_attr(
34069 target_arch = "arm",
34070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34071)]
34072pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
34073 unsafe extern "unadjusted" {
34074 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")]
34075 #[cfg_attr(
34076 any(target_arch = "aarch64", target_arch = "arm64ec"),
34077 link_name = "llvm.aarch64.neon.sqshl.v1i64"
34078 )]
34079 fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
34080 }
34081 unsafe { _vqshl_s64(a, b) }
34082}
34083#[doc = "Signed saturating shift left"]
34084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
34085#[inline]
34086#[target_feature(enable = "neon")]
34087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34089#[cfg_attr(
34090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34091 assert_instr(sqshl)
34092)]
34093#[cfg_attr(
34094 not(target_arch = "arm"),
34095 stable(feature = "neon_intrinsics", since = "1.59.0")
34096)]
34097#[cfg_attr(
34098 target_arch = "arm",
34099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34100)]
34101pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
34102 unsafe extern "unadjusted" {
34103 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")]
34104 #[cfg_attr(
34105 any(target_arch = "aarch64", target_arch = "arm64ec"),
34106 link_name = "llvm.aarch64.neon.sqshl.v2i64"
34107 )]
34108 fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
34109 }
34110 unsafe { _vqshlq_s64(a, b) }
34111}
34112#[doc = "Unsigned saturating shift left"]
34113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
34114#[inline]
34115#[target_feature(enable = "neon")]
34116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34118#[cfg_attr(
34119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34120 assert_instr(uqshl)
34121)]
34122#[cfg_attr(
34123 not(target_arch = "arm"),
34124 stable(feature = "neon_intrinsics", since = "1.59.0")
34125)]
34126#[cfg_attr(
34127 target_arch = "arm",
34128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34129)]
34130pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
34131 unsafe extern "unadjusted" {
34132 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")]
34133 #[cfg_attr(
34134 any(target_arch = "aarch64", target_arch = "arm64ec"),
34135 link_name = "llvm.aarch64.neon.uqshl.v8i8"
34136 )]
34137 fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
34138 }
34139 unsafe { _vqshl_u8(a, b) }
34140}
34141#[doc = "Unsigned saturating shift left"]
34142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
34143#[inline]
34144#[target_feature(enable = "neon")]
34145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34147#[cfg_attr(
34148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34149 assert_instr(uqshl)
34150)]
34151#[cfg_attr(
34152 not(target_arch = "arm"),
34153 stable(feature = "neon_intrinsics", since = "1.59.0")
34154)]
34155#[cfg_attr(
34156 target_arch = "arm",
34157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34158)]
34159pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
34160 unsafe extern "unadjusted" {
34161 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")]
34162 #[cfg_attr(
34163 any(target_arch = "aarch64", target_arch = "arm64ec"),
34164 link_name = "llvm.aarch64.neon.uqshl.v16i8"
34165 )]
34166 fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
34167 }
34168 unsafe { _vqshlq_u8(a, b) }
34169}
34170#[doc = "Unsigned saturating shift left"]
34171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
34172#[inline]
34173#[target_feature(enable = "neon")]
34174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34176#[cfg_attr(
34177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34178 assert_instr(uqshl)
34179)]
34180#[cfg_attr(
34181 not(target_arch = "arm"),
34182 stable(feature = "neon_intrinsics", since = "1.59.0")
34183)]
34184#[cfg_attr(
34185 target_arch = "arm",
34186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34187)]
34188pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
34189 unsafe extern "unadjusted" {
34190 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")]
34191 #[cfg_attr(
34192 any(target_arch = "aarch64", target_arch = "arm64ec"),
34193 link_name = "llvm.aarch64.neon.uqshl.v4i16"
34194 )]
34195 fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
34196 }
34197 unsafe { _vqshl_u16(a, b) }
34198}
34199#[doc = "Unsigned saturating shift left"]
34200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
34201#[inline]
34202#[target_feature(enable = "neon")]
34203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34205#[cfg_attr(
34206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34207 assert_instr(uqshl)
34208)]
34209#[cfg_attr(
34210 not(target_arch = "arm"),
34211 stable(feature = "neon_intrinsics", since = "1.59.0")
34212)]
34213#[cfg_attr(
34214 target_arch = "arm",
34215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34216)]
34217pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
34218 unsafe extern "unadjusted" {
34219 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")]
34220 #[cfg_attr(
34221 any(target_arch = "aarch64", target_arch = "arm64ec"),
34222 link_name = "llvm.aarch64.neon.uqshl.v8i16"
34223 )]
34224 fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
34225 }
34226 unsafe { _vqshlq_u16(a, b) }
34227}
34228#[doc = "Unsigned saturating shift left"]
34229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
34230#[inline]
34231#[target_feature(enable = "neon")]
34232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34234#[cfg_attr(
34235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34236 assert_instr(uqshl)
34237)]
34238#[cfg_attr(
34239 not(target_arch = "arm"),
34240 stable(feature = "neon_intrinsics", since = "1.59.0")
34241)]
34242#[cfg_attr(
34243 target_arch = "arm",
34244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34245)]
34246pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
34247 unsafe extern "unadjusted" {
34248 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")]
34249 #[cfg_attr(
34250 any(target_arch = "aarch64", target_arch = "arm64ec"),
34251 link_name = "llvm.aarch64.neon.uqshl.v2i32"
34252 )]
34253 fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
34254 }
34255 unsafe { _vqshl_u32(a, b) }
34256}
34257#[doc = "Unsigned saturating shift left"]
34258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
34259#[inline]
34260#[target_feature(enable = "neon")]
34261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34263#[cfg_attr(
34264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34265 assert_instr(uqshl)
34266)]
34267#[cfg_attr(
34268 not(target_arch = "arm"),
34269 stable(feature = "neon_intrinsics", since = "1.59.0")
34270)]
34271#[cfg_attr(
34272 target_arch = "arm",
34273 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34274)]
34275pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
34276 unsafe extern "unadjusted" {
34277 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")]
34278 #[cfg_attr(
34279 any(target_arch = "aarch64", target_arch = "arm64ec"),
34280 link_name = "llvm.aarch64.neon.uqshl.v4i32"
34281 )]
34282 fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
34283 }
34284 unsafe { _vqshlq_u32(a, b) }
34285}
34286#[doc = "Unsigned saturating shift left"]
34287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
34288#[inline]
34289#[target_feature(enable = "neon")]
34290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34292#[cfg_attr(
34293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34294 assert_instr(uqshl)
34295)]
34296#[cfg_attr(
34297 not(target_arch = "arm"),
34298 stable(feature = "neon_intrinsics", since = "1.59.0")
34299)]
34300#[cfg_attr(
34301 target_arch = "arm",
34302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34303)]
34304pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
34305 unsafe extern "unadjusted" {
34306 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")]
34307 #[cfg_attr(
34308 any(target_arch = "aarch64", target_arch = "arm64ec"),
34309 link_name = "llvm.aarch64.neon.uqshl.v1i64"
34310 )]
34311 fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
34312 }
34313 unsafe { _vqshl_u64(a, b) }
34314}
34315#[doc = "Unsigned saturating shift left"]
34316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
34317#[inline]
34318#[target_feature(enable = "neon")]
34319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
34321#[cfg_attr(
34322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34323 assert_instr(uqshl)
34324)]
34325#[cfg_attr(
34326 not(target_arch = "arm"),
34327 stable(feature = "neon_intrinsics", since = "1.59.0")
34328)]
34329#[cfg_attr(
34330 target_arch = "arm",
34331 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34332)]
34333pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
34334 unsafe extern "unadjusted" {
34335 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")]
34336 #[cfg_attr(
34337 any(target_arch = "aarch64", target_arch = "arm64ec"),
34338 link_name = "llvm.aarch64.neon.uqshl.v2i64"
34339 )]
34340 fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
34341 }
34342 unsafe { _vqshlq_u64(a, b) }
34343}
34344#[doc = "Signed saturating shift left unsigned"]
34345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
34346#[inline]
34347#[cfg(target_arch = "arm")]
34348#[target_feature(enable = "neon,v7")]
34349#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34350#[rustc_legacy_const_generics(1)]
34351#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34352pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
34353 static_assert_uimm_bits!(N, 3);
34354 unsafe extern "unadjusted" {
34355 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
34356 fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
34357 }
34358 unsafe {
34359 _vqshlu_n_s8(
34360 a,
34361 const {
34362 int8x8_t([
34363 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
34364 ])
34365 },
34366 )
34367 }
34368}
34369#[doc = "Signed saturating shift left unsigned"]
34370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
34371#[inline]
34372#[cfg(target_arch = "arm")]
34373#[target_feature(enable = "neon,v7")]
34374#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34375#[rustc_legacy_const_generics(1)]
34376#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34377pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
34378 static_assert_uimm_bits!(N, 3);
34379 unsafe extern "unadjusted" {
34380 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
34381 fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
34382 }
34383 unsafe {
34384 _vqshluq_n_s8(
34385 a,
34386 const {
34387 int8x16_t([
34388 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
34389 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
34390 ])
34391 },
34392 )
34393 }
34394}
34395#[doc = "Signed saturating shift left unsigned"]
34396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
34397#[inline]
34398#[cfg(target_arch = "arm")]
34399#[target_feature(enable = "neon,v7")]
34400#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34401#[rustc_legacy_const_generics(1)]
34402#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34403pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
34404 static_assert_uimm_bits!(N, 4);
34405 unsafe extern "unadjusted" {
34406 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
34407 fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
34408 }
34409 unsafe {
34410 _vqshlu_n_s16(
34411 a,
34412 const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
34413 )
34414 }
34415}
34416#[doc = "Signed saturating shift left unsigned"]
34417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
34418#[inline]
34419#[cfg(target_arch = "arm")]
34420#[target_feature(enable = "neon,v7")]
34421#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34422#[rustc_legacy_const_generics(1)]
34423#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34424pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
34425 static_assert_uimm_bits!(N, 4);
34426 unsafe extern "unadjusted" {
34427 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
34428 fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
34429 }
34430 unsafe {
34431 _vqshluq_n_s16(
34432 a,
34433 const {
34434 int16x8_t([
34435 N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
34436 ])
34437 },
34438 )
34439 }
34440}
34441#[doc = "Signed saturating shift left unsigned"]
34442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
34443#[inline]
34444#[cfg(target_arch = "arm")]
34445#[target_feature(enable = "neon,v7")]
34446#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34447#[rustc_legacy_const_generics(1)]
34448#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34449pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
34450 static_assert_uimm_bits!(N, 5);
34451 unsafe extern "unadjusted" {
34452 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
34453 fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
34454 }
34455 unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
34456}
34457#[doc = "Signed saturating shift left unsigned"]
34458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
34459#[inline]
34460#[cfg(target_arch = "arm")]
34461#[target_feature(enable = "neon,v7")]
34462#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34463#[rustc_legacy_const_generics(1)]
34464#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34465pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
34466 static_assert_uimm_bits!(N, 5);
34467 unsafe extern "unadjusted" {
34468 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
34469 fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
34470 }
34471 unsafe {
34472 _vqshluq_n_s32(
34473 a,
34474 const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
34475 )
34476 }
34477}
34478#[doc = "Signed saturating shift left unsigned"]
34479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
34480#[inline]
34481#[cfg(target_arch = "arm")]
34482#[target_feature(enable = "neon,v7")]
34483#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34484#[rustc_legacy_const_generics(1)]
34485#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34486pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
34487 static_assert_uimm_bits!(N, 6);
34488 unsafe extern "unadjusted" {
34489 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")]
34490 fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
34491 }
34492 unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
34493}
34494#[doc = "Signed saturating shift left unsigned"]
34495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
34496#[inline]
34497#[cfg(target_arch = "arm")]
34498#[target_feature(enable = "neon,v7")]
34499#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
34500#[rustc_legacy_const_generics(1)]
34501#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34502pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
34503 static_assert_uimm_bits!(N, 6);
34504 unsafe extern "unadjusted" {
34505 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
34506 fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
34507 }
34508 unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
34509}
34510#[doc = "Signed saturating shift left unsigned"]
34511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
34512#[inline]
34513#[target_feature(enable = "neon")]
34514#[cfg(not(target_arch = "arm"))]
34515#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34516#[rustc_legacy_const_generics(1)]
34517#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34518pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
34519 static_assert_uimm_bits!(N, 3);
34520 unsafe extern "unadjusted" {
34521 #[cfg_attr(
34522 any(target_arch = "aarch64", target_arch = "arm64ec"),
34523 link_name = "llvm.aarch64.neon.sqshlu.v8i8"
34524 )]
34525 fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
34526 }
34527 unsafe {
34528 _vqshlu_n_s8(
34529 a,
34530 const {
34531 int8x8_t([
34532 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
34533 ])
34534 },
34535 )
34536 }
34537}
34538#[doc = "Signed saturating shift left unsigned"]
34539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
34540#[inline]
34541#[target_feature(enable = "neon")]
34542#[cfg(not(target_arch = "arm"))]
34543#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34544#[rustc_legacy_const_generics(1)]
34545#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34546pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
34547 static_assert_uimm_bits!(N, 3);
34548 unsafe extern "unadjusted" {
34549 #[cfg_attr(
34550 any(target_arch = "aarch64", target_arch = "arm64ec"),
34551 link_name = "llvm.aarch64.neon.sqshlu.v16i8"
34552 )]
34553 fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
34554 }
34555 unsafe {
34556 _vqshluq_n_s8(
34557 a,
34558 const {
34559 int8x16_t([
34560 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
34561 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
34562 ])
34563 },
34564 )
34565 }
34566}
34567#[doc = "Signed saturating shift left unsigned"]
34568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
34569#[inline]
34570#[target_feature(enable = "neon")]
34571#[cfg(not(target_arch = "arm"))]
34572#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34573#[rustc_legacy_const_generics(1)]
34574#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34575pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
34576 static_assert_uimm_bits!(N, 4);
34577 unsafe extern "unadjusted" {
34578 #[cfg_attr(
34579 any(target_arch = "aarch64", target_arch = "arm64ec"),
34580 link_name = "llvm.aarch64.neon.sqshlu.v4i16"
34581 )]
34582 fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
34583 }
34584 unsafe {
34585 _vqshlu_n_s16(
34586 a,
34587 const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
34588 )
34589 }
34590}
34591#[doc = "Signed saturating shift left unsigned"]
34592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
34593#[inline]
34594#[target_feature(enable = "neon")]
34595#[cfg(not(target_arch = "arm"))]
34596#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34597#[rustc_legacy_const_generics(1)]
34598#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34599pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
34600 static_assert_uimm_bits!(N, 4);
34601 unsafe extern "unadjusted" {
34602 #[cfg_attr(
34603 any(target_arch = "aarch64", target_arch = "arm64ec"),
34604 link_name = "llvm.aarch64.neon.sqshlu.v8i16"
34605 )]
34606 fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
34607 }
34608 unsafe {
34609 _vqshluq_n_s16(
34610 a,
34611 const {
34612 int16x8_t([
34613 N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
34614 ])
34615 },
34616 )
34617 }
34618}
34619#[doc = "Signed saturating shift left unsigned"]
34620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
34621#[inline]
34622#[target_feature(enable = "neon")]
34623#[cfg(not(target_arch = "arm"))]
34624#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34625#[rustc_legacy_const_generics(1)]
34626#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34627pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
34628 static_assert_uimm_bits!(N, 5);
34629 unsafe extern "unadjusted" {
34630 #[cfg_attr(
34631 any(target_arch = "aarch64", target_arch = "arm64ec"),
34632 link_name = "llvm.aarch64.neon.sqshlu.v2i32"
34633 )]
34634 fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
34635 }
34636 unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
34637}
34638#[doc = "Signed saturating shift left unsigned"]
34639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
34640#[inline]
34641#[target_feature(enable = "neon")]
34642#[cfg(not(target_arch = "arm"))]
34643#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34644#[rustc_legacy_const_generics(1)]
34645#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34646pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
34647 static_assert_uimm_bits!(N, 5);
34648 unsafe extern "unadjusted" {
34649 #[cfg_attr(
34650 any(target_arch = "aarch64", target_arch = "arm64ec"),
34651 link_name = "llvm.aarch64.neon.sqshlu.v4i32"
34652 )]
34653 fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
34654 }
34655 unsafe {
34656 _vqshluq_n_s32(
34657 a,
34658 const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
34659 )
34660 }
34661}
34662#[doc = "Signed saturating shift left unsigned"]
34663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
34664#[inline]
34665#[target_feature(enable = "neon")]
34666#[cfg(not(target_arch = "arm"))]
34667#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34668#[rustc_legacy_const_generics(1)]
34669#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34670pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
34671 static_assert_uimm_bits!(N, 6);
34672 unsafe extern "unadjusted" {
34673 #[cfg_attr(
34674 any(target_arch = "aarch64", target_arch = "arm64ec"),
34675 link_name = "llvm.aarch64.neon.sqshlu.v1i64"
34676 )]
34677 fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
34678 }
34679 unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
34680}
34681#[doc = "Signed saturating shift left unsigned"]
34682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
34683#[inline]
34684#[target_feature(enable = "neon")]
34685#[cfg(not(target_arch = "arm"))]
34686#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
34687#[rustc_legacy_const_generics(1)]
34688#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34689pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
34690 static_assert_uimm_bits!(N, 6);
34691 unsafe extern "unadjusted" {
34692 #[cfg_attr(
34693 any(target_arch = "aarch64", target_arch = "arm64ec"),
34694 link_name = "llvm.aarch64.neon.sqshlu.v2i64"
34695 )]
34696 fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
34697 }
34698 unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
34699}
34700#[doc = "Signed saturating shift right narrow"]
34701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
34702#[inline]
34703#[cfg(target_arch = "arm")]
34704#[target_feature(enable = "neon,v7")]
34705#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
34706#[rustc_legacy_const_generics(1)]
34707#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34708pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
34709 static_assert!(N >= 1 && N <= 8);
34710 unsafe extern "unadjusted" {
34711 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")]
34712 fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
34713 }
34714 unsafe {
34715 _vqshrn_n_s16(
34716 a,
34717 const {
34718 int16x8_t([
34719 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
34720 -N as i16,
34721 ])
34722 },
34723 )
34724 }
34725}
34726#[doc = "Signed saturating shift right narrow"]
34727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
34728#[inline]
34729#[cfg(target_arch = "arm")]
34730#[target_feature(enable = "neon,v7")]
34731#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
34732#[rustc_legacy_const_generics(1)]
34733#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34734pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
34735 static_assert!(N >= 1 && N <= 16);
34736 unsafe extern "unadjusted" {
34737 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")]
34738 fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
34739 }
34740 unsafe {
34741 _vqshrn_n_s32(
34742 a,
34743 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
34744 )
34745 }
34746}
34747#[doc = "Signed saturating shift right narrow"]
34748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
34749#[inline]
34750#[cfg(target_arch = "arm")]
34751#[target_feature(enable = "neon,v7")]
34752#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
34753#[rustc_legacy_const_generics(1)]
34754#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34755pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
34756 static_assert!(N >= 1 && N <= 32);
34757 unsafe extern "unadjusted" {
34758 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")]
34759 fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
34760 }
34761 unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
34762}
34763#[doc = "Signed saturating shift right narrow"]
34764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
34765#[inline]
34766#[target_feature(enable = "neon")]
34767#[cfg(not(target_arch = "arm"))]
34768#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
34769#[rustc_legacy_const_generics(1)]
34770#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34771pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
34772 static_assert!(N >= 1 && N <= 8);
34773 unsafe extern "unadjusted" {
34774 #[cfg_attr(
34775 any(target_arch = "aarch64", target_arch = "arm64ec"),
34776 link_name = "llvm.aarch64.neon.sqshrn.v8i8"
34777 )]
34778 fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
34779 }
34780 unsafe { _vqshrn_n_s16(a, N) }
34781}
34782#[doc = "Signed saturating shift right narrow"]
34783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
34784#[inline]
34785#[target_feature(enable = "neon")]
34786#[cfg(not(target_arch = "arm"))]
34787#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
34788#[rustc_legacy_const_generics(1)]
34789#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34790pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
34791 static_assert!(N >= 1 && N <= 16);
34792 unsafe extern "unadjusted" {
34793 #[cfg_attr(
34794 any(target_arch = "aarch64", target_arch = "arm64ec"),
34795 link_name = "llvm.aarch64.neon.sqshrn.v4i16"
34796 )]
34797 fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
34798 }
34799 unsafe { _vqshrn_n_s32(a, N) }
34800}
34801#[doc = "Signed saturating shift right narrow"]
34802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
34803#[inline]
34804#[target_feature(enable = "neon")]
34805#[cfg(not(target_arch = "arm"))]
34806#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
34807#[rustc_legacy_const_generics(1)]
34808#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34809pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
34810 static_assert!(N >= 1 && N <= 32);
34811 unsafe extern "unadjusted" {
34812 #[cfg_attr(
34813 any(target_arch = "aarch64", target_arch = "arm64ec"),
34814 link_name = "llvm.aarch64.neon.sqshrn.v2i32"
34815 )]
34816 fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
34817 }
34818 unsafe { _vqshrn_n_s64(a, N) }
34819}
34820#[doc = "Unsigned saturating shift right narrow"]
34821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
34822#[inline]
34823#[cfg(target_arch = "arm")]
34824#[target_feature(enable = "neon,v7")]
34825#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
34826#[rustc_legacy_const_generics(1)]
34827#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34828pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
34829 static_assert!(N >= 1 && N <= 8);
34830 unsafe extern "unadjusted" {
34831 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")]
34832 fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
34833 }
34834 unsafe {
34835 _vqshrn_n_u16(
34836 a,
34837 const {
34838 uint16x8_t([
34839 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
34840 -N as u16,
34841 ])
34842 },
34843 )
34844 }
34845}
34846#[doc = "Unsigned saturating shift right narrow"]
34847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
34848#[inline]
34849#[cfg(target_arch = "arm")]
34850#[target_feature(enable = "neon,v7")]
34851#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
34852#[rustc_legacy_const_generics(1)]
34853#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34854pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
34855 static_assert!(N >= 1 && N <= 16);
34856 unsafe extern "unadjusted" {
34857 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")]
34858 fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
34859 }
34860 unsafe {
34861 _vqshrn_n_u32(
34862 a,
34863 const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
34864 )
34865 }
34866}
34867#[doc = "Unsigned saturating shift right narrow"]
34868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
34869#[inline]
34870#[cfg(target_arch = "arm")]
34871#[target_feature(enable = "neon,v7")]
34872#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
34873#[rustc_legacy_const_generics(1)]
34874#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34875pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
34876 static_assert!(N >= 1 && N <= 32);
34877 unsafe extern "unadjusted" {
34878 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
34879 fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
34880 }
34881 unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
34882}
34883#[doc = "Unsigned saturating shift right narrow"]
34884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
34885#[inline]
34886#[target_feature(enable = "neon")]
34887#[cfg(not(target_arch = "arm"))]
34888#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
34889#[rustc_legacy_const_generics(1)]
34890#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34891pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
34892 static_assert!(N >= 1 && N <= 8);
34893 unsafe extern "unadjusted" {
34894 #[cfg_attr(
34895 any(target_arch = "aarch64", target_arch = "arm64ec"),
34896 link_name = "llvm.aarch64.neon.uqshrn.v8i8"
34897 )]
34898 fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
34899 }
34900 unsafe { _vqshrn_n_u16(a, N) }
34901}
34902#[doc = "Unsigned saturating shift right narrow"]
34903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
34904#[inline]
34905#[target_feature(enable = "neon")]
34906#[cfg(not(target_arch = "arm"))]
34907#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
34908#[rustc_legacy_const_generics(1)]
34909#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34910pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
34911 static_assert!(N >= 1 && N <= 16);
34912 unsafe extern "unadjusted" {
34913 #[cfg_attr(
34914 any(target_arch = "aarch64", target_arch = "arm64ec"),
34915 link_name = "llvm.aarch64.neon.uqshrn.v4i16"
34916 )]
34917 fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
34918 }
34919 unsafe { _vqshrn_n_u32(a, N) }
34920}
34921#[doc = "Unsigned saturating shift right narrow"]
34922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
34923#[inline]
34924#[target_feature(enable = "neon")]
34925#[cfg(not(target_arch = "arm"))]
34926#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
34927#[rustc_legacy_const_generics(1)]
34928#[stable(feature = "neon_intrinsics", since = "1.59.0")]
34929pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
34930 static_assert!(N >= 1 && N <= 32);
34931 unsafe extern "unadjusted" {
34932 #[cfg_attr(
34933 any(target_arch = "aarch64", target_arch = "arm64ec"),
34934 link_name = "llvm.aarch64.neon.uqshrn.v2i32"
34935 )]
34936 fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
34937 }
34938 unsafe { _vqshrn_n_u64(a, N) }
34939}
34940#[doc = "Signed saturating shift right unsigned narrow"]
34941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
34942#[inline]
34943#[cfg(target_arch = "arm")]
34944#[target_feature(enable = "neon,v7")]
34945#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
34946#[rustc_legacy_const_generics(1)]
34947#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34948pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
34949 static_assert!(N >= 1 && N <= 8);
34950 unsafe extern "unadjusted" {
34951 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
34952 fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
34953 }
34954 unsafe {
34955 _vqshrun_n_s16(
34956 a,
34957 const {
34958 int16x8_t([
34959 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
34960 -N as i16,
34961 ])
34962 },
34963 )
34964 }
34965}
34966#[doc = "Signed saturating shift right unsigned narrow"]
34967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
34968#[inline]
34969#[cfg(target_arch = "arm")]
34970#[target_feature(enable = "neon,v7")]
34971#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
34972#[rustc_legacy_const_generics(1)]
34973#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34974pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
34975 static_assert!(N >= 1 && N <= 16);
34976 unsafe extern "unadjusted" {
34977 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
34978 fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
34979 }
34980 unsafe {
34981 _vqshrun_n_s32(
34982 a,
34983 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
34984 )
34985 }
34986}
34987#[doc = "Signed saturating shift right unsigned narrow"]
34988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
34989#[inline]
34990#[cfg(target_arch = "arm")]
34991#[target_feature(enable = "neon,v7")]
34992#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
34993#[rustc_legacy_const_generics(1)]
34994#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
34995pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
34996 static_assert!(N >= 1 && N <= 32);
34997 unsafe extern "unadjusted" {
34998 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
34999 fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
35000 }
35001 unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
35002}
35003#[doc = "Signed saturating shift right unsigned narrow"]
35004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
35005#[inline]
35006#[target_feature(enable = "neon")]
35007#[cfg(not(target_arch = "arm"))]
35008#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
35009#[rustc_legacy_const_generics(1)]
35010#[stable(feature = "neon_intrinsics", since = "1.59.0")]
35011pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
35012 static_assert!(N >= 1 && N <= 8);
35013 unsafe extern "unadjusted" {
35014 #[cfg_attr(
35015 any(target_arch = "aarch64", target_arch = "arm64ec"),
35016 link_name = "llvm.aarch64.neon.sqshrun.v8i8"
35017 )]
35018 fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
35019 }
35020 unsafe { _vqshrun_n_s16(a, N) }
35021}
35022#[doc = "Signed saturating shift right unsigned narrow"]
35023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
35024#[inline]
35025#[target_feature(enable = "neon")]
35026#[cfg(not(target_arch = "arm"))]
35027#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
35028#[rustc_legacy_const_generics(1)]
35029#[stable(feature = "neon_intrinsics", since = "1.59.0")]
35030pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
35031 static_assert!(N >= 1 && N <= 16);
35032 unsafe extern "unadjusted" {
35033 #[cfg_attr(
35034 any(target_arch = "aarch64", target_arch = "arm64ec"),
35035 link_name = "llvm.aarch64.neon.sqshrun.v4i16"
35036 )]
35037 fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
35038 }
35039 unsafe { _vqshrun_n_s32(a, N) }
35040}
35041#[doc = "Signed saturating shift right unsigned narrow"]
35042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
35043#[inline]
35044#[target_feature(enable = "neon")]
35045#[cfg(not(target_arch = "arm"))]
35046#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
35047#[rustc_legacy_const_generics(1)]
35048#[stable(feature = "neon_intrinsics", since = "1.59.0")]
35049pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
35050 static_assert!(N >= 1 && N <= 32);
35051 unsafe extern "unadjusted" {
35052 #[cfg_attr(
35053 any(target_arch = "aarch64", target_arch = "arm64ec"),
35054 link_name = "llvm.aarch64.neon.sqshrun.v2i32"
35055 )]
35056 fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
35057 }
35058 unsafe { _vqshrun_n_s64(a, N) }
35059}
35060#[doc = "Saturating subtract"]
35061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
35062#[inline]
35063#[target_feature(enable = "neon")]
35064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
35066#[cfg_attr(
35067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35068 assert_instr(sqsub)
35069)]
35070#[cfg_attr(
35071 not(target_arch = "arm"),
35072 stable(feature = "neon_intrinsics", since = "1.59.0")
35073)]
35074#[cfg_attr(
35075 target_arch = "arm",
35076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35077)]
35078pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35079 unsafe extern "unadjusted" {
35080 #[cfg_attr(
35081 any(target_arch = "aarch64", target_arch = "arm64ec"),
35082 link_name = "llvm.aarch64.neon.sqsub.v8i8"
35083 )]
35084 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")]
35085 fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
35086 }
35087 unsafe { _vqsub_s8(a, b) }
35088}
35089#[doc = "Saturating subtract"]
35090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
35091#[inline]
35092#[target_feature(enable = "neon")]
35093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
35095#[cfg_attr(
35096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35097 assert_instr(sqsub)
35098)]
35099#[cfg_attr(
35100 not(target_arch = "arm"),
35101 stable(feature = "neon_intrinsics", since = "1.59.0")
35102)]
35103#[cfg_attr(
35104 target_arch = "arm",
35105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35106)]
35107pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
35108 unsafe extern "unadjusted" {
35109 #[cfg_attr(
35110 any(target_arch = "aarch64", target_arch = "arm64ec"),
35111 link_name = "llvm.aarch64.neon.sqsub.v16i8"
35112 )]
35113 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")]
35114 fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
35115 }
35116 unsafe { _vqsubq_s8(a, b) }
35117}
35118#[doc = "Saturating subtract"]
35119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
35120#[inline]
35121#[target_feature(enable = "neon")]
35122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35123#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
35124#[cfg_attr(
35125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35126 assert_instr(sqsub)
35127)]
35128#[cfg_attr(
35129 not(target_arch = "arm"),
35130 stable(feature = "neon_intrinsics", since = "1.59.0")
35131)]
35132#[cfg_attr(
35133 target_arch = "arm",
35134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35135)]
35136pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
35137 unsafe extern "unadjusted" {
35138 #[cfg_attr(
35139 any(target_arch = "aarch64", target_arch = "arm64ec"),
35140 link_name = "llvm.aarch64.neon.sqsub.v4i16"
35141 )]
35142 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")]
35143 fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
35144 }
35145 unsafe { _vqsub_s16(a, b) }
35146}
35147#[doc = "Saturating subtract"]
35148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
35149#[inline]
35150#[target_feature(enable = "neon")]
35151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
35153#[cfg_attr(
35154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35155 assert_instr(sqsub)
35156)]
35157#[cfg_attr(
35158 not(target_arch = "arm"),
35159 stable(feature = "neon_intrinsics", since = "1.59.0")
35160)]
35161#[cfg_attr(
35162 target_arch = "arm",
35163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35164)]
35165pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
35166 unsafe extern "unadjusted" {
35167 #[cfg_attr(
35168 any(target_arch = "aarch64", target_arch = "arm64ec"),
35169 link_name = "llvm.aarch64.neon.sqsub.v8i16"
35170 )]
35171 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")]
35172 fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
35173 }
35174 unsafe { _vqsubq_s16(a, b) }
35175}
35176#[doc = "Saturating subtract"]
35177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
35178#[inline]
35179#[target_feature(enable = "neon")]
35180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35181#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
35182#[cfg_attr(
35183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35184 assert_instr(sqsub)
35185)]
35186#[cfg_attr(
35187 not(target_arch = "arm"),
35188 stable(feature = "neon_intrinsics", since = "1.59.0")
35189)]
35190#[cfg_attr(
35191 target_arch = "arm",
35192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35193)]
35194pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35195 unsafe extern "unadjusted" {
35196 #[cfg_attr(
35197 any(target_arch = "aarch64", target_arch = "arm64ec"),
35198 link_name = "llvm.aarch64.neon.sqsub.v2i32"
35199 )]
35200 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")]
35201 fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
35202 }
35203 unsafe { _vqsub_s32(a, b) }
35204}
35205#[doc = "Saturating subtract"]
35206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
35207#[inline]
35208#[target_feature(enable = "neon")]
35209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35210#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
35211#[cfg_attr(
35212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35213 assert_instr(sqsub)
35214)]
35215#[cfg_attr(
35216 not(target_arch = "arm"),
35217 stable(feature = "neon_intrinsics", since = "1.59.0")
35218)]
35219#[cfg_attr(
35220 target_arch = "arm",
35221 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35222)]
35223pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
35224 unsafe extern "unadjusted" {
35225 #[cfg_attr(
35226 any(target_arch = "aarch64", target_arch = "arm64ec"),
35227 link_name = "llvm.aarch64.neon.sqsub.v4i32"
35228 )]
35229 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")]
35230 fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
35231 }
35232 unsafe { _vqsubq_s32(a, b) }
35233}
35234#[doc = "Saturating subtract"]
35235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
35236#[inline]
35237#[target_feature(enable = "neon")]
35238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
35240#[cfg_attr(
35241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35242 assert_instr(sqsub)
35243)]
35244#[cfg_attr(
35245 not(target_arch = "arm"),
35246 stable(feature = "neon_intrinsics", since = "1.59.0")
35247)]
35248#[cfg_attr(
35249 target_arch = "arm",
35250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35251)]
35252pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
35253 unsafe extern "unadjusted" {
35254 #[cfg_attr(
35255 any(target_arch = "aarch64", target_arch = "arm64ec"),
35256 link_name = "llvm.aarch64.neon.sqsub.v1i64"
35257 )]
35258 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")]
35259 fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
35260 }
35261 unsafe { _vqsub_s64(a, b) }
35262}
35263#[doc = "Saturating subtract"]
35264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
35265#[inline]
35266#[target_feature(enable = "neon")]
35267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
35269#[cfg_attr(
35270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35271 assert_instr(sqsub)
35272)]
35273#[cfg_attr(
35274 not(target_arch = "arm"),
35275 stable(feature = "neon_intrinsics", since = "1.59.0")
35276)]
35277#[cfg_attr(
35278 target_arch = "arm",
35279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35280)]
35281pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35282 unsafe extern "unadjusted" {
35283 #[cfg_attr(
35284 any(target_arch = "aarch64", target_arch = "arm64ec"),
35285 link_name = "llvm.aarch64.neon.sqsub.v2i64"
35286 )]
35287 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")]
35288 fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
35289 }
35290 unsafe { _vqsubq_s64(a, b) }
35291}
35292#[doc = "Saturating subtract"]
35293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
35294#[inline]
35295#[target_feature(enable = "neon")]
35296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
35298#[cfg_attr(
35299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35300 assert_instr(uqsub)
35301)]
35302#[cfg_attr(
35303 not(target_arch = "arm"),
35304 stable(feature = "neon_intrinsics", since = "1.59.0")
35305)]
35306#[cfg_attr(
35307 target_arch = "arm",
35308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35309)]
35310pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35311 unsafe extern "unadjusted" {
35312 #[cfg_attr(
35313 any(target_arch = "aarch64", target_arch = "arm64ec"),
35314 link_name = "llvm.aarch64.neon.uqsub.v8i8"
35315 )]
35316 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")]
35317 fn _vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
35318 }
35319 unsafe { _vqsub_u8(a, b) }
35320}
35321#[doc = "Saturating subtract"]
35322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
35323#[inline]
35324#[target_feature(enable = "neon")]
35325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
35327#[cfg_attr(
35328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35329 assert_instr(uqsub)
35330)]
35331#[cfg_attr(
35332 not(target_arch = "arm"),
35333 stable(feature = "neon_intrinsics", since = "1.59.0")
35334)]
35335#[cfg_attr(
35336 target_arch = "arm",
35337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35338)]
35339pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35340 unsafe extern "unadjusted" {
35341 #[cfg_attr(
35342 any(target_arch = "aarch64", target_arch = "arm64ec"),
35343 link_name = "llvm.aarch64.neon.uqsub.v16i8"
35344 )]
35345 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")]
35346 fn _vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
35347 }
35348 unsafe { _vqsubq_u8(a, b) }
35349}
35350#[doc = "Saturating subtract"]
35351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
35352#[inline]
35353#[target_feature(enable = "neon")]
35354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35355#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
35356#[cfg_attr(
35357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35358 assert_instr(uqsub)
35359)]
35360#[cfg_attr(
35361 not(target_arch = "arm"),
35362 stable(feature = "neon_intrinsics", since = "1.59.0")
35363)]
35364#[cfg_attr(
35365 target_arch = "arm",
35366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35367)]
35368pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35369 unsafe extern "unadjusted" {
35370 #[cfg_attr(
35371 any(target_arch = "aarch64", target_arch = "arm64ec"),
35372 link_name = "llvm.aarch64.neon.uqsub.v4i16"
35373 )]
35374 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")]
35375 fn _vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
35376 }
35377 unsafe { _vqsub_u16(a, b) }
35378}
35379#[doc = "Saturating subtract"]
35380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
35381#[inline]
35382#[target_feature(enable = "neon")]
35383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35384#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
35385#[cfg_attr(
35386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35387 assert_instr(uqsub)
35388)]
35389#[cfg_attr(
35390 not(target_arch = "arm"),
35391 stable(feature = "neon_intrinsics", since = "1.59.0")
35392)]
35393#[cfg_attr(
35394 target_arch = "arm",
35395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35396)]
35397pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35398 unsafe extern "unadjusted" {
35399 #[cfg_attr(
35400 any(target_arch = "aarch64", target_arch = "arm64ec"),
35401 link_name = "llvm.aarch64.neon.uqsub.v8i16"
35402 )]
35403 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")]
35404 fn _vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
35405 }
35406 unsafe { _vqsubq_u16(a, b) }
35407}
35408#[doc = "Saturating subtract"]
35409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
35410#[inline]
35411#[target_feature(enable = "neon")]
35412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35413#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
35414#[cfg_attr(
35415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35416 assert_instr(uqsub)
35417)]
35418#[cfg_attr(
35419 not(target_arch = "arm"),
35420 stable(feature = "neon_intrinsics", since = "1.59.0")
35421)]
35422#[cfg_attr(
35423 target_arch = "arm",
35424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35425)]
35426pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35427 unsafe extern "unadjusted" {
35428 #[cfg_attr(
35429 any(target_arch = "aarch64", target_arch = "arm64ec"),
35430 link_name = "llvm.aarch64.neon.uqsub.v2i32"
35431 )]
35432 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")]
35433 fn _vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
35434 }
35435 unsafe { _vqsub_u32(a, b) }
35436}
35437#[doc = "Saturating subtract"]
35438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
35439#[inline]
35440#[target_feature(enable = "neon")]
35441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35442#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
35443#[cfg_attr(
35444 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35445 assert_instr(uqsub)
35446)]
35447#[cfg_attr(
35448 not(target_arch = "arm"),
35449 stable(feature = "neon_intrinsics", since = "1.59.0")
35450)]
35451#[cfg_attr(
35452 target_arch = "arm",
35453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35454)]
35455pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35456 unsafe extern "unadjusted" {
35457 #[cfg_attr(
35458 any(target_arch = "aarch64", target_arch = "arm64ec"),
35459 link_name = "llvm.aarch64.neon.uqsub.v4i32"
35460 )]
35461 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")]
35462 fn _vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
35463 }
35464 unsafe { _vqsubq_u32(a, b) }
35465}
35466#[doc = "Saturating subtract"]
35467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
35468#[inline]
35469#[target_feature(enable = "neon")]
35470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
35472#[cfg_attr(
35473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35474 assert_instr(uqsub)
35475)]
35476#[cfg_attr(
35477 not(target_arch = "arm"),
35478 stable(feature = "neon_intrinsics", since = "1.59.0")
35479)]
35480#[cfg_attr(
35481 target_arch = "arm",
35482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35483)]
35484pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35485 unsafe extern "unadjusted" {
35486 #[cfg_attr(
35487 any(target_arch = "aarch64", target_arch = "arm64ec"),
35488 link_name = "llvm.aarch64.neon.uqsub.v1i64"
35489 )]
35490 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")]
35491 fn _vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
35492 }
35493 unsafe { _vqsub_u64(a, b) }
35494}
35495#[doc = "Saturating subtract"]
35496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
35497#[inline]
35498#[target_feature(enable = "neon")]
35499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35500#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
35501#[cfg_attr(
35502 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35503 assert_instr(uqsub)
35504)]
35505#[cfg_attr(
35506 not(target_arch = "arm"),
35507 stable(feature = "neon_intrinsics", since = "1.59.0")
35508)]
35509#[cfg_attr(
35510 target_arch = "arm",
35511 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35512)]
35513pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35514 unsafe extern "unadjusted" {
35515 #[cfg_attr(
35516 any(target_arch = "aarch64", target_arch = "arm64ec"),
35517 link_name = "llvm.aarch64.neon.uqsub.v2i64"
35518 )]
35519 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")]
35520 fn _vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
35521 }
35522 unsafe { _vqsubq_u64(a, b) }
35523}
35524#[doc = "Rounding Add returning High Narrow (high half)."]
35525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
35526#[inline]
35527#[target_feature(enable = "neon")]
35528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
35530#[cfg_attr(
35531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35532 assert_instr(raddhn2)
35533)]
35534#[cfg_attr(
35535 not(target_arch = "arm"),
35536 stable(feature = "neon_intrinsics", since = "1.59.0")
35537)]
35538#[cfg_attr(
35539 target_arch = "arm",
35540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35541)]
35542pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
35543 let x = vraddhn_s16(b, c);
35544 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
35545}
35546#[doc = "Rounding Add returning High Narrow (high half)."]
35547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
35548#[inline]
35549#[target_feature(enable = "neon")]
35550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35551#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
35552#[cfg_attr(
35553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35554 assert_instr(raddhn2)
35555)]
35556#[cfg_attr(
35557 not(target_arch = "arm"),
35558 stable(feature = "neon_intrinsics", since = "1.59.0")
35559)]
35560#[cfg_attr(
35561 target_arch = "arm",
35562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35563)]
35564pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
35565 let x = vraddhn_s32(b, c);
35566 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
35567}
35568#[doc = "Rounding Add returning High Narrow (high half)."]
35569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
35570#[inline]
35571#[target_feature(enable = "neon")]
35572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
35574#[cfg_attr(
35575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35576 assert_instr(raddhn2)
35577)]
35578#[cfg_attr(
35579 not(target_arch = "arm"),
35580 stable(feature = "neon_intrinsics", since = "1.59.0")
35581)]
35582#[cfg_attr(
35583 target_arch = "arm",
35584 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35585)]
35586pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
35587 let x = vraddhn_s64(b, c);
35588 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
35589}
35590#[doc = "Rounding Add returning High Narrow (high half)."]
35591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
35592#[inline]
35593#[target_feature(enable = "neon")]
35594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35595#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
35596#[cfg_attr(
35597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35598 assert_instr(raddhn2)
35599)]
35600#[cfg_attr(
35601 not(target_arch = "arm"),
35602 stable(feature = "neon_intrinsics", since = "1.59.0")
35603)]
35604#[cfg_attr(
35605 target_arch = "arm",
35606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35607)]
35608pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
35609 unsafe {
35610 let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c)));
35611 simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
35612 }
35613}
35614#[doc = "Rounding Add returning High Narrow (high half)."]
35615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
35616#[inline]
35617#[target_feature(enable = "neon")]
35618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35619#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
35620#[cfg_attr(
35621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35622 assert_instr(raddhn2)
35623)]
35624#[cfg_attr(
35625 not(target_arch = "arm"),
35626 stable(feature = "neon_intrinsics", since = "1.59.0")
35627)]
35628#[cfg_attr(
35629 target_arch = "arm",
35630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35631)]
35632pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
35633 unsafe {
35634 let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c)));
35635 simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7])
35636 }
35637}
35638#[doc = "Rounding Add returning High Narrow (high half)."]
35639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
35640#[inline]
35641#[target_feature(enable = "neon")]
35642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
35644#[cfg_attr(
35645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35646 assert_instr(raddhn2)
35647)]
35648#[cfg_attr(
35649 not(target_arch = "arm"),
35650 stable(feature = "neon_intrinsics", since = "1.59.0")
35651)]
35652#[cfg_attr(
35653 target_arch = "arm",
35654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35655)]
35656pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
35657 unsafe {
35658 let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c)));
35659 simd_shuffle!(a, x, [0, 1, 2, 3])
35660 }
35661}
35662#[doc = "Rounding Add returning High Narrow."]
35663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
35664#[inline]
35665#[target_feature(enable = "neon")]
35666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35667#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
35668#[cfg_attr(
35669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35670 assert_instr(raddhn)
35671)]
35672#[cfg_attr(
35673 not(target_arch = "arm"),
35674 stable(feature = "neon_intrinsics", since = "1.59.0")
35675)]
35676#[cfg_attr(
35677 target_arch = "arm",
35678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35679)]
35680pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
35681 unsafe extern "unadjusted" {
35682 #[cfg_attr(
35683 any(target_arch = "aarch64", target_arch = "arm64ec"),
35684 link_name = "llvm.aarch64.neon.raddhn.v8i8"
35685 )]
35686 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")]
35687 fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
35688 }
35689 unsafe { _vraddhn_s16(a, b) }
35690}
35691#[doc = "Rounding Add returning High Narrow."]
35692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
35693#[inline]
35694#[target_feature(enable = "neon")]
35695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35696#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
35697#[cfg_attr(
35698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35699 assert_instr(raddhn)
35700)]
35701#[cfg_attr(
35702 not(target_arch = "arm"),
35703 stable(feature = "neon_intrinsics", since = "1.59.0")
35704)]
35705#[cfg_attr(
35706 target_arch = "arm",
35707 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35708)]
35709pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
35710 unsafe extern "unadjusted" {
35711 #[cfg_attr(
35712 any(target_arch = "aarch64", target_arch = "arm64ec"),
35713 link_name = "llvm.aarch64.neon.raddhn.v4i16"
35714 )]
35715 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")]
35716 fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
35717 }
35718 unsafe { _vraddhn_s32(a, b) }
35719}
35720#[doc = "Rounding Add returning High Narrow."]
35721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
35722#[inline]
35723#[target_feature(enable = "neon")]
35724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35725#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
35726#[cfg_attr(
35727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35728 assert_instr(raddhn)
35729)]
35730#[cfg_attr(
35731 not(target_arch = "arm"),
35732 stable(feature = "neon_intrinsics", since = "1.59.0")
35733)]
35734#[cfg_attr(
35735 target_arch = "arm",
35736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35737)]
35738pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
35739 unsafe extern "unadjusted" {
35740 #[cfg_attr(
35741 any(target_arch = "aarch64", target_arch = "arm64ec"),
35742 link_name = "llvm.aarch64.neon.raddhn.v2i32"
35743 )]
35744 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")]
35745 fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
35746 }
35747 unsafe { _vraddhn_s64(a, b) }
35748}
35749#[doc = "Rounding Add returning High Narrow."]
35750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
35751#[inline]
35752#[cfg(target_endian = "little")]
35753#[target_feature(enable = "neon")]
35754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35755#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
35756#[cfg_attr(
35757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35758 assert_instr(raddhn)
35759)]
35760#[cfg_attr(
35761 not(target_arch = "arm"),
35762 stable(feature = "neon_intrinsics", since = "1.59.0")
35763)]
35764#[cfg_attr(
35765 target_arch = "arm",
35766 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35767)]
35768pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
35769 unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) }
35770}
35771#[doc = "Rounding Add returning High Narrow."]
35772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
35773#[inline]
35774#[cfg(target_endian = "big")]
35775#[target_feature(enable = "neon")]
35776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35777#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
35778#[cfg_attr(
35779 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35780 assert_instr(raddhn)
35781)]
35782#[cfg_attr(
35783 not(target_arch = "arm"),
35784 stable(feature = "neon_intrinsics", since = "1.59.0")
35785)]
35786#[cfg_attr(
35787 target_arch = "arm",
35788 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35789)]
35790pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
35791 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
35792 let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
35793 unsafe {
35794 let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
35795 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
35796 }
35797}
35798#[doc = "Rounding Add returning High Narrow."]
35799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
35800#[inline]
35801#[cfg(target_endian = "little")]
35802#[target_feature(enable = "neon")]
35803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
35805#[cfg_attr(
35806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35807 assert_instr(raddhn)
35808)]
35809#[cfg_attr(
35810 not(target_arch = "arm"),
35811 stable(feature = "neon_intrinsics", since = "1.59.0")
35812)]
35813#[cfg_attr(
35814 target_arch = "arm",
35815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35816)]
35817pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
35818 unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) }
35819}
35820#[doc = "Rounding Add returning High Narrow."]
35821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
35822#[inline]
35823#[cfg(target_endian = "big")]
35824#[target_feature(enable = "neon")]
35825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
35827#[cfg_attr(
35828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35829 assert_instr(raddhn)
35830)]
35831#[cfg_attr(
35832 not(target_arch = "arm"),
35833 stable(feature = "neon_intrinsics", since = "1.59.0")
35834)]
35835#[cfg_attr(
35836 target_arch = "arm",
35837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35838)]
35839pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
35840 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
35841 let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
35842 unsafe {
35843 let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
35844 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
35845 }
35846}
35847#[doc = "Rounding Add returning High Narrow."]
35848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
35849#[inline]
35850#[cfg(target_endian = "little")]
35851#[target_feature(enable = "neon")]
35852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35853#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
35854#[cfg_attr(
35855 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35856 assert_instr(raddhn)
35857)]
35858#[cfg_attr(
35859 not(target_arch = "arm"),
35860 stable(feature = "neon_intrinsics", since = "1.59.0")
35861)]
35862#[cfg_attr(
35863 target_arch = "arm",
35864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35865)]
35866pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
35867 unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) }
35868}
35869#[doc = "Rounding Add returning High Narrow."]
35870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
35871#[inline]
35872#[cfg(target_endian = "big")]
35873#[target_feature(enable = "neon")]
35874#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35875#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
35876#[cfg_attr(
35877 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35878 assert_instr(raddhn)
35879)]
35880#[cfg_attr(
35881 not(target_arch = "arm"),
35882 stable(feature = "neon_intrinsics", since = "1.59.0")
35883)]
35884#[cfg_attr(
35885 target_arch = "arm",
35886 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35887)]
35888pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
35889 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
35890 let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
35891 unsafe {
35892 let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
35893 simd_shuffle!(ret_val, ret_val, [1, 0])
35894 }
35895}
35896#[doc = "Reciprocal estimate."]
35897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
35898#[inline]
35899#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
35900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
35901#[cfg_attr(
35902 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35903 assert_instr(frecpe)
35904)]
35905#[target_feature(enable = "neon,fp16")]
35906#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
35907pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
35908 unsafe extern "unadjusted" {
35909 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")]
35910 #[cfg_attr(
35911 any(target_arch = "aarch64", target_arch = "arm64ec"),
35912 link_name = "llvm.aarch64.neon.frecpe.v4f16"
35913 )]
35914 fn _vrecpe_f16(a: float16x4_t) -> float16x4_t;
35915 }
35916 unsafe { _vrecpe_f16(a) }
35917}
35918#[doc = "Reciprocal estimate."]
35919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
35920#[inline]
35921#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
35922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
35923#[cfg_attr(
35924 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35925 assert_instr(frecpe)
35926)]
35927#[target_feature(enable = "neon,fp16")]
35928#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
35929pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
35930 unsafe extern "unadjusted" {
35931 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")]
35932 #[cfg_attr(
35933 any(target_arch = "aarch64", target_arch = "arm64ec"),
35934 link_name = "llvm.aarch64.neon.frecpe.v8f16"
35935 )]
35936 fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t;
35937 }
35938 unsafe { _vrecpeq_f16(a) }
35939}
35940#[doc = "Reciprocal estimate."]
35941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
35942#[inline]
35943#[target_feature(enable = "neon")]
35944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
35946#[cfg_attr(
35947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35948 assert_instr(frecpe)
35949)]
35950#[cfg_attr(
35951 not(target_arch = "arm"),
35952 stable(feature = "neon_intrinsics", since = "1.59.0")
35953)]
35954#[cfg_attr(
35955 target_arch = "arm",
35956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35957)]
35958pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
35959 unsafe extern "unadjusted" {
35960 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")]
35961 #[cfg_attr(
35962 any(target_arch = "aarch64", target_arch = "arm64ec"),
35963 link_name = "llvm.aarch64.neon.frecpe.v2f32"
35964 )]
35965 fn _vrecpe_f32(a: float32x2_t) -> float32x2_t;
35966 }
35967 unsafe { _vrecpe_f32(a) }
35968}
35969#[doc = "Reciprocal estimate."]
35970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
35971#[inline]
35972#[target_feature(enable = "neon")]
35973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
35975#[cfg_attr(
35976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35977 assert_instr(frecpe)
35978)]
35979#[cfg_attr(
35980 not(target_arch = "arm"),
35981 stable(feature = "neon_intrinsics", since = "1.59.0")
35982)]
35983#[cfg_attr(
35984 target_arch = "arm",
35985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35986)]
35987pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
35988 unsafe extern "unadjusted" {
35989 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")]
35990 #[cfg_attr(
35991 any(target_arch = "aarch64", target_arch = "arm64ec"),
35992 link_name = "llvm.aarch64.neon.frecpe.v4f32"
35993 )]
35994 fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t;
35995 }
35996 unsafe { _vrecpeq_f32(a) }
35997}
35998#[doc = "Unsigned reciprocal estimate"]
35999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
36000#[inline]
36001#[target_feature(enable = "neon")]
36002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
36004#[cfg_attr(
36005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36006 assert_instr(urecpe)
36007)]
36008#[cfg_attr(
36009 not(target_arch = "arm"),
36010 stable(feature = "neon_intrinsics", since = "1.59.0")
36011)]
36012#[cfg_attr(
36013 target_arch = "arm",
36014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36015)]
36016pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
36017 unsafe extern "unadjusted" {
36018 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")]
36019 #[cfg_attr(
36020 any(target_arch = "aarch64", target_arch = "arm64ec"),
36021 link_name = "llvm.aarch64.neon.urecpe.v2i32"
36022 )]
36023 fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t;
36024 }
36025 unsafe { _vrecpe_u32(a) }
36026}
36027#[doc = "Unsigned reciprocal estimate"]
36028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
36029#[inline]
36030#[target_feature(enable = "neon")]
36031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
36033#[cfg_attr(
36034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36035 assert_instr(urecpe)
36036)]
36037#[cfg_attr(
36038 not(target_arch = "arm"),
36039 stable(feature = "neon_intrinsics", since = "1.59.0")
36040)]
36041#[cfg_attr(
36042 target_arch = "arm",
36043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36044)]
36045pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
36046 unsafe extern "unadjusted" {
36047 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")]
36048 #[cfg_attr(
36049 any(target_arch = "aarch64", target_arch = "arm64ec"),
36050 link_name = "llvm.aarch64.neon.urecpe.v4i32"
36051 )]
36052 fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t;
36053 }
36054 unsafe { _vrecpeq_u32(a) }
36055}
36056#[doc = "Floating-point reciprocal step"]
36057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
36058#[inline]
36059#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
36060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
36061#[cfg_attr(
36062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36063 assert_instr(frecps)
36064)]
36065#[target_feature(enable = "neon,fp16")]
36066#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36067pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
36068 unsafe extern "unadjusted" {
36069 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")]
36070 #[cfg_attr(
36071 any(target_arch = "aarch64", target_arch = "arm64ec"),
36072 link_name = "llvm.aarch64.neon.frecps.v4f16"
36073 )]
36074 fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
36075 }
36076 unsafe { _vrecps_f16(a, b) }
36077}
36078#[doc = "Floating-point reciprocal step"]
36079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
36080#[inline]
36081#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
36082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
36083#[cfg_attr(
36084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36085 assert_instr(frecps)
36086)]
36087#[target_feature(enable = "neon,fp16")]
36088#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36089pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
36090 unsafe extern "unadjusted" {
36091 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")]
36092 #[cfg_attr(
36093 any(target_arch = "aarch64", target_arch = "arm64ec"),
36094 link_name = "llvm.aarch64.neon.frecps.v8f16"
36095 )]
36096 fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
36097 }
36098 unsafe { _vrecpsq_f16(a, b) }
36099}
36100#[doc = "Floating-point reciprocal step"]
36101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
36102#[inline]
36103#[target_feature(enable = "neon")]
36104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36105#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
36106#[cfg_attr(
36107 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36108 assert_instr(frecps)
36109)]
36110#[cfg_attr(
36111 not(target_arch = "arm"),
36112 stable(feature = "neon_intrinsics", since = "1.59.0")
36113)]
36114#[cfg_attr(
36115 target_arch = "arm",
36116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36117)]
36118pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36119 unsafe extern "unadjusted" {
36120 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")]
36121 #[cfg_attr(
36122 any(target_arch = "aarch64", target_arch = "arm64ec"),
36123 link_name = "llvm.aarch64.neon.frecps.v2f32"
36124 )]
36125 fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36126 }
36127 unsafe { _vrecps_f32(a, b) }
36128}
36129#[doc = "Floating-point reciprocal step"]
36130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
36131#[inline]
36132#[target_feature(enable = "neon")]
36133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
36135#[cfg_attr(
36136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36137 assert_instr(frecps)
36138)]
36139#[cfg_attr(
36140 not(target_arch = "arm"),
36141 stable(feature = "neon_intrinsics", since = "1.59.0")
36142)]
36143#[cfg_attr(
36144 target_arch = "arm",
36145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36146)]
36147pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
36148 unsafe extern "unadjusted" {
36149 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")]
36150 #[cfg_attr(
36151 any(target_arch = "aarch64", target_arch = "arm64ec"),
36152 link_name = "llvm.aarch64.neon.frecps.v4f32"
36153 )]
36154 fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
36155 }
36156 unsafe { _vrecpsq_f32(a, b) }
36157}
36158#[doc = "Vector reinterpret cast operation"]
36159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
36160#[inline]
36161#[cfg(target_endian = "little")]
36162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36163#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36164#[cfg_attr(
36165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36166 assert_instr(nop)
36167)]
36168#[target_feature(enable = "neon,fp16")]
36169#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36170pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
36171 unsafe { transmute(a) }
36172}
36173#[doc = "Vector reinterpret cast operation"]
36174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
36175#[inline]
36176#[cfg(target_endian = "big")]
36177#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36178#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36179#[cfg_attr(
36180 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36181 assert_instr(nop)
36182)]
36183#[target_feature(enable = "neon,fp16")]
36184#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36185pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
36186 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36187 unsafe {
36188 let ret_val: float32x2_t = transmute(a);
36189 simd_shuffle!(ret_val, ret_val, [1, 0])
36190 }
36191}
36192#[doc = "Vector reinterpret cast operation"]
36193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
36194#[inline]
36195#[cfg(target_endian = "little")]
36196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36198#[cfg_attr(
36199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36200 assert_instr(nop)
36201)]
36202#[target_feature(enable = "neon,fp16")]
36203#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36204pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
36205 unsafe { transmute(a) }
36206}
36207#[doc = "Vector reinterpret cast operation"]
36208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
36209#[inline]
36210#[cfg(target_endian = "big")]
36211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36213#[cfg_attr(
36214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36215 assert_instr(nop)
36216)]
36217#[target_feature(enable = "neon,fp16")]
36218#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36219pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
36220 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36221 unsafe {
36222 let ret_val: int8x8_t = transmute(a);
36223 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36224 }
36225}
36226#[doc = "Vector reinterpret cast operation"]
36227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
36228#[inline]
36229#[cfg(target_endian = "little")]
36230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36232#[cfg_attr(
36233 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36234 assert_instr(nop)
36235)]
36236#[target_feature(enable = "neon,fp16")]
36237#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36238pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
36239 unsafe { transmute(a) }
36240}
36241#[doc = "Vector reinterpret cast operation"]
36242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
36243#[inline]
36244#[cfg(target_endian = "big")]
36245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36247#[cfg_attr(
36248 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36249 assert_instr(nop)
36250)]
36251#[target_feature(enable = "neon,fp16")]
36252#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36253pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
36254 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36255 unsafe {
36256 let ret_val: int16x4_t = transmute(a);
36257 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36258 }
36259}
36260#[doc = "Vector reinterpret cast operation"]
36261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
36262#[inline]
36263#[cfg(target_endian = "little")]
36264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36266#[cfg_attr(
36267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36268 assert_instr(nop)
36269)]
36270#[target_feature(enable = "neon,fp16")]
36271#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36272pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
36273 unsafe { transmute(a) }
36274}
36275#[doc = "Vector reinterpret cast operation"]
36276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
36277#[inline]
36278#[cfg(target_endian = "big")]
36279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36281#[cfg_attr(
36282 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36283 assert_instr(nop)
36284)]
36285#[target_feature(enable = "neon,fp16")]
36286#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36287pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
36288 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36289 unsafe {
36290 let ret_val: int32x2_t = transmute(a);
36291 simd_shuffle!(ret_val, ret_val, [1, 0])
36292 }
36293}
36294#[doc = "Vector reinterpret cast operation"]
36295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
36296#[inline]
36297#[cfg(target_endian = "little")]
36298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36300#[cfg_attr(
36301 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36302 assert_instr(nop)
36303)]
36304#[target_feature(enable = "neon,fp16")]
36305#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36306pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
36307 unsafe { transmute(a) }
36308}
36309#[doc = "Vector reinterpret cast operation"]
36310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
36311#[inline]
36312#[cfg(target_endian = "big")]
36313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36315#[cfg_attr(
36316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36317 assert_instr(nop)
36318)]
36319#[target_feature(enable = "neon,fp16")]
36320#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36321pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
36322 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36323 unsafe { transmute(a) }
36324}
36325#[doc = "Vector reinterpret cast operation"]
36326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
36327#[inline]
36328#[cfg(target_endian = "little")]
36329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36331#[cfg_attr(
36332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36333 assert_instr(nop)
36334)]
36335#[target_feature(enable = "neon,fp16")]
36336#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36337pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
36338 unsafe { transmute(a) }
36339}
36340#[doc = "Vector reinterpret cast operation"]
36341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
36342#[inline]
36343#[cfg(target_endian = "big")]
36344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36346#[cfg_attr(
36347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36348 assert_instr(nop)
36349)]
36350#[target_feature(enable = "neon,fp16")]
36351#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36352pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
36353 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36354 unsafe {
36355 let ret_val: uint8x8_t = transmute(a);
36356 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36357 }
36358}
36359#[doc = "Vector reinterpret cast operation"]
36360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
36361#[inline]
36362#[cfg(target_endian = "little")]
36363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36364#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36365#[cfg_attr(
36366 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36367 assert_instr(nop)
36368)]
36369#[target_feature(enable = "neon,fp16")]
36370#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36371pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
36372 unsafe { transmute(a) }
36373}
36374#[doc = "Vector reinterpret cast operation"]
36375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
36376#[inline]
36377#[cfg(target_endian = "big")]
36378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36380#[cfg_attr(
36381 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36382 assert_instr(nop)
36383)]
36384#[target_feature(enable = "neon,fp16")]
36385#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36386pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
36387 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36388 unsafe {
36389 let ret_val: uint16x4_t = transmute(a);
36390 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36391 }
36392}
36393#[doc = "Vector reinterpret cast operation"]
36394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
36395#[inline]
36396#[cfg(target_endian = "little")]
36397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36399#[cfg_attr(
36400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36401 assert_instr(nop)
36402)]
36403#[target_feature(enable = "neon,fp16")]
36404#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36405pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
36406 unsafe { transmute(a) }
36407}
36408#[doc = "Vector reinterpret cast operation"]
36409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
36410#[inline]
36411#[cfg(target_endian = "big")]
36412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36414#[cfg_attr(
36415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36416 assert_instr(nop)
36417)]
36418#[target_feature(enable = "neon,fp16")]
36419#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36420pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
36421 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36422 unsafe {
36423 let ret_val: uint32x2_t = transmute(a);
36424 simd_shuffle!(ret_val, ret_val, [1, 0])
36425 }
36426}
36427#[doc = "Vector reinterpret cast operation"]
36428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
36429#[inline]
36430#[cfg(target_endian = "little")]
36431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36433#[cfg_attr(
36434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36435 assert_instr(nop)
36436)]
36437#[target_feature(enable = "neon,fp16")]
36438#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36439pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
36440 unsafe { transmute(a) }
36441}
36442#[doc = "Vector reinterpret cast operation"]
36443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
36444#[inline]
36445#[cfg(target_endian = "big")]
36446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36448#[cfg_attr(
36449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36450 assert_instr(nop)
36451)]
36452#[target_feature(enable = "neon,fp16")]
36453#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36454pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
36455 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36456 unsafe { transmute(a) }
36457}
36458#[doc = "Vector reinterpret cast operation"]
36459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
36460#[inline]
36461#[cfg(target_endian = "little")]
36462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36464#[cfg_attr(
36465 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36466 assert_instr(nop)
36467)]
36468#[target_feature(enable = "neon,fp16")]
36469#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36470pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
36471 unsafe { transmute(a) }
36472}
36473#[doc = "Vector reinterpret cast operation"]
36474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
36475#[inline]
36476#[cfg(target_endian = "big")]
36477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36479#[cfg_attr(
36480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36481 assert_instr(nop)
36482)]
36483#[target_feature(enable = "neon,fp16")]
36484#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36485pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
36486 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36487 unsafe {
36488 let ret_val: poly8x8_t = transmute(a);
36489 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36490 }
36491}
36492#[doc = "Vector reinterpret cast operation"]
36493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
36494#[inline]
36495#[cfg(target_endian = "little")]
36496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36498#[cfg_attr(
36499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36500 assert_instr(nop)
36501)]
36502#[target_feature(enable = "neon,fp16")]
36503#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36504pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
36505 unsafe { transmute(a) }
36506}
36507#[doc = "Vector reinterpret cast operation"]
36508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
36509#[inline]
36510#[cfg(target_endian = "big")]
36511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36513#[cfg_attr(
36514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36515 assert_instr(nop)
36516)]
36517#[target_feature(enable = "neon,fp16")]
36518#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36519pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
36520 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36521 unsafe {
36522 let ret_val: poly16x4_t = transmute(a);
36523 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36524 }
36525}
36526#[doc = "Vector reinterpret cast operation"]
36527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
36528#[inline]
36529#[cfg(target_endian = "little")]
36530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36531#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36532#[cfg_attr(
36533 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36534 assert_instr(nop)
36535)]
36536#[target_feature(enable = "neon,fp16")]
36537#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36538pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
36539 unsafe { transmute(a) }
36540}
36541#[doc = "Vector reinterpret cast operation"]
36542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
36543#[inline]
36544#[cfg(target_endian = "big")]
36545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36546#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36547#[cfg_attr(
36548 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36549 assert_instr(nop)
36550)]
36551#[target_feature(enable = "neon,fp16")]
36552#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36553pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
36554 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36555 unsafe {
36556 let ret_val: float32x4_t = transmute(a);
36557 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36558 }
36559}
36560#[doc = "Vector reinterpret cast operation"]
36561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
36562#[inline]
36563#[cfg(target_endian = "little")]
36564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36566#[cfg_attr(
36567 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36568 assert_instr(nop)
36569)]
36570#[target_feature(enable = "neon,fp16")]
36571#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36572pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
36573 unsafe { transmute(a) }
36574}
36575#[doc = "Vector reinterpret cast operation"]
36576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
36577#[inline]
36578#[cfg(target_endian = "big")]
36579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36580#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36581#[cfg_attr(
36582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36583 assert_instr(nop)
36584)]
36585#[target_feature(enable = "neon,fp16")]
36586#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36587pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
36588 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36589 unsafe {
36590 let ret_val: int8x16_t = transmute(a);
36591 simd_shuffle!(
36592 ret_val,
36593 ret_val,
36594 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
36595 )
36596 }
36597}
36598#[doc = "Vector reinterpret cast operation"]
36599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
36600#[inline]
36601#[cfg(target_endian = "little")]
36602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36604#[cfg_attr(
36605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36606 assert_instr(nop)
36607)]
36608#[target_feature(enable = "neon,fp16")]
36609#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36610pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
36611 unsafe { transmute(a) }
36612}
36613#[doc = "Vector reinterpret cast operation"]
36614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
36615#[inline]
36616#[cfg(target_endian = "big")]
36617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36619#[cfg_attr(
36620 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36621 assert_instr(nop)
36622)]
36623#[target_feature(enable = "neon,fp16")]
36624#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36625pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
36626 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36627 unsafe {
36628 let ret_val: int16x8_t = transmute(a);
36629 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36630 }
36631}
36632#[doc = "Vector reinterpret cast operation"]
36633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
36634#[inline]
36635#[cfg(target_endian = "little")]
36636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36638#[cfg_attr(
36639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36640 assert_instr(nop)
36641)]
36642#[target_feature(enable = "neon,fp16")]
36643#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36644pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
36645 unsafe { transmute(a) }
36646}
36647#[doc = "Vector reinterpret cast operation"]
36648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
36649#[inline]
36650#[cfg(target_endian = "big")]
36651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36653#[cfg_attr(
36654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36655 assert_instr(nop)
36656)]
36657#[target_feature(enable = "neon,fp16")]
36658#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36659pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
36660 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36661 unsafe {
36662 let ret_val: int32x4_t = transmute(a);
36663 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36664 }
36665}
36666#[doc = "Vector reinterpret cast operation"]
36667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
36668#[inline]
36669#[cfg(target_endian = "little")]
36670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36672#[cfg_attr(
36673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36674 assert_instr(nop)
36675)]
36676#[target_feature(enable = "neon,fp16")]
36677#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36678pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
36679 unsafe { transmute(a) }
36680}
36681#[doc = "Vector reinterpret cast operation"]
36682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
36683#[inline]
36684#[cfg(target_endian = "big")]
36685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36687#[cfg_attr(
36688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36689 assert_instr(nop)
36690)]
36691#[target_feature(enable = "neon,fp16")]
36692#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36693pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
36694 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36695 unsafe {
36696 let ret_val: int64x2_t = transmute(a);
36697 simd_shuffle!(ret_val, ret_val, [1, 0])
36698 }
36699}
36700#[doc = "Vector reinterpret cast operation"]
36701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
36702#[inline]
36703#[cfg(target_endian = "little")]
36704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36706#[cfg_attr(
36707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36708 assert_instr(nop)
36709)]
36710#[target_feature(enable = "neon,fp16")]
36711#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36712pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
36713 unsafe { transmute(a) }
36714}
36715#[doc = "Vector reinterpret cast operation"]
36716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
36717#[inline]
36718#[cfg(target_endian = "big")]
36719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36721#[cfg_attr(
36722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36723 assert_instr(nop)
36724)]
36725#[target_feature(enable = "neon,fp16")]
36726#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36727pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
36728 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36729 unsafe {
36730 let ret_val: uint8x16_t = transmute(a);
36731 simd_shuffle!(
36732 ret_val,
36733 ret_val,
36734 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
36735 )
36736 }
36737}
36738#[doc = "Vector reinterpret cast operation"]
36739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
36740#[inline]
36741#[cfg(target_endian = "little")]
36742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36744#[cfg_attr(
36745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36746 assert_instr(nop)
36747)]
36748#[target_feature(enable = "neon,fp16")]
36749#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36750pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
36751 unsafe { transmute(a) }
36752}
36753#[doc = "Vector reinterpret cast operation"]
36754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
36755#[inline]
36756#[cfg(target_endian = "big")]
36757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36759#[cfg_attr(
36760 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36761 assert_instr(nop)
36762)]
36763#[target_feature(enable = "neon,fp16")]
36764#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36765pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
36766 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36767 unsafe {
36768 let ret_val: uint16x8_t = transmute(a);
36769 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36770 }
36771}
36772#[doc = "Vector reinterpret cast operation"]
36773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
36774#[inline]
36775#[cfg(target_endian = "little")]
36776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36778#[cfg_attr(
36779 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36780 assert_instr(nop)
36781)]
36782#[target_feature(enable = "neon,fp16")]
36783#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36784pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
36785 unsafe { transmute(a) }
36786}
36787#[doc = "Vector reinterpret cast operation"]
36788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
36789#[inline]
36790#[cfg(target_endian = "big")]
36791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36793#[cfg_attr(
36794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36795 assert_instr(nop)
36796)]
36797#[target_feature(enable = "neon,fp16")]
36798#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36799pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
36800 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36801 unsafe {
36802 let ret_val: uint32x4_t = transmute(a);
36803 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36804 }
36805}
36806#[doc = "Vector reinterpret cast operation"]
36807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
36808#[inline]
36809#[cfg(target_endian = "little")]
36810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36812#[cfg_attr(
36813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36814 assert_instr(nop)
36815)]
36816#[target_feature(enable = "neon,fp16")]
36817#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36818pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
36819 unsafe { transmute(a) }
36820}
36821#[doc = "Vector reinterpret cast operation"]
36822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
36823#[inline]
36824#[cfg(target_endian = "big")]
36825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36827#[cfg_attr(
36828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36829 assert_instr(nop)
36830)]
36831#[target_feature(enable = "neon,fp16")]
36832#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36833pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
36834 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36835 unsafe {
36836 let ret_val: uint64x2_t = transmute(a);
36837 simd_shuffle!(ret_val, ret_val, [1, 0])
36838 }
36839}
36840#[doc = "Vector reinterpret cast operation"]
36841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
36842#[inline]
36843#[cfg(target_endian = "little")]
36844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36845#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36846#[cfg_attr(
36847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36848 assert_instr(nop)
36849)]
36850#[target_feature(enable = "neon,fp16")]
36851#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36852pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
36853 unsafe { transmute(a) }
36854}
36855#[doc = "Vector reinterpret cast operation"]
36856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
36857#[inline]
36858#[cfg(target_endian = "big")]
36859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36861#[cfg_attr(
36862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36863 assert_instr(nop)
36864)]
36865#[target_feature(enable = "neon,fp16")]
36866#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36867pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
36868 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36869 unsafe {
36870 let ret_val: poly8x16_t = transmute(a);
36871 simd_shuffle!(
36872 ret_val,
36873 ret_val,
36874 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
36875 )
36876 }
36877}
36878#[doc = "Vector reinterpret cast operation"]
36879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
36880#[inline]
36881#[cfg(target_endian = "little")]
36882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36883#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36884#[cfg_attr(
36885 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36886 assert_instr(nop)
36887)]
36888#[target_feature(enable = "neon,fp16")]
36889#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36890pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
36891 unsafe { transmute(a) }
36892}
36893#[doc = "Vector reinterpret cast operation"]
36894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
36895#[inline]
36896#[cfg(target_endian = "big")]
36897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36899#[cfg_attr(
36900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36901 assert_instr(nop)
36902)]
36903#[target_feature(enable = "neon,fp16")]
36904#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36905pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
36906 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36907 unsafe {
36908 let ret_val: poly16x8_t = transmute(a);
36909 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36910 }
36911}
36912#[doc = "Vector reinterpret cast operation"]
36913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
36914#[inline]
36915#[cfg(target_endian = "little")]
36916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36918#[cfg_attr(
36919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36920 assert_instr(nop)
36921)]
36922#[target_feature(enable = "neon,fp16")]
36923#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36924pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
36925 unsafe { transmute(a) }
36926}
36927#[doc = "Vector reinterpret cast operation"]
36928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
36929#[inline]
36930#[cfg(target_endian = "big")]
36931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36933#[cfg_attr(
36934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36935 assert_instr(nop)
36936)]
36937#[target_feature(enable = "neon,fp16")]
36938#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36939pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
36940 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
36941 unsafe {
36942 let ret_val: float16x4_t = transmute(a);
36943 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36944 }
36945}
36946#[doc = "Vector reinterpret cast operation"]
36947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
36948#[inline]
36949#[cfg(target_endian = "little")]
36950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36952#[cfg_attr(
36953 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36954 assert_instr(nop)
36955)]
36956#[target_feature(enable = "neon,fp16")]
36957#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36958pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
36959 unsafe { transmute(a) }
36960}
36961#[doc = "Vector reinterpret cast operation"]
36962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
36963#[inline]
36964#[cfg(target_endian = "big")]
36965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36967#[cfg_attr(
36968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36969 assert_instr(nop)
36970)]
36971#[target_feature(enable = "neon,fp16")]
36972#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36973pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
36974 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36975 unsafe {
36976 let ret_val: float16x8_t = transmute(a);
36977 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36978 }
36979}
36980#[doc = "Vector reinterpret cast operation"]
36981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
36982#[inline]
36983#[cfg(target_endian = "little")]
36984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
36986#[cfg_attr(
36987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36988 assert_instr(nop)
36989)]
36990#[target_feature(enable = "neon,fp16")]
36991#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
36992pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
36993 unsafe { transmute(a) }
36994}
36995#[doc = "Vector reinterpret cast operation"]
36996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
36997#[inline]
36998#[cfg(target_endian = "big")]
36999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37001#[cfg_attr(
37002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37003 assert_instr(nop)
37004)]
37005#[target_feature(enable = "neon,fp16")]
37006#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37007pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
37008 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37009 unsafe {
37010 let ret_val: float16x4_t = transmute(a);
37011 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37012 }
37013}
37014#[doc = "Vector reinterpret cast operation"]
37015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
37016#[inline]
37017#[cfg(target_endian = "little")]
37018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37020#[cfg_attr(
37021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37022 assert_instr(nop)
37023)]
37024#[target_feature(enable = "neon,fp16")]
37025#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37026pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
37027 unsafe { transmute(a) }
37028}
37029#[doc = "Vector reinterpret cast operation"]
37030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
37031#[inline]
37032#[cfg(target_endian = "big")]
37033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37035#[cfg_attr(
37036 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37037 assert_instr(nop)
37038)]
37039#[target_feature(enable = "neon,fp16")]
37040#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37041pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
37042 let a: int8x16_t =
37043 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
37044 unsafe {
37045 let ret_val: float16x8_t = transmute(a);
37046 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37047 }
37048}
37049#[doc = "Vector reinterpret cast operation"]
37050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
37051#[inline]
37052#[cfg(target_endian = "little")]
37053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37055#[cfg_attr(
37056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37057 assert_instr(nop)
37058)]
37059#[target_feature(enable = "neon,fp16")]
37060#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37061pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
37062 unsafe { transmute(a) }
37063}
37064#[doc = "Vector reinterpret cast operation"]
37065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
37066#[inline]
37067#[cfg(target_endian = "big")]
37068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37070#[cfg_attr(
37071 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37072 assert_instr(nop)
37073)]
37074#[target_feature(enable = "neon,fp16")]
37075#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37076pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
37077 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
37078 unsafe {
37079 let ret_val: float16x4_t = transmute(a);
37080 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37081 }
37082}
37083#[doc = "Vector reinterpret cast operation"]
37084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
37085#[inline]
37086#[cfg(target_endian = "little")]
37087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37089#[cfg_attr(
37090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37091 assert_instr(nop)
37092)]
37093#[target_feature(enable = "neon,fp16")]
37094#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37095pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
37096 unsafe { transmute(a) }
37097}
37098#[doc = "Vector reinterpret cast operation"]
37099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
37100#[inline]
37101#[cfg(target_endian = "big")]
37102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37104#[cfg_attr(
37105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37106 assert_instr(nop)
37107)]
37108#[target_feature(enable = "neon,fp16")]
37109#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37110pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
37111 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37112 unsafe {
37113 let ret_val: float16x8_t = transmute(a);
37114 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37115 }
37116}
37117#[doc = "Vector reinterpret cast operation"]
37118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
37119#[inline]
37120#[cfg(target_endian = "little")]
37121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37123#[cfg_attr(
37124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37125 assert_instr(nop)
37126)]
37127#[target_feature(enable = "neon,fp16")]
37128#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37129pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
37130 unsafe { transmute(a) }
37131}
37132#[doc = "Vector reinterpret cast operation"]
37133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
37134#[inline]
37135#[cfg(target_endian = "big")]
37136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37138#[cfg_attr(
37139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37140 assert_instr(nop)
37141)]
37142#[target_feature(enable = "neon,fp16")]
37143#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37144pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
37145 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37146 unsafe {
37147 let ret_val: float16x4_t = transmute(a);
37148 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37149 }
37150}
37151#[doc = "Vector reinterpret cast operation"]
37152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
37153#[inline]
37154#[cfg(target_endian = "little")]
37155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37157#[cfg_attr(
37158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37159 assert_instr(nop)
37160)]
37161#[target_feature(enable = "neon,fp16")]
37162#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37163pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
37164 unsafe { transmute(a) }
37165}
37166#[doc = "Vector reinterpret cast operation"]
37167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
37168#[inline]
37169#[cfg(target_endian = "big")]
37170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37171#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37172#[cfg_attr(
37173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37174 assert_instr(nop)
37175)]
37176#[target_feature(enable = "neon,fp16")]
37177#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37178pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
37179 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
37180 unsafe {
37181 let ret_val: float16x8_t = transmute(a);
37182 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37183 }
37184}
37185#[doc = "Vector reinterpret cast operation"]
37186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
37187#[inline]
37188#[cfg(target_endian = "little")]
37189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37191#[cfg_attr(
37192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37193 assert_instr(nop)
37194)]
37195#[target_feature(enable = "neon,fp16")]
37196#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37197pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
37198 unsafe { transmute(a) }
37199}
37200#[doc = "Vector reinterpret cast operation"]
37201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
37202#[inline]
37203#[cfg(target_endian = "big")]
37204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37206#[cfg_attr(
37207 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37208 assert_instr(nop)
37209)]
37210#[target_feature(enable = "neon,fp16")]
37211#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37212pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
37213 unsafe {
37214 let ret_val: float16x4_t = transmute(a);
37215 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37216 }
37217}
37218#[doc = "Vector reinterpret cast operation"]
37219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
37220#[inline]
37221#[cfg(target_endian = "little")]
37222#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37223#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37224#[cfg_attr(
37225 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37226 assert_instr(nop)
37227)]
37228#[target_feature(enable = "neon,fp16")]
37229#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37230pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
37231 unsafe { transmute(a) }
37232}
37233#[doc = "Vector reinterpret cast operation"]
37234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
37235#[inline]
37236#[cfg(target_endian = "big")]
37237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37238#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37239#[cfg_attr(
37240 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37241 assert_instr(nop)
37242)]
37243#[target_feature(enable = "neon,fp16")]
37244#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37245pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
37246 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37247 unsafe {
37248 let ret_val: float16x8_t = transmute(a);
37249 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37250 }
37251}
37252#[doc = "Vector reinterpret cast operation"]
37253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
37254#[inline]
37255#[cfg(target_endian = "little")]
37256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37258#[cfg_attr(
37259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37260 assert_instr(nop)
37261)]
37262#[target_feature(enable = "neon,fp16")]
37263#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37264pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
37265 unsafe { transmute(a) }
37266}
37267#[doc = "Vector reinterpret cast operation"]
37268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
37269#[inline]
37270#[cfg(target_endian = "big")]
37271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37273#[cfg_attr(
37274 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37275 assert_instr(nop)
37276)]
37277#[target_feature(enable = "neon,fp16")]
37278#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37279pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
37280 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37281 unsafe {
37282 let ret_val: float16x4_t = transmute(a);
37283 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37284 }
37285}
37286#[doc = "Vector reinterpret cast operation"]
37287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
37288#[inline]
37289#[cfg(target_endian = "little")]
37290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37292#[cfg_attr(
37293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37294 assert_instr(nop)
37295)]
37296#[target_feature(enable = "neon,fp16")]
37297#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37298pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
37299 unsafe { transmute(a) }
37300}
37301#[doc = "Vector reinterpret cast operation"]
37302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
37303#[inline]
37304#[cfg(target_endian = "big")]
37305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37307#[cfg_attr(
37308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37309 assert_instr(nop)
37310)]
37311#[target_feature(enable = "neon,fp16")]
37312#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37313pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
37314 let a: uint8x16_t =
37315 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
37316 unsafe {
37317 let ret_val: float16x8_t = transmute(a);
37318 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37319 }
37320}
37321#[doc = "Vector reinterpret cast operation"]
37322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
37323#[inline]
37324#[cfg(target_endian = "little")]
37325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37327#[cfg_attr(
37328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37329 assert_instr(nop)
37330)]
37331#[target_feature(enable = "neon,fp16")]
37332#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37333pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
37334 unsafe { transmute(a) }
37335}
37336#[doc = "Vector reinterpret cast operation"]
37337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
37338#[inline]
37339#[cfg(target_endian = "big")]
37340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37342#[cfg_attr(
37343 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37344 assert_instr(nop)
37345)]
37346#[target_feature(enable = "neon,fp16")]
37347#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37348pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
37349 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
37350 unsafe {
37351 let ret_val: float16x4_t = transmute(a);
37352 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37353 }
37354}
37355#[doc = "Vector reinterpret cast operation"]
37356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
37357#[inline]
37358#[cfg(target_endian = "little")]
37359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37361#[cfg_attr(
37362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37363 assert_instr(nop)
37364)]
37365#[target_feature(enable = "neon,fp16")]
37366#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37367pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
37368 unsafe { transmute(a) }
37369}
37370#[doc = "Vector reinterpret cast operation"]
37371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
37372#[inline]
37373#[cfg(target_endian = "big")]
37374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37376#[cfg_attr(
37377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37378 assert_instr(nop)
37379)]
37380#[target_feature(enable = "neon,fp16")]
37381#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37382pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
37383 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37384 unsafe {
37385 let ret_val: float16x8_t = transmute(a);
37386 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37387 }
37388}
37389#[doc = "Vector reinterpret cast operation"]
37390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
37391#[inline]
37392#[cfg(target_endian = "little")]
37393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37395#[cfg_attr(
37396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37397 assert_instr(nop)
37398)]
37399#[target_feature(enable = "neon,fp16")]
37400#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37401pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
37402 unsafe { transmute(a) }
37403}
37404#[doc = "Vector reinterpret cast operation"]
37405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
37406#[inline]
37407#[cfg(target_endian = "big")]
37408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37410#[cfg_attr(
37411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37412 assert_instr(nop)
37413)]
37414#[target_feature(enable = "neon,fp16")]
37415#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37416pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
37417 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37418 unsafe {
37419 let ret_val: float16x4_t = transmute(a);
37420 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37421 }
37422}
37423#[doc = "Vector reinterpret cast operation"]
37424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
37425#[inline]
37426#[cfg(target_endian = "little")]
37427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37429#[cfg_attr(
37430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37431 assert_instr(nop)
37432)]
37433#[target_feature(enable = "neon,fp16")]
37434#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37435pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
37436 unsafe { transmute(a) }
37437}
37438#[doc = "Vector reinterpret cast operation"]
37439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
37440#[inline]
37441#[cfg(target_endian = "big")]
37442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37444#[cfg_attr(
37445 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37446 assert_instr(nop)
37447)]
37448#[target_feature(enable = "neon,fp16")]
37449#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37450pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
37451 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
37452 unsafe {
37453 let ret_val: float16x8_t = transmute(a);
37454 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37455 }
37456}
37457#[doc = "Vector reinterpret cast operation"]
37458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
37459#[inline]
37460#[cfg(target_endian = "little")]
37461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37463#[cfg_attr(
37464 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37465 assert_instr(nop)
37466)]
37467#[target_feature(enable = "neon,fp16")]
37468#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37469pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
37470 unsafe { transmute(a) }
37471}
37472#[doc = "Vector reinterpret cast operation"]
37473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
37474#[inline]
37475#[cfg(target_endian = "big")]
37476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37477#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37478#[cfg_attr(
37479 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37480 assert_instr(nop)
37481)]
37482#[target_feature(enable = "neon,fp16")]
37483#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37484pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
37485 unsafe {
37486 let ret_val: float16x4_t = transmute(a);
37487 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37488 }
37489}
37490#[doc = "Vector reinterpret cast operation"]
37491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
37492#[inline]
37493#[cfg(target_endian = "little")]
37494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37496#[cfg_attr(
37497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37498 assert_instr(nop)
37499)]
37500#[target_feature(enable = "neon,fp16")]
37501#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37502pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
37503 unsafe { transmute(a) }
37504}
37505#[doc = "Vector reinterpret cast operation"]
37506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
37507#[inline]
37508#[cfg(target_endian = "big")]
37509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37511#[cfg_attr(
37512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37513 assert_instr(nop)
37514)]
37515#[target_feature(enable = "neon,fp16")]
37516#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37517pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
37518 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37519 unsafe {
37520 let ret_val: float16x8_t = transmute(a);
37521 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37522 }
37523}
37524#[doc = "Vector reinterpret cast operation"]
37525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
37526#[inline]
37527#[cfg(target_endian = "little")]
37528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37530#[cfg_attr(
37531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37532 assert_instr(nop)
37533)]
37534#[target_feature(enable = "neon,fp16")]
37535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37536pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
37537 unsafe { transmute(a) }
37538}
37539#[doc = "Vector reinterpret cast operation"]
37540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
37541#[inline]
37542#[cfg(target_endian = "big")]
37543#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37544#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37545#[cfg_attr(
37546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37547 assert_instr(nop)
37548)]
37549#[target_feature(enable = "neon,fp16")]
37550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37551pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
37552 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37553 unsafe {
37554 let ret_val: float16x4_t = transmute(a);
37555 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37556 }
37557}
37558#[doc = "Vector reinterpret cast operation"]
37559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
37560#[inline]
37561#[cfg(target_endian = "little")]
37562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37564#[cfg_attr(
37565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37566 assert_instr(nop)
37567)]
37568#[target_feature(enable = "neon,fp16")]
37569#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37570pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
37571 unsafe { transmute(a) }
37572}
37573#[doc = "Vector reinterpret cast operation"]
37574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
37575#[inline]
37576#[cfg(target_endian = "big")]
37577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37579#[cfg_attr(
37580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37581 assert_instr(nop)
37582)]
37583#[target_feature(enable = "neon,fp16")]
37584#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37585pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
37586 let a: poly8x16_t =
37587 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
37588 unsafe {
37589 let ret_val: float16x8_t = transmute(a);
37590 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37591 }
37592}
37593#[doc = "Vector reinterpret cast operation"]
37594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
37595#[inline]
37596#[cfg(target_endian = "little")]
37597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37599#[cfg_attr(
37600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37601 assert_instr(nop)
37602)]
37603#[target_feature(enable = "neon,fp16")]
37604#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37605pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
37606 unsafe { transmute(a) }
37607}
37608#[doc = "Vector reinterpret cast operation"]
37609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
37610#[inline]
37611#[cfg(target_endian = "big")]
37612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37614#[cfg_attr(
37615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37616 assert_instr(nop)
37617)]
37618#[target_feature(enable = "neon,fp16")]
37619#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37620pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
37621 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
37622 unsafe {
37623 let ret_val: float16x4_t = transmute(a);
37624 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37625 }
37626}
37627#[doc = "Vector reinterpret cast operation"]
37628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
37629#[inline]
37630#[cfg(target_endian = "little")]
37631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37633#[cfg_attr(
37634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37635 assert_instr(nop)
37636)]
37637#[target_feature(enable = "neon,fp16")]
37638#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37639pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
37640 unsafe { transmute(a) }
37641}
37642#[doc = "Vector reinterpret cast operation"]
37643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
37644#[inline]
37645#[cfg(target_endian = "big")]
37646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37648#[cfg_attr(
37649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37650 assert_instr(nop)
37651)]
37652#[target_feature(enable = "neon,fp16")]
37653#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37654pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
37655 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37656 unsafe {
37657 let ret_val: float16x8_t = transmute(a);
37658 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37659 }
37660}
37661#[doc = "Vector reinterpret cast operation"]
37662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
37663#[inline]
37664#[cfg(target_endian = "little")]
37665#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37667#[cfg_attr(
37668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37669 assert_instr(nop)
37670)]
37671#[target_feature(enable = "neon,fp16")]
37672#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37673pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
37674 unsafe { transmute(a) }
37675}
37676#[doc = "Vector reinterpret cast operation"]
37677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
37678#[inline]
37679#[cfg(target_endian = "big")]
37680#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37682#[cfg_attr(
37683 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37684 assert_instr(nop)
37685)]
37686#[target_feature(enable = "neon,fp16")]
37687#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37688pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
37689 unsafe {
37690 let ret_val: float16x8_t = transmute(a);
37691 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37692 }
37693}
37694#[doc = "Vector reinterpret cast operation"]
37695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
37696#[inline]
37697#[cfg(target_endian = "little")]
37698#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37700#[cfg_attr(
37701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37702 assert_instr(nop)
37703)]
37704#[target_feature(enable = "neon,fp16")]
37705#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37706pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
37707 unsafe { transmute(a) }
37708}
37709#[doc = "Vector reinterpret cast operation"]
37710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
37711#[inline]
37712#[cfg(target_endian = "big")]
37713#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37714#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37715#[cfg_attr(
37716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37717 assert_instr(nop)
37718)]
37719#[target_feature(enable = "neon,fp16")]
37720#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37721pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
37722 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
37723 unsafe { transmute(a) }
37724}
37725#[doc = "Vector reinterpret cast operation"]
37726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
37727#[inline]
37728#[cfg(target_endian = "little")]
37729#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37731#[cfg_attr(
37732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37733 assert_instr(nop)
37734)]
37735#[target_feature(enable = "neon,fp16")]
37736#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37737pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
37738 unsafe { transmute(a) }
37739}
37740#[doc = "Vector reinterpret cast operation"]
37741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
37742#[inline]
37743#[cfg(target_endian = "big")]
37744#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37746#[cfg_attr(
37747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37748 assert_instr(nop)
37749)]
37750#[target_feature(enable = "neon,fp16")]
37751#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37752pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
37753 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37754 unsafe { transmute(a) }
37755}
37756#[doc = "Vector reinterpret cast operation"]
37757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
37758#[inline]
37759#[cfg(target_endian = "little")]
37760#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37762#[cfg_attr(
37763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37764 assert_instr(nop)
37765)]
37766#[target_feature(enable = "neon,fp16")]
37767#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37768pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
37769 unsafe { transmute(a) }
37770}
37771#[doc = "Vector reinterpret cast operation"]
37772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
37773#[inline]
37774#[cfg(target_endian = "big")]
37775#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37776#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37777#[cfg_attr(
37778 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37779 assert_instr(nop)
37780)]
37781#[target_feature(enable = "neon,fp16")]
37782#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37783pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
37784 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
37785 unsafe {
37786 let ret_val: poly64x2_t = transmute(a);
37787 simd_shuffle!(ret_val, ret_val, [1, 0])
37788 }
37789}
37790#[doc = "Vector reinterpret cast operation"]
37791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
37792#[inline]
37793#[cfg(target_endian = "little")]
37794#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37796#[cfg_attr(
37797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37798 assert_instr(nop)
37799)]
37800#[target_feature(enable = "neon,fp16")]
37801#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37802pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
37803 unsafe { transmute(a) }
37804}
37805#[doc = "Vector reinterpret cast operation"]
37806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
37807#[inline]
37808#[cfg(target_endian = "big")]
37809#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37811#[cfg_attr(
37812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37813 assert_instr(nop)
37814)]
37815#[target_feature(enable = "neon,fp16")]
37816#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37817pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
37818 unsafe {
37819 let ret_val: float16x4_t = transmute(a);
37820 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37821 }
37822}
37823#[doc = "Vector reinterpret cast operation"]
37824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
37825#[inline]
37826#[cfg(target_endian = "little")]
37827#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37829#[cfg_attr(
37830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37831 assert_instr(nop)
37832)]
37833#[target_feature(enable = "neon,fp16")]
37834#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37835pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
37836 unsafe { transmute(a) }
37837}
37838#[doc = "Vector reinterpret cast operation"]
37839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
37840#[inline]
37841#[cfg(target_endian = "big")]
37842#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
37843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37844#[cfg_attr(
37845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37846 assert_instr(nop)
37847)]
37848#[target_feature(enable = "neon,fp16")]
37849#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
37850pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
37851 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37852 unsafe {
37853 let ret_val: float16x8_t = transmute(a);
37854 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37855 }
37856}
37857#[doc = "Vector reinterpret cast operation"]
37858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
37859#[inline]
37860#[cfg(target_endian = "little")]
37861#[target_feature(enable = "neon")]
37862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37863#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37864#[cfg_attr(
37865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37866 assert_instr(nop)
37867)]
37868#[cfg_attr(
37869 not(target_arch = "arm"),
37870 stable(feature = "neon_intrinsics", since = "1.59.0")
37871)]
37872#[cfg_attr(
37873 target_arch = "arm",
37874 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37875)]
37876pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
37877 unsafe { transmute(a) }
37878}
37879#[doc = "Vector reinterpret cast operation"]
37880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
37881#[inline]
37882#[cfg(target_endian = "big")]
37883#[target_feature(enable = "neon")]
37884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37885#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37886#[cfg_attr(
37887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37888 assert_instr(nop)
37889)]
37890#[cfg_attr(
37891 not(target_arch = "arm"),
37892 stable(feature = "neon_intrinsics", since = "1.59.0")
37893)]
37894#[cfg_attr(
37895 target_arch = "arm",
37896 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37897)]
37898pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
37899 unsafe {
37900 let ret_val: float32x4_t = transmute(a);
37901 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37902 }
37903}
37904#[doc = "Vector reinterpret cast operation"]
37905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
37906#[inline]
37907#[cfg(target_endian = "little")]
37908#[target_feature(enable = "neon")]
37909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37910#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37911#[cfg_attr(
37912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37913 assert_instr(nop)
37914)]
37915#[cfg_attr(
37916 not(target_arch = "arm"),
37917 stable(feature = "neon_intrinsics", since = "1.59.0")
37918)]
37919#[cfg_attr(
37920 target_arch = "arm",
37921 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37922)]
37923pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
37924 unsafe { transmute(a) }
37925}
37926#[doc = "Vector reinterpret cast operation"]
37927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
37928#[inline]
37929#[cfg(target_endian = "big")]
37930#[target_feature(enable = "neon")]
37931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37933#[cfg_attr(
37934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37935 assert_instr(nop)
37936)]
37937#[cfg_attr(
37938 not(target_arch = "arm"),
37939 stable(feature = "neon_intrinsics", since = "1.59.0")
37940)]
37941#[cfg_attr(
37942 target_arch = "arm",
37943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37944)]
37945pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
37946 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37947 unsafe {
37948 let ret_val: int8x8_t = transmute(a);
37949 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
37950 }
37951}
37952#[doc = "Vector reinterpret cast operation"]
37953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
37954#[inline]
37955#[cfg(target_endian = "little")]
37956#[target_feature(enable = "neon")]
37957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37959#[cfg_attr(
37960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37961 assert_instr(nop)
37962)]
37963#[cfg_attr(
37964 not(target_arch = "arm"),
37965 stable(feature = "neon_intrinsics", since = "1.59.0")
37966)]
37967#[cfg_attr(
37968 target_arch = "arm",
37969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37970)]
37971pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
37972 unsafe { transmute(a) }
37973}
37974#[doc = "Vector reinterpret cast operation"]
37975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
37976#[inline]
37977#[cfg(target_endian = "big")]
37978#[target_feature(enable = "neon")]
37979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
37981#[cfg_attr(
37982 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37983 assert_instr(nop)
37984)]
37985#[cfg_attr(
37986 not(target_arch = "arm"),
37987 stable(feature = "neon_intrinsics", since = "1.59.0")
37988)]
37989#[cfg_attr(
37990 target_arch = "arm",
37991 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37992)]
37993pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
37994 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
37995 unsafe {
37996 let ret_val: int16x4_t = transmute(a);
37997 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
37998 }
37999}
38000#[doc = "Vector reinterpret cast operation"]
38001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
38002#[inline]
38003#[cfg(target_endian = "little")]
38004#[target_feature(enable = "neon")]
38005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38007#[cfg_attr(
38008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38009 assert_instr(nop)
38010)]
38011#[cfg_attr(
38012 not(target_arch = "arm"),
38013 stable(feature = "neon_intrinsics", since = "1.59.0")
38014)]
38015#[cfg_attr(
38016 target_arch = "arm",
38017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38018)]
38019pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
38020 unsafe { transmute(a) }
38021}
38022#[doc = "Vector reinterpret cast operation"]
38023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
38024#[inline]
38025#[cfg(target_endian = "big")]
38026#[target_feature(enable = "neon")]
38027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38029#[cfg_attr(
38030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38031 assert_instr(nop)
38032)]
38033#[cfg_attr(
38034 not(target_arch = "arm"),
38035 stable(feature = "neon_intrinsics", since = "1.59.0")
38036)]
38037#[cfg_attr(
38038 target_arch = "arm",
38039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38040)]
38041pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
38042 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38043 unsafe {
38044 let ret_val: int32x2_t = transmute(a);
38045 simd_shuffle!(ret_val, ret_val, [1, 0])
38046 }
38047}
38048#[doc = "Vector reinterpret cast operation"]
38049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
38050#[inline]
38051#[cfg(target_endian = "little")]
38052#[target_feature(enable = "neon")]
38053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38055#[cfg_attr(
38056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38057 assert_instr(nop)
38058)]
38059#[cfg_attr(
38060 not(target_arch = "arm"),
38061 stable(feature = "neon_intrinsics", since = "1.59.0")
38062)]
38063#[cfg_attr(
38064 target_arch = "arm",
38065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38066)]
38067pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
38068 unsafe { transmute(a) }
38069}
38070#[doc = "Vector reinterpret cast operation"]
38071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
38072#[inline]
38073#[cfg(target_endian = "big")]
38074#[target_feature(enable = "neon")]
38075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38077#[cfg_attr(
38078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38079 assert_instr(nop)
38080)]
38081#[cfg_attr(
38082 not(target_arch = "arm"),
38083 stable(feature = "neon_intrinsics", since = "1.59.0")
38084)]
38085#[cfg_attr(
38086 target_arch = "arm",
38087 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38088)]
38089pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
38090 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38091 unsafe { transmute(a) }
38092}
38093#[doc = "Vector reinterpret cast operation"]
38094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
38095#[inline]
38096#[cfg(target_endian = "little")]
38097#[target_feature(enable = "neon")]
38098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38100#[cfg_attr(
38101 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38102 assert_instr(nop)
38103)]
38104#[cfg_attr(
38105 not(target_arch = "arm"),
38106 stable(feature = "neon_intrinsics", since = "1.59.0")
38107)]
38108#[cfg_attr(
38109 target_arch = "arm",
38110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38111)]
38112pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
38113 unsafe { transmute(a) }
38114}
38115#[doc = "Vector reinterpret cast operation"]
38116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
38117#[inline]
38118#[cfg(target_endian = "big")]
38119#[target_feature(enable = "neon")]
38120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38122#[cfg_attr(
38123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38124 assert_instr(nop)
38125)]
38126#[cfg_attr(
38127 not(target_arch = "arm"),
38128 stable(feature = "neon_intrinsics", since = "1.59.0")
38129)]
38130#[cfg_attr(
38131 target_arch = "arm",
38132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38133)]
38134pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
38135 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38136 unsafe {
38137 let ret_val: uint8x8_t = transmute(a);
38138 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
38139 }
38140}
38141#[doc = "Vector reinterpret cast operation"]
38142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
38143#[inline]
38144#[cfg(target_endian = "little")]
38145#[target_feature(enable = "neon")]
38146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38148#[cfg_attr(
38149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38150 assert_instr(nop)
38151)]
38152#[cfg_attr(
38153 not(target_arch = "arm"),
38154 stable(feature = "neon_intrinsics", since = "1.59.0")
38155)]
38156#[cfg_attr(
38157 target_arch = "arm",
38158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38159)]
38160pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
38161 unsafe { transmute(a) }
38162}
38163#[doc = "Vector reinterpret cast operation"]
38164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
38165#[inline]
38166#[cfg(target_endian = "big")]
38167#[target_feature(enable = "neon")]
38168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38170#[cfg_attr(
38171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38172 assert_instr(nop)
38173)]
38174#[cfg_attr(
38175 not(target_arch = "arm"),
38176 stable(feature = "neon_intrinsics", since = "1.59.0")
38177)]
38178#[cfg_attr(
38179 target_arch = "arm",
38180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38181)]
38182pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
38183 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38184 unsafe {
38185 let ret_val: uint16x4_t = transmute(a);
38186 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
38187 }
38188}
38189#[doc = "Vector reinterpret cast operation"]
38190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
38191#[inline]
38192#[cfg(target_endian = "little")]
38193#[target_feature(enable = "neon")]
38194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38196#[cfg_attr(
38197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38198 assert_instr(nop)
38199)]
38200#[cfg_attr(
38201 not(target_arch = "arm"),
38202 stable(feature = "neon_intrinsics", since = "1.59.0")
38203)]
38204#[cfg_attr(
38205 target_arch = "arm",
38206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38207)]
38208pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
38209 unsafe { transmute(a) }
38210}
38211#[doc = "Vector reinterpret cast operation"]
38212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
38213#[inline]
38214#[cfg(target_endian = "big")]
38215#[target_feature(enable = "neon")]
38216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38218#[cfg_attr(
38219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38220 assert_instr(nop)
38221)]
38222#[cfg_attr(
38223 not(target_arch = "arm"),
38224 stable(feature = "neon_intrinsics", since = "1.59.0")
38225)]
38226#[cfg_attr(
38227 target_arch = "arm",
38228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38229)]
38230pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
38231 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38232 unsafe {
38233 let ret_val: uint32x2_t = transmute(a);
38234 simd_shuffle!(ret_val, ret_val, [1, 0])
38235 }
38236}
38237#[doc = "Vector reinterpret cast operation"]
38238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
38239#[inline]
38240#[cfg(target_endian = "little")]
38241#[target_feature(enable = "neon")]
38242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38244#[cfg_attr(
38245 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38246 assert_instr(nop)
38247)]
38248#[cfg_attr(
38249 not(target_arch = "arm"),
38250 stable(feature = "neon_intrinsics", since = "1.59.0")
38251)]
38252#[cfg_attr(
38253 target_arch = "arm",
38254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38255)]
38256pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
38257 unsafe { transmute(a) }
38258}
38259#[doc = "Vector reinterpret cast operation"]
38260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
38261#[inline]
38262#[cfg(target_endian = "big")]
38263#[target_feature(enable = "neon")]
38264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38266#[cfg_attr(
38267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38268 assert_instr(nop)
38269)]
38270#[cfg_attr(
38271 not(target_arch = "arm"),
38272 stable(feature = "neon_intrinsics", since = "1.59.0")
38273)]
38274#[cfg_attr(
38275 target_arch = "arm",
38276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38277)]
38278pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
38279 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38280 unsafe { transmute(a) }
38281}
38282#[doc = "Vector reinterpret cast operation"]
38283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
38284#[inline]
38285#[cfg(target_endian = "little")]
38286#[target_feature(enable = "neon")]
38287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38289#[cfg_attr(
38290 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38291 assert_instr(nop)
38292)]
38293#[cfg_attr(
38294 not(target_arch = "arm"),
38295 stable(feature = "neon_intrinsics", since = "1.59.0")
38296)]
38297#[cfg_attr(
38298 target_arch = "arm",
38299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38300)]
38301pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
38302 unsafe { transmute(a) }
38303}
38304#[doc = "Vector reinterpret cast operation"]
38305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
38306#[inline]
38307#[cfg(target_endian = "big")]
38308#[target_feature(enable = "neon")]
38309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38311#[cfg_attr(
38312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38313 assert_instr(nop)
38314)]
38315#[cfg_attr(
38316 not(target_arch = "arm"),
38317 stable(feature = "neon_intrinsics", since = "1.59.0")
38318)]
38319#[cfg_attr(
38320 target_arch = "arm",
38321 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38322)]
38323pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
38324 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38325 unsafe {
38326 let ret_val: poly8x8_t = transmute(a);
38327 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
38328 }
38329}
38330#[doc = "Vector reinterpret cast operation"]
38331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
38332#[inline]
38333#[cfg(target_endian = "little")]
38334#[target_feature(enable = "neon")]
38335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38337#[cfg_attr(
38338 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38339 assert_instr(nop)
38340)]
38341#[cfg_attr(
38342 not(target_arch = "arm"),
38343 stable(feature = "neon_intrinsics", since = "1.59.0")
38344)]
38345#[cfg_attr(
38346 target_arch = "arm",
38347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38348)]
38349pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
38350 unsafe { transmute(a) }
38351}
38352#[doc = "Vector reinterpret cast operation"]
38353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
38354#[inline]
38355#[cfg(target_endian = "big")]
38356#[target_feature(enable = "neon")]
38357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38359#[cfg_attr(
38360 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38361 assert_instr(nop)
38362)]
38363#[cfg_attr(
38364 not(target_arch = "arm"),
38365 stable(feature = "neon_intrinsics", since = "1.59.0")
38366)]
38367#[cfg_attr(
38368 target_arch = "arm",
38369 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38370)]
38371pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
38372 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
38373 unsafe {
38374 let ret_val: poly16x4_t = transmute(a);
38375 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
38376 }
38377}
38378#[doc = "Vector reinterpret cast operation"]
38379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
38380#[inline]
38381#[cfg(target_endian = "little")]
38382#[target_feature(enable = "neon")]
38383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38385#[cfg_attr(
38386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38387 assert_instr(nop)
38388)]
38389#[cfg_attr(
38390 not(target_arch = "arm"),
38391 stable(feature = "neon_intrinsics", since = "1.59.0")
38392)]
38393#[cfg_attr(
38394 target_arch = "arm",
38395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38396)]
38397pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
38398 unsafe { transmute(a) }
38399}
38400#[doc = "Vector reinterpret cast operation"]
38401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
38402#[inline]
38403#[cfg(target_endian = "big")]
38404#[target_feature(enable = "neon")]
38405#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38406#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38407#[cfg_attr(
38408 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38409 assert_instr(nop)
38410)]
38411#[cfg_attr(
38412 not(target_arch = "arm"),
38413 stable(feature = "neon_intrinsics", since = "1.59.0")
38414)]
38415#[cfg_attr(
38416 target_arch = "arm",
38417 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38418)]
38419pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
38420 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38421 unsafe { transmute(a) }
38422}
38423#[doc = "Vector reinterpret cast operation"]
38424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
38425#[inline]
38426#[cfg(target_endian = "little")]
38427#[target_feature(enable = "neon")]
38428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38430#[cfg_attr(
38431 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38432 assert_instr(nop)
38433)]
38434#[cfg_attr(
38435 not(target_arch = "arm"),
38436 stable(feature = "neon_intrinsics", since = "1.59.0")
38437)]
38438#[cfg_attr(
38439 target_arch = "arm",
38440 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38441)]
38442pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
38443 unsafe { transmute(a) }
38444}
38445#[doc = "Vector reinterpret cast operation"]
38446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
38447#[inline]
38448#[cfg(target_endian = "big")]
38449#[target_feature(enable = "neon")]
38450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38452#[cfg_attr(
38453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38454 assert_instr(nop)
38455)]
38456#[cfg_attr(
38457 not(target_arch = "arm"),
38458 stable(feature = "neon_intrinsics", since = "1.59.0")
38459)]
38460#[cfg_attr(
38461 target_arch = "arm",
38462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38463)]
38464pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
38465 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38466 unsafe {
38467 let ret_val: int8x16_t = transmute(a);
38468 simd_shuffle!(
38469 ret_val,
38470 ret_val,
38471 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
38472 )
38473 }
38474}
38475#[doc = "Vector reinterpret cast operation"]
38476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
38477#[inline]
38478#[cfg(target_endian = "little")]
38479#[target_feature(enable = "neon")]
38480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38482#[cfg_attr(
38483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38484 assert_instr(nop)
38485)]
38486#[cfg_attr(
38487 not(target_arch = "arm"),
38488 stable(feature = "neon_intrinsics", since = "1.59.0")
38489)]
38490#[cfg_attr(
38491 target_arch = "arm",
38492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38493)]
38494pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
38495 unsafe { transmute(a) }
38496}
38497#[doc = "Vector reinterpret cast operation"]
38498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
38499#[inline]
38500#[cfg(target_endian = "big")]
38501#[target_feature(enable = "neon")]
38502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38504#[cfg_attr(
38505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38506 assert_instr(nop)
38507)]
38508#[cfg_attr(
38509 not(target_arch = "arm"),
38510 stable(feature = "neon_intrinsics", since = "1.59.0")
38511)]
38512#[cfg_attr(
38513 target_arch = "arm",
38514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38515)]
38516pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
38517 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38518 unsafe {
38519 let ret_val: int16x8_t = transmute(a);
38520 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
38521 }
38522}
38523#[doc = "Vector reinterpret cast operation"]
38524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
38525#[inline]
38526#[cfg(target_endian = "little")]
38527#[target_feature(enable = "neon")]
38528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38530#[cfg_attr(
38531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38532 assert_instr(nop)
38533)]
38534#[cfg_attr(
38535 not(target_arch = "arm"),
38536 stable(feature = "neon_intrinsics", since = "1.59.0")
38537)]
38538#[cfg_attr(
38539 target_arch = "arm",
38540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38541)]
38542pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
38543 unsafe { transmute(a) }
38544}
38545#[doc = "Vector reinterpret cast operation"]
38546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
38547#[inline]
38548#[cfg(target_endian = "big")]
38549#[target_feature(enable = "neon")]
38550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38552#[cfg_attr(
38553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38554 assert_instr(nop)
38555)]
38556#[cfg_attr(
38557 not(target_arch = "arm"),
38558 stable(feature = "neon_intrinsics", since = "1.59.0")
38559)]
38560#[cfg_attr(
38561 target_arch = "arm",
38562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38563)]
38564pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
38565 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38566 unsafe {
38567 let ret_val: int32x4_t = transmute(a);
38568 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
38569 }
38570}
38571#[doc = "Vector reinterpret cast operation"]
38572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
38573#[inline]
38574#[cfg(target_endian = "little")]
38575#[target_feature(enable = "neon")]
38576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38578#[cfg_attr(
38579 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38580 assert_instr(nop)
38581)]
38582#[cfg_attr(
38583 not(target_arch = "arm"),
38584 stable(feature = "neon_intrinsics", since = "1.59.0")
38585)]
38586#[cfg_attr(
38587 target_arch = "arm",
38588 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38589)]
38590pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
38591 unsafe { transmute(a) }
38592}
38593#[doc = "Vector reinterpret cast operation"]
38594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
38595#[inline]
38596#[cfg(target_endian = "big")]
38597#[target_feature(enable = "neon")]
38598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38600#[cfg_attr(
38601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38602 assert_instr(nop)
38603)]
38604#[cfg_attr(
38605 not(target_arch = "arm"),
38606 stable(feature = "neon_intrinsics", since = "1.59.0")
38607)]
38608#[cfg_attr(
38609 target_arch = "arm",
38610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38611)]
38612pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
38613 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38614 unsafe {
38615 let ret_val: int64x2_t = transmute(a);
38616 simd_shuffle!(ret_val, ret_val, [1, 0])
38617 }
38618}
38619#[doc = "Vector reinterpret cast operation"]
38620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
38621#[inline]
38622#[cfg(target_endian = "little")]
38623#[target_feature(enable = "neon")]
38624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38625#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38626#[cfg_attr(
38627 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38628 assert_instr(nop)
38629)]
38630#[cfg_attr(
38631 not(target_arch = "arm"),
38632 stable(feature = "neon_intrinsics", since = "1.59.0")
38633)]
38634#[cfg_attr(
38635 target_arch = "arm",
38636 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38637)]
38638pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
38639 unsafe { transmute(a) }
38640}
38641#[doc = "Vector reinterpret cast operation"]
38642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
38643#[inline]
38644#[cfg(target_endian = "big")]
38645#[target_feature(enable = "neon")]
38646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38648#[cfg_attr(
38649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38650 assert_instr(nop)
38651)]
38652#[cfg_attr(
38653 not(target_arch = "arm"),
38654 stable(feature = "neon_intrinsics", since = "1.59.0")
38655)]
38656#[cfg_attr(
38657 target_arch = "arm",
38658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38659)]
38660pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
38661 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38662 unsafe {
38663 let ret_val: uint8x16_t = transmute(a);
38664 simd_shuffle!(
38665 ret_val,
38666 ret_val,
38667 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
38668 )
38669 }
38670}
38671#[doc = "Vector reinterpret cast operation"]
38672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
38673#[inline]
38674#[cfg(target_endian = "little")]
38675#[target_feature(enable = "neon")]
38676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38677#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38678#[cfg_attr(
38679 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38680 assert_instr(nop)
38681)]
38682#[cfg_attr(
38683 not(target_arch = "arm"),
38684 stable(feature = "neon_intrinsics", since = "1.59.0")
38685)]
38686#[cfg_attr(
38687 target_arch = "arm",
38688 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38689)]
38690pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
38691 unsafe { transmute(a) }
38692}
38693#[doc = "Vector reinterpret cast operation"]
38694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
38695#[inline]
38696#[cfg(target_endian = "big")]
38697#[target_feature(enable = "neon")]
38698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38700#[cfg_attr(
38701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38702 assert_instr(nop)
38703)]
38704#[cfg_attr(
38705 not(target_arch = "arm"),
38706 stable(feature = "neon_intrinsics", since = "1.59.0")
38707)]
38708#[cfg_attr(
38709 target_arch = "arm",
38710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38711)]
38712pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
38713 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38714 unsafe {
38715 let ret_val: uint16x8_t = transmute(a);
38716 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
38717 }
38718}
38719#[doc = "Vector reinterpret cast operation"]
38720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
38721#[inline]
38722#[cfg(target_endian = "little")]
38723#[target_feature(enable = "neon")]
38724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38726#[cfg_attr(
38727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38728 assert_instr(nop)
38729)]
38730#[cfg_attr(
38731 not(target_arch = "arm"),
38732 stable(feature = "neon_intrinsics", since = "1.59.0")
38733)]
38734#[cfg_attr(
38735 target_arch = "arm",
38736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38737)]
38738pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
38739 unsafe { transmute(a) }
38740}
38741#[doc = "Vector reinterpret cast operation"]
38742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
38743#[inline]
38744#[cfg(target_endian = "big")]
38745#[target_feature(enable = "neon")]
38746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38748#[cfg_attr(
38749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38750 assert_instr(nop)
38751)]
38752#[cfg_attr(
38753 not(target_arch = "arm"),
38754 stable(feature = "neon_intrinsics", since = "1.59.0")
38755)]
38756#[cfg_attr(
38757 target_arch = "arm",
38758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38759)]
38760pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
38761 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38762 unsafe {
38763 let ret_val: uint32x4_t = transmute(a);
38764 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
38765 }
38766}
38767#[doc = "Vector reinterpret cast operation"]
38768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
38769#[inline]
38770#[cfg(target_endian = "little")]
38771#[target_feature(enable = "neon")]
38772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38773#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38774#[cfg_attr(
38775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38776 assert_instr(nop)
38777)]
38778#[cfg_attr(
38779 not(target_arch = "arm"),
38780 stable(feature = "neon_intrinsics", since = "1.59.0")
38781)]
38782#[cfg_attr(
38783 target_arch = "arm",
38784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38785)]
38786pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
38787 unsafe { transmute(a) }
38788}
38789#[doc = "Vector reinterpret cast operation"]
38790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
38791#[inline]
38792#[cfg(target_endian = "big")]
38793#[target_feature(enable = "neon")]
38794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38796#[cfg_attr(
38797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38798 assert_instr(nop)
38799)]
38800#[cfg_attr(
38801 not(target_arch = "arm"),
38802 stable(feature = "neon_intrinsics", since = "1.59.0")
38803)]
38804#[cfg_attr(
38805 target_arch = "arm",
38806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38807)]
38808pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
38809 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38810 unsafe {
38811 let ret_val: uint64x2_t = transmute(a);
38812 simd_shuffle!(ret_val, ret_val, [1, 0])
38813 }
38814}
38815#[doc = "Vector reinterpret cast operation"]
38816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
38817#[inline]
38818#[cfg(target_endian = "little")]
38819#[target_feature(enable = "neon")]
38820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38822#[cfg_attr(
38823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38824 assert_instr(nop)
38825)]
38826#[cfg_attr(
38827 not(target_arch = "arm"),
38828 stable(feature = "neon_intrinsics", since = "1.59.0")
38829)]
38830#[cfg_attr(
38831 target_arch = "arm",
38832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38833)]
38834pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
38835 unsafe { transmute(a) }
38836}
38837#[doc = "Vector reinterpret cast operation"]
38838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
38839#[inline]
38840#[cfg(target_endian = "big")]
38841#[target_feature(enable = "neon")]
38842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38844#[cfg_attr(
38845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38846 assert_instr(nop)
38847)]
38848#[cfg_attr(
38849 not(target_arch = "arm"),
38850 stable(feature = "neon_intrinsics", since = "1.59.0")
38851)]
38852#[cfg_attr(
38853 target_arch = "arm",
38854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38855)]
38856pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
38857 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38858 unsafe {
38859 let ret_val: poly8x16_t = transmute(a);
38860 simd_shuffle!(
38861 ret_val,
38862 ret_val,
38863 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
38864 )
38865 }
38866}
38867#[doc = "Vector reinterpret cast operation"]
38868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
38869#[inline]
38870#[cfg(target_endian = "little")]
38871#[target_feature(enable = "neon")]
38872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38874#[cfg_attr(
38875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38876 assert_instr(nop)
38877)]
38878#[cfg_attr(
38879 not(target_arch = "arm"),
38880 stable(feature = "neon_intrinsics", since = "1.59.0")
38881)]
38882#[cfg_attr(
38883 target_arch = "arm",
38884 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38885)]
38886pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
38887 unsafe { transmute(a) }
38888}
38889#[doc = "Vector reinterpret cast operation"]
38890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
38891#[inline]
38892#[cfg(target_endian = "big")]
38893#[target_feature(enable = "neon")]
38894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38896#[cfg_attr(
38897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38898 assert_instr(nop)
38899)]
38900#[cfg_attr(
38901 not(target_arch = "arm"),
38902 stable(feature = "neon_intrinsics", since = "1.59.0")
38903)]
38904#[cfg_attr(
38905 target_arch = "arm",
38906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38907)]
38908pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
38909 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
38910 unsafe {
38911 let ret_val: poly16x8_t = transmute(a);
38912 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
38913 }
38914}
38915#[doc = "Vector reinterpret cast operation"]
38916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
38917#[inline]
38918#[cfg(target_endian = "little")]
38919#[target_feature(enable = "neon")]
38920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38921#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38922#[cfg_attr(
38923 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38924 assert_instr(nop)
38925)]
38926#[cfg_attr(
38927 not(target_arch = "arm"),
38928 stable(feature = "neon_intrinsics", since = "1.59.0")
38929)]
38930#[cfg_attr(
38931 target_arch = "arm",
38932 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38933)]
38934pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
38935 unsafe { transmute(a) }
38936}
38937#[doc = "Vector reinterpret cast operation"]
38938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
38939#[inline]
38940#[cfg(target_endian = "big")]
38941#[target_feature(enable = "neon")]
38942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38944#[cfg_attr(
38945 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38946 assert_instr(nop)
38947)]
38948#[cfg_attr(
38949 not(target_arch = "arm"),
38950 stable(feature = "neon_intrinsics", since = "1.59.0")
38951)]
38952#[cfg_attr(
38953 target_arch = "arm",
38954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38955)]
38956pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
38957 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
38958 unsafe {
38959 let ret_val: float32x2_t = transmute(a);
38960 simd_shuffle!(ret_val, ret_val, [1, 0])
38961 }
38962}
38963#[doc = "Vector reinterpret cast operation"]
38964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
38965#[inline]
38966#[cfg(target_endian = "little")]
38967#[target_feature(enable = "neon")]
38968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38969#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38970#[cfg_attr(
38971 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38972 assert_instr(nop)
38973)]
38974#[cfg_attr(
38975 not(target_arch = "arm"),
38976 stable(feature = "neon_intrinsics", since = "1.59.0")
38977)]
38978#[cfg_attr(
38979 target_arch = "arm",
38980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38981)]
38982pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
38983 unsafe { transmute(a) }
38984}
38985#[doc = "Vector reinterpret cast operation"]
38986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
38987#[inline]
38988#[cfg(target_endian = "big")]
38989#[target_feature(enable = "neon")]
38990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38991#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
38992#[cfg_attr(
38993 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38994 assert_instr(nop)
38995)]
38996#[cfg_attr(
38997 not(target_arch = "arm"),
38998 stable(feature = "neon_intrinsics", since = "1.59.0")
38999)]
39000#[cfg_attr(
39001 target_arch = "arm",
39002 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39003)]
39004pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
39005 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39006 unsafe {
39007 let ret_val: int16x4_t = transmute(a);
39008 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
39009 }
39010}
39011#[doc = "Vector reinterpret cast operation"]
39012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
39013#[inline]
39014#[cfg(target_endian = "little")]
39015#[target_feature(enable = "neon")]
39016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39018#[cfg_attr(
39019 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39020 assert_instr(nop)
39021)]
39022#[cfg_attr(
39023 not(target_arch = "arm"),
39024 stable(feature = "neon_intrinsics", since = "1.59.0")
39025)]
39026#[cfg_attr(
39027 target_arch = "arm",
39028 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39029)]
39030pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
39031 unsafe { transmute(a) }
39032}
39033#[doc = "Vector reinterpret cast operation"]
39034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
39035#[inline]
39036#[cfg(target_endian = "big")]
39037#[target_feature(enable = "neon")]
39038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39040#[cfg_attr(
39041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39042 assert_instr(nop)
39043)]
39044#[cfg_attr(
39045 not(target_arch = "arm"),
39046 stable(feature = "neon_intrinsics", since = "1.59.0")
39047)]
39048#[cfg_attr(
39049 target_arch = "arm",
39050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39051)]
39052pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
39053 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39054 unsafe {
39055 let ret_val: int32x2_t = transmute(a);
39056 simd_shuffle!(ret_val, ret_val, [1, 0])
39057 }
39058}
39059#[doc = "Vector reinterpret cast operation"]
39060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
39061#[inline]
39062#[cfg(target_endian = "little")]
39063#[target_feature(enable = "neon")]
39064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39065#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39066#[cfg_attr(
39067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39068 assert_instr(nop)
39069)]
39070#[cfg_attr(
39071 not(target_arch = "arm"),
39072 stable(feature = "neon_intrinsics", since = "1.59.0")
39073)]
39074#[cfg_attr(
39075 target_arch = "arm",
39076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39077)]
39078pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
39079 unsafe { transmute(a) }
39080}
39081#[doc = "Vector reinterpret cast operation"]
39082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
39083#[inline]
39084#[cfg(target_endian = "big")]
39085#[target_feature(enable = "neon")]
39086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39088#[cfg_attr(
39089 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39090 assert_instr(nop)
39091)]
39092#[cfg_attr(
39093 not(target_arch = "arm"),
39094 stable(feature = "neon_intrinsics", since = "1.59.0")
39095)]
39096#[cfg_attr(
39097 target_arch = "arm",
39098 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39099)]
39100pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
39101 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39102 unsafe { transmute(a) }
39103}
39104#[doc = "Vector reinterpret cast operation"]
39105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
39106#[inline]
39107#[cfg(target_endian = "little")]
39108#[target_feature(enable = "neon")]
39109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39111#[cfg_attr(
39112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39113 assert_instr(nop)
39114)]
39115#[cfg_attr(
39116 not(target_arch = "arm"),
39117 stable(feature = "neon_intrinsics", since = "1.59.0")
39118)]
39119#[cfg_attr(
39120 target_arch = "arm",
39121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39122)]
39123pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
39124 unsafe { transmute(a) }
39125}
39126#[doc = "Vector reinterpret cast operation"]
39127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
39128#[inline]
39129#[cfg(target_endian = "big")]
39130#[target_feature(enable = "neon")]
39131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39133#[cfg_attr(
39134 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39135 assert_instr(nop)
39136)]
39137#[cfg_attr(
39138 not(target_arch = "arm"),
39139 stable(feature = "neon_intrinsics", since = "1.59.0")
39140)]
39141#[cfg_attr(
39142 target_arch = "arm",
39143 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39144)]
39145pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
39146 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39147 unsafe {
39148 let ret_val: uint8x8_t = transmute(a);
39149 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
39150 }
39151}
39152#[doc = "Vector reinterpret cast operation"]
39153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
39154#[inline]
39155#[cfg(target_endian = "little")]
39156#[target_feature(enable = "neon")]
39157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39159#[cfg_attr(
39160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39161 assert_instr(nop)
39162)]
39163#[cfg_attr(
39164 not(target_arch = "arm"),
39165 stable(feature = "neon_intrinsics", since = "1.59.0")
39166)]
39167#[cfg_attr(
39168 target_arch = "arm",
39169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39170)]
39171pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
39172 unsafe { transmute(a) }
39173}
39174#[doc = "Vector reinterpret cast operation"]
39175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
39176#[inline]
39177#[cfg(target_endian = "big")]
39178#[target_feature(enable = "neon")]
39179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39180#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39181#[cfg_attr(
39182 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39183 assert_instr(nop)
39184)]
39185#[cfg_attr(
39186 not(target_arch = "arm"),
39187 stable(feature = "neon_intrinsics", since = "1.59.0")
39188)]
39189#[cfg_attr(
39190 target_arch = "arm",
39191 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39192)]
39193pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
39194 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39195 unsafe {
39196 let ret_val: uint16x4_t = transmute(a);
39197 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
39198 }
39199}
39200#[doc = "Vector reinterpret cast operation"]
39201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
39202#[inline]
39203#[cfg(target_endian = "little")]
39204#[target_feature(enable = "neon")]
39205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39207#[cfg_attr(
39208 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39209 assert_instr(nop)
39210)]
39211#[cfg_attr(
39212 not(target_arch = "arm"),
39213 stable(feature = "neon_intrinsics", since = "1.59.0")
39214)]
39215#[cfg_attr(
39216 target_arch = "arm",
39217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39218)]
39219pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
39220 unsafe { transmute(a) }
39221}
39222#[doc = "Vector reinterpret cast operation"]
39223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
39224#[inline]
39225#[cfg(target_endian = "big")]
39226#[target_feature(enable = "neon")]
39227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39229#[cfg_attr(
39230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39231 assert_instr(nop)
39232)]
39233#[cfg_attr(
39234 not(target_arch = "arm"),
39235 stable(feature = "neon_intrinsics", since = "1.59.0")
39236)]
39237#[cfg_attr(
39238 target_arch = "arm",
39239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39240)]
39241pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
39242 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39243 unsafe {
39244 let ret_val: uint32x2_t = transmute(a);
39245 simd_shuffle!(ret_val, ret_val, [1, 0])
39246 }
39247}
39248#[doc = "Vector reinterpret cast operation"]
39249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
39250#[inline]
39251#[cfg(target_endian = "little")]
39252#[target_feature(enable = "neon")]
39253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39255#[cfg_attr(
39256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39257 assert_instr(nop)
39258)]
39259#[cfg_attr(
39260 not(target_arch = "arm"),
39261 stable(feature = "neon_intrinsics", since = "1.59.0")
39262)]
39263#[cfg_attr(
39264 target_arch = "arm",
39265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39266)]
39267pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
39268 unsafe { transmute(a) }
39269}
39270#[doc = "Vector reinterpret cast operation"]
39271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
39272#[inline]
39273#[cfg(target_endian = "big")]
39274#[target_feature(enable = "neon")]
39275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39277#[cfg_attr(
39278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39279 assert_instr(nop)
39280)]
39281#[cfg_attr(
39282 not(target_arch = "arm"),
39283 stable(feature = "neon_intrinsics", since = "1.59.0")
39284)]
39285#[cfg_attr(
39286 target_arch = "arm",
39287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39288)]
39289pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
39290 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39291 unsafe { transmute(a) }
39292}
39293#[doc = "Vector reinterpret cast operation"]
39294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
39295#[inline]
39296#[cfg(target_endian = "little")]
39297#[target_feature(enable = "neon")]
39298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39300#[cfg_attr(
39301 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39302 assert_instr(nop)
39303)]
39304#[cfg_attr(
39305 not(target_arch = "arm"),
39306 stable(feature = "neon_intrinsics", since = "1.59.0")
39307)]
39308#[cfg_attr(
39309 target_arch = "arm",
39310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39311)]
39312pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
39313 unsafe { transmute(a) }
39314}
39315#[doc = "Vector reinterpret cast operation"]
39316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
39317#[inline]
39318#[cfg(target_endian = "big")]
39319#[target_feature(enable = "neon")]
39320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39322#[cfg_attr(
39323 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39324 assert_instr(nop)
39325)]
39326#[cfg_attr(
39327 not(target_arch = "arm"),
39328 stable(feature = "neon_intrinsics", since = "1.59.0")
39329)]
39330#[cfg_attr(
39331 target_arch = "arm",
39332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39333)]
39334pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
39335 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39336 unsafe {
39337 let ret_val: poly8x8_t = transmute(a);
39338 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
39339 }
39340}
39341#[doc = "Vector reinterpret cast operation"]
39342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
39343#[inline]
39344#[cfg(target_endian = "little")]
39345#[target_feature(enable = "neon")]
39346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39348#[cfg_attr(
39349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39350 assert_instr(nop)
39351)]
39352#[cfg_attr(
39353 not(target_arch = "arm"),
39354 stable(feature = "neon_intrinsics", since = "1.59.0")
39355)]
39356#[cfg_attr(
39357 target_arch = "arm",
39358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39359)]
39360pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
39361 unsafe { transmute(a) }
39362}
39363#[doc = "Vector reinterpret cast operation"]
39364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
39365#[inline]
39366#[cfg(target_endian = "big")]
39367#[target_feature(enable = "neon")]
39368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39370#[cfg_attr(
39371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39372 assert_instr(nop)
39373)]
39374#[cfg_attr(
39375 not(target_arch = "arm"),
39376 stable(feature = "neon_intrinsics", since = "1.59.0")
39377)]
39378#[cfg_attr(
39379 target_arch = "arm",
39380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39381)]
39382pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
39383 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
39384 unsafe {
39385 let ret_val: poly16x4_t = transmute(a);
39386 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
39387 }
39388}
39389#[doc = "Vector reinterpret cast operation"]
39390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
39391#[inline]
39392#[cfg(target_endian = "little")]
39393#[target_feature(enable = "neon")]
39394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39396#[cfg_attr(
39397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39398 assert_instr(nop)
39399)]
39400#[cfg_attr(
39401 not(target_arch = "arm"),
39402 stable(feature = "neon_intrinsics", since = "1.59.0")
39403)]
39404#[cfg_attr(
39405 target_arch = "arm",
39406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39407)]
39408pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
39409 unsafe { transmute(a) }
39410}
39411#[doc = "Vector reinterpret cast operation"]
39412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
39413#[inline]
39414#[cfg(target_endian = "big")]
39415#[target_feature(enable = "neon")]
39416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39418#[cfg_attr(
39419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39420 assert_instr(nop)
39421)]
39422#[cfg_attr(
39423 not(target_arch = "arm"),
39424 stable(feature = "neon_intrinsics", since = "1.59.0")
39425)]
39426#[cfg_attr(
39427 target_arch = "arm",
39428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39429)]
39430pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
39431 let a: int8x16_t =
39432 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39433 unsafe {
39434 let ret_val: float32x4_t = transmute(a);
39435 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
39436 }
39437}
39438#[doc = "Vector reinterpret cast operation"]
39439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
39440#[inline]
39441#[cfg(target_endian = "little")]
39442#[target_feature(enable = "neon")]
39443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39445#[cfg_attr(
39446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39447 assert_instr(nop)
39448)]
39449#[cfg_attr(
39450 not(target_arch = "arm"),
39451 stable(feature = "neon_intrinsics", since = "1.59.0")
39452)]
39453#[cfg_attr(
39454 target_arch = "arm",
39455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39456)]
39457pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
39458 unsafe { transmute(a) }
39459}
39460#[doc = "Vector reinterpret cast operation"]
39461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
39462#[inline]
39463#[cfg(target_endian = "big")]
39464#[target_feature(enable = "neon")]
39465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39467#[cfg_attr(
39468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39469 assert_instr(nop)
39470)]
39471#[cfg_attr(
39472 not(target_arch = "arm"),
39473 stable(feature = "neon_intrinsics", since = "1.59.0")
39474)]
39475#[cfg_attr(
39476 target_arch = "arm",
39477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39478)]
39479pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
39480 let a: int8x16_t =
39481 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39482 unsafe {
39483 let ret_val: int16x8_t = transmute(a);
39484 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
39485 }
39486}
39487#[doc = "Vector reinterpret cast operation"]
39488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
39489#[inline]
39490#[cfg(target_endian = "little")]
39491#[target_feature(enable = "neon")]
39492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39493#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39494#[cfg_attr(
39495 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39496 assert_instr(nop)
39497)]
39498#[cfg_attr(
39499 not(target_arch = "arm"),
39500 stable(feature = "neon_intrinsics", since = "1.59.0")
39501)]
39502#[cfg_attr(
39503 target_arch = "arm",
39504 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39505)]
39506pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
39507 unsafe { transmute(a) }
39508}
39509#[doc = "Vector reinterpret cast operation"]
39510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
39511#[inline]
39512#[cfg(target_endian = "big")]
39513#[target_feature(enable = "neon")]
39514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39516#[cfg_attr(
39517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39518 assert_instr(nop)
39519)]
39520#[cfg_attr(
39521 not(target_arch = "arm"),
39522 stable(feature = "neon_intrinsics", since = "1.59.0")
39523)]
39524#[cfg_attr(
39525 target_arch = "arm",
39526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39527)]
39528pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
39529 let a: int8x16_t =
39530 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39531 unsafe {
39532 let ret_val: int32x4_t = transmute(a);
39533 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
39534 }
39535}
39536#[doc = "Vector reinterpret cast operation"]
39537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
39538#[inline]
39539#[cfg(target_endian = "little")]
39540#[target_feature(enable = "neon")]
39541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39543#[cfg_attr(
39544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39545 assert_instr(nop)
39546)]
39547#[cfg_attr(
39548 not(target_arch = "arm"),
39549 stable(feature = "neon_intrinsics", since = "1.59.0")
39550)]
39551#[cfg_attr(
39552 target_arch = "arm",
39553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39554)]
39555pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
39556 unsafe { transmute(a) }
39557}
39558#[doc = "Vector reinterpret cast operation"]
39559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
39560#[inline]
39561#[cfg(target_endian = "big")]
39562#[target_feature(enable = "neon")]
39563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39565#[cfg_attr(
39566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39567 assert_instr(nop)
39568)]
39569#[cfg_attr(
39570 not(target_arch = "arm"),
39571 stable(feature = "neon_intrinsics", since = "1.59.0")
39572)]
39573#[cfg_attr(
39574 target_arch = "arm",
39575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39576)]
39577pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
39578 let a: int8x16_t =
39579 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39580 unsafe {
39581 let ret_val: int64x2_t = transmute(a);
39582 simd_shuffle!(ret_val, ret_val, [1, 0])
39583 }
39584}
39585#[doc = "Vector reinterpret cast operation"]
39586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
39587#[inline]
39588#[cfg(target_endian = "little")]
39589#[target_feature(enable = "neon")]
39590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39592#[cfg_attr(
39593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39594 assert_instr(nop)
39595)]
39596#[cfg_attr(
39597 not(target_arch = "arm"),
39598 stable(feature = "neon_intrinsics", since = "1.59.0")
39599)]
39600#[cfg_attr(
39601 target_arch = "arm",
39602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39603)]
39604pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
39605 unsafe { transmute(a) }
39606}
39607#[doc = "Vector reinterpret cast operation"]
39608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
39609#[inline]
39610#[cfg(target_endian = "big")]
39611#[target_feature(enable = "neon")]
39612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39614#[cfg_attr(
39615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39616 assert_instr(nop)
39617)]
39618#[cfg_attr(
39619 not(target_arch = "arm"),
39620 stable(feature = "neon_intrinsics", since = "1.59.0")
39621)]
39622#[cfg_attr(
39623 target_arch = "arm",
39624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39625)]
39626pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
39627 let a: int8x16_t =
39628 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39629 unsafe {
39630 let ret_val: uint8x16_t = transmute(a);
39631 simd_shuffle!(
39632 ret_val,
39633 ret_val,
39634 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
39635 )
39636 }
39637}
39638#[doc = "Vector reinterpret cast operation"]
39639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
39640#[inline]
39641#[cfg(target_endian = "little")]
39642#[target_feature(enable = "neon")]
39643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39645#[cfg_attr(
39646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39647 assert_instr(nop)
39648)]
39649#[cfg_attr(
39650 not(target_arch = "arm"),
39651 stable(feature = "neon_intrinsics", since = "1.59.0")
39652)]
39653#[cfg_attr(
39654 target_arch = "arm",
39655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39656)]
39657pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
39658 unsafe { transmute(a) }
39659}
39660#[doc = "Vector reinterpret cast operation"]
39661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
39662#[inline]
39663#[cfg(target_endian = "big")]
39664#[target_feature(enable = "neon")]
39665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39667#[cfg_attr(
39668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39669 assert_instr(nop)
39670)]
39671#[cfg_attr(
39672 not(target_arch = "arm"),
39673 stable(feature = "neon_intrinsics", since = "1.59.0")
39674)]
39675#[cfg_attr(
39676 target_arch = "arm",
39677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39678)]
39679pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
39680 let a: int8x16_t =
39681 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39682 unsafe {
39683 let ret_val: uint16x8_t = transmute(a);
39684 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
39685 }
39686}
39687#[doc = "Vector reinterpret cast operation"]
39688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
39689#[inline]
39690#[cfg(target_endian = "little")]
39691#[target_feature(enable = "neon")]
39692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39694#[cfg_attr(
39695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39696 assert_instr(nop)
39697)]
39698#[cfg_attr(
39699 not(target_arch = "arm"),
39700 stable(feature = "neon_intrinsics", since = "1.59.0")
39701)]
39702#[cfg_attr(
39703 target_arch = "arm",
39704 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39705)]
39706pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
39707 unsafe { transmute(a) }
39708}
39709#[doc = "Vector reinterpret cast operation"]
39710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
39711#[inline]
39712#[cfg(target_endian = "big")]
39713#[target_feature(enable = "neon")]
39714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39716#[cfg_attr(
39717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39718 assert_instr(nop)
39719)]
39720#[cfg_attr(
39721 not(target_arch = "arm"),
39722 stable(feature = "neon_intrinsics", since = "1.59.0")
39723)]
39724#[cfg_attr(
39725 target_arch = "arm",
39726 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39727)]
39728pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
39729 let a: int8x16_t =
39730 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39731 unsafe {
39732 let ret_val: uint32x4_t = transmute(a);
39733 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
39734 }
39735}
39736#[doc = "Vector reinterpret cast operation"]
39737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
39738#[inline]
39739#[cfg(target_endian = "little")]
39740#[target_feature(enable = "neon")]
39741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39743#[cfg_attr(
39744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39745 assert_instr(nop)
39746)]
39747#[cfg_attr(
39748 not(target_arch = "arm"),
39749 stable(feature = "neon_intrinsics", since = "1.59.0")
39750)]
39751#[cfg_attr(
39752 target_arch = "arm",
39753 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39754)]
39755pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
39756 unsafe { transmute(a) }
39757}
39758#[doc = "Vector reinterpret cast operation"]
39759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
39760#[inline]
39761#[cfg(target_endian = "big")]
39762#[target_feature(enable = "neon")]
39763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39765#[cfg_attr(
39766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39767 assert_instr(nop)
39768)]
39769#[cfg_attr(
39770 not(target_arch = "arm"),
39771 stable(feature = "neon_intrinsics", since = "1.59.0")
39772)]
39773#[cfg_attr(
39774 target_arch = "arm",
39775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39776)]
39777pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
39778 let a: int8x16_t =
39779 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39780 unsafe {
39781 let ret_val: uint64x2_t = transmute(a);
39782 simd_shuffle!(ret_val, ret_val, [1, 0])
39783 }
39784}
39785#[doc = "Vector reinterpret cast operation"]
39786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
39787#[inline]
39788#[cfg(target_endian = "little")]
39789#[target_feature(enable = "neon")]
39790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39792#[cfg_attr(
39793 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39794 assert_instr(nop)
39795)]
39796#[cfg_attr(
39797 not(target_arch = "arm"),
39798 stable(feature = "neon_intrinsics", since = "1.59.0")
39799)]
39800#[cfg_attr(
39801 target_arch = "arm",
39802 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39803)]
39804pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
39805 unsafe { transmute(a) }
39806}
39807#[doc = "Vector reinterpret cast operation"]
39808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
39809#[inline]
39810#[cfg(target_endian = "big")]
39811#[target_feature(enable = "neon")]
39812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39814#[cfg_attr(
39815 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39816 assert_instr(nop)
39817)]
39818#[cfg_attr(
39819 not(target_arch = "arm"),
39820 stable(feature = "neon_intrinsics", since = "1.59.0")
39821)]
39822#[cfg_attr(
39823 target_arch = "arm",
39824 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39825)]
39826pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
39827 let a: int8x16_t =
39828 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39829 unsafe {
39830 let ret_val: poly8x16_t = transmute(a);
39831 simd_shuffle!(
39832 ret_val,
39833 ret_val,
39834 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
39835 )
39836 }
39837}
39838#[doc = "Vector reinterpret cast operation"]
39839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
39840#[inline]
39841#[cfg(target_endian = "little")]
39842#[target_feature(enable = "neon")]
39843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39845#[cfg_attr(
39846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39847 assert_instr(nop)
39848)]
39849#[cfg_attr(
39850 not(target_arch = "arm"),
39851 stable(feature = "neon_intrinsics", since = "1.59.0")
39852)]
39853#[cfg_attr(
39854 target_arch = "arm",
39855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39856)]
39857pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
39858 unsafe { transmute(a) }
39859}
39860#[doc = "Vector reinterpret cast operation"]
39861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
39862#[inline]
39863#[cfg(target_endian = "big")]
39864#[target_feature(enable = "neon")]
39865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39867#[cfg_attr(
39868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39869 assert_instr(nop)
39870)]
39871#[cfg_attr(
39872 not(target_arch = "arm"),
39873 stable(feature = "neon_intrinsics", since = "1.59.0")
39874)]
39875#[cfg_attr(
39876 target_arch = "arm",
39877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39878)]
39879pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
39880 let a: int8x16_t =
39881 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
39882 unsafe {
39883 let ret_val: poly16x8_t = transmute(a);
39884 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
39885 }
39886}
39887#[doc = "Vector reinterpret cast operation"]
39888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
39889#[inline]
39890#[cfg(target_endian = "little")]
39891#[target_feature(enable = "neon")]
39892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39893#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39894#[cfg_attr(
39895 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39896 assert_instr(nop)
39897)]
39898#[cfg_attr(
39899 not(target_arch = "arm"),
39900 stable(feature = "neon_intrinsics", since = "1.59.0")
39901)]
39902#[cfg_attr(
39903 target_arch = "arm",
39904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39905)]
39906pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
39907 unsafe { transmute(a) }
39908}
39909#[doc = "Vector reinterpret cast operation"]
39910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
39911#[inline]
39912#[cfg(target_endian = "big")]
39913#[target_feature(enable = "neon")]
39914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39916#[cfg_attr(
39917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39918 assert_instr(nop)
39919)]
39920#[cfg_attr(
39921 not(target_arch = "arm"),
39922 stable(feature = "neon_intrinsics", since = "1.59.0")
39923)]
39924#[cfg_attr(
39925 target_arch = "arm",
39926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39927)]
39928pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
39929 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
39930 unsafe {
39931 let ret_val: float32x2_t = transmute(a);
39932 simd_shuffle!(ret_val, ret_val, [1, 0])
39933 }
39934}
39935#[doc = "Vector reinterpret cast operation"]
39936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
39937#[inline]
39938#[cfg(target_endian = "little")]
39939#[target_feature(enable = "neon")]
39940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39942#[cfg_attr(
39943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39944 assert_instr(nop)
39945)]
39946#[cfg_attr(
39947 not(target_arch = "arm"),
39948 stable(feature = "neon_intrinsics", since = "1.59.0")
39949)]
39950#[cfg_attr(
39951 target_arch = "arm",
39952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39953)]
39954pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
39955 unsafe { transmute(a) }
39956}
39957#[doc = "Vector reinterpret cast operation"]
39958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
39959#[inline]
39960#[cfg(target_endian = "big")]
39961#[target_feature(enable = "neon")]
39962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39963#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39964#[cfg_attr(
39965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39966 assert_instr(nop)
39967)]
39968#[cfg_attr(
39969 not(target_arch = "arm"),
39970 stable(feature = "neon_intrinsics", since = "1.59.0")
39971)]
39972#[cfg_attr(
39973 target_arch = "arm",
39974 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39975)]
39976pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
39977 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
39978 unsafe {
39979 let ret_val: int8x8_t = transmute(a);
39980 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
39981 }
39982}
39983#[doc = "Vector reinterpret cast operation"]
39984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
39985#[inline]
39986#[cfg(target_endian = "little")]
39987#[target_feature(enable = "neon")]
39988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
39990#[cfg_attr(
39991 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39992 assert_instr(nop)
39993)]
39994#[cfg_attr(
39995 not(target_arch = "arm"),
39996 stable(feature = "neon_intrinsics", since = "1.59.0")
39997)]
39998#[cfg_attr(
39999 target_arch = "arm",
40000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40001)]
40002pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
40003 unsafe { transmute(a) }
40004}
40005#[doc = "Vector reinterpret cast operation"]
40006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
40007#[inline]
40008#[cfg(target_endian = "big")]
40009#[target_feature(enable = "neon")]
40010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40012#[cfg_attr(
40013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40014 assert_instr(nop)
40015)]
40016#[cfg_attr(
40017 not(target_arch = "arm"),
40018 stable(feature = "neon_intrinsics", since = "1.59.0")
40019)]
40020#[cfg_attr(
40021 target_arch = "arm",
40022 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40023)]
40024pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
40025 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40026 unsafe {
40027 let ret_val: int32x2_t = transmute(a);
40028 simd_shuffle!(ret_val, ret_val, [1, 0])
40029 }
40030}
40031#[doc = "Vector reinterpret cast operation"]
40032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
40033#[inline]
40034#[cfg(target_endian = "little")]
40035#[target_feature(enable = "neon")]
40036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40037#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40038#[cfg_attr(
40039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40040 assert_instr(nop)
40041)]
40042#[cfg_attr(
40043 not(target_arch = "arm"),
40044 stable(feature = "neon_intrinsics", since = "1.59.0")
40045)]
40046#[cfg_attr(
40047 target_arch = "arm",
40048 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40049)]
40050pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
40051 unsafe { transmute(a) }
40052}
40053#[doc = "Vector reinterpret cast operation"]
40054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
40055#[inline]
40056#[cfg(target_endian = "big")]
40057#[target_feature(enable = "neon")]
40058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40060#[cfg_attr(
40061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40062 assert_instr(nop)
40063)]
40064#[cfg_attr(
40065 not(target_arch = "arm"),
40066 stable(feature = "neon_intrinsics", since = "1.59.0")
40067)]
40068#[cfg_attr(
40069 target_arch = "arm",
40070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40071)]
40072pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
40073 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40074 unsafe { transmute(a) }
40075}
40076#[doc = "Vector reinterpret cast operation"]
40077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
40078#[inline]
40079#[cfg(target_endian = "little")]
40080#[target_feature(enable = "neon")]
40081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40083#[cfg_attr(
40084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40085 assert_instr(nop)
40086)]
40087#[cfg_attr(
40088 not(target_arch = "arm"),
40089 stable(feature = "neon_intrinsics", since = "1.59.0")
40090)]
40091#[cfg_attr(
40092 target_arch = "arm",
40093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40094)]
40095pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
40096 unsafe { transmute(a) }
40097}
40098#[doc = "Vector reinterpret cast operation"]
40099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
40100#[inline]
40101#[cfg(target_endian = "big")]
40102#[target_feature(enable = "neon")]
40103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40105#[cfg_attr(
40106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40107 assert_instr(nop)
40108)]
40109#[cfg_attr(
40110 not(target_arch = "arm"),
40111 stable(feature = "neon_intrinsics", since = "1.59.0")
40112)]
40113#[cfg_attr(
40114 target_arch = "arm",
40115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40116)]
40117pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
40118 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40119 unsafe {
40120 let ret_val: uint8x8_t = transmute(a);
40121 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
40122 }
40123}
40124#[doc = "Vector reinterpret cast operation"]
40125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
40126#[inline]
40127#[cfg(target_endian = "little")]
40128#[target_feature(enable = "neon")]
40129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40130#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40131#[cfg_attr(
40132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40133 assert_instr(nop)
40134)]
40135#[cfg_attr(
40136 not(target_arch = "arm"),
40137 stable(feature = "neon_intrinsics", since = "1.59.0")
40138)]
40139#[cfg_attr(
40140 target_arch = "arm",
40141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40142)]
40143pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
40144 unsafe { transmute(a) }
40145}
40146#[doc = "Vector reinterpret cast operation"]
40147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
40148#[inline]
40149#[cfg(target_endian = "big")]
40150#[target_feature(enable = "neon")]
40151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40153#[cfg_attr(
40154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40155 assert_instr(nop)
40156)]
40157#[cfg_attr(
40158 not(target_arch = "arm"),
40159 stable(feature = "neon_intrinsics", since = "1.59.0")
40160)]
40161#[cfg_attr(
40162 target_arch = "arm",
40163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40164)]
40165pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
40166 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40167 unsafe {
40168 let ret_val: uint16x4_t = transmute(a);
40169 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
40170 }
40171}
40172#[doc = "Vector reinterpret cast operation"]
40173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
40174#[inline]
40175#[cfg(target_endian = "little")]
40176#[target_feature(enable = "neon")]
40177#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40178#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40179#[cfg_attr(
40180 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40181 assert_instr(nop)
40182)]
40183#[cfg_attr(
40184 not(target_arch = "arm"),
40185 stable(feature = "neon_intrinsics", since = "1.59.0")
40186)]
40187#[cfg_attr(
40188 target_arch = "arm",
40189 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40190)]
40191pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
40192 unsafe { transmute(a) }
40193}
40194#[doc = "Vector reinterpret cast operation"]
40195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
40196#[inline]
40197#[cfg(target_endian = "big")]
40198#[target_feature(enable = "neon")]
40199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40201#[cfg_attr(
40202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40203 assert_instr(nop)
40204)]
40205#[cfg_attr(
40206 not(target_arch = "arm"),
40207 stable(feature = "neon_intrinsics", since = "1.59.0")
40208)]
40209#[cfg_attr(
40210 target_arch = "arm",
40211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40212)]
40213pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
40214 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40215 unsafe {
40216 let ret_val: uint32x2_t = transmute(a);
40217 simd_shuffle!(ret_val, ret_val, [1, 0])
40218 }
40219}
40220#[doc = "Vector reinterpret cast operation"]
40221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
40222#[inline]
40223#[cfg(target_endian = "little")]
40224#[target_feature(enable = "neon")]
40225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40227#[cfg_attr(
40228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40229 assert_instr(nop)
40230)]
40231#[cfg_attr(
40232 not(target_arch = "arm"),
40233 stable(feature = "neon_intrinsics", since = "1.59.0")
40234)]
40235#[cfg_attr(
40236 target_arch = "arm",
40237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40238)]
40239pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
40240 unsafe { transmute(a) }
40241}
40242#[doc = "Vector reinterpret cast operation"]
40243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
40244#[inline]
40245#[cfg(target_endian = "big")]
40246#[target_feature(enable = "neon")]
40247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40249#[cfg_attr(
40250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40251 assert_instr(nop)
40252)]
40253#[cfg_attr(
40254 not(target_arch = "arm"),
40255 stable(feature = "neon_intrinsics", since = "1.59.0")
40256)]
40257#[cfg_attr(
40258 target_arch = "arm",
40259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40260)]
40261pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
40262 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40263 unsafe { transmute(a) }
40264}
40265#[doc = "Vector reinterpret cast operation"]
40266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
40267#[inline]
40268#[cfg(target_endian = "little")]
40269#[target_feature(enable = "neon")]
40270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40272#[cfg_attr(
40273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40274 assert_instr(nop)
40275)]
40276#[cfg_attr(
40277 not(target_arch = "arm"),
40278 stable(feature = "neon_intrinsics", since = "1.59.0")
40279)]
40280#[cfg_attr(
40281 target_arch = "arm",
40282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40283)]
40284pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
40285 unsafe { transmute(a) }
40286}
40287#[doc = "Vector reinterpret cast operation"]
40288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
40289#[inline]
40290#[cfg(target_endian = "big")]
40291#[target_feature(enable = "neon")]
40292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40294#[cfg_attr(
40295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40296 assert_instr(nop)
40297)]
40298#[cfg_attr(
40299 not(target_arch = "arm"),
40300 stable(feature = "neon_intrinsics", since = "1.59.0")
40301)]
40302#[cfg_attr(
40303 target_arch = "arm",
40304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40305)]
40306pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
40307 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40308 unsafe {
40309 let ret_val: poly8x8_t = transmute(a);
40310 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
40311 }
40312}
40313#[doc = "Vector reinterpret cast operation"]
40314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
40315#[inline]
40316#[cfg(target_endian = "little")]
40317#[target_feature(enable = "neon")]
40318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40320#[cfg_attr(
40321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40322 assert_instr(nop)
40323)]
40324#[cfg_attr(
40325 not(target_arch = "arm"),
40326 stable(feature = "neon_intrinsics", since = "1.59.0")
40327)]
40328#[cfg_attr(
40329 target_arch = "arm",
40330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40331)]
40332pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
40333 unsafe { transmute(a) }
40334}
40335#[doc = "Vector reinterpret cast operation"]
40336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
40337#[inline]
40338#[cfg(target_endian = "big")]
40339#[target_feature(enable = "neon")]
40340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40342#[cfg_attr(
40343 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40344 assert_instr(nop)
40345)]
40346#[cfg_attr(
40347 not(target_arch = "arm"),
40348 stable(feature = "neon_intrinsics", since = "1.59.0")
40349)]
40350#[cfg_attr(
40351 target_arch = "arm",
40352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40353)]
40354pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
40355 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
40356 unsafe {
40357 let ret_val: poly16x4_t = transmute(a);
40358 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
40359 }
40360}
40361#[doc = "Vector reinterpret cast operation"]
40362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
40363#[inline]
40364#[cfg(target_endian = "little")]
40365#[target_feature(enable = "neon")]
40366#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40368#[cfg_attr(
40369 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40370 assert_instr(nop)
40371)]
40372#[cfg_attr(
40373 not(target_arch = "arm"),
40374 stable(feature = "neon_intrinsics", since = "1.59.0")
40375)]
40376#[cfg_attr(
40377 target_arch = "arm",
40378 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40379)]
40380pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
40381 unsafe { transmute(a) }
40382}
40383#[doc = "Vector reinterpret cast operation"]
40384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
40385#[inline]
40386#[cfg(target_endian = "big")]
40387#[target_feature(enable = "neon")]
40388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40390#[cfg_attr(
40391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40392 assert_instr(nop)
40393)]
40394#[cfg_attr(
40395 not(target_arch = "arm"),
40396 stable(feature = "neon_intrinsics", since = "1.59.0")
40397)]
40398#[cfg_attr(
40399 target_arch = "arm",
40400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40401)]
40402pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
40403 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40404 unsafe {
40405 let ret_val: float32x4_t = transmute(a);
40406 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
40407 }
40408}
40409#[doc = "Vector reinterpret cast operation"]
40410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
40411#[inline]
40412#[cfg(target_endian = "little")]
40413#[target_feature(enable = "neon")]
40414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40416#[cfg_attr(
40417 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40418 assert_instr(nop)
40419)]
40420#[cfg_attr(
40421 not(target_arch = "arm"),
40422 stable(feature = "neon_intrinsics", since = "1.59.0")
40423)]
40424#[cfg_attr(
40425 target_arch = "arm",
40426 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40427)]
40428pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
40429 unsafe { transmute(a) }
40430}
40431#[doc = "Vector reinterpret cast operation"]
40432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
40433#[inline]
40434#[cfg(target_endian = "big")]
40435#[target_feature(enable = "neon")]
40436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40438#[cfg_attr(
40439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40440 assert_instr(nop)
40441)]
40442#[cfg_attr(
40443 not(target_arch = "arm"),
40444 stable(feature = "neon_intrinsics", since = "1.59.0")
40445)]
40446#[cfg_attr(
40447 target_arch = "arm",
40448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40449)]
40450pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
40451 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40452 unsafe {
40453 let ret_val: int8x16_t = transmute(a);
40454 simd_shuffle!(
40455 ret_val,
40456 ret_val,
40457 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
40458 )
40459 }
40460}
40461#[doc = "Vector reinterpret cast operation"]
40462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
40463#[inline]
40464#[cfg(target_endian = "little")]
40465#[target_feature(enable = "neon")]
40466#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40468#[cfg_attr(
40469 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40470 assert_instr(nop)
40471)]
40472#[cfg_attr(
40473 not(target_arch = "arm"),
40474 stable(feature = "neon_intrinsics", since = "1.59.0")
40475)]
40476#[cfg_attr(
40477 target_arch = "arm",
40478 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40479)]
40480pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
40481 unsafe { transmute(a) }
40482}
40483#[doc = "Vector reinterpret cast operation"]
40484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
40485#[inline]
40486#[cfg(target_endian = "big")]
40487#[target_feature(enable = "neon")]
40488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40490#[cfg_attr(
40491 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40492 assert_instr(nop)
40493)]
40494#[cfg_attr(
40495 not(target_arch = "arm"),
40496 stable(feature = "neon_intrinsics", since = "1.59.0")
40497)]
40498#[cfg_attr(
40499 target_arch = "arm",
40500 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40501)]
40502pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
40503 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40504 unsafe {
40505 let ret_val: int32x4_t = transmute(a);
40506 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
40507 }
40508}
40509#[doc = "Vector reinterpret cast operation"]
40510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
40511#[inline]
40512#[cfg(target_endian = "little")]
40513#[target_feature(enable = "neon")]
40514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40516#[cfg_attr(
40517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40518 assert_instr(nop)
40519)]
40520#[cfg_attr(
40521 not(target_arch = "arm"),
40522 stable(feature = "neon_intrinsics", since = "1.59.0")
40523)]
40524#[cfg_attr(
40525 target_arch = "arm",
40526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40527)]
40528pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
40529 unsafe { transmute(a) }
40530}
40531#[doc = "Vector reinterpret cast operation"]
40532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
40533#[inline]
40534#[cfg(target_endian = "big")]
40535#[target_feature(enable = "neon")]
40536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40538#[cfg_attr(
40539 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40540 assert_instr(nop)
40541)]
40542#[cfg_attr(
40543 not(target_arch = "arm"),
40544 stable(feature = "neon_intrinsics", since = "1.59.0")
40545)]
40546#[cfg_attr(
40547 target_arch = "arm",
40548 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40549)]
40550pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
40551 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40552 unsafe {
40553 let ret_val: int64x2_t = transmute(a);
40554 simd_shuffle!(ret_val, ret_val, [1, 0])
40555 }
40556}
40557#[doc = "Vector reinterpret cast operation"]
40558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
40559#[inline]
40560#[cfg(target_endian = "little")]
40561#[target_feature(enable = "neon")]
40562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40564#[cfg_attr(
40565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40566 assert_instr(nop)
40567)]
40568#[cfg_attr(
40569 not(target_arch = "arm"),
40570 stable(feature = "neon_intrinsics", since = "1.59.0")
40571)]
40572#[cfg_attr(
40573 target_arch = "arm",
40574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40575)]
40576pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
40577 unsafe { transmute(a) }
40578}
40579#[doc = "Vector reinterpret cast operation"]
40580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
40581#[inline]
40582#[cfg(target_endian = "big")]
40583#[target_feature(enable = "neon")]
40584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40586#[cfg_attr(
40587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40588 assert_instr(nop)
40589)]
40590#[cfg_attr(
40591 not(target_arch = "arm"),
40592 stable(feature = "neon_intrinsics", since = "1.59.0")
40593)]
40594#[cfg_attr(
40595 target_arch = "arm",
40596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40597)]
40598pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
40599 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40600 unsafe {
40601 let ret_val: uint8x16_t = transmute(a);
40602 simd_shuffle!(
40603 ret_val,
40604 ret_val,
40605 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
40606 )
40607 }
40608}
40609#[doc = "Vector reinterpret cast operation"]
40610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
40611#[inline]
40612#[cfg(target_endian = "little")]
40613#[target_feature(enable = "neon")]
40614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40615#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40616#[cfg_attr(
40617 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40618 assert_instr(nop)
40619)]
40620#[cfg_attr(
40621 not(target_arch = "arm"),
40622 stable(feature = "neon_intrinsics", since = "1.59.0")
40623)]
40624#[cfg_attr(
40625 target_arch = "arm",
40626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40627)]
40628pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
40629 unsafe { transmute(a) }
40630}
40631#[doc = "Vector reinterpret cast operation"]
40632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
40633#[inline]
40634#[cfg(target_endian = "big")]
40635#[target_feature(enable = "neon")]
40636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40638#[cfg_attr(
40639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40640 assert_instr(nop)
40641)]
40642#[cfg_attr(
40643 not(target_arch = "arm"),
40644 stable(feature = "neon_intrinsics", since = "1.59.0")
40645)]
40646#[cfg_attr(
40647 target_arch = "arm",
40648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40649)]
40650pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
40651 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40652 unsafe {
40653 let ret_val: uint16x8_t = transmute(a);
40654 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
40655 }
40656}
40657#[doc = "Vector reinterpret cast operation"]
40658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
40659#[inline]
40660#[cfg(target_endian = "little")]
40661#[target_feature(enable = "neon")]
40662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40664#[cfg_attr(
40665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40666 assert_instr(nop)
40667)]
40668#[cfg_attr(
40669 not(target_arch = "arm"),
40670 stable(feature = "neon_intrinsics", since = "1.59.0")
40671)]
40672#[cfg_attr(
40673 target_arch = "arm",
40674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40675)]
40676pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
40677 unsafe { transmute(a) }
40678}
40679#[doc = "Vector reinterpret cast operation"]
40680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
40681#[inline]
40682#[cfg(target_endian = "big")]
40683#[target_feature(enable = "neon")]
40684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40686#[cfg_attr(
40687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40688 assert_instr(nop)
40689)]
40690#[cfg_attr(
40691 not(target_arch = "arm"),
40692 stable(feature = "neon_intrinsics", since = "1.59.0")
40693)]
40694#[cfg_attr(
40695 target_arch = "arm",
40696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40697)]
40698pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
40699 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40700 unsafe {
40701 let ret_val: uint32x4_t = transmute(a);
40702 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
40703 }
40704}
40705#[doc = "Vector reinterpret cast operation"]
40706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
40707#[inline]
40708#[cfg(target_endian = "little")]
40709#[target_feature(enable = "neon")]
40710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40712#[cfg_attr(
40713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40714 assert_instr(nop)
40715)]
40716#[cfg_attr(
40717 not(target_arch = "arm"),
40718 stable(feature = "neon_intrinsics", since = "1.59.0")
40719)]
40720#[cfg_attr(
40721 target_arch = "arm",
40722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40723)]
40724pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
40725 unsafe { transmute(a) }
40726}
40727#[doc = "Vector reinterpret cast operation"]
40728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
40729#[inline]
40730#[cfg(target_endian = "big")]
40731#[target_feature(enable = "neon")]
40732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40734#[cfg_attr(
40735 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40736 assert_instr(nop)
40737)]
40738#[cfg_attr(
40739 not(target_arch = "arm"),
40740 stable(feature = "neon_intrinsics", since = "1.59.0")
40741)]
40742#[cfg_attr(
40743 target_arch = "arm",
40744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40745)]
40746pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
40747 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40748 unsafe {
40749 let ret_val: uint64x2_t = transmute(a);
40750 simd_shuffle!(ret_val, ret_val, [1, 0])
40751 }
40752}
40753#[doc = "Vector reinterpret cast operation"]
40754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
40755#[inline]
40756#[cfg(target_endian = "little")]
40757#[target_feature(enable = "neon")]
40758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40760#[cfg_attr(
40761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40762 assert_instr(nop)
40763)]
40764#[cfg_attr(
40765 not(target_arch = "arm"),
40766 stable(feature = "neon_intrinsics", since = "1.59.0")
40767)]
40768#[cfg_attr(
40769 target_arch = "arm",
40770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40771)]
40772pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
40773 unsafe { transmute(a) }
40774}
40775#[doc = "Vector reinterpret cast operation"]
40776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
40777#[inline]
40778#[cfg(target_endian = "big")]
40779#[target_feature(enable = "neon")]
40780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40782#[cfg_attr(
40783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40784 assert_instr(nop)
40785)]
40786#[cfg_attr(
40787 not(target_arch = "arm"),
40788 stable(feature = "neon_intrinsics", since = "1.59.0")
40789)]
40790#[cfg_attr(
40791 target_arch = "arm",
40792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40793)]
40794pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
40795 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40796 unsafe {
40797 let ret_val: poly8x16_t = transmute(a);
40798 simd_shuffle!(
40799 ret_val,
40800 ret_val,
40801 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
40802 )
40803 }
40804}
40805#[doc = "Vector reinterpret cast operation"]
40806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
40807#[inline]
40808#[cfg(target_endian = "little")]
40809#[target_feature(enable = "neon")]
40810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40812#[cfg_attr(
40813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40814 assert_instr(nop)
40815)]
40816#[cfg_attr(
40817 not(target_arch = "arm"),
40818 stable(feature = "neon_intrinsics", since = "1.59.0")
40819)]
40820#[cfg_attr(
40821 target_arch = "arm",
40822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40823)]
40824pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
40825 unsafe { transmute(a) }
40826}
40827#[doc = "Vector reinterpret cast operation"]
40828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
40829#[inline]
40830#[cfg(target_endian = "big")]
40831#[target_feature(enable = "neon")]
40832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40833#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40834#[cfg_attr(
40835 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40836 assert_instr(nop)
40837)]
40838#[cfg_attr(
40839 not(target_arch = "arm"),
40840 stable(feature = "neon_intrinsics", since = "1.59.0")
40841)]
40842#[cfg_attr(
40843 target_arch = "arm",
40844 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40845)]
40846pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
40847 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
40848 unsafe {
40849 let ret_val: poly16x8_t = transmute(a);
40850 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
40851 }
40852}
40853#[doc = "Vector reinterpret cast operation"]
40854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
40855#[inline]
40856#[cfg(target_endian = "little")]
40857#[target_feature(enable = "neon")]
40858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40860#[cfg_attr(
40861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40862 assert_instr(nop)
40863)]
40864#[cfg_attr(
40865 not(target_arch = "arm"),
40866 stable(feature = "neon_intrinsics", since = "1.59.0")
40867)]
40868#[cfg_attr(
40869 target_arch = "arm",
40870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40871)]
40872pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
40873 unsafe { transmute(a) }
40874}
40875#[doc = "Vector reinterpret cast operation"]
40876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
40877#[inline]
40878#[cfg(target_endian = "big")]
40879#[target_feature(enable = "neon")]
40880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40882#[cfg_attr(
40883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40884 assert_instr(nop)
40885)]
40886#[cfg_attr(
40887 not(target_arch = "arm"),
40888 stable(feature = "neon_intrinsics", since = "1.59.0")
40889)]
40890#[cfg_attr(
40891 target_arch = "arm",
40892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40893)]
40894pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
40895 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
40896 unsafe {
40897 let ret_val: float32x2_t = transmute(a);
40898 simd_shuffle!(ret_val, ret_val, [1, 0])
40899 }
40900}
40901#[doc = "Vector reinterpret cast operation"]
40902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
40903#[inline]
40904#[cfg(target_endian = "little")]
40905#[target_feature(enable = "neon")]
40906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40908#[cfg_attr(
40909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40910 assert_instr(nop)
40911)]
40912#[cfg_attr(
40913 not(target_arch = "arm"),
40914 stable(feature = "neon_intrinsics", since = "1.59.0")
40915)]
40916#[cfg_attr(
40917 target_arch = "arm",
40918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40919)]
40920pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
40921 unsafe { transmute(a) }
40922}
40923#[doc = "Vector reinterpret cast operation"]
40924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
40925#[inline]
40926#[cfg(target_endian = "big")]
40927#[target_feature(enable = "neon")]
40928#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40929#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40930#[cfg_attr(
40931 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40932 assert_instr(nop)
40933)]
40934#[cfg_attr(
40935 not(target_arch = "arm"),
40936 stable(feature = "neon_intrinsics", since = "1.59.0")
40937)]
40938#[cfg_attr(
40939 target_arch = "arm",
40940 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40941)]
40942pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
40943 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
40944 unsafe {
40945 let ret_val: int8x8_t = transmute(a);
40946 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
40947 }
40948}
40949#[doc = "Vector reinterpret cast operation"]
40950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
40951#[inline]
40952#[cfg(target_endian = "little")]
40953#[target_feature(enable = "neon")]
40954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40955#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40956#[cfg_attr(
40957 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40958 assert_instr(nop)
40959)]
40960#[cfg_attr(
40961 not(target_arch = "arm"),
40962 stable(feature = "neon_intrinsics", since = "1.59.0")
40963)]
40964#[cfg_attr(
40965 target_arch = "arm",
40966 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40967)]
40968pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
40969 unsafe { transmute(a) }
40970}
40971#[doc = "Vector reinterpret cast operation"]
40972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
40973#[inline]
40974#[cfg(target_endian = "big")]
40975#[target_feature(enable = "neon")]
40976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
40978#[cfg_attr(
40979 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40980 assert_instr(nop)
40981)]
40982#[cfg_attr(
40983 not(target_arch = "arm"),
40984 stable(feature = "neon_intrinsics", since = "1.59.0")
40985)]
40986#[cfg_attr(
40987 target_arch = "arm",
40988 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40989)]
40990pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
40991 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
40992 unsafe {
40993 let ret_val: int16x4_t = transmute(a);
40994 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
40995 }
40996}
40997#[doc = "Vector reinterpret cast operation"]
40998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
40999#[inline]
41000#[cfg(target_endian = "little")]
41001#[target_feature(enable = "neon")]
41002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41004#[cfg_attr(
41005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41006 assert_instr(nop)
41007)]
41008#[cfg_attr(
41009 not(target_arch = "arm"),
41010 stable(feature = "neon_intrinsics", since = "1.59.0")
41011)]
41012#[cfg_attr(
41013 target_arch = "arm",
41014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41015)]
41016pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
41017 unsafe { transmute(a) }
41018}
41019#[doc = "Vector reinterpret cast operation"]
41020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
41021#[inline]
41022#[cfg(target_endian = "big")]
41023#[target_feature(enable = "neon")]
41024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41026#[cfg_attr(
41027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41028 assert_instr(nop)
41029)]
41030#[cfg_attr(
41031 not(target_arch = "arm"),
41032 stable(feature = "neon_intrinsics", since = "1.59.0")
41033)]
41034#[cfg_attr(
41035 target_arch = "arm",
41036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41037)]
41038pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
41039 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41040 unsafe { transmute(a) }
41041}
41042#[doc = "Vector reinterpret cast operation"]
41043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
41044#[inline]
41045#[cfg(target_endian = "little")]
41046#[target_feature(enable = "neon")]
41047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41049#[cfg_attr(
41050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41051 assert_instr(nop)
41052)]
41053#[cfg_attr(
41054 not(target_arch = "arm"),
41055 stable(feature = "neon_intrinsics", since = "1.59.0")
41056)]
41057#[cfg_attr(
41058 target_arch = "arm",
41059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41060)]
41061pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
41062 unsafe { transmute(a) }
41063}
41064#[doc = "Vector reinterpret cast operation"]
41065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
41066#[inline]
41067#[cfg(target_endian = "big")]
41068#[target_feature(enable = "neon")]
41069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41070#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41071#[cfg_attr(
41072 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41073 assert_instr(nop)
41074)]
41075#[cfg_attr(
41076 not(target_arch = "arm"),
41077 stable(feature = "neon_intrinsics", since = "1.59.0")
41078)]
41079#[cfg_attr(
41080 target_arch = "arm",
41081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41082)]
41083pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
41084 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41085 unsafe {
41086 let ret_val: uint8x8_t = transmute(a);
41087 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41088 }
41089}
41090#[doc = "Vector reinterpret cast operation"]
41091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
41092#[inline]
41093#[cfg(target_endian = "little")]
41094#[target_feature(enable = "neon")]
41095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41097#[cfg_attr(
41098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41099 assert_instr(nop)
41100)]
41101#[cfg_attr(
41102 not(target_arch = "arm"),
41103 stable(feature = "neon_intrinsics", since = "1.59.0")
41104)]
41105#[cfg_attr(
41106 target_arch = "arm",
41107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41108)]
41109pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
41110 unsafe { transmute(a) }
41111}
41112#[doc = "Vector reinterpret cast operation"]
41113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
41114#[inline]
41115#[cfg(target_endian = "big")]
41116#[target_feature(enable = "neon")]
41117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41119#[cfg_attr(
41120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41121 assert_instr(nop)
41122)]
41123#[cfg_attr(
41124 not(target_arch = "arm"),
41125 stable(feature = "neon_intrinsics", since = "1.59.0")
41126)]
41127#[cfg_attr(
41128 target_arch = "arm",
41129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41130)]
41131pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
41132 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41133 unsafe {
41134 let ret_val: uint16x4_t = transmute(a);
41135 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
41136 }
41137}
41138#[doc = "Vector reinterpret cast operation"]
41139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
41140#[inline]
41141#[cfg(target_endian = "little")]
41142#[target_feature(enable = "neon")]
41143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41145#[cfg_attr(
41146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41147 assert_instr(nop)
41148)]
41149#[cfg_attr(
41150 not(target_arch = "arm"),
41151 stable(feature = "neon_intrinsics", since = "1.59.0")
41152)]
41153#[cfg_attr(
41154 target_arch = "arm",
41155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41156)]
41157pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
41158 unsafe { transmute(a) }
41159}
41160#[doc = "Vector reinterpret cast operation"]
41161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
41162#[inline]
41163#[cfg(target_endian = "big")]
41164#[target_feature(enable = "neon")]
41165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41167#[cfg_attr(
41168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41169 assert_instr(nop)
41170)]
41171#[cfg_attr(
41172 not(target_arch = "arm"),
41173 stable(feature = "neon_intrinsics", since = "1.59.0")
41174)]
41175#[cfg_attr(
41176 target_arch = "arm",
41177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41178)]
41179pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
41180 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41181 unsafe {
41182 let ret_val: uint32x2_t = transmute(a);
41183 simd_shuffle!(ret_val, ret_val, [1, 0])
41184 }
41185}
41186#[doc = "Vector reinterpret cast operation"]
41187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
41188#[inline]
41189#[cfg(target_endian = "little")]
41190#[target_feature(enable = "neon")]
41191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41193#[cfg_attr(
41194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41195 assert_instr(nop)
41196)]
41197#[cfg_attr(
41198 not(target_arch = "arm"),
41199 stable(feature = "neon_intrinsics", since = "1.59.0")
41200)]
41201#[cfg_attr(
41202 target_arch = "arm",
41203 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41204)]
41205pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
41206 unsafe { transmute(a) }
41207}
41208#[doc = "Vector reinterpret cast operation"]
41209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
41210#[inline]
41211#[cfg(target_endian = "big")]
41212#[target_feature(enable = "neon")]
41213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41215#[cfg_attr(
41216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41217 assert_instr(nop)
41218)]
41219#[cfg_attr(
41220 not(target_arch = "arm"),
41221 stable(feature = "neon_intrinsics", since = "1.59.0")
41222)]
41223#[cfg_attr(
41224 target_arch = "arm",
41225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41226)]
41227pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
41228 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41229 unsafe { transmute(a) }
41230}
41231#[doc = "Vector reinterpret cast operation"]
41232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
41233#[inline]
41234#[cfg(target_endian = "little")]
41235#[target_feature(enable = "neon")]
41236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41238#[cfg_attr(
41239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41240 assert_instr(nop)
41241)]
41242#[cfg_attr(
41243 not(target_arch = "arm"),
41244 stable(feature = "neon_intrinsics", since = "1.59.0")
41245)]
41246#[cfg_attr(
41247 target_arch = "arm",
41248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41249)]
41250pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
41251 unsafe { transmute(a) }
41252}
41253#[doc = "Vector reinterpret cast operation"]
41254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
41255#[inline]
41256#[cfg(target_endian = "big")]
41257#[target_feature(enable = "neon")]
41258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41260#[cfg_attr(
41261 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41262 assert_instr(nop)
41263)]
41264#[cfg_attr(
41265 not(target_arch = "arm"),
41266 stable(feature = "neon_intrinsics", since = "1.59.0")
41267)]
41268#[cfg_attr(
41269 target_arch = "arm",
41270 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41271)]
41272pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
41273 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41274 unsafe {
41275 let ret_val: poly8x8_t = transmute(a);
41276 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41277 }
41278}
41279#[doc = "Vector reinterpret cast operation"]
41280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
41281#[inline]
41282#[cfg(target_endian = "little")]
41283#[target_feature(enable = "neon")]
41284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41285#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41286#[cfg_attr(
41287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41288 assert_instr(nop)
41289)]
41290#[cfg_attr(
41291 not(target_arch = "arm"),
41292 stable(feature = "neon_intrinsics", since = "1.59.0")
41293)]
41294#[cfg_attr(
41295 target_arch = "arm",
41296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41297)]
41298pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
41299 unsafe { transmute(a) }
41300}
41301#[doc = "Vector reinterpret cast operation"]
41302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
41303#[inline]
41304#[cfg(target_endian = "big")]
41305#[target_feature(enable = "neon")]
41306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41308#[cfg_attr(
41309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41310 assert_instr(nop)
41311)]
41312#[cfg_attr(
41313 not(target_arch = "arm"),
41314 stable(feature = "neon_intrinsics", since = "1.59.0")
41315)]
41316#[cfg_attr(
41317 target_arch = "arm",
41318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41319)]
41320pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
41321 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41322 unsafe {
41323 let ret_val: poly16x4_t = transmute(a);
41324 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
41325 }
41326}
41327#[doc = "Vector reinterpret cast operation"]
41328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
41329#[inline]
41330#[cfg(target_endian = "little")]
41331#[target_feature(enable = "neon")]
41332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41334#[cfg_attr(
41335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41336 assert_instr(nop)
41337)]
41338#[cfg_attr(
41339 not(target_arch = "arm"),
41340 stable(feature = "neon_intrinsics", since = "1.59.0")
41341)]
41342#[cfg_attr(
41343 target_arch = "arm",
41344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41345)]
41346pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
41347 unsafe { transmute(a) }
41348}
41349#[doc = "Vector reinterpret cast operation"]
41350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
41351#[inline]
41352#[cfg(target_endian = "big")]
41353#[target_feature(enable = "neon")]
41354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41356#[cfg_attr(
41357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41358 assert_instr(nop)
41359)]
41360#[cfg_attr(
41361 not(target_arch = "arm"),
41362 stable(feature = "neon_intrinsics", since = "1.59.0")
41363)]
41364#[cfg_attr(
41365 target_arch = "arm",
41366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41367)]
41368pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
41369 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41370 unsafe {
41371 let ret_val: float32x4_t = transmute(a);
41372 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
41373 }
41374}
41375#[doc = "Vector reinterpret cast operation"]
41376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
41377#[inline]
41378#[cfg(target_endian = "little")]
41379#[target_feature(enable = "neon")]
41380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41382#[cfg_attr(
41383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41384 assert_instr(nop)
41385)]
41386#[cfg_attr(
41387 not(target_arch = "arm"),
41388 stable(feature = "neon_intrinsics", since = "1.59.0")
41389)]
41390#[cfg_attr(
41391 target_arch = "arm",
41392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41393)]
41394pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
41395 unsafe { transmute(a) }
41396}
41397#[doc = "Vector reinterpret cast operation"]
41398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
41399#[inline]
41400#[cfg(target_endian = "big")]
41401#[target_feature(enable = "neon")]
41402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41404#[cfg_attr(
41405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41406 assert_instr(nop)
41407)]
41408#[cfg_attr(
41409 not(target_arch = "arm"),
41410 stable(feature = "neon_intrinsics", since = "1.59.0")
41411)]
41412#[cfg_attr(
41413 target_arch = "arm",
41414 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41415)]
41416pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
41417 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41418 unsafe {
41419 let ret_val: int8x16_t = transmute(a);
41420 simd_shuffle!(
41421 ret_val,
41422 ret_val,
41423 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
41424 )
41425 }
41426}
41427#[doc = "Vector reinterpret cast operation"]
41428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
41429#[inline]
41430#[cfg(target_endian = "little")]
41431#[target_feature(enable = "neon")]
41432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41434#[cfg_attr(
41435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41436 assert_instr(nop)
41437)]
41438#[cfg_attr(
41439 not(target_arch = "arm"),
41440 stable(feature = "neon_intrinsics", since = "1.59.0")
41441)]
41442#[cfg_attr(
41443 target_arch = "arm",
41444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41445)]
41446pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
41447 unsafe { transmute(a) }
41448}
41449#[doc = "Vector reinterpret cast operation"]
41450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
41451#[inline]
41452#[cfg(target_endian = "big")]
41453#[target_feature(enable = "neon")]
41454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41456#[cfg_attr(
41457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41458 assert_instr(nop)
41459)]
41460#[cfg_attr(
41461 not(target_arch = "arm"),
41462 stable(feature = "neon_intrinsics", since = "1.59.0")
41463)]
41464#[cfg_attr(
41465 target_arch = "arm",
41466 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41467)]
41468pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
41469 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41470 unsafe {
41471 let ret_val: int16x8_t = transmute(a);
41472 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41473 }
41474}
41475#[doc = "Vector reinterpret cast operation"]
41476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
41477#[inline]
41478#[cfg(target_endian = "little")]
41479#[target_feature(enable = "neon")]
41480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41482#[cfg_attr(
41483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41484 assert_instr(nop)
41485)]
41486#[cfg_attr(
41487 not(target_arch = "arm"),
41488 stable(feature = "neon_intrinsics", since = "1.59.0")
41489)]
41490#[cfg_attr(
41491 target_arch = "arm",
41492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41493)]
41494pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
41495 unsafe { transmute(a) }
41496}
41497#[doc = "Vector reinterpret cast operation"]
41498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
41499#[inline]
41500#[cfg(target_endian = "big")]
41501#[target_feature(enable = "neon")]
41502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41504#[cfg_attr(
41505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41506 assert_instr(nop)
41507)]
41508#[cfg_attr(
41509 not(target_arch = "arm"),
41510 stable(feature = "neon_intrinsics", since = "1.59.0")
41511)]
41512#[cfg_attr(
41513 target_arch = "arm",
41514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41515)]
41516pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
41517 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41518 unsafe {
41519 let ret_val: int64x2_t = transmute(a);
41520 simd_shuffle!(ret_val, ret_val, [1, 0])
41521 }
41522}
41523#[doc = "Vector reinterpret cast operation"]
41524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
41525#[inline]
41526#[cfg(target_endian = "little")]
41527#[target_feature(enable = "neon")]
41528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41530#[cfg_attr(
41531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41532 assert_instr(nop)
41533)]
41534#[cfg_attr(
41535 not(target_arch = "arm"),
41536 stable(feature = "neon_intrinsics", since = "1.59.0")
41537)]
41538#[cfg_attr(
41539 target_arch = "arm",
41540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41541)]
41542pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
41543 unsafe { transmute(a) }
41544}
41545#[doc = "Vector reinterpret cast operation"]
41546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
41547#[inline]
41548#[cfg(target_endian = "big")]
41549#[target_feature(enable = "neon")]
41550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41552#[cfg_attr(
41553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41554 assert_instr(nop)
41555)]
41556#[cfg_attr(
41557 not(target_arch = "arm"),
41558 stable(feature = "neon_intrinsics", since = "1.59.0")
41559)]
41560#[cfg_attr(
41561 target_arch = "arm",
41562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41563)]
41564pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
41565 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41566 unsafe {
41567 let ret_val: uint8x16_t = transmute(a);
41568 simd_shuffle!(
41569 ret_val,
41570 ret_val,
41571 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
41572 )
41573 }
41574}
41575#[doc = "Vector reinterpret cast operation"]
41576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
41577#[inline]
41578#[cfg(target_endian = "little")]
41579#[target_feature(enable = "neon")]
41580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41582#[cfg_attr(
41583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41584 assert_instr(nop)
41585)]
41586#[cfg_attr(
41587 not(target_arch = "arm"),
41588 stable(feature = "neon_intrinsics", since = "1.59.0")
41589)]
41590#[cfg_attr(
41591 target_arch = "arm",
41592 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41593)]
41594pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
41595 unsafe { transmute(a) }
41596}
41597#[doc = "Vector reinterpret cast operation"]
41598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
41599#[inline]
41600#[cfg(target_endian = "big")]
41601#[target_feature(enable = "neon")]
41602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41604#[cfg_attr(
41605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41606 assert_instr(nop)
41607)]
41608#[cfg_attr(
41609 not(target_arch = "arm"),
41610 stable(feature = "neon_intrinsics", since = "1.59.0")
41611)]
41612#[cfg_attr(
41613 target_arch = "arm",
41614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41615)]
41616pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
41617 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41618 unsafe {
41619 let ret_val: uint16x8_t = transmute(a);
41620 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41621 }
41622}
41623#[doc = "Vector reinterpret cast operation"]
41624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
41625#[inline]
41626#[cfg(target_endian = "little")]
41627#[target_feature(enable = "neon")]
41628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41630#[cfg_attr(
41631 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41632 assert_instr(nop)
41633)]
41634#[cfg_attr(
41635 not(target_arch = "arm"),
41636 stable(feature = "neon_intrinsics", since = "1.59.0")
41637)]
41638#[cfg_attr(
41639 target_arch = "arm",
41640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41641)]
41642pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
41643 unsafe { transmute(a) }
41644}
41645#[doc = "Vector reinterpret cast operation"]
41646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
41647#[inline]
41648#[cfg(target_endian = "big")]
41649#[target_feature(enable = "neon")]
41650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41652#[cfg_attr(
41653 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41654 assert_instr(nop)
41655)]
41656#[cfg_attr(
41657 not(target_arch = "arm"),
41658 stable(feature = "neon_intrinsics", since = "1.59.0")
41659)]
41660#[cfg_attr(
41661 target_arch = "arm",
41662 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41663)]
41664pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
41665 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41666 unsafe {
41667 let ret_val: uint32x4_t = transmute(a);
41668 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
41669 }
41670}
41671#[doc = "Vector reinterpret cast operation"]
41672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
41673#[inline]
41674#[cfg(target_endian = "little")]
41675#[target_feature(enable = "neon")]
41676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41677#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41678#[cfg_attr(
41679 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41680 assert_instr(nop)
41681)]
41682#[cfg_attr(
41683 not(target_arch = "arm"),
41684 stable(feature = "neon_intrinsics", since = "1.59.0")
41685)]
41686#[cfg_attr(
41687 target_arch = "arm",
41688 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41689)]
41690pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
41691 unsafe { transmute(a) }
41692}
41693#[doc = "Vector reinterpret cast operation"]
41694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
41695#[inline]
41696#[cfg(target_endian = "big")]
41697#[target_feature(enable = "neon")]
41698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41700#[cfg_attr(
41701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41702 assert_instr(nop)
41703)]
41704#[cfg_attr(
41705 not(target_arch = "arm"),
41706 stable(feature = "neon_intrinsics", since = "1.59.0")
41707)]
41708#[cfg_attr(
41709 target_arch = "arm",
41710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41711)]
41712pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
41713 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41714 unsafe {
41715 let ret_val: uint64x2_t = transmute(a);
41716 simd_shuffle!(ret_val, ret_val, [1, 0])
41717 }
41718}
41719#[doc = "Vector reinterpret cast operation"]
41720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
41721#[inline]
41722#[cfg(target_endian = "little")]
41723#[target_feature(enable = "neon")]
41724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41726#[cfg_attr(
41727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41728 assert_instr(nop)
41729)]
41730#[cfg_attr(
41731 not(target_arch = "arm"),
41732 stable(feature = "neon_intrinsics", since = "1.59.0")
41733)]
41734#[cfg_attr(
41735 target_arch = "arm",
41736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41737)]
41738pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
41739 unsafe { transmute(a) }
41740}
41741#[doc = "Vector reinterpret cast operation"]
41742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
41743#[inline]
41744#[cfg(target_endian = "big")]
41745#[target_feature(enable = "neon")]
41746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41748#[cfg_attr(
41749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41750 assert_instr(nop)
41751)]
41752#[cfg_attr(
41753 not(target_arch = "arm"),
41754 stable(feature = "neon_intrinsics", since = "1.59.0")
41755)]
41756#[cfg_attr(
41757 target_arch = "arm",
41758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41759)]
41760pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
41761 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41762 unsafe {
41763 let ret_val: poly8x16_t = transmute(a);
41764 simd_shuffle!(
41765 ret_val,
41766 ret_val,
41767 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
41768 )
41769 }
41770}
41771#[doc = "Vector reinterpret cast operation"]
41772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
41773#[inline]
41774#[cfg(target_endian = "little")]
41775#[target_feature(enable = "neon")]
41776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41778#[cfg_attr(
41779 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41780 assert_instr(nop)
41781)]
41782#[cfg_attr(
41783 not(target_arch = "arm"),
41784 stable(feature = "neon_intrinsics", since = "1.59.0")
41785)]
41786#[cfg_attr(
41787 target_arch = "arm",
41788 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41789)]
41790pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
41791 unsafe { transmute(a) }
41792}
41793#[doc = "Vector reinterpret cast operation"]
41794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
41795#[inline]
41796#[cfg(target_endian = "big")]
41797#[target_feature(enable = "neon")]
41798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41800#[cfg_attr(
41801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41802 assert_instr(nop)
41803)]
41804#[cfg_attr(
41805 not(target_arch = "arm"),
41806 stable(feature = "neon_intrinsics", since = "1.59.0")
41807)]
41808#[cfg_attr(
41809 target_arch = "arm",
41810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41811)]
41812pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
41813 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41814 unsafe {
41815 let ret_val: poly16x8_t = transmute(a);
41816 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41817 }
41818}
41819#[doc = "Vector reinterpret cast operation"]
41820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
41821#[inline]
41822#[cfg(target_endian = "little")]
41823#[target_feature(enable = "neon")]
41824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41826#[cfg_attr(
41827 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41828 assert_instr(nop)
41829)]
41830#[cfg_attr(
41831 not(target_arch = "arm"),
41832 stable(feature = "neon_intrinsics", since = "1.59.0")
41833)]
41834#[cfg_attr(
41835 target_arch = "arm",
41836 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41837)]
41838pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
41839 unsafe { transmute(a) }
41840}
41841#[doc = "Vector reinterpret cast operation"]
41842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
41843#[inline]
41844#[cfg(target_endian = "big")]
41845#[target_feature(enable = "neon")]
41846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41848#[cfg_attr(
41849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41850 assert_instr(nop)
41851)]
41852#[cfg_attr(
41853 not(target_arch = "arm"),
41854 stable(feature = "neon_intrinsics", since = "1.59.0")
41855)]
41856#[cfg_attr(
41857 target_arch = "arm",
41858 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41859)]
41860pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
41861 unsafe {
41862 let ret_val: float32x2_t = transmute(a);
41863 simd_shuffle!(ret_val, ret_val, [1, 0])
41864 }
41865}
41866#[doc = "Vector reinterpret cast operation"]
41867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
41868#[inline]
41869#[cfg(target_endian = "little")]
41870#[target_feature(enable = "neon")]
41871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41872#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41873#[cfg_attr(
41874 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41875 assert_instr(nop)
41876)]
41877#[cfg_attr(
41878 not(target_arch = "arm"),
41879 stable(feature = "neon_intrinsics", since = "1.59.0")
41880)]
41881#[cfg_attr(
41882 target_arch = "arm",
41883 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41884)]
41885pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
41886 unsafe { transmute(a) }
41887}
41888#[doc = "Vector reinterpret cast operation"]
41889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
41890#[inline]
41891#[cfg(target_endian = "big")]
41892#[target_feature(enable = "neon")]
41893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41895#[cfg_attr(
41896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41897 assert_instr(nop)
41898)]
41899#[cfg_attr(
41900 not(target_arch = "arm"),
41901 stable(feature = "neon_intrinsics", since = "1.59.0")
41902)]
41903#[cfg_attr(
41904 target_arch = "arm",
41905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41906)]
41907pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
41908 unsafe {
41909 let ret_val: int8x8_t = transmute(a);
41910 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41911 }
41912}
41913#[doc = "Vector reinterpret cast operation"]
41914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
41915#[inline]
41916#[cfg(target_endian = "little")]
41917#[target_feature(enable = "neon")]
41918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41920#[cfg_attr(
41921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41922 assert_instr(nop)
41923)]
41924#[cfg_attr(
41925 not(target_arch = "arm"),
41926 stable(feature = "neon_intrinsics", since = "1.59.0")
41927)]
41928#[cfg_attr(
41929 target_arch = "arm",
41930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41931)]
41932pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
41933 unsafe { transmute(a) }
41934}
41935#[doc = "Vector reinterpret cast operation"]
41936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
41937#[inline]
41938#[cfg(target_endian = "big")]
41939#[target_feature(enable = "neon")]
41940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41942#[cfg_attr(
41943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41944 assert_instr(nop)
41945)]
41946#[cfg_attr(
41947 not(target_arch = "arm"),
41948 stable(feature = "neon_intrinsics", since = "1.59.0")
41949)]
41950#[cfg_attr(
41951 target_arch = "arm",
41952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41953)]
41954pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
41955 unsafe {
41956 let ret_val: int16x4_t = transmute(a);
41957 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
41958 }
41959}
41960#[doc = "Vector reinterpret cast operation"]
41961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
41962#[inline]
41963#[cfg(target_endian = "little")]
41964#[target_feature(enable = "neon")]
41965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41967#[cfg_attr(
41968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41969 assert_instr(nop)
41970)]
41971#[cfg_attr(
41972 not(target_arch = "arm"),
41973 stable(feature = "neon_intrinsics", since = "1.59.0")
41974)]
41975#[cfg_attr(
41976 target_arch = "arm",
41977 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41978)]
41979pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
41980 unsafe { transmute(a) }
41981}
41982#[doc = "Vector reinterpret cast operation"]
41983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
41984#[inline]
41985#[cfg(target_endian = "big")]
41986#[target_feature(enable = "neon")]
41987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
41989#[cfg_attr(
41990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41991 assert_instr(nop)
41992)]
41993#[cfg_attr(
41994 not(target_arch = "arm"),
41995 stable(feature = "neon_intrinsics", since = "1.59.0")
41996)]
41997#[cfg_attr(
41998 target_arch = "arm",
41999 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42000)]
42001pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
42002 unsafe {
42003 let ret_val: int32x2_t = transmute(a);
42004 simd_shuffle!(ret_val, ret_val, [1, 0])
42005 }
42006}
42007#[doc = "Vector reinterpret cast operation"]
42008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
42009#[inline]
42010#[cfg(target_endian = "little")]
42011#[target_feature(enable = "neon")]
42012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42014#[cfg_attr(
42015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42016 assert_instr(nop)
42017)]
42018#[cfg_attr(
42019 not(target_arch = "arm"),
42020 stable(feature = "neon_intrinsics", since = "1.59.0")
42021)]
42022#[cfg_attr(
42023 target_arch = "arm",
42024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42025)]
42026pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
42027 unsafe { transmute(a) }
42028}
42029#[doc = "Vector reinterpret cast operation"]
42030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
42031#[inline]
42032#[cfg(target_endian = "big")]
42033#[target_feature(enable = "neon")]
42034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42036#[cfg_attr(
42037 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42038 assert_instr(nop)
42039)]
42040#[cfg_attr(
42041 not(target_arch = "arm"),
42042 stable(feature = "neon_intrinsics", since = "1.59.0")
42043)]
42044#[cfg_attr(
42045 target_arch = "arm",
42046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42047)]
42048pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
42049 unsafe {
42050 let ret_val: uint8x8_t = transmute(a);
42051 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42052 }
42053}
42054#[doc = "Vector reinterpret cast operation"]
42055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
42056#[inline]
42057#[cfg(target_endian = "little")]
42058#[target_feature(enable = "neon")]
42059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42061#[cfg_attr(
42062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42063 assert_instr(nop)
42064)]
42065#[cfg_attr(
42066 not(target_arch = "arm"),
42067 stable(feature = "neon_intrinsics", since = "1.59.0")
42068)]
42069#[cfg_attr(
42070 target_arch = "arm",
42071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42072)]
42073pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
42074 unsafe { transmute(a) }
42075}
42076#[doc = "Vector reinterpret cast operation"]
42077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
42078#[inline]
42079#[cfg(target_endian = "big")]
42080#[target_feature(enable = "neon")]
42081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42083#[cfg_attr(
42084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42085 assert_instr(nop)
42086)]
42087#[cfg_attr(
42088 not(target_arch = "arm"),
42089 stable(feature = "neon_intrinsics", since = "1.59.0")
42090)]
42091#[cfg_attr(
42092 target_arch = "arm",
42093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42094)]
42095pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
42096 unsafe {
42097 let ret_val: uint16x4_t = transmute(a);
42098 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42099 }
42100}
42101#[doc = "Vector reinterpret cast operation"]
42102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
42103#[inline]
42104#[cfg(target_endian = "little")]
42105#[target_feature(enable = "neon")]
42106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42108#[cfg_attr(
42109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42110 assert_instr(nop)
42111)]
42112#[cfg_attr(
42113 not(target_arch = "arm"),
42114 stable(feature = "neon_intrinsics", since = "1.59.0")
42115)]
42116#[cfg_attr(
42117 target_arch = "arm",
42118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42119)]
42120pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
42121 unsafe { transmute(a) }
42122}
42123#[doc = "Vector reinterpret cast operation"]
42124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
42125#[inline]
42126#[cfg(target_endian = "big")]
42127#[target_feature(enable = "neon")]
42128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42130#[cfg_attr(
42131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42132 assert_instr(nop)
42133)]
42134#[cfg_attr(
42135 not(target_arch = "arm"),
42136 stable(feature = "neon_intrinsics", since = "1.59.0")
42137)]
42138#[cfg_attr(
42139 target_arch = "arm",
42140 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42141)]
42142pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
42143 unsafe {
42144 let ret_val: uint32x2_t = transmute(a);
42145 simd_shuffle!(ret_val, ret_val, [1, 0])
42146 }
42147}
42148#[doc = "Vector reinterpret cast operation"]
42149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
42150#[inline]
42151#[target_feature(enable = "neon")]
42152#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42154#[cfg_attr(
42155 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42156 assert_instr(nop)
42157)]
42158#[cfg_attr(
42159 not(target_arch = "arm"),
42160 stable(feature = "neon_intrinsics", since = "1.59.0")
42161)]
42162#[cfg_attr(
42163 target_arch = "arm",
42164 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42165)]
42166pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
42167 unsafe { transmute(a) }
42168}
42169#[doc = "Vector reinterpret cast operation"]
42170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
42171#[inline]
42172#[cfg(target_endian = "little")]
42173#[target_feature(enable = "neon")]
42174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42176#[cfg_attr(
42177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42178 assert_instr(nop)
42179)]
42180#[cfg_attr(
42181 not(target_arch = "arm"),
42182 stable(feature = "neon_intrinsics", since = "1.59.0")
42183)]
42184#[cfg_attr(
42185 target_arch = "arm",
42186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42187)]
42188pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
42189 unsafe { transmute(a) }
42190}
42191#[doc = "Vector reinterpret cast operation"]
42192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
42193#[inline]
42194#[cfg(target_endian = "big")]
42195#[target_feature(enable = "neon")]
42196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42198#[cfg_attr(
42199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42200 assert_instr(nop)
42201)]
42202#[cfg_attr(
42203 not(target_arch = "arm"),
42204 stable(feature = "neon_intrinsics", since = "1.59.0")
42205)]
42206#[cfg_attr(
42207 target_arch = "arm",
42208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42209)]
42210pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
42211 unsafe {
42212 let ret_val: poly8x8_t = transmute(a);
42213 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42214 }
42215}
42216#[doc = "Vector reinterpret cast operation"]
42217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
42218#[inline]
42219#[cfg(target_endian = "little")]
42220#[target_feature(enable = "neon")]
42221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42223#[cfg_attr(
42224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42225 assert_instr(nop)
42226)]
42227#[cfg_attr(
42228 not(target_arch = "arm"),
42229 stable(feature = "neon_intrinsics", since = "1.59.0")
42230)]
42231#[cfg_attr(
42232 target_arch = "arm",
42233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42234)]
42235pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
42236 unsafe { transmute(a) }
42237}
42238#[doc = "Vector reinterpret cast operation"]
42239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
42240#[inline]
42241#[cfg(target_endian = "big")]
42242#[target_feature(enable = "neon")]
42243#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42244#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42245#[cfg_attr(
42246 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42247 assert_instr(nop)
42248)]
42249#[cfg_attr(
42250 not(target_arch = "arm"),
42251 stable(feature = "neon_intrinsics", since = "1.59.0")
42252)]
42253#[cfg_attr(
42254 target_arch = "arm",
42255 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42256)]
42257pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
42258 unsafe {
42259 let ret_val: poly16x4_t = transmute(a);
42260 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42261 }
42262}
42263#[doc = "Vector reinterpret cast operation"]
42264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
42265#[inline]
42266#[cfg(target_endian = "little")]
42267#[target_feature(enable = "neon")]
42268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42270#[cfg_attr(
42271 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42272 assert_instr(nop)
42273)]
42274#[cfg_attr(
42275 not(target_arch = "arm"),
42276 stable(feature = "neon_intrinsics", since = "1.59.0")
42277)]
42278#[cfg_attr(
42279 target_arch = "arm",
42280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42281)]
42282pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
42283 unsafe { transmute(a) }
42284}
42285#[doc = "Vector reinterpret cast operation"]
42286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
42287#[inline]
42288#[cfg(target_endian = "big")]
42289#[target_feature(enable = "neon")]
42290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42292#[cfg_attr(
42293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42294 assert_instr(nop)
42295)]
42296#[cfg_attr(
42297 not(target_arch = "arm"),
42298 stable(feature = "neon_intrinsics", since = "1.59.0")
42299)]
42300#[cfg_attr(
42301 target_arch = "arm",
42302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42303)]
42304pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
42305 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42306 unsafe {
42307 let ret_val: float32x4_t = transmute(a);
42308 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42309 }
42310}
42311#[doc = "Vector reinterpret cast operation"]
42312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
42313#[inline]
42314#[cfg(target_endian = "little")]
42315#[target_feature(enable = "neon")]
42316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42318#[cfg_attr(
42319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42320 assert_instr(nop)
42321)]
42322#[cfg_attr(
42323 not(target_arch = "arm"),
42324 stable(feature = "neon_intrinsics", since = "1.59.0")
42325)]
42326#[cfg_attr(
42327 target_arch = "arm",
42328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42329)]
42330pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
42331 unsafe { transmute(a) }
42332}
42333#[doc = "Vector reinterpret cast operation"]
42334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
42335#[inline]
42336#[cfg(target_endian = "big")]
42337#[target_feature(enable = "neon")]
42338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42340#[cfg_attr(
42341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42342 assert_instr(nop)
42343)]
42344#[cfg_attr(
42345 not(target_arch = "arm"),
42346 stable(feature = "neon_intrinsics", since = "1.59.0")
42347)]
42348#[cfg_attr(
42349 target_arch = "arm",
42350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42351)]
42352pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
42353 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42354 unsafe {
42355 let ret_val: int8x16_t = transmute(a);
42356 simd_shuffle!(
42357 ret_val,
42358 ret_val,
42359 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42360 )
42361 }
42362}
42363#[doc = "Vector reinterpret cast operation"]
42364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
42365#[inline]
42366#[cfg(target_endian = "little")]
42367#[target_feature(enable = "neon")]
42368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42370#[cfg_attr(
42371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42372 assert_instr(nop)
42373)]
42374#[cfg_attr(
42375 not(target_arch = "arm"),
42376 stable(feature = "neon_intrinsics", since = "1.59.0")
42377)]
42378#[cfg_attr(
42379 target_arch = "arm",
42380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42381)]
42382pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
42383 unsafe { transmute(a) }
42384}
42385#[doc = "Vector reinterpret cast operation"]
42386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
42387#[inline]
42388#[cfg(target_endian = "big")]
42389#[target_feature(enable = "neon")]
42390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42392#[cfg_attr(
42393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42394 assert_instr(nop)
42395)]
42396#[cfg_attr(
42397 not(target_arch = "arm"),
42398 stable(feature = "neon_intrinsics", since = "1.59.0")
42399)]
42400#[cfg_attr(
42401 target_arch = "arm",
42402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42403)]
42404pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
42405 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42406 unsafe {
42407 let ret_val: int16x8_t = transmute(a);
42408 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42409 }
42410}
42411#[doc = "Vector reinterpret cast operation"]
42412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
42413#[inline]
42414#[cfg(target_endian = "little")]
42415#[target_feature(enable = "neon")]
42416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42418#[cfg_attr(
42419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42420 assert_instr(nop)
42421)]
42422#[cfg_attr(
42423 not(target_arch = "arm"),
42424 stable(feature = "neon_intrinsics", since = "1.59.0")
42425)]
42426#[cfg_attr(
42427 target_arch = "arm",
42428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42429)]
42430pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
42431 unsafe { transmute(a) }
42432}
42433#[doc = "Vector reinterpret cast operation"]
42434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
42435#[inline]
42436#[cfg(target_endian = "big")]
42437#[target_feature(enable = "neon")]
42438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42440#[cfg_attr(
42441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42442 assert_instr(nop)
42443)]
42444#[cfg_attr(
42445 not(target_arch = "arm"),
42446 stable(feature = "neon_intrinsics", since = "1.59.0")
42447)]
42448#[cfg_attr(
42449 target_arch = "arm",
42450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42451)]
42452pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
42453 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42454 unsafe {
42455 let ret_val: int32x4_t = transmute(a);
42456 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42457 }
42458}
42459#[doc = "Vector reinterpret cast operation"]
42460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
42461#[inline]
42462#[cfg(target_endian = "little")]
42463#[target_feature(enable = "neon")]
42464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42466#[cfg_attr(
42467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42468 assert_instr(nop)
42469)]
42470#[cfg_attr(
42471 not(target_arch = "arm"),
42472 stable(feature = "neon_intrinsics", since = "1.59.0")
42473)]
42474#[cfg_attr(
42475 target_arch = "arm",
42476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42477)]
42478pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
42479 unsafe { transmute(a) }
42480}
42481#[doc = "Vector reinterpret cast operation"]
42482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
42483#[inline]
42484#[cfg(target_endian = "big")]
42485#[target_feature(enable = "neon")]
42486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42488#[cfg_attr(
42489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42490 assert_instr(nop)
42491)]
42492#[cfg_attr(
42493 not(target_arch = "arm"),
42494 stable(feature = "neon_intrinsics", since = "1.59.0")
42495)]
42496#[cfg_attr(
42497 target_arch = "arm",
42498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42499)]
42500pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
42501 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42502 unsafe {
42503 let ret_val: uint8x16_t = transmute(a);
42504 simd_shuffle!(
42505 ret_val,
42506 ret_val,
42507 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42508 )
42509 }
42510}
42511#[doc = "Vector reinterpret cast operation"]
42512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
42513#[inline]
42514#[cfg(target_endian = "little")]
42515#[target_feature(enable = "neon")]
42516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42518#[cfg_attr(
42519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42520 assert_instr(nop)
42521)]
42522#[cfg_attr(
42523 not(target_arch = "arm"),
42524 stable(feature = "neon_intrinsics", since = "1.59.0")
42525)]
42526#[cfg_attr(
42527 target_arch = "arm",
42528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42529)]
42530pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
42531 unsafe { transmute(a) }
42532}
42533#[doc = "Vector reinterpret cast operation"]
42534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
42535#[inline]
42536#[cfg(target_endian = "big")]
42537#[target_feature(enable = "neon")]
42538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42540#[cfg_attr(
42541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42542 assert_instr(nop)
42543)]
42544#[cfg_attr(
42545 not(target_arch = "arm"),
42546 stable(feature = "neon_intrinsics", since = "1.59.0")
42547)]
42548#[cfg_attr(
42549 target_arch = "arm",
42550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42551)]
42552pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
42553 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42554 unsafe {
42555 let ret_val: uint16x8_t = transmute(a);
42556 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42557 }
42558}
42559#[doc = "Vector reinterpret cast operation"]
42560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
42561#[inline]
42562#[cfg(target_endian = "little")]
42563#[target_feature(enable = "neon")]
42564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42566#[cfg_attr(
42567 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42568 assert_instr(nop)
42569)]
42570#[cfg_attr(
42571 not(target_arch = "arm"),
42572 stable(feature = "neon_intrinsics", since = "1.59.0")
42573)]
42574#[cfg_attr(
42575 target_arch = "arm",
42576 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42577)]
42578pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
42579 unsafe { transmute(a) }
42580}
42581#[doc = "Vector reinterpret cast operation"]
42582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
42583#[inline]
42584#[cfg(target_endian = "big")]
42585#[target_feature(enable = "neon")]
42586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42588#[cfg_attr(
42589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42590 assert_instr(nop)
42591)]
42592#[cfg_attr(
42593 not(target_arch = "arm"),
42594 stable(feature = "neon_intrinsics", since = "1.59.0")
42595)]
42596#[cfg_attr(
42597 target_arch = "arm",
42598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42599)]
42600pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
42601 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42602 unsafe {
42603 let ret_val: uint32x4_t = transmute(a);
42604 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42605 }
42606}
42607#[doc = "Vector reinterpret cast operation"]
42608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
42609#[inline]
42610#[cfg(target_endian = "little")]
42611#[target_feature(enable = "neon")]
42612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42614#[cfg_attr(
42615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42616 assert_instr(nop)
42617)]
42618#[cfg_attr(
42619 not(target_arch = "arm"),
42620 stable(feature = "neon_intrinsics", since = "1.59.0")
42621)]
42622#[cfg_attr(
42623 target_arch = "arm",
42624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42625)]
42626pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
42627 unsafe { transmute(a) }
42628}
42629#[doc = "Vector reinterpret cast operation"]
42630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
42631#[inline]
42632#[cfg(target_endian = "big")]
42633#[target_feature(enable = "neon")]
42634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42636#[cfg_attr(
42637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42638 assert_instr(nop)
42639)]
42640#[cfg_attr(
42641 not(target_arch = "arm"),
42642 stable(feature = "neon_intrinsics", since = "1.59.0")
42643)]
42644#[cfg_attr(
42645 target_arch = "arm",
42646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42647)]
42648pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
42649 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42650 unsafe {
42651 let ret_val: uint64x2_t = transmute(a);
42652 simd_shuffle!(ret_val, ret_val, [1, 0])
42653 }
42654}
42655#[doc = "Vector reinterpret cast operation"]
42656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
42657#[inline]
42658#[cfg(target_endian = "little")]
42659#[target_feature(enable = "neon")]
42660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42662#[cfg_attr(
42663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42664 assert_instr(nop)
42665)]
42666#[cfg_attr(
42667 not(target_arch = "arm"),
42668 stable(feature = "neon_intrinsics", since = "1.59.0")
42669)]
42670#[cfg_attr(
42671 target_arch = "arm",
42672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42673)]
42674pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
42675 unsafe { transmute(a) }
42676}
42677#[doc = "Vector reinterpret cast operation"]
42678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
42679#[inline]
42680#[cfg(target_endian = "big")]
42681#[target_feature(enable = "neon")]
42682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42684#[cfg_attr(
42685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42686 assert_instr(nop)
42687)]
42688#[cfg_attr(
42689 not(target_arch = "arm"),
42690 stable(feature = "neon_intrinsics", since = "1.59.0")
42691)]
42692#[cfg_attr(
42693 target_arch = "arm",
42694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42695)]
42696pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
42697 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42698 unsafe {
42699 let ret_val: poly8x16_t = transmute(a);
42700 simd_shuffle!(
42701 ret_val,
42702 ret_val,
42703 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42704 )
42705 }
42706}
42707#[doc = "Vector reinterpret cast operation"]
42708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
42709#[inline]
42710#[cfg(target_endian = "little")]
42711#[target_feature(enable = "neon")]
42712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42714#[cfg_attr(
42715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42716 assert_instr(nop)
42717)]
42718#[cfg_attr(
42719 not(target_arch = "arm"),
42720 stable(feature = "neon_intrinsics", since = "1.59.0")
42721)]
42722#[cfg_attr(
42723 target_arch = "arm",
42724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42725)]
42726pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
42727 unsafe { transmute(a) }
42728}
42729#[doc = "Vector reinterpret cast operation"]
42730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
42731#[inline]
42732#[cfg(target_endian = "big")]
42733#[target_feature(enable = "neon")]
42734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42736#[cfg_attr(
42737 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42738 assert_instr(nop)
42739)]
42740#[cfg_attr(
42741 not(target_arch = "arm"),
42742 stable(feature = "neon_intrinsics", since = "1.59.0")
42743)]
42744#[cfg_attr(
42745 target_arch = "arm",
42746 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42747)]
42748pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
42749 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42750 unsafe {
42751 let ret_val: poly16x8_t = transmute(a);
42752 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42753 }
42754}
42755#[doc = "Vector reinterpret cast operation"]
42756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
42757#[inline]
42758#[cfg(target_endian = "little")]
42759#[target_feature(enable = "neon")]
42760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42762#[cfg_attr(
42763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42764 assert_instr(nop)
42765)]
42766#[cfg_attr(
42767 not(target_arch = "arm"),
42768 stable(feature = "neon_intrinsics", since = "1.59.0")
42769)]
42770#[cfg_attr(
42771 target_arch = "arm",
42772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42773)]
42774pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
42775 unsafe { transmute(a) }
42776}
42777#[doc = "Vector reinterpret cast operation"]
42778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
42779#[inline]
42780#[cfg(target_endian = "big")]
42781#[target_feature(enable = "neon")]
42782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42784#[cfg_attr(
42785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42786 assert_instr(nop)
42787)]
42788#[cfg_attr(
42789 not(target_arch = "arm"),
42790 stable(feature = "neon_intrinsics", since = "1.59.0")
42791)]
42792#[cfg_attr(
42793 target_arch = "arm",
42794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42795)]
42796pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
42797 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42798 unsafe {
42799 let ret_val: float32x2_t = transmute(a);
42800 simd_shuffle!(ret_val, ret_val, [1, 0])
42801 }
42802}
42803#[doc = "Vector reinterpret cast operation"]
42804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
42805#[inline]
42806#[cfg(target_endian = "little")]
42807#[target_feature(enable = "neon")]
42808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42810#[cfg_attr(
42811 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42812 assert_instr(nop)
42813)]
42814#[cfg_attr(
42815 not(target_arch = "arm"),
42816 stable(feature = "neon_intrinsics", since = "1.59.0")
42817)]
42818#[cfg_attr(
42819 target_arch = "arm",
42820 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42821)]
42822pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
42823 unsafe { transmute(a) }
42824}
42825#[doc = "Vector reinterpret cast operation"]
42826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
42827#[inline]
42828#[cfg(target_endian = "big")]
42829#[target_feature(enable = "neon")]
42830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42831#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42832#[cfg_attr(
42833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42834 assert_instr(nop)
42835)]
42836#[cfg_attr(
42837 not(target_arch = "arm"),
42838 stable(feature = "neon_intrinsics", since = "1.59.0")
42839)]
42840#[cfg_attr(
42841 target_arch = "arm",
42842 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42843)]
42844pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
42845 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42846 unsafe {
42847 let ret_val: int8x8_t = transmute(a);
42848 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42849 }
42850}
42851#[doc = "Vector reinterpret cast operation"]
42852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
42853#[inline]
42854#[cfg(target_endian = "little")]
42855#[target_feature(enable = "neon")]
42856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42858#[cfg_attr(
42859 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42860 assert_instr(nop)
42861)]
42862#[cfg_attr(
42863 not(target_arch = "arm"),
42864 stable(feature = "neon_intrinsics", since = "1.59.0")
42865)]
42866#[cfg_attr(
42867 target_arch = "arm",
42868 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42869)]
42870pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
42871 unsafe { transmute(a) }
42872}
42873#[doc = "Vector reinterpret cast operation"]
42874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
42875#[inline]
42876#[cfg(target_endian = "big")]
42877#[target_feature(enable = "neon")]
42878#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42879#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42880#[cfg_attr(
42881 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42882 assert_instr(nop)
42883)]
42884#[cfg_attr(
42885 not(target_arch = "arm"),
42886 stable(feature = "neon_intrinsics", since = "1.59.0")
42887)]
42888#[cfg_attr(
42889 target_arch = "arm",
42890 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42891)]
42892pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
42893 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42894 unsafe {
42895 let ret_val: int16x4_t = transmute(a);
42896 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42897 }
42898}
42899#[doc = "Vector reinterpret cast operation"]
42900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
42901#[inline]
42902#[cfg(target_endian = "little")]
42903#[target_feature(enable = "neon")]
42904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42906#[cfg_attr(
42907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42908 assert_instr(nop)
42909)]
42910#[cfg_attr(
42911 not(target_arch = "arm"),
42912 stable(feature = "neon_intrinsics", since = "1.59.0")
42913)]
42914#[cfg_attr(
42915 target_arch = "arm",
42916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42917)]
42918pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
42919 unsafe { transmute(a) }
42920}
42921#[doc = "Vector reinterpret cast operation"]
42922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
42923#[inline]
42924#[cfg(target_endian = "big")]
42925#[target_feature(enable = "neon")]
42926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42928#[cfg_attr(
42929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42930 assert_instr(nop)
42931)]
42932#[cfg_attr(
42933 not(target_arch = "arm"),
42934 stable(feature = "neon_intrinsics", since = "1.59.0")
42935)]
42936#[cfg_attr(
42937 target_arch = "arm",
42938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42939)]
42940pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
42941 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42942 unsafe {
42943 let ret_val: int32x2_t = transmute(a);
42944 simd_shuffle!(ret_val, ret_val, [1, 0])
42945 }
42946}
42947#[doc = "Vector reinterpret cast operation"]
42948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
42949#[inline]
42950#[cfg(target_endian = "little")]
42951#[target_feature(enable = "neon")]
42952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42954#[cfg_attr(
42955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42956 assert_instr(nop)
42957)]
42958#[cfg_attr(
42959 not(target_arch = "arm"),
42960 stable(feature = "neon_intrinsics", since = "1.59.0")
42961)]
42962#[cfg_attr(
42963 target_arch = "arm",
42964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42965)]
42966pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
42967 unsafe { transmute(a) }
42968}
42969#[doc = "Vector reinterpret cast operation"]
42970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
42971#[inline]
42972#[cfg(target_endian = "big")]
42973#[target_feature(enable = "neon")]
42974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42976#[cfg_attr(
42977 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42978 assert_instr(nop)
42979)]
42980#[cfg_attr(
42981 not(target_arch = "arm"),
42982 stable(feature = "neon_intrinsics", since = "1.59.0")
42983)]
42984#[cfg_attr(
42985 target_arch = "arm",
42986 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42987)]
42988pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
42989 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42990 unsafe { transmute(a) }
42991}
42992#[doc = "Vector reinterpret cast operation"]
42993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
42994#[inline]
42995#[cfg(target_endian = "little")]
42996#[target_feature(enable = "neon")]
42997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42999#[cfg_attr(
43000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43001 assert_instr(nop)
43002)]
43003#[cfg_attr(
43004 not(target_arch = "arm"),
43005 stable(feature = "neon_intrinsics", since = "1.59.0")
43006)]
43007#[cfg_attr(
43008 target_arch = "arm",
43009 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43010)]
43011pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
43012 unsafe { transmute(a) }
43013}
43014#[doc = "Vector reinterpret cast operation"]
43015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
43016#[inline]
43017#[cfg(target_endian = "big")]
43018#[target_feature(enable = "neon")]
43019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43021#[cfg_attr(
43022 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43023 assert_instr(nop)
43024)]
43025#[cfg_attr(
43026 not(target_arch = "arm"),
43027 stable(feature = "neon_intrinsics", since = "1.59.0")
43028)]
43029#[cfg_attr(
43030 target_arch = "arm",
43031 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43032)]
43033pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
43034 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43035 unsafe {
43036 let ret_val: uint16x4_t = transmute(a);
43037 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43038 }
43039}
43040#[doc = "Vector reinterpret cast operation"]
43041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
43042#[inline]
43043#[cfg(target_endian = "little")]
43044#[target_feature(enable = "neon")]
43045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43047#[cfg_attr(
43048 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43049 assert_instr(nop)
43050)]
43051#[cfg_attr(
43052 not(target_arch = "arm"),
43053 stable(feature = "neon_intrinsics", since = "1.59.0")
43054)]
43055#[cfg_attr(
43056 target_arch = "arm",
43057 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43058)]
43059pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
43060 unsafe { transmute(a) }
43061}
43062#[doc = "Vector reinterpret cast operation"]
43063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
43064#[inline]
43065#[cfg(target_endian = "big")]
43066#[target_feature(enable = "neon")]
43067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43069#[cfg_attr(
43070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43071 assert_instr(nop)
43072)]
43073#[cfg_attr(
43074 not(target_arch = "arm"),
43075 stable(feature = "neon_intrinsics", since = "1.59.0")
43076)]
43077#[cfg_attr(
43078 target_arch = "arm",
43079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43080)]
43081pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
43082 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43083 unsafe {
43084 let ret_val: uint32x2_t = transmute(a);
43085 simd_shuffle!(ret_val, ret_val, [1, 0])
43086 }
43087}
43088#[doc = "Vector reinterpret cast operation"]
43089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
43090#[inline]
43091#[cfg(target_endian = "little")]
43092#[target_feature(enable = "neon")]
43093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43095#[cfg_attr(
43096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43097 assert_instr(nop)
43098)]
43099#[cfg_attr(
43100 not(target_arch = "arm"),
43101 stable(feature = "neon_intrinsics", since = "1.59.0")
43102)]
43103#[cfg_attr(
43104 target_arch = "arm",
43105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43106)]
43107pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
43108 unsafe { transmute(a) }
43109}
43110#[doc = "Vector reinterpret cast operation"]
43111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
43112#[inline]
43113#[cfg(target_endian = "big")]
43114#[target_feature(enable = "neon")]
43115#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43116#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43117#[cfg_attr(
43118 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43119 assert_instr(nop)
43120)]
43121#[cfg_attr(
43122 not(target_arch = "arm"),
43123 stable(feature = "neon_intrinsics", since = "1.59.0")
43124)]
43125#[cfg_attr(
43126 target_arch = "arm",
43127 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43128)]
43129pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
43130 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43131 unsafe { transmute(a) }
43132}
43133#[doc = "Vector reinterpret cast operation"]
43134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
43135#[inline]
43136#[cfg(target_endian = "little")]
43137#[target_feature(enable = "neon")]
43138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43139#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43140#[cfg_attr(
43141 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43142 assert_instr(nop)
43143)]
43144#[cfg_attr(
43145 not(target_arch = "arm"),
43146 stable(feature = "neon_intrinsics", since = "1.59.0")
43147)]
43148#[cfg_attr(
43149 target_arch = "arm",
43150 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43151)]
43152pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
43153 unsafe { transmute(a) }
43154}
43155#[doc = "Vector reinterpret cast operation"]
43156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
43157#[inline]
43158#[cfg(target_endian = "big")]
43159#[target_feature(enable = "neon")]
43160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43162#[cfg_attr(
43163 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43164 assert_instr(nop)
43165)]
43166#[cfg_attr(
43167 not(target_arch = "arm"),
43168 stable(feature = "neon_intrinsics", since = "1.59.0")
43169)]
43170#[cfg_attr(
43171 target_arch = "arm",
43172 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43173)]
43174pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
43175 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43176 unsafe {
43177 let ret_val: poly8x8_t = transmute(a);
43178 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43179 }
43180}
43181#[doc = "Vector reinterpret cast operation"]
43182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
43183#[inline]
43184#[cfg(target_endian = "little")]
43185#[target_feature(enable = "neon")]
43186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43188#[cfg_attr(
43189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43190 assert_instr(nop)
43191)]
43192#[cfg_attr(
43193 not(target_arch = "arm"),
43194 stable(feature = "neon_intrinsics", since = "1.59.0")
43195)]
43196#[cfg_attr(
43197 target_arch = "arm",
43198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43199)]
43200pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
43201 unsafe { transmute(a) }
43202}
43203#[doc = "Vector reinterpret cast operation"]
43204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
43205#[inline]
43206#[cfg(target_endian = "big")]
43207#[target_feature(enable = "neon")]
43208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43210#[cfg_attr(
43211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43212 assert_instr(nop)
43213)]
43214#[cfg_attr(
43215 not(target_arch = "arm"),
43216 stable(feature = "neon_intrinsics", since = "1.59.0")
43217)]
43218#[cfg_attr(
43219 target_arch = "arm",
43220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43221)]
43222pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
43223 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43224 unsafe {
43225 let ret_val: poly16x4_t = transmute(a);
43226 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43227 }
43228}
43229#[doc = "Vector reinterpret cast operation"]
43230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
43231#[inline]
43232#[cfg(target_endian = "little")]
43233#[target_feature(enable = "neon")]
43234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43236#[cfg_attr(
43237 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43238 assert_instr(nop)
43239)]
43240#[cfg_attr(
43241 not(target_arch = "arm"),
43242 stable(feature = "neon_intrinsics", since = "1.59.0")
43243)]
43244#[cfg_attr(
43245 target_arch = "arm",
43246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43247)]
43248pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
43249 unsafe { transmute(a) }
43250}
43251#[doc = "Vector reinterpret cast operation"]
43252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
43253#[inline]
43254#[cfg(target_endian = "big")]
43255#[target_feature(enable = "neon")]
43256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43258#[cfg_attr(
43259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43260 assert_instr(nop)
43261)]
43262#[cfg_attr(
43263 not(target_arch = "arm"),
43264 stable(feature = "neon_intrinsics", since = "1.59.0")
43265)]
43266#[cfg_attr(
43267 target_arch = "arm",
43268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43269)]
43270pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
43271 let a: uint8x16_t =
43272 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43273 unsafe {
43274 let ret_val: float32x4_t = transmute(a);
43275 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43276 }
43277}
43278#[doc = "Vector reinterpret cast operation"]
43279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
43280#[inline]
43281#[cfg(target_endian = "little")]
43282#[target_feature(enable = "neon")]
43283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43285#[cfg_attr(
43286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43287 assert_instr(nop)
43288)]
43289#[cfg_attr(
43290 not(target_arch = "arm"),
43291 stable(feature = "neon_intrinsics", since = "1.59.0")
43292)]
43293#[cfg_attr(
43294 target_arch = "arm",
43295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43296)]
43297pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
43298 unsafe { transmute(a) }
43299}
43300#[doc = "Vector reinterpret cast operation"]
43301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
43302#[inline]
43303#[cfg(target_endian = "big")]
43304#[target_feature(enable = "neon")]
43305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43307#[cfg_attr(
43308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43309 assert_instr(nop)
43310)]
43311#[cfg_attr(
43312 not(target_arch = "arm"),
43313 stable(feature = "neon_intrinsics", since = "1.59.0")
43314)]
43315#[cfg_attr(
43316 target_arch = "arm",
43317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43318)]
43319pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
43320 let a: uint8x16_t =
43321 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43322 unsafe {
43323 let ret_val: int8x16_t = transmute(a);
43324 simd_shuffle!(
43325 ret_val,
43326 ret_val,
43327 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43328 )
43329 }
43330}
43331#[doc = "Vector reinterpret cast operation"]
43332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
43333#[inline]
43334#[cfg(target_endian = "little")]
43335#[target_feature(enable = "neon")]
43336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43338#[cfg_attr(
43339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43340 assert_instr(nop)
43341)]
43342#[cfg_attr(
43343 not(target_arch = "arm"),
43344 stable(feature = "neon_intrinsics", since = "1.59.0")
43345)]
43346#[cfg_attr(
43347 target_arch = "arm",
43348 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43349)]
43350pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
43351 unsafe { transmute(a) }
43352}
43353#[doc = "Vector reinterpret cast operation"]
43354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
43355#[inline]
43356#[cfg(target_endian = "big")]
43357#[target_feature(enable = "neon")]
43358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43360#[cfg_attr(
43361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43362 assert_instr(nop)
43363)]
43364#[cfg_attr(
43365 not(target_arch = "arm"),
43366 stable(feature = "neon_intrinsics", since = "1.59.0")
43367)]
43368#[cfg_attr(
43369 target_arch = "arm",
43370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43371)]
43372pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
43373 let a: uint8x16_t =
43374 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43375 unsafe {
43376 let ret_val: int16x8_t = transmute(a);
43377 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43378 }
43379}
43380#[doc = "Vector reinterpret cast operation"]
43381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
43382#[inline]
43383#[cfg(target_endian = "little")]
43384#[target_feature(enable = "neon")]
43385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43387#[cfg_attr(
43388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43389 assert_instr(nop)
43390)]
43391#[cfg_attr(
43392 not(target_arch = "arm"),
43393 stable(feature = "neon_intrinsics", since = "1.59.0")
43394)]
43395#[cfg_attr(
43396 target_arch = "arm",
43397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43398)]
43399pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
43400 unsafe { transmute(a) }
43401}
43402#[doc = "Vector reinterpret cast operation"]
43403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
43404#[inline]
43405#[cfg(target_endian = "big")]
43406#[target_feature(enable = "neon")]
43407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43409#[cfg_attr(
43410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43411 assert_instr(nop)
43412)]
43413#[cfg_attr(
43414 not(target_arch = "arm"),
43415 stable(feature = "neon_intrinsics", since = "1.59.0")
43416)]
43417#[cfg_attr(
43418 target_arch = "arm",
43419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43420)]
43421pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
43422 let a: uint8x16_t =
43423 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43424 unsafe {
43425 let ret_val: int32x4_t = transmute(a);
43426 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43427 }
43428}
43429#[doc = "Vector reinterpret cast operation"]
43430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
43431#[inline]
43432#[cfg(target_endian = "little")]
43433#[target_feature(enable = "neon")]
43434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43436#[cfg_attr(
43437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43438 assert_instr(nop)
43439)]
43440#[cfg_attr(
43441 not(target_arch = "arm"),
43442 stable(feature = "neon_intrinsics", since = "1.59.0")
43443)]
43444#[cfg_attr(
43445 target_arch = "arm",
43446 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43447)]
43448pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
43449 unsafe { transmute(a) }
43450}
43451#[doc = "Vector reinterpret cast operation"]
43452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
43453#[inline]
43454#[cfg(target_endian = "big")]
43455#[target_feature(enable = "neon")]
43456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43458#[cfg_attr(
43459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43460 assert_instr(nop)
43461)]
43462#[cfg_attr(
43463 not(target_arch = "arm"),
43464 stable(feature = "neon_intrinsics", since = "1.59.0")
43465)]
43466#[cfg_attr(
43467 target_arch = "arm",
43468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43469)]
43470pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
43471 let a: uint8x16_t =
43472 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43473 unsafe {
43474 let ret_val: int64x2_t = transmute(a);
43475 simd_shuffle!(ret_val, ret_val, [1, 0])
43476 }
43477}
43478#[doc = "Vector reinterpret cast operation"]
43479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
43480#[inline]
43481#[cfg(target_endian = "little")]
43482#[target_feature(enable = "neon")]
43483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43485#[cfg_attr(
43486 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43487 assert_instr(nop)
43488)]
43489#[cfg_attr(
43490 not(target_arch = "arm"),
43491 stable(feature = "neon_intrinsics", since = "1.59.0")
43492)]
43493#[cfg_attr(
43494 target_arch = "arm",
43495 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43496)]
43497pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
43498 unsafe { transmute(a) }
43499}
43500#[doc = "Vector reinterpret cast operation"]
43501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
43502#[inline]
43503#[cfg(target_endian = "big")]
43504#[target_feature(enable = "neon")]
43505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43507#[cfg_attr(
43508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43509 assert_instr(nop)
43510)]
43511#[cfg_attr(
43512 not(target_arch = "arm"),
43513 stable(feature = "neon_intrinsics", since = "1.59.0")
43514)]
43515#[cfg_attr(
43516 target_arch = "arm",
43517 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43518)]
43519pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
43520 let a: uint8x16_t =
43521 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43522 unsafe {
43523 let ret_val: uint16x8_t = transmute(a);
43524 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43525 }
43526}
43527#[doc = "Vector reinterpret cast operation"]
43528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
43529#[inline]
43530#[cfg(target_endian = "little")]
43531#[target_feature(enable = "neon")]
43532#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43534#[cfg_attr(
43535 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43536 assert_instr(nop)
43537)]
43538#[cfg_attr(
43539 not(target_arch = "arm"),
43540 stable(feature = "neon_intrinsics", since = "1.59.0")
43541)]
43542#[cfg_attr(
43543 target_arch = "arm",
43544 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43545)]
43546pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
43547 unsafe { transmute(a) }
43548}
43549#[doc = "Vector reinterpret cast operation"]
43550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
43551#[inline]
43552#[cfg(target_endian = "big")]
43553#[target_feature(enable = "neon")]
43554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43556#[cfg_attr(
43557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43558 assert_instr(nop)
43559)]
43560#[cfg_attr(
43561 not(target_arch = "arm"),
43562 stable(feature = "neon_intrinsics", since = "1.59.0")
43563)]
43564#[cfg_attr(
43565 target_arch = "arm",
43566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43567)]
43568pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
43569 let a: uint8x16_t =
43570 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43571 unsafe {
43572 let ret_val: uint32x4_t = transmute(a);
43573 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43574 }
43575}
43576#[doc = "Vector reinterpret cast operation"]
43577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
43578#[inline]
43579#[cfg(target_endian = "little")]
43580#[target_feature(enable = "neon")]
43581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43583#[cfg_attr(
43584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43585 assert_instr(nop)
43586)]
43587#[cfg_attr(
43588 not(target_arch = "arm"),
43589 stable(feature = "neon_intrinsics", since = "1.59.0")
43590)]
43591#[cfg_attr(
43592 target_arch = "arm",
43593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43594)]
43595pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
43596 unsafe { transmute(a) }
43597}
43598#[doc = "Vector reinterpret cast operation"]
43599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
43600#[inline]
43601#[cfg(target_endian = "big")]
43602#[target_feature(enable = "neon")]
43603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43605#[cfg_attr(
43606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43607 assert_instr(nop)
43608)]
43609#[cfg_attr(
43610 not(target_arch = "arm"),
43611 stable(feature = "neon_intrinsics", since = "1.59.0")
43612)]
43613#[cfg_attr(
43614 target_arch = "arm",
43615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43616)]
43617pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
43618 let a: uint8x16_t =
43619 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43620 unsafe {
43621 let ret_val: uint64x2_t = transmute(a);
43622 simd_shuffle!(ret_val, ret_val, [1, 0])
43623 }
43624}
43625#[doc = "Vector reinterpret cast operation"]
43626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
43627#[inline]
43628#[cfg(target_endian = "little")]
43629#[target_feature(enable = "neon")]
43630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43632#[cfg_attr(
43633 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43634 assert_instr(nop)
43635)]
43636#[cfg_attr(
43637 not(target_arch = "arm"),
43638 stable(feature = "neon_intrinsics", since = "1.59.0")
43639)]
43640#[cfg_attr(
43641 target_arch = "arm",
43642 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43643)]
43644pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
43645 unsafe { transmute(a) }
43646}
43647#[doc = "Vector reinterpret cast operation"]
43648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
43649#[inline]
43650#[cfg(target_endian = "big")]
43651#[target_feature(enable = "neon")]
43652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43654#[cfg_attr(
43655 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43656 assert_instr(nop)
43657)]
43658#[cfg_attr(
43659 not(target_arch = "arm"),
43660 stable(feature = "neon_intrinsics", since = "1.59.0")
43661)]
43662#[cfg_attr(
43663 target_arch = "arm",
43664 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43665)]
43666pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
43667 let a: uint8x16_t =
43668 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43669 unsafe {
43670 let ret_val: poly8x16_t = transmute(a);
43671 simd_shuffle!(
43672 ret_val,
43673 ret_val,
43674 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43675 )
43676 }
43677}
43678#[doc = "Vector reinterpret cast operation"]
43679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
43680#[inline]
43681#[cfg(target_endian = "little")]
43682#[target_feature(enable = "neon")]
43683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43685#[cfg_attr(
43686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43687 assert_instr(nop)
43688)]
43689#[cfg_attr(
43690 not(target_arch = "arm"),
43691 stable(feature = "neon_intrinsics", since = "1.59.0")
43692)]
43693#[cfg_attr(
43694 target_arch = "arm",
43695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43696)]
43697pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
43698 unsafe { transmute(a) }
43699}
43700#[doc = "Vector reinterpret cast operation"]
43701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
43702#[inline]
43703#[cfg(target_endian = "big")]
43704#[target_feature(enable = "neon")]
43705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43707#[cfg_attr(
43708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43709 assert_instr(nop)
43710)]
43711#[cfg_attr(
43712 not(target_arch = "arm"),
43713 stable(feature = "neon_intrinsics", since = "1.59.0")
43714)]
43715#[cfg_attr(
43716 target_arch = "arm",
43717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43718)]
43719pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
43720 let a: uint8x16_t =
43721 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43722 unsafe {
43723 let ret_val: poly16x8_t = transmute(a);
43724 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43725 }
43726}
43727#[doc = "Vector reinterpret cast operation"]
43728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
43729#[inline]
43730#[cfg(target_endian = "little")]
43731#[target_feature(enable = "neon")]
43732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43734#[cfg_attr(
43735 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43736 assert_instr(nop)
43737)]
43738#[cfg_attr(
43739 not(target_arch = "arm"),
43740 stable(feature = "neon_intrinsics", since = "1.59.0")
43741)]
43742#[cfg_attr(
43743 target_arch = "arm",
43744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43745)]
43746pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
43747 unsafe { transmute(a) }
43748}
43749#[doc = "Vector reinterpret cast operation"]
43750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
43751#[inline]
43752#[cfg(target_endian = "big")]
43753#[target_feature(enable = "neon")]
43754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43756#[cfg_attr(
43757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43758 assert_instr(nop)
43759)]
43760#[cfg_attr(
43761 not(target_arch = "arm"),
43762 stable(feature = "neon_intrinsics", since = "1.59.0")
43763)]
43764#[cfg_attr(
43765 target_arch = "arm",
43766 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43767)]
43768pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
43769 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43770 unsafe {
43771 let ret_val: float32x2_t = transmute(a);
43772 simd_shuffle!(ret_val, ret_val, [1, 0])
43773 }
43774}
43775#[doc = "Vector reinterpret cast operation"]
43776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
43777#[inline]
43778#[cfg(target_endian = "little")]
43779#[target_feature(enable = "neon")]
43780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43782#[cfg_attr(
43783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43784 assert_instr(nop)
43785)]
43786#[cfg_attr(
43787 not(target_arch = "arm"),
43788 stable(feature = "neon_intrinsics", since = "1.59.0")
43789)]
43790#[cfg_attr(
43791 target_arch = "arm",
43792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43793)]
43794pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
43795 unsafe { transmute(a) }
43796}
43797#[doc = "Vector reinterpret cast operation"]
43798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
43799#[inline]
43800#[cfg(target_endian = "big")]
43801#[target_feature(enable = "neon")]
43802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43804#[cfg_attr(
43805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43806 assert_instr(nop)
43807)]
43808#[cfg_attr(
43809 not(target_arch = "arm"),
43810 stable(feature = "neon_intrinsics", since = "1.59.0")
43811)]
43812#[cfg_attr(
43813 target_arch = "arm",
43814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43815)]
43816pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
43817 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43818 unsafe {
43819 let ret_val: int8x8_t = transmute(a);
43820 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43821 }
43822}
43823#[doc = "Vector reinterpret cast operation"]
43824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
43825#[inline]
43826#[cfg(target_endian = "little")]
43827#[target_feature(enable = "neon")]
43828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43830#[cfg_attr(
43831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43832 assert_instr(nop)
43833)]
43834#[cfg_attr(
43835 not(target_arch = "arm"),
43836 stable(feature = "neon_intrinsics", since = "1.59.0")
43837)]
43838#[cfg_attr(
43839 target_arch = "arm",
43840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43841)]
43842pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
43843 unsafe { transmute(a) }
43844}
43845#[doc = "Vector reinterpret cast operation"]
43846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
43847#[inline]
43848#[cfg(target_endian = "big")]
43849#[target_feature(enable = "neon")]
43850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43852#[cfg_attr(
43853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43854 assert_instr(nop)
43855)]
43856#[cfg_attr(
43857 not(target_arch = "arm"),
43858 stable(feature = "neon_intrinsics", since = "1.59.0")
43859)]
43860#[cfg_attr(
43861 target_arch = "arm",
43862 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43863)]
43864pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
43865 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43866 unsafe {
43867 let ret_val: int16x4_t = transmute(a);
43868 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43869 }
43870}
43871#[doc = "Vector reinterpret cast operation"]
43872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
43873#[inline]
43874#[cfg(target_endian = "little")]
43875#[target_feature(enable = "neon")]
43876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43878#[cfg_attr(
43879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43880 assert_instr(nop)
43881)]
43882#[cfg_attr(
43883 not(target_arch = "arm"),
43884 stable(feature = "neon_intrinsics", since = "1.59.0")
43885)]
43886#[cfg_attr(
43887 target_arch = "arm",
43888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43889)]
43890pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
43891 unsafe { transmute(a) }
43892}
43893#[doc = "Vector reinterpret cast operation"]
43894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
43895#[inline]
43896#[cfg(target_endian = "big")]
43897#[target_feature(enable = "neon")]
43898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43900#[cfg_attr(
43901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43902 assert_instr(nop)
43903)]
43904#[cfg_attr(
43905 not(target_arch = "arm"),
43906 stable(feature = "neon_intrinsics", since = "1.59.0")
43907)]
43908#[cfg_attr(
43909 target_arch = "arm",
43910 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43911)]
43912pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
43913 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43914 unsafe {
43915 let ret_val: int32x2_t = transmute(a);
43916 simd_shuffle!(ret_val, ret_val, [1, 0])
43917 }
43918}
43919#[doc = "Vector reinterpret cast operation"]
43920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
43921#[inline]
43922#[cfg(target_endian = "little")]
43923#[target_feature(enable = "neon")]
43924#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43926#[cfg_attr(
43927 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43928 assert_instr(nop)
43929)]
43930#[cfg_attr(
43931 not(target_arch = "arm"),
43932 stable(feature = "neon_intrinsics", since = "1.59.0")
43933)]
43934#[cfg_attr(
43935 target_arch = "arm",
43936 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43937)]
43938pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
43939 unsafe { transmute(a) }
43940}
43941#[doc = "Vector reinterpret cast operation"]
43942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
43943#[inline]
43944#[cfg(target_endian = "big")]
43945#[target_feature(enable = "neon")]
43946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43948#[cfg_attr(
43949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43950 assert_instr(nop)
43951)]
43952#[cfg_attr(
43953 not(target_arch = "arm"),
43954 stable(feature = "neon_intrinsics", since = "1.59.0")
43955)]
43956#[cfg_attr(
43957 target_arch = "arm",
43958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43959)]
43960pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
43961 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43962 unsafe { transmute(a) }
43963}
43964#[doc = "Vector reinterpret cast operation"]
43965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
43966#[inline]
43967#[cfg(target_endian = "little")]
43968#[target_feature(enable = "neon")]
43969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43971#[cfg_attr(
43972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43973 assert_instr(nop)
43974)]
43975#[cfg_attr(
43976 not(target_arch = "arm"),
43977 stable(feature = "neon_intrinsics", since = "1.59.0")
43978)]
43979#[cfg_attr(
43980 target_arch = "arm",
43981 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43982)]
43983pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
43984 unsafe { transmute(a) }
43985}
43986#[doc = "Vector reinterpret cast operation"]
43987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
43988#[inline]
43989#[cfg(target_endian = "big")]
43990#[target_feature(enable = "neon")]
43991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43993#[cfg_attr(
43994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43995 assert_instr(nop)
43996)]
43997#[cfg_attr(
43998 not(target_arch = "arm"),
43999 stable(feature = "neon_intrinsics", since = "1.59.0")
44000)]
44001#[cfg_attr(
44002 target_arch = "arm",
44003 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44004)]
44005pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
44006 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44007 unsafe {
44008 let ret_val: uint8x8_t = transmute(a);
44009 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44010 }
44011}
44012#[doc = "Vector reinterpret cast operation"]
44013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
44014#[inline]
44015#[cfg(target_endian = "little")]
44016#[target_feature(enable = "neon")]
44017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44019#[cfg_attr(
44020 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44021 assert_instr(nop)
44022)]
44023#[cfg_attr(
44024 not(target_arch = "arm"),
44025 stable(feature = "neon_intrinsics", since = "1.59.0")
44026)]
44027#[cfg_attr(
44028 target_arch = "arm",
44029 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44030)]
44031pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
44032 unsafe { transmute(a) }
44033}
44034#[doc = "Vector reinterpret cast operation"]
44035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
44036#[inline]
44037#[cfg(target_endian = "big")]
44038#[target_feature(enable = "neon")]
44039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44041#[cfg_attr(
44042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44043 assert_instr(nop)
44044)]
44045#[cfg_attr(
44046 not(target_arch = "arm"),
44047 stable(feature = "neon_intrinsics", since = "1.59.0")
44048)]
44049#[cfg_attr(
44050 target_arch = "arm",
44051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44052)]
44053pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
44054 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44055 unsafe {
44056 let ret_val: uint32x2_t = transmute(a);
44057 simd_shuffle!(ret_val, ret_val, [1, 0])
44058 }
44059}
44060#[doc = "Vector reinterpret cast operation"]
44061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
44062#[inline]
44063#[cfg(target_endian = "little")]
44064#[target_feature(enable = "neon")]
44065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44067#[cfg_attr(
44068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44069 assert_instr(nop)
44070)]
44071#[cfg_attr(
44072 not(target_arch = "arm"),
44073 stable(feature = "neon_intrinsics", since = "1.59.0")
44074)]
44075#[cfg_attr(
44076 target_arch = "arm",
44077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44078)]
44079pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
44080 unsafe { transmute(a) }
44081}
44082#[doc = "Vector reinterpret cast operation"]
44083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
44084#[inline]
44085#[cfg(target_endian = "big")]
44086#[target_feature(enable = "neon")]
44087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44089#[cfg_attr(
44090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44091 assert_instr(nop)
44092)]
44093#[cfg_attr(
44094 not(target_arch = "arm"),
44095 stable(feature = "neon_intrinsics", since = "1.59.0")
44096)]
44097#[cfg_attr(
44098 target_arch = "arm",
44099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44100)]
44101pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
44102 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44103 unsafe { transmute(a) }
44104}
44105#[doc = "Vector reinterpret cast operation"]
44106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
44107#[inline]
44108#[cfg(target_endian = "little")]
44109#[target_feature(enable = "neon")]
44110#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44111#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44112#[cfg_attr(
44113 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44114 assert_instr(nop)
44115)]
44116#[cfg_attr(
44117 not(target_arch = "arm"),
44118 stable(feature = "neon_intrinsics", since = "1.59.0")
44119)]
44120#[cfg_attr(
44121 target_arch = "arm",
44122 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44123)]
44124pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
44125 unsafe { transmute(a) }
44126}
44127#[doc = "Vector reinterpret cast operation"]
44128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
44129#[inline]
44130#[cfg(target_endian = "big")]
44131#[target_feature(enable = "neon")]
44132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44134#[cfg_attr(
44135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44136 assert_instr(nop)
44137)]
44138#[cfg_attr(
44139 not(target_arch = "arm"),
44140 stable(feature = "neon_intrinsics", since = "1.59.0")
44141)]
44142#[cfg_attr(
44143 target_arch = "arm",
44144 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44145)]
44146pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
44147 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44148 unsafe {
44149 let ret_val: poly8x8_t = transmute(a);
44150 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44151 }
44152}
44153#[doc = "Vector reinterpret cast operation"]
44154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
44155#[inline]
44156#[cfg(target_endian = "little")]
44157#[target_feature(enable = "neon")]
44158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44160#[cfg_attr(
44161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44162 assert_instr(nop)
44163)]
44164#[cfg_attr(
44165 not(target_arch = "arm"),
44166 stable(feature = "neon_intrinsics", since = "1.59.0")
44167)]
44168#[cfg_attr(
44169 target_arch = "arm",
44170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44171)]
44172pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
44173 unsafe { transmute(a) }
44174}
44175#[doc = "Vector reinterpret cast operation"]
44176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
44177#[inline]
44178#[cfg(target_endian = "big")]
44179#[target_feature(enable = "neon")]
44180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44182#[cfg_attr(
44183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44184 assert_instr(nop)
44185)]
44186#[cfg_attr(
44187 not(target_arch = "arm"),
44188 stable(feature = "neon_intrinsics", since = "1.59.0")
44189)]
44190#[cfg_attr(
44191 target_arch = "arm",
44192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44193)]
44194pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
44195 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44196 unsafe {
44197 let ret_val: poly16x4_t = transmute(a);
44198 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44199 }
44200}
44201#[doc = "Vector reinterpret cast operation"]
44202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
44203#[inline]
44204#[cfg(target_endian = "little")]
44205#[target_feature(enable = "neon")]
44206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44208#[cfg_attr(
44209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44210 assert_instr(nop)
44211)]
44212#[cfg_attr(
44213 not(target_arch = "arm"),
44214 stable(feature = "neon_intrinsics", since = "1.59.0")
44215)]
44216#[cfg_attr(
44217 target_arch = "arm",
44218 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44219)]
44220pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
44221 unsafe { transmute(a) }
44222}
44223#[doc = "Vector reinterpret cast operation"]
44224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
44225#[inline]
44226#[cfg(target_endian = "big")]
44227#[target_feature(enable = "neon")]
44228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44230#[cfg_attr(
44231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44232 assert_instr(nop)
44233)]
44234#[cfg_attr(
44235 not(target_arch = "arm"),
44236 stable(feature = "neon_intrinsics", since = "1.59.0")
44237)]
44238#[cfg_attr(
44239 target_arch = "arm",
44240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44241)]
44242pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
44243 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44244 unsafe {
44245 let ret_val: float32x4_t = transmute(a);
44246 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44247 }
44248}
44249#[doc = "Vector reinterpret cast operation"]
44250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
44251#[inline]
44252#[cfg(target_endian = "little")]
44253#[target_feature(enable = "neon")]
44254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44256#[cfg_attr(
44257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44258 assert_instr(nop)
44259)]
44260#[cfg_attr(
44261 not(target_arch = "arm"),
44262 stable(feature = "neon_intrinsics", since = "1.59.0")
44263)]
44264#[cfg_attr(
44265 target_arch = "arm",
44266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44267)]
44268pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
44269 unsafe { transmute(a) }
44270}
44271#[doc = "Vector reinterpret cast operation"]
44272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
44273#[inline]
44274#[cfg(target_endian = "big")]
44275#[target_feature(enable = "neon")]
44276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44278#[cfg_attr(
44279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44280 assert_instr(nop)
44281)]
44282#[cfg_attr(
44283 not(target_arch = "arm"),
44284 stable(feature = "neon_intrinsics", since = "1.59.0")
44285)]
44286#[cfg_attr(
44287 target_arch = "arm",
44288 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44289)]
44290pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
44291 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44292 unsafe {
44293 let ret_val: int8x16_t = transmute(a);
44294 simd_shuffle!(
44295 ret_val,
44296 ret_val,
44297 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44298 )
44299 }
44300}
44301#[doc = "Vector reinterpret cast operation"]
44302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
44303#[inline]
44304#[cfg(target_endian = "little")]
44305#[target_feature(enable = "neon")]
44306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44308#[cfg_attr(
44309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44310 assert_instr(nop)
44311)]
44312#[cfg_attr(
44313 not(target_arch = "arm"),
44314 stable(feature = "neon_intrinsics", since = "1.59.0")
44315)]
44316#[cfg_attr(
44317 target_arch = "arm",
44318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44319)]
44320pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
44321 unsafe { transmute(a) }
44322}
44323#[doc = "Vector reinterpret cast operation"]
44324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
44325#[inline]
44326#[cfg(target_endian = "big")]
44327#[target_feature(enable = "neon")]
44328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44330#[cfg_attr(
44331 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44332 assert_instr(nop)
44333)]
44334#[cfg_attr(
44335 not(target_arch = "arm"),
44336 stable(feature = "neon_intrinsics", since = "1.59.0")
44337)]
44338#[cfg_attr(
44339 target_arch = "arm",
44340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44341)]
44342pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
44343 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44344 unsafe {
44345 let ret_val: int16x8_t = transmute(a);
44346 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44347 }
44348}
44349#[doc = "Vector reinterpret cast operation"]
44350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
44351#[inline]
44352#[cfg(target_endian = "little")]
44353#[target_feature(enable = "neon")]
44354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44356#[cfg_attr(
44357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44358 assert_instr(nop)
44359)]
44360#[cfg_attr(
44361 not(target_arch = "arm"),
44362 stable(feature = "neon_intrinsics", since = "1.59.0")
44363)]
44364#[cfg_attr(
44365 target_arch = "arm",
44366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44367)]
44368pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
44369 unsafe { transmute(a) }
44370}
44371#[doc = "Vector reinterpret cast operation"]
44372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
44373#[inline]
44374#[cfg(target_endian = "big")]
44375#[target_feature(enable = "neon")]
44376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44378#[cfg_attr(
44379 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44380 assert_instr(nop)
44381)]
44382#[cfg_attr(
44383 not(target_arch = "arm"),
44384 stable(feature = "neon_intrinsics", since = "1.59.0")
44385)]
44386#[cfg_attr(
44387 target_arch = "arm",
44388 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44389)]
44390pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
44391 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44392 unsafe {
44393 let ret_val: int32x4_t = transmute(a);
44394 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44395 }
44396}
44397#[doc = "Vector reinterpret cast operation"]
44398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
44399#[inline]
44400#[cfg(target_endian = "little")]
44401#[target_feature(enable = "neon")]
44402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44404#[cfg_attr(
44405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44406 assert_instr(nop)
44407)]
44408#[cfg_attr(
44409 not(target_arch = "arm"),
44410 stable(feature = "neon_intrinsics", since = "1.59.0")
44411)]
44412#[cfg_attr(
44413 target_arch = "arm",
44414 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44415)]
44416pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
44417 unsafe { transmute(a) }
44418}
44419#[doc = "Vector reinterpret cast operation"]
44420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
44421#[inline]
44422#[cfg(target_endian = "big")]
44423#[target_feature(enable = "neon")]
44424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44426#[cfg_attr(
44427 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44428 assert_instr(nop)
44429)]
44430#[cfg_attr(
44431 not(target_arch = "arm"),
44432 stable(feature = "neon_intrinsics", since = "1.59.0")
44433)]
44434#[cfg_attr(
44435 target_arch = "arm",
44436 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44437)]
44438pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
44439 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44440 unsafe {
44441 let ret_val: int64x2_t = transmute(a);
44442 simd_shuffle!(ret_val, ret_val, [1, 0])
44443 }
44444}
44445#[doc = "Vector reinterpret cast operation"]
44446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
44447#[inline]
44448#[cfg(target_endian = "little")]
44449#[target_feature(enable = "neon")]
44450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44452#[cfg_attr(
44453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44454 assert_instr(nop)
44455)]
44456#[cfg_attr(
44457 not(target_arch = "arm"),
44458 stable(feature = "neon_intrinsics", since = "1.59.0")
44459)]
44460#[cfg_attr(
44461 target_arch = "arm",
44462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44463)]
44464pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
44465 unsafe { transmute(a) }
44466}
44467#[doc = "Vector reinterpret cast operation"]
44468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
44469#[inline]
44470#[cfg(target_endian = "big")]
44471#[target_feature(enable = "neon")]
44472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44474#[cfg_attr(
44475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44476 assert_instr(nop)
44477)]
44478#[cfg_attr(
44479 not(target_arch = "arm"),
44480 stable(feature = "neon_intrinsics", since = "1.59.0")
44481)]
44482#[cfg_attr(
44483 target_arch = "arm",
44484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44485)]
44486pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
44487 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44488 unsafe {
44489 let ret_val: uint8x16_t = transmute(a);
44490 simd_shuffle!(
44491 ret_val,
44492 ret_val,
44493 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44494 )
44495 }
44496}
44497#[doc = "Vector reinterpret cast operation"]
44498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
44499#[inline]
44500#[cfg(target_endian = "little")]
44501#[target_feature(enable = "neon")]
44502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44504#[cfg_attr(
44505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44506 assert_instr(nop)
44507)]
44508#[cfg_attr(
44509 not(target_arch = "arm"),
44510 stable(feature = "neon_intrinsics", since = "1.59.0")
44511)]
44512#[cfg_attr(
44513 target_arch = "arm",
44514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44515)]
44516pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
44517 unsafe { transmute(a) }
44518}
44519#[doc = "Vector reinterpret cast operation"]
44520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
44521#[inline]
44522#[cfg(target_endian = "big")]
44523#[target_feature(enable = "neon")]
44524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44526#[cfg_attr(
44527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44528 assert_instr(nop)
44529)]
44530#[cfg_attr(
44531 not(target_arch = "arm"),
44532 stable(feature = "neon_intrinsics", since = "1.59.0")
44533)]
44534#[cfg_attr(
44535 target_arch = "arm",
44536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44537)]
44538pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
44539 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44540 unsafe {
44541 let ret_val: uint32x4_t = transmute(a);
44542 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44543 }
44544}
44545#[doc = "Vector reinterpret cast operation"]
44546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
44547#[inline]
44548#[cfg(target_endian = "little")]
44549#[target_feature(enable = "neon")]
44550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44552#[cfg_attr(
44553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44554 assert_instr(nop)
44555)]
44556#[cfg_attr(
44557 not(target_arch = "arm"),
44558 stable(feature = "neon_intrinsics", since = "1.59.0")
44559)]
44560#[cfg_attr(
44561 target_arch = "arm",
44562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44563)]
44564pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
44565 unsafe { transmute(a) }
44566}
44567#[doc = "Vector reinterpret cast operation"]
44568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
44569#[inline]
44570#[cfg(target_endian = "big")]
44571#[target_feature(enable = "neon")]
44572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44574#[cfg_attr(
44575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44576 assert_instr(nop)
44577)]
44578#[cfg_attr(
44579 not(target_arch = "arm"),
44580 stable(feature = "neon_intrinsics", since = "1.59.0")
44581)]
44582#[cfg_attr(
44583 target_arch = "arm",
44584 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44585)]
44586pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
44587 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44588 unsafe {
44589 let ret_val: uint64x2_t = transmute(a);
44590 simd_shuffle!(ret_val, ret_val, [1, 0])
44591 }
44592}
44593#[doc = "Vector reinterpret cast operation"]
44594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
44595#[inline]
44596#[cfg(target_endian = "little")]
44597#[target_feature(enable = "neon")]
44598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44600#[cfg_attr(
44601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44602 assert_instr(nop)
44603)]
44604#[cfg_attr(
44605 not(target_arch = "arm"),
44606 stable(feature = "neon_intrinsics", since = "1.59.0")
44607)]
44608#[cfg_attr(
44609 target_arch = "arm",
44610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44611)]
44612pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
44613 unsafe { transmute(a) }
44614}
44615#[doc = "Vector reinterpret cast operation"]
44616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
44617#[inline]
44618#[cfg(target_endian = "big")]
44619#[target_feature(enable = "neon")]
44620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44622#[cfg_attr(
44623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44624 assert_instr(nop)
44625)]
44626#[cfg_attr(
44627 not(target_arch = "arm"),
44628 stable(feature = "neon_intrinsics", since = "1.59.0")
44629)]
44630#[cfg_attr(
44631 target_arch = "arm",
44632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44633)]
44634pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
44635 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44636 unsafe {
44637 let ret_val: poly8x16_t = transmute(a);
44638 simd_shuffle!(
44639 ret_val,
44640 ret_val,
44641 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44642 )
44643 }
44644}
44645#[doc = "Vector reinterpret cast operation"]
44646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
44647#[inline]
44648#[cfg(target_endian = "little")]
44649#[target_feature(enable = "neon")]
44650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44652#[cfg_attr(
44653 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44654 assert_instr(nop)
44655)]
44656#[cfg_attr(
44657 not(target_arch = "arm"),
44658 stable(feature = "neon_intrinsics", since = "1.59.0")
44659)]
44660#[cfg_attr(
44661 target_arch = "arm",
44662 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44663)]
44664pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
44665 unsafe { transmute(a) }
44666}
44667#[doc = "Vector reinterpret cast operation"]
44668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
44669#[inline]
44670#[cfg(target_endian = "big")]
44671#[target_feature(enable = "neon")]
44672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44674#[cfg_attr(
44675 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44676 assert_instr(nop)
44677)]
44678#[cfg_attr(
44679 not(target_arch = "arm"),
44680 stable(feature = "neon_intrinsics", since = "1.59.0")
44681)]
44682#[cfg_attr(
44683 target_arch = "arm",
44684 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44685)]
44686pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
44687 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44688 unsafe {
44689 let ret_val: poly16x8_t = transmute(a);
44690 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44691 }
44692}
44693#[doc = "Vector reinterpret cast operation"]
44694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
44695#[inline]
44696#[cfg(target_endian = "little")]
44697#[target_feature(enable = "neon")]
44698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44700#[cfg_attr(
44701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44702 assert_instr(nop)
44703)]
44704#[cfg_attr(
44705 not(target_arch = "arm"),
44706 stable(feature = "neon_intrinsics", since = "1.59.0")
44707)]
44708#[cfg_attr(
44709 target_arch = "arm",
44710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44711)]
44712pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
44713 unsafe { transmute(a) }
44714}
44715#[doc = "Vector reinterpret cast operation"]
44716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
44717#[inline]
44718#[cfg(target_endian = "big")]
44719#[target_feature(enable = "neon")]
44720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44721#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44722#[cfg_attr(
44723 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44724 assert_instr(nop)
44725)]
44726#[cfg_attr(
44727 not(target_arch = "arm"),
44728 stable(feature = "neon_intrinsics", since = "1.59.0")
44729)]
44730#[cfg_attr(
44731 target_arch = "arm",
44732 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44733)]
44734pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
44735 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44736 unsafe {
44737 let ret_val: float32x2_t = transmute(a);
44738 simd_shuffle!(ret_val, ret_val, [1, 0])
44739 }
44740}
44741#[doc = "Vector reinterpret cast operation"]
44742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
44743#[inline]
44744#[cfg(target_endian = "little")]
44745#[target_feature(enable = "neon")]
44746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44748#[cfg_attr(
44749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44750 assert_instr(nop)
44751)]
44752#[cfg_attr(
44753 not(target_arch = "arm"),
44754 stable(feature = "neon_intrinsics", since = "1.59.0")
44755)]
44756#[cfg_attr(
44757 target_arch = "arm",
44758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44759)]
44760pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
44761 unsafe { transmute(a) }
44762}
44763#[doc = "Vector reinterpret cast operation"]
44764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
44765#[inline]
44766#[cfg(target_endian = "big")]
44767#[target_feature(enable = "neon")]
44768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44770#[cfg_attr(
44771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44772 assert_instr(nop)
44773)]
44774#[cfg_attr(
44775 not(target_arch = "arm"),
44776 stable(feature = "neon_intrinsics", since = "1.59.0")
44777)]
44778#[cfg_attr(
44779 target_arch = "arm",
44780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44781)]
44782pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
44783 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44784 unsafe {
44785 let ret_val: int8x8_t = transmute(a);
44786 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44787 }
44788}
44789#[doc = "Vector reinterpret cast operation"]
44790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
44791#[inline]
44792#[cfg(target_endian = "little")]
44793#[target_feature(enable = "neon")]
44794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44796#[cfg_attr(
44797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44798 assert_instr(nop)
44799)]
44800#[cfg_attr(
44801 not(target_arch = "arm"),
44802 stable(feature = "neon_intrinsics", since = "1.59.0")
44803)]
44804#[cfg_attr(
44805 target_arch = "arm",
44806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44807)]
44808pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
44809 unsafe { transmute(a) }
44810}
44811#[doc = "Vector reinterpret cast operation"]
44812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
44813#[inline]
44814#[cfg(target_endian = "big")]
44815#[target_feature(enable = "neon")]
44816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44817#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44818#[cfg_attr(
44819 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44820 assert_instr(nop)
44821)]
44822#[cfg_attr(
44823 not(target_arch = "arm"),
44824 stable(feature = "neon_intrinsics", since = "1.59.0")
44825)]
44826#[cfg_attr(
44827 target_arch = "arm",
44828 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44829)]
44830pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
44831 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44832 unsafe {
44833 let ret_val: int16x4_t = transmute(a);
44834 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44835 }
44836}
44837#[doc = "Vector reinterpret cast operation"]
44838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
44839#[inline]
44840#[cfg(target_endian = "little")]
44841#[target_feature(enable = "neon")]
44842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44844#[cfg_attr(
44845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44846 assert_instr(nop)
44847)]
44848#[cfg_attr(
44849 not(target_arch = "arm"),
44850 stable(feature = "neon_intrinsics", since = "1.59.0")
44851)]
44852#[cfg_attr(
44853 target_arch = "arm",
44854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44855)]
44856pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
44857 unsafe { transmute(a) }
44858}
44859#[doc = "Vector reinterpret cast operation"]
44860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
44861#[inline]
44862#[cfg(target_endian = "big")]
44863#[target_feature(enable = "neon")]
44864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44866#[cfg_attr(
44867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44868 assert_instr(nop)
44869)]
44870#[cfg_attr(
44871 not(target_arch = "arm"),
44872 stable(feature = "neon_intrinsics", since = "1.59.0")
44873)]
44874#[cfg_attr(
44875 target_arch = "arm",
44876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44877)]
44878pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
44879 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44880 unsafe {
44881 let ret_val: int32x2_t = transmute(a);
44882 simd_shuffle!(ret_val, ret_val, [1, 0])
44883 }
44884}
44885#[doc = "Vector reinterpret cast operation"]
44886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
44887#[inline]
44888#[cfg(target_endian = "little")]
44889#[target_feature(enable = "neon")]
44890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44892#[cfg_attr(
44893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44894 assert_instr(nop)
44895)]
44896#[cfg_attr(
44897 not(target_arch = "arm"),
44898 stable(feature = "neon_intrinsics", since = "1.59.0")
44899)]
44900#[cfg_attr(
44901 target_arch = "arm",
44902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44903)]
44904pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
44905 unsafe { transmute(a) }
44906}
44907#[doc = "Vector reinterpret cast operation"]
44908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
44909#[inline]
44910#[cfg(target_endian = "big")]
44911#[target_feature(enable = "neon")]
44912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44914#[cfg_attr(
44915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44916 assert_instr(nop)
44917)]
44918#[cfg_attr(
44919 not(target_arch = "arm"),
44920 stable(feature = "neon_intrinsics", since = "1.59.0")
44921)]
44922#[cfg_attr(
44923 target_arch = "arm",
44924 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44925)]
44926pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
44927 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44928 unsafe { transmute(a) }
44929}
44930#[doc = "Vector reinterpret cast operation"]
44931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
44932#[inline]
44933#[cfg(target_endian = "little")]
44934#[target_feature(enable = "neon")]
44935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44937#[cfg_attr(
44938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44939 assert_instr(nop)
44940)]
44941#[cfg_attr(
44942 not(target_arch = "arm"),
44943 stable(feature = "neon_intrinsics", since = "1.59.0")
44944)]
44945#[cfg_attr(
44946 target_arch = "arm",
44947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44948)]
44949pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
44950 unsafe { transmute(a) }
44951}
44952#[doc = "Vector reinterpret cast operation"]
44953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
44954#[inline]
44955#[cfg(target_endian = "big")]
44956#[target_feature(enable = "neon")]
44957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44959#[cfg_attr(
44960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44961 assert_instr(nop)
44962)]
44963#[cfg_attr(
44964 not(target_arch = "arm"),
44965 stable(feature = "neon_intrinsics", since = "1.59.0")
44966)]
44967#[cfg_attr(
44968 target_arch = "arm",
44969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44970)]
44971pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
44972 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44973 unsafe {
44974 let ret_val: uint8x8_t = transmute(a);
44975 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44976 }
44977}
44978#[doc = "Vector reinterpret cast operation"]
44979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
44980#[inline]
44981#[cfg(target_endian = "little")]
44982#[target_feature(enable = "neon")]
44983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44985#[cfg_attr(
44986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44987 assert_instr(nop)
44988)]
44989#[cfg_attr(
44990 not(target_arch = "arm"),
44991 stable(feature = "neon_intrinsics", since = "1.59.0")
44992)]
44993#[cfg_attr(
44994 target_arch = "arm",
44995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44996)]
44997pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
44998 unsafe { transmute(a) }
44999}
45000#[doc = "Vector reinterpret cast operation"]
45001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
45002#[inline]
45003#[cfg(target_endian = "big")]
45004#[target_feature(enable = "neon")]
45005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45007#[cfg_attr(
45008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45009 assert_instr(nop)
45010)]
45011#[cfg_attr(
45012 not(target_arch = "arm"),
45013 stable(feature = "neon_intrinsics", since = "1.59.0")
45014)]
45015#[cfg_attr(
45016 target_arch = "arm",
45017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45018)]
45019pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
45020 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
45021 unsafe {
45022 let ret_val: uint16x4_t = transmute(a);
45023 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45024 }
45025}
45026#[doc = "Vector reinterpret cast operation"]
45027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
45028#[inline]
45029#[cfg(target_endian = "little")]
45030#[target_feature(enable = "neon")]
45031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45033#[cfg_attr(
45034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45035 assert_instr(nop)
45036)]
45037#[cfg_attr(
45038 not(target_arch = "arm"),
45039 stable(feature = "neon_intrinsics", since = "1.59.0")
45040)]
45041#[cfg_attr(
45042 target_arch = "arm",
45043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45044)]
45045pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
45046 unsafe { transmute(a) }
45047}
45048#[doc = "Vector reinterpret cast operation"]
45049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
45050#[inline]
45051#[cfg(target_endian = "big")]
45052#[target_feature(enable = "neon")]
45053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45055#[cfg_attr(
45056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45057 assert_instr(nop)
45058)]
45059#[cfg_attr(
45060 not(target_arch = "arm"),
45061 stable(feature = "neon_intrinsics", since = "1.59.0")
45062)]
45063#[cfg_attr(
45064 target_arch = "arm",
45065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45066)]
45067pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
45068 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
45069 unsafe { transmute(a) }
45070}
45071#[doc = "Vector reinterpret cast operation"]
45072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
45073#[inline]
45074#[cfg(target_endian = "little")]
45075#[target_feature(enable = "neon")]
45076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45077#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45078#[cfg_attr(
45079 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45080 assert_instr(nop)
45081)]
45082#[cfg_attr(
45083 not(target_arch = "arm"),
45084 stable(feature = "neon_intrinsics", since = "1.59.0")
45085)]
45086#[cfg_attr(
45087 target_arch = "arm",
45088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45089)]
45090pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
45091 unsafe { transmute(a) }
45092}
45093#[doc = "Vector reinterpret cast operation"]
45094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
45095#[inline]
45096#[cfg(target_endian = "big")]
45097#[target_feature(enable = "neon")]
45098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45100#[cfg_attr(
45101 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45102 assert_instr(nop)
45103)]
45104#[cfg_attr(
45105 not(target_arch = "arm"),
45106 stable(feature = "neon_intrinsics", since = "1.59.0")
45107)]
45108#[cfg_attr(
45109 target_arch = "arm",
45110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45111)]
45112pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
45113 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
45114 unsafe {
45115 let ret_val: poly8x8_t = transmute(a);
45116 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45117 }
45118}
45119#[doc = "Vector reinterpret cast operation"]
45120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
45121#[inline]
45122#[cfg(target_endian = "little")]
45123#[target_feature(enable = "neon")]
45124#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45125#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45126#[cfg_attr(
45127 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45128 assert_instr(nop)
45129)]
45130#[cfg_attr(
45131 not(target_arch = "arm"),
45132 stable(feature = "neon_intrinsics", since = "1.59.0")
45133)]
45134#[cfg_attr(
45135 target_arch = "arm",
45136 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45137)]
45138pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
45139 unsafe { transmute(a) }
45140}
45141#[doc = "Vector reinterpret cast operation"]
45142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
45143#[inline]
45144#[cfg(target_endian = "big")]
45145#[target_feature(enable = "neon")]
45146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45148#[cfg_attr(
45149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45150 assert_instr(nop)
45151)]
45152#[cfg_attr(
45153 not(target_arch = "arm"),
45154 stable(feature = "neon_intrinsics", since = "1.59.0")
45155)]
45156#[cfg_attr(
45157 target_arch = "arm",
45158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45159)]
45160pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
45161 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
45162 unsafe {
45163 let ret_val: poly16x4_t = transmute(a);
45164 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45165 }
45166}
45167#[doc = "Vector reinterpret cast operation"]
45168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
45169#[inline]
45170#[cfg(target_endian = "little")]
45171#[target_feature(enable = "neon")]
45172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45174#[cfg_attr(
45175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45176 assert_instr(nop)
45177)]
45178#[cfg_attr(
45179 not(target_arch = "arm"),
45180 stable(feature = "neon_intrinsics", since = "1.59.0")
45181)]
45182#[cfg_attr(
45183 target_arch = "arm",
45184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45185)]
45186pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
45187 unsafe { transmute(a) }
45188}
45189#[doc = "Vector reinterpret cast operation"]
45190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
45191#[inline]
45192#[cfg(target_endian = "big")]
45193#[target_feature(enable = "neon")]
45194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45196#[cfg_attr(
45197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45198 assert_instr(nop)
45199)]
45200#[cfg_attr(
45201 not(target_arch = "arm"),
45202 stable(feature = "neon_intrinsics", since = "1.59.0")
45203)]
45204#[cfg_attr(
45205 target_arch = "arm",
45206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45207)]
45208pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
45209 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45210 unsafe {
45211 let ret_val: float32x4_t = transmute(a);
45212 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45213 }
45214}
45215#[doc = "Vector reinterpret cast operation"]
45216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
45217#[inline]
45218#[cfg(target_endian = "little")]
45219#[target_feature(enable = "neon")]
45220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45222#[cfg_attr(
45223 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45224 assert_instr(nop)
45225)]
45226#[cfg_attr(
45227 not(target_arch = "arm"),
45228 stable(feature = "neon_intrinsics", since = "1.59.0")
45229)]
45230#[cfg_attr(
45231 target_arch = "arm",
45232 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45233)]
45234pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
45235 unsafe { transmute(a) }
45236}
45237#[doc = "Vector reinterpret cast operation"]
45238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
45239#[inline]
45240#[cfg(target_endian = "big")]
45241#[target_feature(enable = "neon")]
45242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45244#[cfg_attr(
45245 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45246 assert_instr(nop)
45247)]
45248#[cfg_attr(
45249 not(target_arch = "arm"),
45250 stable(feature = "neon_intrinsics", since = "1.59.0")
45251)]
45252#[cfg_attr(
45253 target_arch = "arm",
45254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45255)]
45256pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
45257 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45258 unsafe {
45259 let ret_val: int8x16_t = transmute(a);
45260 simd_shuffle!(
45261 ret_val,
45262 ret_val,
45263 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45264 )
45265 }
45266}
45267#[doc = "Vector reinterpret cast operation"]
45268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
45269#[inline]
45270#[cfg(target_endian = "little")]
45271#[target_feature(enable = "neon")]
45272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45273#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45274#[cfg_attr(
45275 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45276 assert_instr(nop)
45277)]
45278#[cfg_attr(
45279 not(target_arch = "arm"),
45280 stable(feature = "neon_intrinsics", since = "1.59.0")
45281)]
45282#[cfg_attr(
45283 target_arch = "arm",
45284 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45285)]
45286pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
45287 unsafe { transmute(a) }
45288}
45289#[doc = "Vector reinterpret cast operation"]
45290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
45291#[inline]
45292#[cfg(target_endian = "big")]
45293#[target_feature(enable = "neon")]
45294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45296#[cfg_attr(
45297 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45298 assert_instr(nop)
45299)]
45300#[cfg_attr(
45301 not(target_arch = "arm"),
45302 stable(feature = "neon_intrinsics", since = "1.59.0")
45303)]
45304#[cfg_attr(
45305 target_arch = "arm",
45306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45307)]
45308pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
45309 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45310 unsafe {
45311 let ret_val: int16x8_t = transmute(a);
45312 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45313 }
45314}
45315#[doc = "Vector reinterpret cast operation"]
45316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
45317#[inline]
45318#[cfg(target_endian = "little")]
45319#[target_feature(enable = "neon")]
45320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45322#[cfg_attr(
45323 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45324 assert_instr(nop)
45325)]
45326#[cfg_attr(
45327 not(target_arch = "arm"),
45328 stable(feature = "neon_intrinsics", since = "1.59.0")
45329)]
45330#[cfg_attr(
45331 target_arch = "arm",
45332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45333)]
45334pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
45335 unsafe { transmute(a) }
45336}
45337#[doc = "Vector reinterpret cast operation"]
45338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
45339#[inline]
45340#[cfg(target_endian = "big")]
45341#[target_feature(enable = "neon")]
45342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45343#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45344#[cfg_attr(
45345 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45346 assert_instr(nop)
45347)]
45348#[cfg_attr(
45349 not(target_arch = "arm"),
45350 stable(feature = "neon_intrinsics", since = "1.59.0")
45351)]
45352#[cfg_attr(
45353 target_arch = "arm",
45354 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45355)]
45356pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
45357 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45358 unsafe {
45359 let ret_val: int32x4_t = transmute(a);
45360 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45361 }
45362}
45363#[doc = "Vector reinterpret cast operation"]
45364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
45365#[inline]
45366#[cfg(target_endian = "little")]
45367#[target_feature(enable = "neon")]
45368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45370#[cfg_attr(
45371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45372 assert_instr(nop)
45373)]
45374#[cfg_attr(
45375 not(target_arch = "arm"),
45376 stable(feature = "neon_intrinsics", since = "1.59.0")
45377)]
45378#[cfg_attr(
45379 target_arch = "arm",
45380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45381)]
45382pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
45383 unsafe { transmute(a) }
45384}
45385#[doc = "Vector reinterpret cast operation"]
45386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
45387#[inline]
45388#[cfg(target_endian = "big")]
45389#[target_feature(enable = "neon")]
45390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45392#[cfg_attr(
45393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45394 assert_instr(nop)
45395)]
45396#[cfg_attr(
45397 not(target_arch = "arm"),
45398 stable(feature = "neon_intrinsics", since = "1.59.0")
45399)]
45400#[cfg_attr(
45401 target_arch = "arm",
45402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45403)]
45404pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
45405 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45406 unsafe {
45407 let ret_val: int64x2_t = transmute(a);
45408 simd_shuffle!(ret_val, ret_val, [1, 0])
45409 }
45410}
45411#[doc = "Vector reinterpret cast operation"]
45412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
45413#[inline]
45414#[cfg(target_endian = "little")]
45415#[target_feature(enable = "neon")]
45416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45418#[cfg_attr(
45419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45420 assert_instr(nop)
45421)]
45422#[cfg_attr(
45423 not(target_arch = "arm"),
45424 stable(feature = "neon_intrinsics", since = "1.59.0")
45425)]
45426#[cfg_attr(
45427 target_arch = "arm",
45428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45429)]
45430pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
45431 unsafe { transmute(a) }
45432}
45433#[doc = "Vector reinterpret cast operation"]
45434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
45435#[inline]
45436#[cfg(target_endian = "big")]
45437#[target_feature(enable = "neon")]
45438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45440#[cfg_attr(
45441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45442 assert_instr(nop)
45443)]
45444#[cfg_attr(
45445 not(target_arch = "arm"),
45446 stable(feature = "neon_intrinsics", since = "1.59.0")
45447)]
45448#[cfg_attr(
45449 target_arch = "arm",
45450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45451)]
45452pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
45453 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45454 unsafe {
45455 let ret_val: uint8x16_t = transmute(a);
45456 simd_shuffle!(
45457 ret_val,
45458 ret_val,
45459 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45460 )
45461 }
45462}
45463#[doc = "Vector reinterpret cast operation"]
45464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
45465#[inline]
45466#[cfg(target_endian = "little")]
45467#[target_feature(enable = "neon")]
45468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45469#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45470#[cfg_attr(
45471 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45472 assert_instr(nop)
45473)]
45474#[cfg_attr(
45475 not(target_arch = "arm"),
45476 stable(feature = "neon_intrinsics", since = "1.59.0")
45477)]
45478#[cfg_attr(
45479 target_arch = "arm",
45480 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45481)]
45482pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
45483 unsafe { transmute(a) }
45484}
45485#[doc = "Vector reinterpret cast operation"]
45486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
45487#[inline]
45488#[cfg(target_endian = "big")]
45489#[target_feature(enable = "neon")]
45490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45492#[cfg_attr(
45493 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45494 assert_instr(nop)
45495)]
45496#[cfg_attr(
45497 not(target_arch = "arm"),
45498 stable(feature = "neon_intrinsics", since = "1.59.0")
45499)]
45500#[cfg_attr(
45501 target_arch = "arm",
45502 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45503)]
45504pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
45505 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45506 unsafe {
45507 let ret_val: uint16x8_t = transmute(a);
45508 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45509 }
45510}
45511#[doc = "Vector reinterpret cast operation"]
45512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
45513#[inline]
45514#[cfg(target_endian = "little")]
45515#[target_feature(enable = "neon")]
45516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45518#[cfg_attr(
45519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45520 assert_instr(nop)
45521)]
45522#[cfg_attr(
45523 not(target_arch = "arm"),
45524 stable(feature = "neon_intrinsics", since = "1.59.0")
45525)]
45526#[cfg_attr(
45527 target_arch = "arm",
45528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45529)]
45530pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
45531 unsafe { transmute(a) }
45532}
45533#[doc = "Vector reinterpret cast operation"]
45534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
45535#[inline]
45536#[cfg(target_endian = "big")]
45537#[target_feature(enable = "neon")]
45538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45540#[cfg_attr(
45541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45542 assert_instr(nop)
45543)]
45544#[cfg_attr(
45545 not(target_arch = "arm"),
45546 stable(feature = "neon_intrinsics", since = "1.59.0")
45547)]
45548#[cfg_attr(
45549 target_arch = "arm",
45550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45551)]
45552pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
45553 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45554 unsafe {
45555 let ret_val: uint64x2_t = transmute(a);
45556 simd_shuffle!(ret_val, ret_val, [1, 0])
45557 }
45558}
45559#[doc = "Vector reinterpret cast operation"]
45560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
45561#[inline]
45562#[cfg(target_endian = "little")]
45563#[target_feature(enable = "neon")]
45564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45566#[cfg_attr(
45567 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45568 assert_instr(nop)
45569)]
45570#[cfg_attr(
45571 not(target_arch = "arm"),
45572 stable(feature = "neon_intrinsics", since = "1.59.0")
45573)]
45574#[cfg_attr(
45575 target_arch = "arm",
45576 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45577)]
45578pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
45579 unsafe { transmute(a) }
45580}
45581#[doc = "Vector reinterpret cast operation"]
45582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
45583#[inline]
45584#[cfg(target_endian = "big")]
45585#[target_feature(enable = "neon")]
45586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45588#[cfg_attr(
45589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45590 assert_instr(nop)
45591)]
45592#[cfg_attr(
45593 not(target_arch = "arm"),
45594 stable(feature = "neon_intrinsics", since = "1.59.0")
45595)]
45596#[cfg_attr(
45597 target_arch = "arm",
45598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45599)]
45600pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
45601 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45602 unsafe {
45603 let ret_val: poly8x16_t = transmute(a);
45604 simd_shuffle!(
45605 ret_val,
45606 ret_val,
45607 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45608 )
45609 }
45610}
45611#[doc = "Vector reinterpret cast operation"]
45612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
45613#[inline]
45614#[cfg(target_endian = "little")]
45615#[target_feature(enable = "neon")]
45616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45618#[cfg_attr(
45619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45620 assert_instr(nop)
45621)]
45622#[cfg_attr(
45623 not(target_arch = "arm"),
45624 stable(feature = "neon_intrinsics", since = "1.59.0")
45625)]
45626#[cfg_attr(
45627 target_arch = "arm",
45628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45629)]
45630pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
45631 unsafe { transmute(a) }
45632}
45633#[doc = "Vector reinterpret cast operation"]
45634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
45635#[inline]
45636#[cfg(target_endian = "big")]
45637#[target_feature(enable = "neon")]
45638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45640#[cfg_attr(
45641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45642 assert_instr(nop)
45643)]
45644#[cfg_attr(
45645 not(target_arch = "arm"),
45646 stable(feature = "neon_intrinsics", since = "1.59.0")
45647)]
45648#[cfg_attr(
45649 target_arch = "arm",
45650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45651)]
45652pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
45653 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45654 unsafe {
45655 let ret_val: poly16x8_t = transmute(a);
45656 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45657 }
45658}
45659#[doc = "Vector reinterpret cast operation"]
45660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
45661#[inline]
45662#[cfg(target_endian = "little")]
45663#[target_feature(enable = "neon")]
45664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45666#[cfg_attr(
45667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45668 assert_instr(nop)
45669)]
45670#[cfg_attr(
45671 not(target_arch = "arm"),
45672 stable(feature = "neon_intrinsics", since = "1.59.0")
45673)]
45674#[cfg_attr(
45675 target_arch = "arm",
45676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45677)]
45678pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
45679 unsafe { transmute(a) }
45680}
45681#[doc = "Vector reinterpret cast operation"]
45682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
45683#[inline]
45684#[cfg(target_endian = "big")]
45685#[target_feature(enable = "neon")]
45686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45688#[cfg_attr(
45689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45690 assert_instr(nop)
45691)]
45692#[cfg_attr(
45693 not(target_arch = "arm"),
45694 stable(feature = "neon_intrinsics", since = "1.59.0")
45695)]
45696#[cfg_attr(
45697 target_arch = "arm",
45698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45699)]
45700pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
45701 unsafe {
45702 let ret_val: float32x2_t = transmute(a);
45703 simd_shuffle!(ret_val, ret_val, [1, 0])
45704 }
45705}
45706#[doc = "Vector reinterpret cast operation"]
45707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
45708#[inline]
45709#[cfg(target_endian = "little")]
45710#[target_feature(enable = "neon")]
45711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45713#[cfg_attr(
45714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45715 assert_instr(nop)
45716)]
45717#[cfg_attr(
45718 not(target_arch = "arm"),
45719 stable(feature = "neon_intrinsics", since = "1.59.0")
45720)]
45721#[cfg_attr(
45722 target_arch = "arm",
45723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45724)]
45725pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
45726 unsafe { transmute(a) }
45727}
45728#[doc = "Vector reinterpret cast operation"]
45729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
45730#[inline]
45731#[cfg(target_endian = "big")]
45732#[target_feature(enable = "neon")]
45733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45735#[cfg_attr(
45736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45737 assert_instr(nop)
45738)]
45739#[cfg_attr(
45740 not(target_arch = "arm"),
45741 stable(feature = "neon_intrinsics", since = "1.59.0")
45742)]
45743#[cfg_attr(
45744 target_arch = "arm",
45745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45746)]
45747pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
45748 unsafe {
45749 let ret_val: int8x8_t = transmute(a);
45750 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45751 }
45752}
45753#[doc = "Vector reinterpret cast operation"]
45754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
45755#[inline]
45756#[cfg(target_endian = "little")]
45757#[target_feature(enable = "neon")]
45758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45760#[cfg_attr(
45761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45762 assert_instr(nop)
45763)]
45764#[cfg_attr(
45765 not(target_arch = "arm"),
45766 stable(feature = "neon_intrinsics", since = "1.59.0")
45767)]
45768#[cfg_attr(
45769 target_arch = "arm",
45770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45771)]
45772pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
45773 unsafe { transmute(a) }
45774}
45775#[doc = "Vector reinterpret cast operation"]
45776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
45777#[inline]
45778#[cfg(target_endian = "big")]
45779#[target_feature(enable = "neon")]
45780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45782#[cfg_attr(
45783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45784 assert_instr(nop)
45785)]
45786#[cfg_attr(
45787 not(target_arch = "arm"),
45788 stable(feature = "neon_intrinsics", since = "1.59.0")
45789)]
45790#[cfg_attr(
45791 target_arch = "arm",
45792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45793)]
45794pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
45795 unsafe {
45796 let ret_val: int16x4_t = transmute(a);
45797 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45798 }
45799}
45800#[doc = "Vector reinterpret cast operation"]
45801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
45802#[inline]
45803#[cfg(target_endian = "little")]
45804#[target_feature(enable = "neon")]
45805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45807#[cfg_attr(
45808 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45809 assert_instr(nop)
45810)]
45811#[cfg_attr(
45812 not(target_arch = "arm"),
45813 stable(feature = "neon_intrinsics", since = "1.59.0")
45814)]
45815#[cfg_attr(
45816 target_arch = "arm",
45817 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45818)]
45819pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
45820 unsafe { transmute(a) }
45821}
45822#[doc = "Vector reinterpret cast operation"]
45823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
45824#[inline]
45825#[cfg(target_endian = "big")]
45826#[target_feature(enable = "neon")]
45827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45829#[cfg_attr(
45830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45831 assert_instr(nop)
45832)]
45833#[cfg_attr(
45834 not(target_arch = "arm"),
45835 stable(feature = "neon_intrinsics", since = "1.59.0")
45836)]
45837#[cfg_attr(
45838 target_arch = "arm",
45839 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45840)]
45841pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
45842 unsafe {
45843 let ret_val: int32x2_t = transmute(a);
45844 simd_shuffle!(ret_val, ret_val, [1, 0])
45845 }
45846}
45847#[doc = "Vector reinterpret cast operation"]
45848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
45849#[inline]
45850#[target_feature(enable = "neon")]
45851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45853#[cfg_attr(
45854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45855 assert_instr(nop)
45856)]
45857#[cfg_attr(
45858 not(target_arch = "arm"),
45859 stable(feature = "neon_intrinsics", since = "1.59.0")
45860)]
45861#[cfg_attr(
45862 target_arch = "arm",
45863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45864)]
45865pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
45866 unsafe { transmute(a) }
45867}
45868#[doc = "Vector reinterpret cast operation"]
45869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
45870#[inline]
45871#[cfg(target_endian = "little")]
45872#[target_feature(enable = "neon")]
45873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45875#[cfg_attr(
45876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45877 assert_instr(nop)
45878)]
45879#[cfg_attr(
45880 not(target_arch = "arm"),
45881 stable(feature = "neon_intrinsics", since = "1.59.0")
45882)]
45883#[cfg_attr(
45884 target_arch = "arm",
45885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45886)]
45887pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
45888 unsafe { transmute(a) }
45889}
45890#[doc = "Vector reinterpret cast operation"]
45891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
45892#[inline]
45893#[cfg(target_endian = "big")]
45894#[target_feature(enable = "neon")]
45895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45897#[cfg_attr(
45898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45899 assert_instr(nop)
45900)]
45901#[cfg_attr(
45902 not(target_arch = "arm"),
45903 stable(feature = "neon_intrinsics", since = "1.59.0")
45904)]
45905#[cfg_attr(
45906 target_arch = "arm",
45907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45908)]
45909pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
45910 unsafe {
45911 let ret_val: uint8x8_t = transmute(a);
45912 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45913 }
45914}
45915#[doc = "Vector reinterpret cast operation"]
45916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
45917#[inline]
45918#[cfg(target_endian = "little")]
45919#[target_feature(enable = "neon")]
45920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45921#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45922#[cfg_attr(
45923 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45924 assert_instr(nop)
45925)]
45926#[cfg_attr(
45927 not(target_arch = "arm"),
45928 stable(feature = "neon_intrinsics", since = "1.59.0")
45929)]
45930#[cfg_attr(
45931 target_arch = "arm",
45932 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45933)]
45934pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
45935 unsafe { transmute(a) }
45936}
45937#[doc = "Vector reinterpret cast operation"]
45938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
45939#[inline]
45940#[cfg(target_endian = "big")]
45941#[target_feature(enable = "neon")]
45942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45944#[cfg_attr(
45945 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45946 assert_instr(nop)
45947)]
45948#[cfg_attr(
45949 not(target_arch = "arm"),
45950 stable(feature = "neon_intrinsics", since = "1.59.0")
45951)]
45952#[cfg_attr(
45953 target_arch = "arm",
45954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45955)]
45956pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
45957 unsafe {
45958 let ret_val: uint16x4_t = transmute(a);
45959 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45960 }
45961}
45962#[doc = "Vector reinterpret cast operation"]
45963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
45964#[inline]
45965#[cfg(target_endian = "little")]
45966#[target_feature(enable = "neon")]
45967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45969#[cfg_attr(
45970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45971 assert_instr(nop)
45972)]
45973#[cfg_attr(
45974 not(target_arch = "arm"),
45975 stable(feature = "neon_intrinsics", since = "1.59.0")
45976)]
45977#[cfg_attr(
45978 target_arch = "arm",
45979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45980)]
45981pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
45982 unsafe { transmute(a) }
45983}
45984#[doc = "Vector reinterpret cast operation"]
45985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
45986#[inline]
45987#[cfg(target_endian = "big")]
45988#[target_feature(enable = "neon")]
45989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45991#[cfg_attr(
45992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45993 assert_instr(nop)
45994)]
45995#[cfg_attr(
45996 not(target_arch = "arm"),
45997 stable(feature = "neon_intrinsics", since = "1.59.0")
45998)]
45999#[cfg_attr(
46000 target_arch = "arm",
46001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46002)]
46003pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
46004 unsafe {
46005 let ret_val: uint32x2_t = transmute(a);
46006 simd_shuffle!(ret_val, ret_val, [1, 0])
46007 }
46008}
46009#[doc = "Vector reinterpret cast operation"]
46010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
46011#[inline]
46012#[cfg(target_endian = "little")]
46013#[target_feature(enable = "neon")]
46014#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46015#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46016#[cfg_attr(
46017 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46018 assert_instr(nop)
46019)]
46020#[cfg_attr(
46021 not(target_arch = "arm"),
46022 stable(feature = "neon_intrinsics", since = "1.59.0")
46023)]
46024#[cfg_attr(
46025 target_arch = "arm",
46026 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46027)]
46028pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
46029 unsafe { transmute(a) }
46030}
46031#[doc = "Vector reinterpret cast operation"]
46032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
46033#[inline]
46034#[cfg(target_endian = "big")]
46035#[target_feature(enable = "neon")]
46036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46037#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46038#[cfg_attr(
46039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46040 assert_instr(nop)
46041)]
46042#[cfg_attr(
46043 not(target_arch = "arm"),
46044 stable(feature = "neon_intrinsics", since = "1.59.0")
46045)]
46046#[cfg_attr(
46047 target_arch = "arm",
46048 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46049)]
46050pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
46051 unsafe {
46052 let ret_val: poly8x8_t = transmute(a);
46053 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46054 }
46055}
46056#[doc = "Vector reinterpret cast operation"]
46057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
46058#[inline]
46059#[cfg(target_endian = "little")]
46060#[target_feature(enable = "neon")]
46061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46063#[cfg_attr(
46064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46065 assert_instr(nop)
46066)]
46067#[cfg_attr(
46068 not(target_arch = "arm"),
46069 stable(feature = "neon_intrinsics", since = "1.59.0")
46070)]
46071#[cfg_attr(
46072 target_arch = "arm",
46073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46074)]
46075pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
46076 unsafe { transmute(a) }
46077}
46078#[doc = "Vector reinterpret cast operation"]
46079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
46080#[inline]
46081#[cfg(target_endian = "big")]
46082#[target_feature(enable = "neon")]
46083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46084#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46085#[cfg_attr(
46086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46087 assert_instr(nop)
46088)]
46089#[cfg_attr(
46090 not(target_arch = "arm"),
46091 stable(feature = "neon_intrinsics", since = "1.59.0")
46092)]
46093#[cfg_attr(
46094 target_arch = "arm",
46095 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46096)]
46097pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
46098 unsafe {
46099 let ret_val: poly16x4_t = transmute(a);
46100 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46101 }
46102}
46103#[doc = "Vector reinterpret cast operation"]
46104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
46105#[inline]
46106#[cfg(target_endian = "little")]
46107#[target_feature(enable = "neon")]
46108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46110#[cfg_attr(
46111 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46112 assert_instr(nop)
46113)]
46114#[cfg_attr(
46115 not(target_arch = "arm"),
46116 stable(feature = "neon_intrinsics", since = "1.59.0")
46117)]
46118#[cfg_attr(
46119 target_arch = "arm",
46120 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46121)]
46122pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
46123 unsafe { transmute(a) }
46124}
46125#[doc = "Vector reinterpret cast operation"]
46126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
46127#[inline]
46128#[cfg(target_endian = "big")]
46129#[target_feature(enable = "neon")]
46130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46132#[cfg_attr(
46133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46134 assert_instr(nop)
46135)]
46136#[cfg_attr(
46137 not(target_arch = "arm"),
46138 stable(feature = "neon_intrinsics", since = "1.59.0")
46139)]
46140#[cfg_attr(
46141 target_arch = "arm",
46142 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46143)]
46144pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
46145 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46146 unsafe {
46147 let ret_val: float32x4_t = transmute(a);
46148 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46149 }
46150}
46151#[doc = "Vector reinterpret cast operation"]
46152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
46153#[inline]
46154#[cfg(target_endian = "little")]
46155#[target_feature(enable = "neon")]
46156#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46157#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46158#[cfg_attr(
46159 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46160 assert_instr(nop)
46161)]
46162#[cfg_attr(
46163 not(target_arch = "arm"),
46164 stable(feature = "neon_intrinsics", since = "1.59.0")
46165)]
46166#[cfg_attr(
46167 target_arch = "arm",
46168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46169)]
46170pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
46171 unsafe { transmute(a) }
46172}
46173#[doc = "Vector reinterpret cast operation"]
46174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
46175#[inline]
46176#[cfg(target_endian = "big")]
46177#[target_feature(enable = "neon")]
46178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46180#[cfg_attr(
46181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46182 assert_instr(nop)
46183)]
46184#[cfg_attr(
46185 not(target_arch = "arm"),
46186 stable(feature = "neon_intrinsics", since = "1.59.0")
46187)]
46188#[cfg_attr(
46189 target_arch = "arm",
46190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46191)]
46192pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
46193 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46194 unsafe {
46195 let ret_val: int8x16_t = transmute(a);
46196 simd_shuffle!(
46197 ret_val,
46198 ret_val,
46199 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46200 )
46201 }
46202}
46203#[doc = "Vector reinterpret cast operation"]
46204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
46205#[inline]
46206#[cfg(target_endian = "little")]
46207#[target_feature(enable = "neon")]
46208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46210#[cfg_attr(
46211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46212 assert_instr(nop)
46213)]
46214#[cfg_attr(
46215 not(target_arch = "arm"),
46216 stable(feature = "neon_intrinsics", since = "1.59.0")
46217)]
46218#[cfg_attr(
46219 target_arch = "arm",
46220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46221)]
46222pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
46223 unsafe { transmute(a) }
46224}
46225#[doc = "Vector reinterpret cast operation"]
46226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
46227#[inline]
46228#[cfg(target_endian = "big")]
46229#[target_feature(enable = "neon")]
46230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46232#[cfg_attr(
46233 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46234 assert_instr(nop)
46235)]
46236#[cfg_attr(
46237 not(target_arch = "arm"),
46238 stable(feature = "neon_intrinsics", since = "1.59.0")
46239)]
46240#[cfg_attr(
46241 target_arch = "arm",
46242 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46243)]
46244pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
46245 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46246 unsafe {
46247 let ret_val: int16x8_t = transmute(a);
46248 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46249 }
46250}
46251#[doc = "Vector reinterpret cast operation"]
46252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
46253#[inline]
46254#[cfg(target_endian = "little")]
46255#[target_feature(enable = "neon")]
46256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46258#[cfg_attr(
46259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46260 assert_instr(nop)
46261)]
46262#[cfg_attr(
46263 not(target_arch = "arm"),
46264 stable(feature = "neon_intrinsics", since = "1.59.0")
46265)]
46266#[cfg_attr(
46267 target_arch = "arm",
46268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46269)]
46270pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
46271 unsafe { transmute(a) }
46272}
46273#[doc = "Vector reinterpret cast operation"]
46274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
46275#[inline]
46276#[cfg(target_endian = "big")]
46277#[target_feature(enable = "neon")]
46278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46280#[cfg_attr(
46281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46282 assert_instr(nop)
46283)]
46284#[cfg_attr(
46285 not(target_arch = "arm"),
46286 stable(feature = "neon_intrinsics", since = "1.59.0")
46287)]
46288#[cfg_attr(
46289 target_arch = "arm",
46290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46291)]
46292pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
46293 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46294 unsafe {
46295 let ret_val: int32x4_t = transmute(a);
46296 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46297 }
46298}
46299#[doc = "Vector reinterpret cast operation"]
46300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
46301#[inline]
46302#[cfg(target_endian = "little")]
46303#[target_feature(enable = "neon")]
46304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46306#[cfg_attr(
46307 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46308 assert_instr(nop)
46309)]
46310#[cfg_attr(
46311 not(target_arch = "arm"),
46312 stable(feature = "neon_intrinsics", since = "1.59.0")
46313)]
46314#[cfg_attr(
46315 target_arch = "arm",
46316 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46317)]
46318pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
46319 unsafe { transmute(a) }
46320}
46321#[doc = "Vector reinterpret cast operation"]
46322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
46323#[inline]
46324#[cfg(target_endian = "big")]
46325#[target_feature(enable = "neon")]
46326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46328#[cfg_attr(
46329 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46330 assert_instr(nop)
46331)]
46332#[cfg_attr(
46333 not(target_arch = "arm"),
46334 stable(feature = "neon_intrinsics", since = "1.59.0")
46335)]
46336#[cfg_attr(
46337 target_arch = "arm",
46338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46339)]
46340pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
46341 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46342 unsafe {
46343 let ret_val: int64x2_t = transmute(a);
46344 simd_shuffle!(ret_val, ret_val, [1, 0])
46345 }
46346}
46347#[doc = "Vector reinterpret cast operation"]
46348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
46349#[inline]
46350#[cfg(target_endian = "little")]
46351#[target_feature(enable = "neon")]
46352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46353#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46354#[cfg_attr(
46355 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46356 assert_instr(nop)
46357)]
46358#[cfg_attr(
46359 not(target_arch = "arm"),
46360 stable(feature = "neon_intrinsics", since = "1.59.0")
46361)]
46362#[cfg_attr(
46363 target_arch = "arm",
46364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46365)]
46366pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
46367 unsafe { transmute(a) }
46368}
46369#[doc = "Vector reinterpret cast operation"]
46370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
46371#[inline]
46372#[cfg(target_endian = "big")]
46373#[target_feature(enable = "neon")]
46374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46376#[cfg_attr(
46377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46378 assert_instr(nop)
46379)]
46380#[cfg_attr(
46381 not(target_arch = "arm"),
46382 stable(feature = "neon_intrinsics", since = "1.59.0")
46383)]
46384#[cfg_attr(
46385 target_arch = "arm",
46386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46387)]
46388pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
46389 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46390 unsafe {
46391 let ret_val: uint8x16_t = transmute(a);
46392 simd_shuffle!(
46393 ret_val,
46394 ret_val,
46395 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46396 )
46397 }
46398}
46399#[doc = "Vector reinterpret cast operation"]
46400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
46401#[inline]
46402#[cfg(target_endian = "little")]
46403#[target_feature(enable = "neon")]
46404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46405#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46406#[cfg_attr(
46407 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46408 assert_instr(nop)
46409)]
46410#[cfg_attr(
46411 not(target_arch = "arm"),
46412 stable(feature = "neon_intrinsics", since = "1.59.0")
46413)]
46414#[cfg_attr(
46415 target_arch = "arm",
46416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46417)]
46418pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
46419 unsafe { transmute(a) }
46420}
46421#[doc = "Vector reinterpret cast operation"]
46422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
46423#[inline]
46424#[cfg(target_endian = "big")]
46425#[target_feature(enable = "neon")]
46426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46427#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46428#[cfg_attr(
46429 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46430 assert_instr(nop)
46431)]
46432#[cfg_attr(
46433 not(target_arch = "arm"),
46434 stable(feature = "neon_intrinsics", since = "1.59.0")
46435)]
46436#[cfg_attr(
46437 target_arch = "arm",
46438 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46439)]
46440pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
46441 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46442 unsafe {
46443 let ret_val: uint16x8_t = transmute(a);
46444 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46445 }
46446}
46447#[doc = "Vector reinterpret cast operation"]
46448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
46449#[inline]
46450#[cfg(target_endian = "little")]
46451#[target_feature(enable = "neon")]
46452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46454#[cfg_attr(
46455 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46456 assert_instr(nop)
46457)]
46458#[cfg_attr(
46459 not(target_arch = "arm"),
46460 stable(feature = "neon_intrinsics", since = "1.59.0")
46461)]
46462#[cfg_attr(
46463 target_arch = "arm",
46464 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46465)]
46466pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
46467 unsafe { transmute(a) }
46468}
46469#[doc = "Vector reinterpret cast operation"]
46470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
46471#[inline]
46472#[cfg(target_endian = "big")]
46473#[target_feature(enable = "neon")]
46474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46476#[cfg_attr(
46477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46478 assert_instr(nop)
46479)]
46480#[cfg_attr(
46481 not(target_arch = "arm"),
46482 stable(feature = "neon_intrinsics", since = "1.59.0")
46483)]
46484#[cfg_attr(
46485 target_arch = "arm",
46486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46487)]
46488pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
46489 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46490 unsafe {
46491 let ret_val: uint32x4_t = transmute(a);
46492 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46493 }
46494}
46495#[doc = "Vector reinterpret cast operation"]
46496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
46497#[inline]
46498#[cfg(target_endian = "little")]
46499#[target_feature(enable = "neon")]
46500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46502#[cfg_attr(
46503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46504 assert_instr(nop)
46505)]
46506#[cfg_attr(
46507 not(target_arch = "arm"),
46508 stable(feature = "neon_intrinsics", since = "1.59.0")
46509)]
46510#[cfg_attr(
46511 target_arch = "arm",
46512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46513)]
46514pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
46515 unsafe { transmute(a) }
46516}
46517#[doc = "Vector reinterpret cast operation"]
46518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
46519#[inline]
46520#[cfg(target_endian = "big")]
46521#[target_feature(enable = "neon")]
46522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46524#[cfg_attr(
46525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46526 assert_instr(nop)
46527)]
46528#[cfg_attr(
46529 not(target_arch = "arm"),
46530 stable(feature = "neon_intrinsics", since = "1.59.0")
46531)]
46532#[cfg_attr(
46533 target_arch = "arm",
46534 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46535)]
46536pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
46537 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46538 unsafe {
46539 let ret_val: poly8x16_t = transmute(a);
46540 simd_shuffle!(
46541 ret_val,
46542 ret_val,
46543 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46544 )
46545 }
46546}
46547#[doc = "Vector reinterpret cast operation"]
46548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
46549#[inline]
46550#[cfg(target_endian = "little")]
46551#[target_feature(enable = "neon")]
46552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46553#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46554#[cfg_attr(
46555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46556 assert_instr(nop)
46557)]
46558#[cfg_attr(
46559 not(target_arch = "arm"),
46560 stable(feature = "neon_intrinsics", since = "1.59.0")
46561)]
46562#[cfg_attr(
46563 target_arch = "arm",
46564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46565)]
46566pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
46567 unsafe { transmute(a) }
46568}
46569#[doc = "Vector reinterpret cast operation"]
46570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
46571#[inline]
46572#[cfg(target_endian = "big")]
46573#[target_feature(enable = "neon")]
46574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46576#[cfg_attr(
46577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46578 assert_instr(nop)
46579)]
46580#[cfg_attr(
46581 not(target_arch = "arm"),
46582 stable(feature = "neon_intrinsics", since = "1.59.0")
46583)]
46584#[cfg_attr(
46585 target_arch = "arm",
46586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46587)]
46588pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
46589 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46590 unsafe {
46591 let ret_val: poly16x8_t = transmute(a);
46592 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46593 }
46594}
46595#[doc = "Vector reinterpret cast operation"]
46596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
46597#[inline]
46598#[cfg(target_endian = "little")]
46599#[target_feature(enable = "neon")]
46600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46602#[cfg_attr(
46603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46604 assert_instr(nop)
46605)]
46606#[cfg_attr(
46607 not(target_arch = "arm"),
46608 stable(feature = "neon_intrinsics", since = "1.59.0")
46609)]
46610#[cfg_attr(
46611 target_arch = "arm",
46612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46613)]
46614pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
46615 unsafe { transmute(a) }
46616}
46617#[doc = "Vector reinterpret cast operation"]
46618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
46619#[inline]
46620#[cfg(target_endian = "big")]
46621#[target_feature(enable = "neon")]
46622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46624#[cfg_attr(
46625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46626 assert_instr(nop)
46627)]
46628#[cfg_attr(
46629 not(target_arch = "arm"),
46630 stable(feature = "neon_intrinsics", since = "1.59.0")
46631)]
46632#[cfg_attr(
46633 target_arch = "arm",
46634 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46635)]
46636pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
46637 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46638 unsafe {
46639 let ret_val: float32x2_t = transmute(a);
46640 simd_shuffle!(ret_val, ret_val, [1, 0])
46641 }
46642}
46643#[doc = "Vector reinterpret cast operation"]
46644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
46645#[inline]
46646#[cfg(target_endian = "little")]
46647#[target_feature(enable = "neon")]
46648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46650#[cfg_attr(
46651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46652 assert_instr(nop)
46653)]
46654#[cfg_attr(
46655 not(target_arch = "arm"),
46656 stable(feature = "neon_intrinsics", since = "1.59.0")
46657)]
46658#[cfg_attr(
46659 target_arch = "arm",
46660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46661)]
46662pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
46663 unsafe { transmute(a) }
46664}
46665#[doc = "Vector reinterpret cast operation"]
46666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
46667#[inline]
46668#[cfg(target_endian = "big")]
46669#[target_feature(enable = "neon")]
46670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46672#[cfg_attr(
46673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46674 assert_instr(nop)
46675)]
46676#[cfg_attr(
46677 not(target_arch = "arm"),
46678 stable(feature = "neon_intrinsics", since = "1.59.0")
46679)]
46680#[cfg_attr(
46681 target_arch = "arm",
46682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46683)]
46684pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
46685 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46686 unsafe {
46687 let ret_val: int8x8_t = transmute(a);
46688 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46689 }
46690}
46691#[doc = "Vector reinterpret cast operation"]
46692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
46693#[inline]
46694#[cfg(target_endian = "little")]
46695#[target_feature(enable = "neon")]
46696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46698#[cfg_attr(
46699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46700 assert_instr(nop)
46701)]
46702#[cfg_attr(
46703 not(target_arch = "arm"),
46704 stable(feature = "neon_intrinsics", since = "1.59.0")
46705)]
46706#[cfg_attr(
46707 target_arch = "arm",
46708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46709)]
46710pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
46711 unsafe { transmute(a) }
46712}
46713#[doc = "Vector reinterpret cast operation"]
46714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
46715#[inline]
46716#[cfg(target_endian = "big")]
46717#[target_feature(enable = "neon")]
46718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46720#[cfg_attr(
46721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46722 assert_instr(nop)
46723)]
46724#[cfg_attr(
46725 not(target_arch = "arm"),
46726 stable(feature = "neon_intrinsics", since = "1.59.0")
46727)]
46728#[cfg_attr(
46729 target_arch = "arm",
46730 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46731)]
46732pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
46733 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46734 unsafe {
46735 let ret_val: int16x4_t = transmute(a);
46736 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46737 }
46738}
46739#[doc = "Vector reinterpret cast operation"]
46740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
46741#[inline]
46742#[cfg(target_endian = "little")]
46743#[target_feature(enable = "neon")]
46744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46746#[cfg_attr(
46747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46748 assert_instr(nop)
46749)]
46750#[cfg_attr(
46751 not(target_arch = "arm"),
46752 stable(feature = "neon_intrinsics", since = "1.59.0")
46753)]
46754#[cfg_attr(
46755 target_arch = "arm",
46756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46757)]
46758pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
46759 unsafe { transmute(a) }
46760}
46761#[doc = "Vector reinterpret cast operation"]
46762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
46763#[inline]
46764#[cfg(target_endian = "big")]
46765#[target_feature(enable = "neon")]
46766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46768#[cfg_attr(
46769 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46770 assert_instr(nop)
46771)]
46772#[cfg_attr(
46773 not(target_arch = "arm"),
46774 stable(feature = "neon_intrinsics", since = "1.59.0")
46775)]
46776#[cfg_attr(
46777 target_arch = "arm",
46778 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46779)]
46780pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
46781 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46782 unsafe {
46783 let ret_val: int32x2_t = transmute(a);
46784 simd_shuffle!(ret_val, ret_val, [1, 0])
46785 }
46786}
46787#[doc = "Vector reinterpret cast operation"]
46788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
46789#[inline]
46790#[cfg(target_endian = "little")]
46791#[target_feature(enable = "neon")]
46792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46794#[cfg_attr(
46795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46796 assert_instr(nop)
46797)]
46798#[cfg_attr(
46799 not(target_arch = "arm"),
46800 stable(feature = "neon_intrinsics", since = "1.59.0")
46801)]
46802#[cfg_attr(
46803 target_arch = "arm",
46804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46805)]
46806pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
46807 unsafe { transmute(a) }
46808}
46809#[doc = "Vector reinterpret cast operation"]
46810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
46811#[inline]
46812#[cfg(target_endian = "big")]
46813#[target_feature(enable = "neon")]
46814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46816#[cfg_attr(
46817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46818 assert_instr(nop)
46819)]
46820#[cfg_attr(
46821 not(target_arch = "arm"),
46822 stable(feature = "neon_intrinsics", since = "1.59.0")
46823)]
46824#[cfg_attr(
46825 target_arch = "arm",
46826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46827)]
46828pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
46829 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46830 unsafe { transmute(a) }
46831}
46832#[doc = "Vector reinterpret cast operation"]
46833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
46834#[inline]
46835#[cfg(target_endian = "little")]
46836#[target_feature(enable = "neon")]
46837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46839#[cfg_attr(
46840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46841 assert_instr(nop)
46842)]
46843#[cfg_attr(
46844 not(target_arch = "arm"),
46845 stable(feature = "neon_intrinsics", since = "1.59.0")
46846)]
46847#[cfg_attr(
46848 target_arch = "arm",
46849 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46850)]
46851pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
46852 unsafe { transmute(a) }
46853}
46854#[doc = "Vector reinterpret cast operation"]
46855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
46856#[inline]
46857#[cfg(target_endian = "big")]
46858#[target_feature(enable = "neon")]
46859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46861#[cfg_attr(
46862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46863 assert_instr(nop)
46864)]
46865#[cfg_attr(
46866 not(target_arch = "arm"),
46867 stable(feature = "neon_intrinsics", since = "1.59.0")
46868)]
46869#[cfg_attr(
46870 target_arch = "arm",
46871 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46872)]
46873pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
46874 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46875 unsafe {
46876 let ret_val: uint8x8_t = transmute(a);
46877 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46878 }
46879}
46880#[doc = "Vector reinterpret cast operation"]
46881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
46882#[inline]
46883#[cfg(target_endian = "little")]
46884#[target_feature(enable = "neon")]
46885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46887#[cfg_attr(
46888 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46889 assert_instr(nop)
46890)]
46891#[cfg_attr(
46892 not(target_arch = "arm"),
46893 stable(feature = "neon_intrinsics", since = "1.59.0")
46894)]
46895#[cfg_attr(
46896 target_arch = "arm",
46897 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46898)]
46899pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
46900 unsafe { transmute(a) }
46901}
46902#[doc = "Vector reinterpret cast operation"]
46903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
46904#[inline]
46905#[cfg(target_endian = "big")]
46906#[target_feature(enable = "neon")]
46907#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46909#[cfg_attr(
46910 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46911 assert_instr(nop)
46912)]
46913#[cfg_attr(
46914 not(target_arch = "arm"),
46915 stable(feature = "neon_intrinsics", since = "1.59.0")
46916)]
46917#[cfg_attr(
46918 target_arch = "arm",
46919 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46920)]
46921pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
46922 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46923 unsafe {
46924 let ret_val: uint16x4_t = transmute(a);
46925 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46926 }
46927}
46928#[doc = "Vector reinterpret cast operation"]
46929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
46930#[inline]
46931#[cfg(target_endian = "little")]
46932#[target_feature(enable = "neon")]
46933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46935#[cfg_attr(
46936 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46937 assert_instr(nop)
46938)]
46939#[cfg_attr(
46940 not(target_arch = "arm"),
46941 stable(feature = "neon_intrinsics", since = "1.59.0")
46942)]
46943#[cfg_attr(
46944 target_arch = "arm",
46945 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46946)]
46947pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
46948 unsafe { transmute(a) }
46949}
46950#[doc = "Vector reinterpret cast operation"]
46951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
46952#[inline]
46953#[cfg(target_endian = "big")]
46954#[target_feature(enable = "neon")]
46955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46957#[cfg_attr(
46958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46959 assert_instr(nop)
46960)]
46961#[cfg_attr(
46962 not(target_arch = "arm"),
46963 stable(feature = "neon_intrinsics", since = "1.59.0")
46964)]
46965#[cfg_attr(
46966 target_arch = "arm",
46967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46968)]
46969pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
46970 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46971 unsafe {
46972 let ret_val: uint32x2_t = transmute(a);
46973 simd_shuffle!(ret_val, ret_val, [1, 0])
46974 }
46975}
46976#[doc = "Vector reinterpret cast operation"]
46977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
46978#[inline]
46979#[cfg(target_endian = "little")]
46980#[target_feature(enable = "neon")]
46981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46983#[cfg_attr(
46984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46985 assert_instr(nop)
46986)]
46987#[cfg_attr(
46988 not(target_arch = "arm"),
46989 stable(feature = "neon_intrinsics", since = "1.59.0")
46990)]
46991#[cfg_attr(
46992 target_arch = "arm",
46993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46994)]
46995pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
46996 unsafe { transmute(a) }
46997}
46998#[doc = "Vector reinterpret cast operation"]
46999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
47000#[inline]
47001#[cfg(target_endian = "big")]
47002#[target_feature(enable = "neon")]
47003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47005#[cfg_attr(
47006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47007 assert_instr(nop)
47008)]
47009#[cfg_attr(
47010 not(target_arch = "arm"),
47011 stable(feature = "neon_intrinsics", since = "1.59.0")
47012)]
47013#[cfg_attr(
47014 target_arch = "arm",
47015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47016)]
47017pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
47018 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47019 unsafe { transmute(a) }
47020}
47021#[doc = "Vector reinterpret cast operation"]
47022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
47023#[inline]
47024#[cfg(target_endian = "little")]
47025#[target_feature(enable = "neon")]
47026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47027#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47028#[cfg_attr(
47029 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47030 assert_instr(nop)
47031)]
47032#[cfg_attr(
47033 not(target_arch = "arm"),
47034 stable(feature = "neon_intrinsics", since = "1.59.0")
47035)]
47036#[cfg_attr(
47037 target_arch = "arm",
47038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47039)]
47040pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
47041 unsafe { transmute(a) }
47042}
47043#[doc = "Vector reinterpret cast operation"]
47044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
47045#[inline]
47046#[cfg(target_endian = "big")]
47047#[target_feature(enable = "neon")]
47048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47049#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47050#[cfg_attr(
47051 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47052 assert_instr(nop)
47053)]
47054#[cfg_attr(
47055 not(target_arch = "arm"),
47056 stable(feature = "neon_intrinsics", since = "1.59.0")
47057)]
47058#[cfg_attr(
47059 target_arch = "arm",
47060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47061)]
47062pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
47063 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47064 unsafe {
47065 let ret_val: poly16x4_t = transmute(a);
47066 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47067 }
47068}
47069#[doc = "Vector reinterpret cast operation"]
47070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
47071#[inline]
47072#[cfg(target_endian = "little")]
47073#[target_feature(enable = "neon")]
47074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47076#[cfg_attr(
47077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47078 assert_instr(nop)
47079)]
47080#[cfg_attr(
47081 not(target_arch = "arm"),
47082 stable(feature = "neon_intrinsics", since = "1.59.0")
47083)]
47084#[cfg_attr(
47085 target_arch = "arm",
47086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47087)]
47088pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
47089 unsafe { transmute(a) }
47090}
47091#[doc = "Vector reinterpret cast operation"]
47092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
47093#[inline]
47094#[cfg(target_endian = "big")]
47095#[target_feature(enable = "neon")]
47096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47098#[cfg_attr(
47099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47100 assert_instr(nop)
47101)]
47102#[cfg_attr(
47103 not(target_arch = "arm"),
47104 stable(feature = "neon_intrinsics", since = "1.59.0")
47105)]
47106#[cfg_attr(
47107 target_arch = "arm",
47108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47109)]
47110pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
47111 let a: poly8x16_t =
47112 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47113 unsafe {
47114 let ret_val: float32x4_t = transmute(a);
47115 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47116 }
47117}
47118#[doc = "Vector reinterpret cast operation"]
47119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
47120#[inline]
47121#[cfg(target_endian = "little")]
47122#[target_feature(enable = "neon")]
47123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47125#[cfg_attr(
47126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47127 assert_instr(nop)
47128)]
47129#[cfg_attr(
47130 not(target_arch = "arm"),
47131 stable(feature = "neon_intrinsics", since = "1.59.0")
47132)]
47133#[cfg_attr(
47134 target_arch = "arm",
47135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47136)]
47137pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
47138 unsafe { transmute(a) }
47139}
47140#[doc = "Vector reinterpret cast operation"]
47141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
47142#[inline]
47143#[cfg(target_endian = "big")]
47144#[target_feature(enable = "neon")]
47145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47147#[cfg_attr(
47148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47149 assert_instr(nop)
47150)]
47151#[cfg_attr(
47152 not(target_arch = "arm"),
47153 stable(feature = "neon_intrinsics", since = "1.59.0")
47154)]
47155#[cfg_attr(
47156 target_arch = "arm",
47157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47158)]
47159pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
47160 let a: poly8x16_t =
47161 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47162 unsafe {
47163 let ret_val: int8x16_t = transmute(a);
47164 simd_shuffle!(
47165 ret_val,
47166 ret_val,
47167 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47168 )
47169 }
47170}
47171#[doc = "Vector reinterpret cast operation"]
47172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
47173#[inline]
47174#[cfg(target_endian = "little")]
47175#[target_feature(enable = "neon")]
47176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47177#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47178#[cfg_attr(
47179 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47180 assert_instr(nop)
47181)]
47182#[cfg_attr(
47183 not(target_arch = "arm"),
47184 stable(feature = "neon_intrinsics", since = "1.59.0")
47185)]
47186#[cfg_attr(
47187 target_arch = "arm",
47188 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47189)]
47190pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
47191 unsafe { transmute(a) }
47192}
47193#[doc = "Vector reinterpret cast operation"]
47194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
47195#[inline]
47196#[cfg(target_endian = "big")]
47197#[target_feature(enable = "neon")]
47198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47200#[cfg_attr(
47201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47202 assert_instr(nop)
47203)]
47204#[cfg_attr(
47205 not(target_arch = "arm"),
47206 stable(feature = "neon_intrinsics", since = "1.59.0")
47207)]
47208#[cfg_attr(
47209 target_arch = "arm",
47210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47211)]
47212pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
47213 let a: poly8x16_t =
47214 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47215 unsafe {
47216 let ret_val: int16x8_t = transmute(a);
47217 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47218 }
47219}
47220#[doc = "Vector reinterpret cast operation"]
47221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
47222#[inline]
47223#[cfg(target_endian = "little")]
47224#[target_feature(enable = "neon")]
47225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47227#[cfg_attr(
47228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47229 assert_instr(nop)
47230)]
47231#[cfg_attr(
47232 not(target_arch = "arm"),
47233 stable(feature = "neon_intrinsics", since = "1.59.0")
47234)]
47235#[cfg_attr(
47236 target_arch = "arm",
47237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47238)]
47239pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
47240 unsafe { transmute(a) }
47241}
47242#[doc = "Vector reinterpret cast operation"]
47243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
47244#[inline]
47245#[cfg(target_endian = "big")]
47246#[target_feature(enable = "neon")]
47247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47249#[cfg_attr(
47250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47251 assert_instr(nop)
47252)]
47253#[cfg_attr(
47254 not(target_arch = "arm"),
47255 stable(feature = "neon_intrinsics", since = "1.59.0")
47256)]
47257#[cfg_attr(
47258 target_arch = "arm",
47259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47260)]
47261pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
47262 let a: poly8x16_t =
47263 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47264 unsafe {
47265 let ret_val: int32x4_t = transmute(a);
47266 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47267 }
47268}
47269#[doc = "Vector reinterpret cast operation"]
47270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
47271#[inline]
47272#[cfg(target_endian = "little")]
47273#[target_feature(enable = "neon")]
47274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47276#[cfg_attr(
47277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47278 assert_instr(nop)
47279)]
47280#[cfg_attr(
47281 not(target_arch = "arm"),
47282 stable(feature = "neon_intrinsics", since = "1.59.0")
47283)]
47284#[cfg_attr(
47285 target_arch = "arm",
47286 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47287)]
47288pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
47289 unsafe { transmute(a) }
47290}
47291#[doc = "Vector reinterpret cast operation"]
47292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
47293#[inline]
47294#[cfg(target_endian = "big")]
47295#[target_feature(enable = "neon")]
47296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47298#[cfg_attr(
47299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47300 assert_instr(nop)
47301)]
47302#[cfg_attr(
47303 not(target_arch = "arm"),
47304 stable(feature = "neon_intrinsics", since = "1.59.0")
47305)]
47306#[cfg_attr(
47307 target_arch = "arm",
47308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47309)]
47310pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
47311 let a: poly8x16_t =
47312 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47313 unsafe {
47314 let ret_val: int64x2_t = transmute(a);
47315 simd_shuffle!(ret_val, ret_val, [1, 0])
47316 }
47317}
47318#[doc = "Vector reinterpret cast operation"]
47319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
47320#[inline]
47321#[cfg(target_endian = "little")]
47322#[target_feature(enable = "neon")]
47323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47325#[cfg_attr(
47326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47327 assert_instr(nop)
47328)]
47329#[cfg_attr(
47330 not(target_arch = "arm"),
47331 stable(feature = "neon_intrinsics", since = "1.59.0")
47332)]
47333#[cfg_attr(
47334 target_arch = "arm",
47335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47336)]
47337pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
47338 unsafe { transmute(a) }
47339}
47340#[doc = "Vector reinterpret cast operation"]
47341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
47342#[inline]
47343#[cfg(target_endian = "big")]
47344#[target_feature(enable = "neon")]
47345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47347#[cfg_attr(
47348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47349 assert_instr(nop)
47350)]
47351#[cfg_attr(
47352 not(target_arch = "arm"),
47353 stable(feature = "neon_intrinsics", since = "1.59.0")
47354)]
47355#[cfg_attr(
47356 target_arch = "arm",
47357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47358)]
47359pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
47360 let a: poly8x16_t =
47361 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47362 unsafe {
47363 let ret_val: uint8x16_t = transmute(a);
47364 simd_shuffle!(
47365 ret_val,
47366 ret_val,
47367 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47368 )
47369 }
47370}
47371#[doc = "Vector reinterpret cast operation"]
47372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
47373#[inline]
47374#[cfg(target_endian = "little")]
47375#[target_feature(enable = "neon")]
47376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47378#[cfg_attr(
47379 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47380 assert_instr(nop)
47381)]
47382#[cfg_attr(
47383 not(target_arch = "arm"),
47384 stable(feature = "neon_intrinsics", since = "1.59.0")
47385)]
47386#[cfg_attr(
47387 target_arch = "arm",
47388 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47389)]
47390pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
47391 unsafe { transmute(a) }
47392}
47393#[doc = "Vector reinterpret cast operation"]
47394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
47395#[inline]
47396#[cfg(target_endian = "big")]
47397#[target_feature(enable = "neon")]
47398#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47399#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47400#[cfg_attr(
47401 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47402 assert_instr(nop)
47403)]
47404#[cfg_attr(
47405 not(target_arch = "arm"),
47406 stable(feature = "neon_intrinsics", since = "1.59.0")
47407)]
47408#[cfg_attr(
47409 target_arch = "arm",
47410 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47411)]
47412pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
47413 let a: poly8x16_t =
47414 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47415 unsafe {
47416 let ret_val: uint16x8_t = transmute(a);
47417 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47418 }
47419}
47420#[doc = "Vector reinterpret cast operation"]
47421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
47422#[inline]
47423#[cfg(target_endian = "little")]
47424#[target_feature(enable = "neon")]
47425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47426#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47427#[cfg_attr(
47428 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47429 assert_instr(nop)
47430)]
47431#[cfg_attr(
47432 not(target_arch = "arm"),
47433 stable(feature = "neon_intrinsics", since = "1.59.0")
47434)]
47435#[cfg_attr(
47436 target_arch = "arm",
47437 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47438)]
47439pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
47440 unsafe { transmute(a) }
47441}
47442#[doc = "Vector reinterpret cast operation"]
47443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
47444#[inline]
47445#[cfg(target_endian = "big")]
47446#[target_feature(enable = "neon")]
47447#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47448#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47449#[cfg_attr(
47450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47451 assert_instr(nop)
47452)]
47453#[cfg_attr(
47454 not(target_arch = "arm"),
47455 stable(feature = "neon_intrinsics", since = "1.59.0")
47456)]
47457#[cfg_attr(
47458 target_arch = "arm",
47459 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47460)]
47461pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
47462 let a: poly8x16_t =
47463 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47464 unsafe {
47465 let ret_val: uint32x4_t = transmute(a);
47466 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47467 }
47468}
47469#[doc = "Vector reinterpret cast operation"]
47470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
47471#[inline]
47472#[cfg(target_endian = "little")]
47473#[target_feature(enable = "neon")]
47474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47476#[cfg_attr(
47477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47478 assert_instr(nop)
47479)]
47480#[cfg_attr(
47481 not(target_arch = "arm"),
47482 stable(feature = "neon_intrinsics", since = "1.59.0")
47483)]
47484#[cfg_attr(
47485 target_arch = "arm",
47486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47487)]
47488pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
47489 unsafe { transmute(a) }
47490}
47491#[doc = "Vector reinterpret cast operation"]
47492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
47493#[inline]
47494#[cfg(target_endian = "big")]
47495#[target_feature(enable = "neon")]
47496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47498#[cfg_attr(
47499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47500 assert_instr(nop)
47501)]
47502#[cfg_attr(
47503 not(target_arch = "arm"),
47504 stable(feature = "neon_intrinsics", since = "1.59.0")
47505)]
47506#[cfg_attr(
47507 target_arch = "arm",
47508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47509)]
47510pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
47511 let a: poly8x16_t =
47512 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47513 unsafe {
47514 let ret_val: uint64x2_t = transmute(a);
47515 simd_shuffle!(ret_val, ret_val, [1, 0])
47516 }
47517}
47518#[doc = "Vector reinterpret cast operation"]
47519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
47520#[inline]
47521#[cfg(target_endian = "little")]
47522#[target_feature(enable = "neon")]
47523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47525#[cfg_attr(
47526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47527 assert_instr(nop)
47528)]
47529#[cfg_attr(
47530 not(target_arch = "arm"),
47531 stable(feature = "neon_intrinsics", since = "1.59.0")
47532)]
47533#[cfg_attr(
47534 target_arch = "arm",
47535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47536)]
47537pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
47538 unsafe { transmute(a) }
47539}
47540#[doc = "Vector reinterpret cast operation"]
47541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
47542#[inline]
47543#[cfg(target_endian = "big")]
47544#[target_feature(enable = "neon")]
47545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47546#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47547#[cfg_attr(
47548 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47549 assert_instr(nop)
47550)]
47551#[cfg_attr(
47552 not(target_arch = "arm"),
47553 stable(feature = "neon_intrinsics", since = "1.59.0")
47554)]
47555#[cfg_attr(
47556 target_arch = "arm",
47557 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47558)]
47559pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
47560 let a: poly8x16_t =
47561 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
47562 unsafe {
47563 let ret_val: poly16x8_t = transmute(a);
47564 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47565 }
47566}
47567#[doc = "Vector reinterpret cast operation"]
47568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
47569#[inline]
47570#[cfg(target_endian = "little")]
47571#[target_feature(enable = "neon")]
47572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47574#[cfg_attr(
47575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47576 assert_instr(nop)
47577)]
47578#[cfg_attr(
47579 not(target_arch = "arm"),
47580 stable(feature = "neon_intrinsics", since = "1.59.0")
47581)]
47582#[cfg_attr(
47583 target_arch = "arm",
47584 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47585)]
47586pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
47587 unsafe { transmute(a) }
47588}
47589#[doc = "Vector reinterpret cast operation"]
47590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
47591#[inline]
47592#[cfg(target_endian = "big")]
47593#[target_feature(enable = "neon")]
47594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47596#[cfg_attr(
47597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47598 assert_instr(nop)
47599)]
47600#[cfg_attr(
47601 not(target_arch = "arm"),
47602 stable(feature = "neon_intrinsics", since = "1.59.0")
47603)]
47604#[cfg_attr(
47605 target_arch = "arm",
47606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47607)]
47608pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
47609 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47610 unsafe {
47611 let ret_val: float32x2_t = transmute(a);
47612 simd_shuffle!(ret_val, ret_val, [1, 0])
47613 }
47614}
47615#[doc = "Vector reinterpret cast operation"]
47616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
47617#[inline]
47618#[cfg(target_endian = "little")]
47619#[target_feature(enable = "neon")]
47620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47622#[cfg_attr(
47623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47624 assert_instr(nop)
47625)]
47626#[cfg_attr(
47627 not(target_arch = "arm"),
47628 stable(feature = "neon_intrinsics", since = "1.59.0")
47629)]
47630#[cfg_attr(
47631 target_arch = "arm",
47632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47633)]
47634pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
47635 unsafe { transmute(a) }
47636}
47637#[doc = "Vector reinterpret cast operation"]
47638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
47639#[inline]
47640#[cfg(target_endian = "big")]
47641#[target_feature(enable = "neon")]
47642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47644#[cfg_attr(
47645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47646 assert_instr(nop)
47647)]
47648#[cfg_attr(
47649 not(target_arch = "arm"),
47650 stable(feature = "neon_intrinsics", since = "1.59.0")
47651)]
47652#[cfg_attr(
47653 target_arch = "arm",
47654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47655)]
47656pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
47657 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47658 unsafe {
47659 let ret_val: int8x8_t = transmute(a);
47660 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47661 }
47662}
47663#[doc = "Vector reinterpret cast operation"]
47664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
47665#[inline]
47666#[cfg(target_endian = "little")]
47667#[target_feature(enable = "neon")]
47668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47669#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47670#[cfg_attr(
47671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47672 assert_instr(nop)
47673)]
47674#[cfg_attr(
47675 not(target_arch = "arm"),
47676 stable(feature = "neon_intrinsics", since = "1.59.0")
47677)]
47678#[cfg_attr(
47679 target_arch = "arm",
47680 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47681)]
47682pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
47683 unsafe { transmute(a) }
47684}
47685#[doc = "Vector reinterpret cast operation"]
47686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
47687#[inline]
47688#[cfg(target_endian = "big")]
47689#[target_feature(enable = "neon")]
47690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47692#[cfg_attr(
47693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47694 assert_instr(nop)
47695)]
47696#[cfg_attr(
47697 not(target_arch = "arm"),
47698 stable(feature = "neon_intrinsics", since = "1.59.0")
47699)]
47700#[cfg_attr(
47701 target_arch = "arm",
47702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47703)]
47704pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
47705 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47706 unsafe {
47707 let ret_val: int16x4_t = transmute(a);
47708 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47709 }
47710}
47711#[doc = "Vector reinterpret cast operation"]
47712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
47713#[inline]
47714#[cfg(target_endian = "little")]
47715#[target_feature(enable = "neon")]
47716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47718#[cfg_attr(
47719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47720 assert_instr(nop)
47721)]
47722#[cfg_attr(
47723 not(target_arch = "arm"),
47724 stable(feature = "neon_intrinsics", since = "1.59.0")
47725)]
47726#[cfg_attr(
47727 target_arch = "arm",
47728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47729)]
47730pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
47731 unsafe { transmute(a) }
47732}
47733#[doc = "Vector reinterpret cast operation"]
47734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
47735#[inline]
47736#[cfg(target_endian = "big")]
47737#[target_feature(enable = "neon")]
47738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47740#[cfg_attr(
47741 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47742 assert_instr(nop)
47743)]
47744#[cfg_attr(
47745 not(target_arch = "arm"),
47746 stable(feature = "neon_intrinsics", since = "1.59.0")
47747)]
47748#[cfg_attr(
47749 target_arch = "arm",
47750 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47751)]
47752pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
47753 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47754 unsafe {
47755 let ret_val: int32x2_t = transmute(a);
47756 simd_shuffle!(ret_val, ret_val, [1, 0])
47757 }
47758}
47759#[doc = "Vector reinterpret cast operation"]
47760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
47761#[inline]
47762#[cfg(target_endian = "little")]
47763#[target_feature(enable = "neon")]
47764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47766#[cfg_attr(
47767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47768 assert_instr(nop)
47769)]
47770#[cfg_attr(
47771 not(target_arch = "arm"),
47772 stable(feature = "neon_intrinsics", since = "1.59.0")
47773)]
47774#[cfg_attr(
47775 target_arch = "arm",
47776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47777)]
47778pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
47779 unsafe { transmute(a) }
47780}
47781#[doc = "Vector reinterpret cast operation"]
47782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
47783#[inline]
47784#[cfg(target_endian = "big")]
47785#[target_feature(enable = "neon")]
47786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47788#[cfg_attr(
47789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47790 assert_instr(nop)
47791)]
47792#[cfg_attr(
47793 not(target_arch = "arm"),
47794 stable(feature = "neon_intrinsics", since = "1.59.0")
47795)]
47796#[cfg_attr(
47797 target_arch = "arm",
47798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47799)]
47800pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
47801 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47802 unsafe { transmute(a) }
47803}
47804#[doc = "Vector reinterpret cast operation"]
47805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
47806#[inline]
47807#[cfg(target_endian = "little")]
47808#[target_feature(enable = "neon")]
47809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47811#[cfg_attr(
47812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47813 assert_instr(nop)
47814)]
47815#[cfg_attr(
47816 not(target_arch = "arm"),
47817 stable(feature = "neon_intrinsics", since = "1.59.0")
47818)]
47819#[cfg_attr(
47820 target_arch = "arm",
47821 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47822)]
47823pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
47824 unsafe { transmute(a) }
47825}
47826#[doc = "Vector reinterpret cast operation"]
47827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
47828#[inline]
47829#[cfg(target_endian = "big")]
47830#[target_feature(enable = "neon")]
47831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47833#[cfg_attr(
47834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47835 assert_instr(nop)
47836)]
47837#[cfg_attr(
47838 not(target_arch = "arm"),
47839 stable(feature = "neon_intrinsics", since = "1.59.0")
47840)]
47841#[cfg_attr(
47842 target_arch = "arm",
47843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47844)]
47845pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
47846 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47847 unsafe {
47848 let ret_val: uint8x8_t = transmute(a);
47849 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47850 }
47851}
47852#[doc = "Vector reinterpret cast operation"]
47853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
47854#[inline]
47855#[cfg(target_endian = "little")]
47856#[target_feature(enable = "neon")]
47857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47859#[cfg_attr(
47860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47861 assert_instr(nop)
47862)]
47863#[cfg_attr(
47864 not(target_arch = "arm"),
47865 stable(feature = "neon_intrinsics", since = "1.59.0")
47866)]
47867#[cfg_attr(
47868 target_arch = "arm",
47869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47870)]
47871pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
47872 unsafe { transmute(a) }
47873}
47874#[doc = "Vector reinterpret cast operation"]
47875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
47876#[inline]
47877#[cfg(target_endian = "big")]
47878#[target_feature(enable = "neon")]
47879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47881#[cfg_attr(
47882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47883 assert_instr(nop)
47884)]
47885#[cfg_attr(
47886 not(target_arch = "arm"),
47887 stable(feature = "neon_intrinsics", since = "1.59.0")
47888)]
47889#[cfg_attr(
47890 target_arch = "arm",
47891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47892)]
47893pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
47894 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47895 unsafe {
47896 let ret_val: uint16x4_t = transmute(a);
47897 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47898 }
47899}
47900#[doc = "Vector reinterpret cast operation"]
47901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
47902#[inline]
47903#[cfg(target_endian = "little")]
47904#[target_feature(enable = "neon")]
47905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47907#[cfg_attr(
47908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47909 assert_instr(nop)
47910)]
47911#[cfg_attr(
47912 not(target_arch = "arm"),
47913 stable(feature = "neon_intrinsics", since = "1.59.0")
47914)]
47915#[cfg_attr(
47916 target_arch = "arm",
47917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47918)]
47919pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
47920 unsafe { transmute(a) }
47921}
47922#[doc = "Vector reinterpret cast operation"]
47923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
47924#[inline]
47925#[cfg(target_endian = "big")]
47926#[target_feature(enable = "neon")]
47927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47929#[cfg_attr(
47930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47931 assert_instr(nop)
47932)]
47933#[cfg_attr(
47934 not(target_arch = "arm"),
47935 stable(feature = "neon_intrinsics", since = "1.59.0")
47936)]
47937#[cfg_attr(
47938 target_arch = "arm",
47939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47940)]
47941pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
47942 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47943 unsafe {
47944 let ret_val: uint32x2_t = transmute(a);
47945 simd_shuffle!(ret_val, ret_val, [1, 0])
47946 }
47947}
47948#[doc = "Vector reinterpret cast operation"]
47949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
47950#[inline]
47951#[cfg(target_endian = "little")]
47952#[target_feature(enable = "neon")]
47953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47955#[cfg_attr(
47956 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47957 assert_instr(nop)
47958)]
47959#[cfg_attr(
47960 not(target_arch = "arm"),
47961 stable(feature = "neon_intrinsics", since = "1.59.0")
47962)]
47963#[cfg_attr(
47964 target_arch = "arm",
47965 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47966)]
47967pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
47968 unsafe { transmute(a) }
47969}
47970#[doc = "Vector reinterpret cast operation"]
47971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
47972#[inline]
47973#[cfg(target_endian = "big")]
47974#[target_feature(enable = "neon")]
47975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47977#[cfg_attr(
47978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47979 assert_instr(nop)
47980)]
47981#[cfg_attr(
47982 not(target_arch = "arm"),
47983 stable(feature = "neon_intrinsics", since = "1.59.0")
47984)]
47985#[cfg_attr(
47986 target_arch = "arm",
47987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47988)]
47989pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
47990 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47991 unsafe { transmute(a) }
47992}
47993#[doc = "Vector reinterpret cast operation"]
47994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
47995#[inline]
47996#[cfg(target_endian = "little")]
47997#[target_feature(enable = "neon")]
47998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48000#[cfg_attr(
48001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48002 assert_instr(nop)
48003)]
48004#[cfg_attr(
48005 not(target_arch = "arm"),
48006 stable(feature = "neon_intrinsics", since = "1.59.0")
48007)]
48008#[cfg_attr(
48009 target_arch = "arm",
48010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48011)]
48012pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
48013 unsafe { transmute(a) }
48014}
48015#[doc = "Vector reinterpret cast operation"]
48016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
48017#[inline]
48018#[cfg(target_endian = "big")]
48019#[target_feature(enable = "neon")]
48020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48022#[cfg_attr(
48023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48024 assert_instr(nop)
48025)]
48026#[cfg_attr(
48027 not(target_arch = "arm"),
48028 stable(feature = "neon_intrinsics", since = "1.59.0")
48029)]
48030#[cfg_attr(
48031 target_arch = "arm",
48032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48033)]
48034pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
48035 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48036 unsafe {
48037 let ret_val: poly8x8_t = transmute(a);
48038 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48039 }
48040}
48041#[doc = "Vector reinterpret cast operation"]
48042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
48043#[inline]
48044#[cfg(target_endian = "little")]
48045#[target_feature(enable = "neon")]
48046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48048#[cfg_attr(
48049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48050 assert_instr(nop)
48051)]
48052#[cfg_attr(
48053 not(target_arch = "arm"),
48054 stable(feature = "neon_intrinsics", since = "1.59.0")
48055)]
48056#[cfg_attr(
48057 target_arch = "arm",
48058 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48059)]
48060pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
48061 unsafe { transmute(a) }
48062}
48063#[doc = "Vector reinterpret cast operation"]
48064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
48065#[inline]
48066#[cfg(target_endian = "big")]
48067#[target_feature(enable = "neon")]
48068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48070#[cfg_attr(
48071 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48072 assert_instr(nop)
48073)]
48074#[cfg_attr(
48075 not(target_arch = "arm"),
48076 stable(feature = "neon_intrinsics", since = "1.59.0")
48077)]
48078#[cfg_attr(
48079 target_arch = "arm",
48080 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48081)]
48082pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
48083 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48084 unsafe {
48085 let ret_val: float32x4_t = transmute(a);
48086 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48087 }
48088}
48089#[doc = "Vector reinterpret cast operation"]
48090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
48091#[inline]
48092#[cfg(target_endian = "little")]
48093#[target_feature(enable = "neon")]
48094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48095#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48096#[cfg_attr(
48097 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48098 assert_instr(nop)
48099)]
48100#[cfg_attr(
48101 not(target_arch = "arm"),
48102 stable(feature = "neon_intrinsics", since = "1.59.0")
48103)]
48104#[cfg_attr(
48105 target_arch = "arm",
48106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48107)]
48108pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
48109 unsafe { transmute(a) }
48110}
48111#[doc = "Vector reinterpret cast operation"]
48112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
48113#[inline]
48114#[cfg(target_endian = "big")]
48115#[target_feature(enable = "neon")]
48116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48118#[cfg_attr(
48119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48120 assert_instr(nop)
48121)]
48122#[cfg_attr(
48123 not(target_arch = "arm"),
48124 stable(feature = "neon_intrinsics", since = "1.59.0")
48125)]
48126#[cfg_attr(
48127 target_arch = "arm",
48128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48129)]
48130pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
48131 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48132 unsafe {
48133 let ret_val: int8x16_t = transmute(a);
48134 simd_shuffle!(
48135 ret_val,
48136 ret_val,
48137 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48138 )
48139 }
48140}
48141#[doc = "Vector reinterpret cast operation"]
48142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
48143#[inline]
48144#[cfg(target_endian = "little")]
48145#[target_feature(enable = "neon")]
48146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48148#[cfg_attr(
48149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48150 assert_instr(nop)
48151)]
48152#[cfg_attr(
48153 not(target_arch = "arm"),
48154 stable(feature = "neon_intrinsics", since = "1.59.0")
48155)]
48156#[cfg_attr(
48157 target_arch = "arm",
48158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48159)]
48160pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
48161 unsafe { transmute(a) }
48162}
48163#[doc = "Vector reinterpret cast operation"]
48164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
48165#[inline]
48166#[cfg(target_endian = "big")]
48167#[target_feature(enable = "neon")]
48168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48170#[cfg_attr(
48171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48172 assert_instr(nop)
48173)]
48174#[cfg_attr(
48175 not(target_arch = "arm"),
48176 stable(feature = "neon_intrinsics", since = "1.59.0")
48177)]
48178#[cfg_attr(
48179 target_arch = "arm",
48180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48181)]
48182pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
48183 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48184 unsafe {
48185 let ret_val: int16x8_t = transmute(a);
48186 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48187 }
48188}
48189#[doc = "Vector reinterpret cast operation"]
48190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
48191#[inline]
48192#[cfg(target_endian = "little")]
48193#[target_feature(enable = "neon")]
48194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48196#[cfg_attr(
48197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48198 assert_instr(nop)
48199)]
48200#[cfg_attr(
48201 not(target_arch = "arm"),
48202 stable(feature = "neon_intrinsics", since = "1.59.0")
48203)]
48204#[cfg_attr(
48205 target_arch = "arm",
48206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48207)]
48208pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
48209 unsafe { transmute(a) }
48210}
48211#[doc = "Vector reinterpret cast operation"]
48212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
48213#[inline]
48214#[cfg(target_endian = "big")]
48215#[target_feature(enable = "neon")]
48216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48218#[cfg_attr(
48219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48220 assert_instr(nop)
48221)]
48222#[cfg_attr(
48223 not(target_arch = "arm"),
48224 stable(feature = "neon_intrinsics", since = "1.59.0")
48225)]
48226#[cfg_attr(
48227 target_arch = "arm",
48228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48229)]
48230pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
48231 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48232 unsafe {
48233 let ret_val: int32x4_t = transmute(a);
48234 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48235 }
48236}
48237#[doc = "Vector reinterpret cast operation"]
48238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
48239#[inline]
48240#[cfg(target_endian = "little")]
48241#[target_feature(enable = "neon")]
48242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48244#[cfg_attr(
48245 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48246 assert_instr(nop)
48247)]
48248#[cfg_attr(
48249 not(target_arch = "arm"),
48250 stable(feature = "neon_intrinsics", since = "1.59.0")
48251)]
48252#[cfg_attr(
48253 target_arch = "arm",
48254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48255)]
48256pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
48257 unsafe { transmute(a) }
48258}
48259#[doc = "Vector reinterpret cast operation"]
48260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
48261#[inline]
48262#[cfg(target_endian = "big")]
48263#[target_feature(enable = "neon")]
48264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48266#[cfg_attr(
48267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48268 assert_instr(nop)
48269)]
48270#[cfg_attr(
48271 not(target_arch = "arm"),
48272 stable(feature = "neon_intrinsics", since = "1.59.0")
48273)]
48274#[cfg_attr(
48275 target_arch = "arm",
48276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48277)]
48278pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
48279 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48280 unsafe {
48281 let ret_val: int64x2_t = transmute(a);
48282 simd_shuffle!(ret_val, ret_val, [1, 0])
48283 }
48284}
48285#[doc = "Vector reinterpret cast operation"]
48286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
48287#[inline]
48288#[cfg(target_endian = "little")]
48289#[target_feature(enable = "neon")]
48290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48292#[cfg_attr(
48293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48294 assert_instr(nop)
48295)]
48296#[cfg_attr(
48297 not(target_arch = "arm"),
48298 stable(feature = "neon_intrinsics", since = "1.59.0")
48299)]
48300#[cfg_attr(
48301 target_arch = "arm",
48302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48303)]
48304pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
48305 unsafe { transmute(a) }
48306}
48307#[doc = "Vector reinterpret cast operation"]
48308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
48309#[inline]
48310#[cfg(target_endian = "big")]
48311#[target_feature(enable = "neon")]
48312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48313#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48314#[cfg_attr(
48315 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48316 assert_instr(nop)
48317)]
48318#[cfg_attr(
48319 not(target_arch = "arm"),
48320 stable(feature = "neon_intrinsics", since = "1.59.0")
48321)]
48322#[cfg_attr(
48323 target_arch = "arm",
48324 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48325)]
48326pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
48327 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48328 unsafe {
48329 let ret_val: uint8x16_t = transmute(a);
48330 simd_shuffle!(
48331 ret_val,
48332 ret_val,
48333 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48334 )
48335 }
48336}
48337#[doc = "Vector reinterpret cast operation"]
48338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
48339#[inline]
48340#[cfg(target_endian = "little")]
48341#[target_feature(enable = "neon")]
48342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48343#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48344#[cfg_attr(
48345 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48346 assert_instr(nop)
48347)]
48348#[cfg_attr(
48349 not(target_arch = "arm"),
48350 stable(feature = "neon_intrinsics", since = "1.59.0")
48351)]
48352#[cfg_attr(
48353 target_arch = "arm",
48354 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48355)]
48356pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
48357 unsafe { transmute(a) }
48358}
48359#[doc = "Vector reinterpret cast operation"]
48360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
48361#[inline]
48362#[cfg(target_endian = "big")]
48363#[target_feature(enable = "neon")]
48364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48366#[cfg_attr(
48367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48368 assert_instr(nop)
48369)]
48370#[cfg_attr(
48371 not(target_arch = "arm"),
48372 stable(feature = "neon_intrinsics", since = "1.59.0")
48373)]
48374#[cfg_attr(
48375 target_arch = "arm",
48376 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48377)]
48378pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
48379 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48380 unsafe {
48381 let ret_val: uint16x8_t = transmute(a);
48382 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48383 }
48384}
48385#[doc = "Vector reinterpret cast operation"]
48386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
48387#[inline]
48388#[cfg(target_endian = "little")]
48389#[target_feature(enable = "neon")]
48390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48392#[cfg_attr(
48393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48394 assert_instr(nop)
48395)]
48396#[cfg_attr(
48397 not(target_arch = "arm"),
48398 stable(feature = "neon_intrinsics", since = "1.59.0")
48399)]
48400#[cfg_attr(
48401 target_arch = "arm",
48402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48403)]
48404pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
48405 unsafe { transmute(a) }
48406}
48407#[doc = "Vector reinterpret cast operation"]
48408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
48409#[inline]
48410#[cfg(target_endian = "big")]
48411#[target_feature(enable = "neon")]
48412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48414#[cfg_attr(
48415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48416 assert_instr(nop)
48417)]
48418#[cfg_attr(
48419 not(target_arch = "arm"),
48420 stable(feature = "neon_intrinsics", since = "1.59.0")
48421)]
48422#[cfg_attr(
48423 target_arch = "arm",
48424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48425)]
48426pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
48427 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48428 unsafe {
48429 let ret_val: uint32x4_t = transmute(a);
48430 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48431 }
48432}
48433#[doc = "Vector reinterpret cast operation"]
48434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
48435#[inline]
48436#[cfg(target_endian = "little")]
48437#[target_feature(enable = "neon")]
48438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48440#[cfg_attr(
48441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48442 assert_instr(nop)
48443)]
48444#[cfg_attr(
48445 not(target_arch = "arm"),
48446 stable(feature = "neon_intrinsics", since = "1.59.0")
48447)]
48448#[cfg_attr(
48449 target_arch = "arm",
48450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48451)]
48452pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
48453 unsafe { transmute(a) }
48454}
48455#[doc = "Vector reinterpret cast operation"]
48456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
48457#[inline]
48458#[cfg(target_endian = "big")]
48459#[target_feature(enable = "neon")]
48460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48462#[cfg_attr(
48463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48464 assert_instr(nop)
48465)]
48466#[cfg_attr(
48467 not(target_arch = "arm"),
48468 stable(feature = "neon_intrinsics", since = "1.59.0")
48469)]
48470#[cfg_attr(
48471 target_arch = "arm",
48472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48473)]
48474pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
48475 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48476 unsafe {
48477 let ret_val: uint64x2_t = transmute(a);
48478 simd_shuffle!(ret_val, ret_val, [1, 0])
48479 }
48480}
48481#[doc = "Vector reinterpret cast operation"]
48482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
48483#[inline]
48484#[cfg(target_endian = "little")]
48485#[target_feature(enable = "neon")]
48486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48488#[cfg_attr(
48489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48490 assert_instr(nop)
48491)]
48492#[cfg_attr(
48493 not(target_arch = "arm"),
48494 stable(feature = "neon_intrinsics", since = "1.59.0")
48495)]
48496#[cfg_attr(
48497 target_arch = "arm",
48498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48499)]
48500pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
48501 unsafe { transmute(a) }
48502}
48503#[doc = "Vector reinterpret cast operation"]
48504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
48505#[inline]
48506#[cfg(target_endian = "big")]
48507#[target_feature(enable = "neon")]
48508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48510#[cfg_attr(
48511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48512 assert_instr(nop)
48513)]
48514#[cfg_attr(
48515 not(target_arch = "arm"),
48516 stable(feature = "neon_intrinsics", since = "1.59.0")
48517)]
48518#[cfg_attr(
48519 target_arch = "arm",
48520 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48521)]
48522pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
48523 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48524 unsafe {
48525 let ret_val: poly8x16_t = transmute(a);
48526 simd_shuffle!(
48527 ret_val,
48528 ret_val,
48529 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48530 )
48531 }
48532}
48533#[doc = "Vector reinterpret cast operation"]
48534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
48535#[inline]
48536#[cfg(target_endian = "little")]
48537#[target_feature(enable = "neon,aes")]
48538#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48540#[cfg_attr(
48541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48542 assert_instr(nop)
48543)]
48544#[cfg_attr(
48545 not(target_arch = "arm"),
48546 stable(feature = "neon_intrinsics", since = "1.59.0")
48547)]
48548#[cfg_attr(
48549 target_arch = "arm",
48550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48551)]
48552pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
48553 unsafe { transmute(a) }
48554}
48555#[doc = "Vector reinterpret cast operation"]
48556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
48557#[inline]
48558#[cfg(target_endian = "big")]
48559#[target_feature(enable = "neon,aes")]
48560#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48562#[cfg_attr(
48563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48564 assert_instr(nop)
48565)]
48566#[cfg_attr(
48567 not(target_arch = "arm"),
48568 stable(feature = "neon_intrinsics", since = "1.59.0")
48569)]
48570#[cfg_attr(
48571 target_arch = "arm",
48572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48573)]
48574pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
48575 unsafe {
48576 let ret_val: int8x16_t = transmute(a);
48577 simd_shuffle!(
48578 ret_val,
48579 ret_val,
48580 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48581 )
48582 }
48583}
48584#[doc = "Vector reinterpret cast operation"]
48585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
48586#[inline]
48587#[cfg(target_endian = "little")]
48588#[target_feature(enable = "neon,aes")]
48589#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48591#[cfg_attr(
48592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48593 assert_instr(nop)
48594)]
48595#[cfg_attr(
48596 not(target_arch = "arm"),
48597 stable(feature = "neon_intrinsics", since = "1.59.0")
48598)]
48599#[cfg_attr(
48600 target_arch = "arm",
48601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48602)]
48603pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
48604 unsafe { transmute(a) }
48605}
48606#[doc = "Vector reinterpret cast operation"]
48607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
48608#[inline]
48609#[cfg(target_endian = "big")]
48610#[target_feature(enable = "neon,aes")]
48611#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48613#[cfg_attr(
48614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48615 assert_instr(nop)
48616)]
48617#[cfg_attr(
48618 not(target_arch = "arm"),
48619 stable(feature = "neon_intrinsics", since = "1.59.0")
48620)]
48621#[cfg_attr(
48622 target_arch = "arm",
48623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48624)]
48625pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
48626 unsafe {
48627 let ret_val: int16x8_t = transmute(a);
48628 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48629 }
48630}
48631#[doc = "Vector reinterpret cast operation"]
48632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
48633#[inline]
48634#[cfg(target_endian = "little")]
48635#[target_feature(enable = "neon,aes")]
48636#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48638#[cfg_attr(
48639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48640 assert_instr(nop)
48641)]
48642#[cfg_attr(
48643 not(target_arch = "arm"),
48644 stable(feature = "neon_intrinsics", since = "1.59.0")
48645)]
48646#[cfg_attr(
48647 target_arch = "arm",
48648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48649)]
48650pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
48651 unsafe { transmute(a) }
48652}
48653#[doc = "Vector reinterpret cast operation"]
48654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
48655#[inline]
48656#[cfg(target_endian = "big")]
48657#[target_feature(enable = "neon,aes")]
48658#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48660#[cfg_attr(
48661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48662 assert_instr(nop)
48663)]
48664#[cfg_attr(
48665 not(target_arch = "arm"),
48666 stable(feature = "neon_intrinsics", since = "1.59.0")
48667)]
48668#[cfg_attr(
48669 target_arch = "arm",
48670 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48671)]
48672pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
48673 unsafe {
48674 let ret_val: int32x4_t = transmute(a);
48675 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48676 }
48677}
48678#[doc = "Vector reinterpret cast operation"]
48679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
48680#[inline]
48681#[cfg(target_endian = "little")]
48682#[target_feature(enable = "neon,aes")]
48683#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48685#[cfg_attr(
48686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48687 assert_instr(nop)
48688)]
48689#[cfg_attr(
48690 not(target_arch = "arm"),
48691 stable(feature = "neon_intrinsics", since = "1.59.0")
48692)]
48693#[cfg_attr(
48694 target_arch = "arm",
48695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48696)]
48697pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
48698 unsafe { transmute(a) }
48699}
48700#[doc = "Vector reinterpret cast operation"]
48701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
48702#[inline]
48703#[cfg(target_endian = "big")]
48704#[target_feature(enable = "neon,aes")]
48705#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48707#[cfg_attr(
48708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48709 assert_instr(nop)
48710)]
48711#[cfg_attr(
48712 not(target_arch = "arm"),
48713 stable(feature = "neon_intrinsics", since = "1.59.0")
48714)]
48715#[cfg_attr(
48716 target_arch = "arm",
48717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48718)]
48719pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
48720 unsafe {
48721 let ret_val: int64x2_t = transmute(a);
48722 simd_shuffle!(ret_val, ret_val, [1, 0])
48723 }
48724}
48725#[doc = "Vector reinterpret cast operation"]
48726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
48727#[inline]
48728#[cfg(target_endian = "little")]
48729#[target_feature(enable = "neon,aes")]
48730#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48732#[cfg_attr(
48733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48734 assert_instr(nop)
48735)]
48736#[cfg_attr(
48737 not(target_arch = "arm"),
48738 stable(feature = "neon_intrinsics", since = "1.59.0")
48739)]
48740#[cfg_attr(
48741 target_arch = "arm",
48742 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48743)]
48744pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
48745 unsafe { transmute(a) }
48746}
48747#[doc = "Vector reinterpret cast operation"]
48748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
48749#[inline]
48750#[cfg(target_endian = "big")]
48751#[target_feature(enable = "neon,aes")]
48752#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48754#[cfg_attr(
48755 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48756 assert_instr(nop)
48757)]
48758#[cfg_attr(
48759 not(target_arch = "arm"),
48760 stable(feature = "neon_intrinsics", since = "1.59.0")
48761)]
48762#[cfg_attr(
48763 target_arch = "arm",
48764 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48765)]
48766pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
48767 unsafe {
48768 let ret_val: uint8x16_t = transmute(a);
48769 simd_shuffle!(
48770 ret_val,
48771 ret_val,
48772 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48773 )
48774 }
48775}
48776#[doc = "Vector reinterpret cast operation"]
48777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
48778#[inline]
48779#[cfg(target_endian = "little")]
48780#[target_feature(enable = "neon,aes")]
48781#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48783#[cfg_attr(
48784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48785 assert_instr(nop)
48786)]
48787#[cfg_attr(
48788 not(target_arch = "arm"),
48789 stable(feature = "neon_intrinsics", since = "1.59.0")
48790)]
48791#[cfg_attr(
48792 target_arch = "arm",
48793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48794)]
48795pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
48796 unsafe { transmute(a) }
48797}
48798#[doc = "Vector reinterpret cast operation"]
48799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
48800#[inline]
48801#[cfg(target_endian = "big")]
48802#[target_feature(enable = "neon,aes")]
48803#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48804#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48805#[cfg_attr(
48806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48807 assert_instr(nop)
48808)]
48809#[cfg_attr(
48810 not(target_arch = "arm"),
48811 stable(feature = "neon_intrinsics", since = "1.59.0")
48812)]
48813#[cfg_attr(
48814 target_arch = "arm",
48815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48816)]
48817pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
48818 unsafe {
48819 let ret_val: uint16x8_t = transmute(a);
48820 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48821 }
48822}
48823#[doc = "Vector reinterpret cast operation"]
48824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
48825#[inline]
48826#[cfg(target_endian = "little")]
48827#[target_feature(enable = "neon,aes")]
48828#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48830#[cfg_attr(
48831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48832 assert_instr(nop)
48833)]
48834#[cfg_attr(
48835 not(target_arch = "arm"),
48836 stable(feature = "neon_intrinsics", since = "1.59.0")
48837)]
48838#[cfg_attr(
48839 target_arch = "arm",
48840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48841)]
48842pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
48843 unsafe { transmute(a) }
48844}
48845#[doc = "Vector reinterpret cast operation"]
48846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
48847#[inline]
48848#[cfg(target_endian = "big")]
48849#[target_feature(enable = "neon,aes")]
48850#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48852#[cfg_attr(
48853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48854 assert_instr(nop)
48855)]
48856#[cfg_attr(
48857 not(target_arch = "arm"),
48858 stable(feature = "neon_intrinsics", since = "1.59.0")
48859)]
48860#[cfg_attr(
48861 target_arch = "arm",
48862 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48863)]
48864pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
48865 unsafe {
48866 let ret_val: uint32x4_t = transmute(a);
48867 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48868 }
48869}
48870#[doc = "Vector reinterpret cast operation"]
48871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
48872#[inline]
48873#[cfg(target_endian = "little")]
48874#[target_feature(enable = "neon,aes")]
48875#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48877#[cfg_attr(
48878 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48879 assert_instr(nop)
48880)]
48881#[cfg_attr(
48882 not(target_arch = "arm"),
48883 stable(feature = "neon_intrinsics", since = "1.59.0")
48884)]
48885#[cfg_attr(
48886 target_arch = "arm",
48887 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48888)]
48889pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
48890 unsafe { transmute(a) }
48891}
48892#[doc = "Vector reinterpret cast operation"]
48893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
48894#[inline]
48895#[cfg(target_endian = "big")]
48896#[target_feature(enable = "neon,aes")]
48897#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48899#[cfg_attr(
48900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48901 assert_instr(nop)
48902)]
48903#[cfg_attr(
48904 not(target_arch = "arm"),
48905 stable(feature = "neon_intrinsics", since = "1.59.0")
48906)]
48907#[cfg_attr(
48908 target_arch = "arm",
48909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48910)]
48911pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
48912 unsafe {
48913 let ret_val: uint64x2_t = transmute(a);
48914 simd_shuffle!(ret_val, ret_val, [1, 0])
48915 }
48916}
48917#[doc = "Vector reinterpret cast operation"]
48918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
48919#[inline]
48920#[cfg(target_endian = "little")]
48921#[target_feature(enable = "neon,aes")]
48922#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48924#[cfg_attr(
48925 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48926 assert_instr(nop)
48927)]
48928#[cfg_attr(
48929 not(target_arch = "arm"),
48930 stable(feature = "neon_intrinsics", since = "1.59.0")
48931)]
48932#[cfg_attr(
48933 target_arch = "arm",
48934 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48935)]
48936pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
48937 unsafe { transmute(a) }
48938}
48939#[doc = "Vector reinterpret cast operation"]
48940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
48941#[inline]
48942#[cfg(target_endian = "big")]
48943#[target_feature(enable = "neon,aes")]
48944#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48946#[cfg_attr(
48947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48948 assert_instr(nop)
48949)]
48950#[cfg_attr(
48951 not(target_arch = "arm"),
48952 stable(feature = "neon_intrinsics", since = "1.59.0")
48953)]
48954#[cfg_attr(
48955 target_arch = "arm",
48956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48957)]
48958pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
48959 unsafe {
48960 let ret_val: poly8x16_t = transmute(a);
48961 simd_shuffle!(
48962 ret_val,
48963 ret_val,
48964 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48965 )
48966 }
48967}
48968#[doc = "Vector reinterpret cast operation"]
48969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
48970#[inline]
48971#[cfg(target_endian = "little")]
48972#[target_feature(enable = "neon,aes")]
48973#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48975#[cfg_attr(
48976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48977 assert_instr(nop)
48978)]
48979#[cfg_attr(
48980 not(target_arch = "arm"),
48981 stable(feature = "neon_intrinsics", since = "1.59.0")
48982)]
48983#[cfg_attr(
48984 target_arch = "arm",
48985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48986)]
48987pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
48988 unsafe { transmute(a) }
48989}
48990#[doc = "Vector reinterpret cast operation"]
48991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
48992#[inline]
48993#[cfg(target_endian = "big")]
48994#[target_feature(enable = "neon,aes")]
48995#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
48996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48997#[cfg_attr(
48998 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48999 assert_instr(nop)
49000)]
49001#[cfg_attr(
49002 not(target_arch = "arm"),
49003 stable(feature = "neon_intrinsics", since = "1.59.0")
49004)]
49005#[cfg_attr(
49006 target_arch = "arm",
49007 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49008)]
49009pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
49010 unsafe {
49011 let ret_val: poly16x8_t = transmute(a);
49012 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49013 }
49014}
49015#[doc = "Vector reinterpret cast operation"]
49016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
49017#[inline]
49018#[cfg(target_endian = "little")]
49019#[target_feature(enable = "neon,aes")]
49020#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49022#[cfg_attr(
49023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49024 assert_instr(nop)
49025)]
49026#[cfg_attr(
49027 not(target_arch = "arm"),
49028 stable(feature = "neon_intrinsics", since = "1.59.0")
49029)]
49030#[cfg_attr(
49031 target_arch = "arm",
49032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49033)]
49034pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
49035 unsafe { transmute(a) }
49036}
49037#[doc = "Vector reinterpret cast operation"]
49038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
49039#[inline]
49040#[cfg(target_endian = "big")]
49041#[target_feature(enable = "neon,aes")]
49042#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49043#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49044#[cfg_attr(
49045 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49046 assert_instr(nop)
49047)]
49048#[cfg_attr(
49049 not(target_arch = "arm"),
49050 stable(feature = "neon_intrinsics", since = "1.59.0")
49051)]
49052#[cfg_attr(
49053 target_arch = "arm",
49054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49055)]
49056pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
49057 unsafe {
49058 let ret_val: poly64x2_t = transmute(a);
49059 simd_shuffle!(ret_val, ret_val, [1, 0])
49060 }
49061}
49062#[doc = "Vector reinterpret cast operation"]
49063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
49064#[inline]
49065#[cfg(target_endian = "little")]
49066#[target_feature(enable = "neon,aes")]
49067#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49069#[cfg_attr(
49070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49071 assert_instr(nop)
49072)]
49073#[cfg_attr(
49074 not(target_arch = "arm"),
49075 stable(feature = "neon_intrinsics", since = "1.59.0")
49076)]
49077#[cfg_attr(
49078 target_arch = "arm",
49079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49080)]
49081pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
49082 unsafe { transmute(a) }
49083}
49084#[doc = "Vector reinterpret cast operation"]
49085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
49086#[inline]
49087#[cfg(target_endian = "big")]
49088#[target_feature(enable = "neon,aes")]
49089#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49091#[cfg_attr(
49092 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49093 assert_instr(nop)
49094)]
49095#[cfg_attr(
49096 not(target_arch = "arm"),
49097 stable(feature = "neon_intrinsics", since = "1.59.0")
49098)]
49099#[cfg_attr(
49100 target_arch = "arm",
49101 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49102)]
49103pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
49104 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49105 unsafe { transmute(a) }
49106}
49107#[doc = "Vector reinterpret cast operation"]
49108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
49109#[inline]
49110#[cfg(target_endian = "little")]
49111#[target_feature(enable = "neon,aes")]
49112#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49114#[cfg_attr(
49115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49116 assert_instr(nop)
49117)]
49118#[cfg_attr(
49119 not(target_arch = "arm"),
49120 stable(feature = "neon_intrinsics", since = "1.59.0")
49121)]
49122#[cfg_attr(
49123 target_arch = "arm",
49124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49125)]
49126pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
49127 unsafe { transmute(a) }
49128}
49129#[doc = "Vector reinterpret cast operation"]
49130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
49131#[inline]
49132#[cfg(target_endian = "big")]
49133#[target_feature(enable = "neon,aes")]
49134#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49136#[cfg_attr(
49137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49138 assert_instr(nop)
49139)]
49140#[cfg_attr(
49141 not(target_arch = "arm"),
49142 stable(feature = "neon_intrinsics", since = "1.59.0")
49143)]
49144#[cfg_attr(
49145 target_arch = "arm",
49146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49147)]
49148pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
49149 let a: int8x16_t =
49150 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49151 unsafe { transmute(a) }
49152}
49153#[doc = "Vector reinterpret cast operation"]
49154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
49155#[inline]
49156#[cfg(target_endian = "little")]
49157#[target_feature(enable = "neon,aes")]
49158#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49160#[cfg_attr(
49161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49162 assert_instr(nop)
49163)]
49164#[cfg_attr(
49165 not(target_arch = "arm"),
49166 stable(feature = "neon_intrinsics", since = "1.59.0")
49167)]
49168#[cfg_attr(
49169 target_arch = "arm",
49170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49171)]
49172pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
49173 unsafe { transmute(a) }
49174}
49175#[doc = "Vector reinterpret cast operation"]
49176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
49177#[inline]
49178#[cfg(target_endian = "big")]
49179#[target_feature(enable = "neon,aes")]
49180#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49182#[cfg_attr(
49183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49184 assert_instr(nop)
49185)]
49186#[cfg_attr(
49187 not(target_arch = "arm"),
49188 stable(feature = "neon_intrinsics", since = "1.59.0")
49189)]
49190#[cfg_attr(
49191 target_arch = "arm",
49192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49193)]
49194pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
49195 let a: int8x16_t =
49196 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49197 unsafe {
49198 let ret_val: poly64x2_t = transmute(a);
49199 simd_shuffle!(ret_val, ret_val, [1, 0])
49200 }
49201}
49202#[doc = "Vector reinterpret cast operation"]
49203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
49204#[inline]
49205#[cfg(target_endian = "little")]
49206#[target_feature(enable = "neon,aes")]
49207#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49209#[cfg_attr(
49210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49211 assert_instr(nop)
49212)]
49213#[cfg_attr(
49214 not(target_arch = "arm"),
49215 stable(feature = "neon_intrinsics", since = "1.59.0")
49216)]
49217#[cfg_attr(
49218 target_arch = "arm",
49219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49220)]
49221pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
49222 unsafe { transmute(a) }
49223}
49224#[doc = "Vector reinterpret cast operation"]
49225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
49226#[inline]
49227#[cfg(target_endian = "big")]
49228#[target_feature(enable = "neon,aes")]
49229#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49231#[cfg_attr(
49232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49233 assert_instr(nop)
49234)]
49235#[cfg_attr(
49236 not(target_arch = "arm"),
49237 stable(feature = "neon_intrinsics", since = "1.59.0")
49238)]
49239#[cfg_attr(
49240 target_arch = "arm",
49241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49242)]
49243pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
49244 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49245 unsafe { transmute(a) }
49246}
49247#[doc = "Vector reinterpret cast operation"]
49248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
49249#[inline]
49250#[cfg(target_endian = "little")]
49251#[target_feature(enable = "neon,aes")]
49252#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49254#[cfg_attr(
49255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49256 assert_instr(nop)
49257)]
49258#[cfg_attr(
49259 not(target_arch = "arm"),
49260 stable(feature = "neon_intrinsics", since = "1.59.0")
49261)]
49262#[cfg_attr(
49263 target_arch = "arm",
49264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49265)]
49266pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
49267 unsafe { transmute(a) }
49268}
49269#[doc = "Vector reinterpret cast operation"]
49270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
49271#[inline]
49272#[cfg(target_endian = "big")]
49273#[target_feature(enable = "neon,aes")]
49274#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49276#[cfg_attr(
49277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49278 assert_instr(nop)
49279)]
49280#[cfg_attr(
49281 not(target_arch = "arm"),
49282 stable(feature = "neon_intrinsics", since = "1.59.0")
49283)]
49284#[cfg_attr(
49285 target_arch = "arm",
49286 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49287)]
49288pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
49289 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49290 unsafe { transmute(a) }
49291}
49292#[doc = "Vector reinterpret cast operation"]
49293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
49294#[inline]
49295#[cfg(target_endian = "little")]
49296#[target_feature(enable = "neon,aes")]
49297#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49299#[cfg_attr(
49300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49301 assert_instr(nop)
49302)]
49303#[cfg_attr(
49304 not(target_arch = "arm"),
49305 stable(feature = "neon_intrinsics", since = "1.59.0")
49306)]
49307#[cfg_attr(
49308 target_arch = "arm",
49309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49310)]
49311pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
49312 unsafe { transmute(a) }
49313}
49314#[doc = "Vector reinterpret cast operation"]
49315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
49316#[inline]
49317#[cfg(target_endian = "big")]
49318#[target_feature(enable = "neon,aes")]
49319#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49321#[cfg_attr(
49322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49323 assert_instr(nop)
49324)]
49325#[cfg_attr(
49326 not(target_arch = "arm"),
49327 stable(feature = "neon_intrinsics", since = "1.59.0")
49328)]
49329#[cfg_attr(
49330 target_arch = "arm",
49331 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49332)]
49333pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
49334 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49335 unsafe {
49336 let ret_val: poly64x2_t = transmute(a);
49337 simd_shuffle!(ret_val, ret_val, [1, 0])
49338 }
49339}
49340#[doc = "Vector reinterpret cast operation"]
49341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
49342#[inline]
49343#[cfg(target_endian = "little")]
49344#[target_feature(enable = "neon,aes")]
49345#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49347#[cfg_attr(
49348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49349 assert_instr(nop)
49350)]
49351#[cfg_attr(
49352 not(target_arch = "arm"),
49353 stable(feature = "neon_intrinsics", since = "1.59.0")
49354)]
49355#[cfg_attr(
49356 target_arch = "arm",
49357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49358)]
49359pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
49360 unsafe { transmute(a) }
49361}
49362#[doc = "Vector reinterpret cast operation"]
49363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
49364#[inline]
49365#[cfg(target_endian = "big")]
49366#[target_feature(enable = "neon,aes")]
49367#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49369#[cfg_attr(
49370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49371 assert_instr(nop)
49372)]
49373#[cfg_attr(
49374 not(target_arch = "arm"),
49375 stable(feature = "neon_intrinsics", since = "1.59.0")
49376)]
49377#[cfg_attr(
49378 target_arch = "arm",
49379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49380)]
49381pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
49382 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49383 unsafe { transmute(a) }
49384}
49385#[doc = "Vector reinterpret cast operation"]
49386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
49387#[inline]
49388#[cfg(target_endian = "little")]
49389#[target_feature(enable = "neon,aes")]
49390#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49392#[cfg_attr(
49393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49394 assert_instr(nop)
49395)]
49396#[cfg_attr(
49397 not(target_arch = "arm"),
49398 stable(feature = "neon_intrinsics", since = "1.59.0")
49399)]
49400#[cfg_attr(
49401 target_arch = "arm",
49402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49403)]
49404pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
49405 unsafe { transmute(a) }
49406}
49407#[doc = "Vector reinterpret cast operation"]
49408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
49409#[inline]
49410#[cfg(target_endian = "big")]
49411#[target_feature(enable = "neon,aes")]
49412#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49414#[cfg_attr(
49415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49416 assert_instr(nop)
49417)]
49418#[cfg_attr(
49419 not(target_arch = "arm"),
49420 stable(feature = "neon_intrinsics", since = "1.59.0")
49421)]
49422#[cfg_attr(
49423 target_arch = "arm",
49424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49425)]
49426pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
49427 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49428 unsafe { transmute(a) }
49429}
49430#[doc = "Vector reinterpret cast operation"]
49431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
49432#[inline]
49433#[cfg(target_endian = "little")]
49434#[target_feature(enable = "neon,aes")]
49435#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49437#[cfg_attr(
49438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49439 assert_instr(nop)
49440)]
49441#[cfg_attr(
49442 not(target_arch = "arm"),
49443 stable(feature = "neon_intrinsics", since = "1.59.0")
49444)]
49445#[cfg_attr(
49446 target_arch = "arm",
49447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49448)]
49449pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
49450 unsafe { transmute(a) }
49451}
49452#[doc = "Vector reinterpret cast operation"]
49453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
49454#[inline]
49455#[cfg(target_endian = "big")]
49456#[target_feature(enable = "neon,aes")]
49457#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49459#[cfg_attr(
49460 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49461 assert_instr(nop)
49462)]
49463#[cfg_attr(
49464 not(target_arch = "arm"),
49465 stable(feature = "neon_intrinsics", since = "1.59.0")
49466)]
49467#[cfg_attr(
49468 target_arch = "arm",
49469 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49470)]
49471pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
49472 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49473 unsafe {
49474 let ret_val: poly64x2_t = transmute(a);
49475 simd_shuffle!(ret_val, ret_val, [1, 0])
49476 }
49477}
49478#[doc = "Vector reinterpret cast operation"]
49479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
49480#[inline]
49481#[cfg(target_endian = "little")]
49482#[target_feature(enable = "neon,aes")]
49483#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49485#[cfg_attr(
49486 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49487 assert_instr(nop)
49488)]
49489#[cfg_attr(
49490 not(target_arch = "arm"),
49491 stable(feature = "neon_intrinsics", since = "1.59.0")
49492)]
49493#[cfg_attr(
49494 target_arch = "arm",
49495 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49496)]
49497pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
49498 unsafe { transmute(a) }
49499}
49500#[doc = "Vector reinterpret cast operation"]
49501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
49502#[inline]
49503#[cfg(target_endian = "big")]
49504#[target_feature(enable = "neon,aes")]
49505#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49507#[cfg_attr(
49508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49509 assert_instr(nop)
49510)]
49511#[cfg_attr(
49512 not(target_arch = "arm"),
49513 stable(feature = "neon_intrinsics", since = "1.59.0")
49514)]
49515#[cfg_attr(
49516 target_arch = "arm",
49517 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49518)]
49519pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
49520 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49521 unsafe { transmute(a) }
49522}
49523#[doc = "Vector reinterpret cast operation"]
49524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
49525#[inline]
49526#[cfg(target_endian = "little")]
49527#[target_feature(enable = "neon,aes")]
49528#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49530#[cfg_attr(
49531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49532 assert_instr(nop)
49533)]
49534#[cfg_attr(
49535 not(target_arch = "arm"),
49536 stable(feature = "neon_intrinsics", since = "1.59.0")
49537)]
49538#[cfg_attr(
49539 target_arch = "arm",
49540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49541)]
49542pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
49543 unsafe { transmute(a) }
49544}
49545#[doc = "Vector reinterpret cast operation"]
49546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
49547#[inline]
49548#[cfg(target_endian = "big")]
49549#[target_feature(enable = "neon,aes")]
49550#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49552#[cfg_attr(
49553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49554 assert_instr(nop)
49555)]
49556#[cfg_attr(
49557 not(target_arch = "arm"),
49558 stable(feature = "neon_intrinsics", since = "1.59.0")
49559)]
49560#[cfg_attr(
49561 target_arch = "arm",
49562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49563)]
49564pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
49565 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49566 unsafe { transmute(a) }
49567}
49568#[doc = "Vector reinterpret cast operation"]
49569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
49570#[inline]
49571#[cfg(target_endian = "little")]
49572#[target_feature(enable = "neon,aes")]
49573#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49575#[cfg_attr(
49576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49577 assert_instr(nop)
49578)]
49579#[cfg_attr(
49580 not(target_arch = "arm"),
49581 stable(feature = "neon_intrinsics", since = "1.59.0")
49582)]
49583#[cfg_attr(
49584 target_arch = "arm",
49585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49586)]
49587pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
49588 unsafe { transmute(a) }
49589}
49590#[doc = "Vector reinterpret cast operation"]
49591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
49592#[inline]
49593#[cfg(target_endian = "big")]
49594#[target_feature(enable = "neon,aes")]
49595#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49597#[cfg_attr(
49598 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49599 assert_instr(nop)
49600)]
49601#[cfg_attr(
49602 not(target_arch = "arm"),
49603 stable(feature = "neon_intrinsics", since = "1.59.0")
49604)]
49605#[cfg_attr(
49606 target_arch = "arm",
49607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49608)]
49609pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
49610 let a: uint8x16_t =
49611 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49612 unsafe { transmute(a) }
49613}
49614#[doc = "Vector reinterpret cast operation"]
49615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
49616#[inline]
49617#[cfg(target_endian = "little")]
49618#[target_feature(enable = "neon,aes")]
49619#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49621#[cfg_attr(
49622 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49623 assert_instr(nop)
49624)]
49625#[cfg_attr(
49626 not(target_arch = "arm"),
49627 stable(feature = "neon_intrinsics", since = "1.59.0")
49628)]
49629#[cfg_attr(
49630 target_arch = "arm",
49631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49632)]
49633pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
49634 unsafe { transmute(a) }
49635}
49636#[doc = "Vector reinterpret cast operation"]
49637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
49638#[inline]
49639#[cfg(target_endian = "big")]
49640#[target_feature(enable = "neon,aes")]
49641#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49643#[cfg_attr(
49644 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49645 assert_instr(nop)
49646)]
49647#[cfg_attr(
49648 not(target_arch = "arm"),
49649 stable(feature = "neon_intrinsics", since = "1.59.0")
49650)]
49651#[cfg_attr(
49652 target_arch = "arm",
49653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49654)]
49655pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
49656 let a: uint8x16_t =
49657 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49658 unsafe {
49659 let ret_val: poly64x2_t = transmute(a);
49660 simd_shuffle!(ret_val, ret_val, [1, 0])
49661 }
49662}
49663#[doc = "Vector reinterpret cast operation"]
49664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
49665#[inline]
49666#[cfg(target_endian = "little")]
49667#[target_feature(enable = "neon,aes")]
49668#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49669#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49670#[cfg_attr(
49671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49672 assert_instr(nop)
49673)]
49674#[cfg_attr(
49675 not(target_arch = "arm"),
49676 stable(feature = "neon_intrinsics", since = "1.59.0")
49677)]
49678#[cfg_attr(
49679 target_arch = "arm",
49680 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49681)]
49682pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
49683 unsafe { transmute(a) }
49684}
49685#[doc = "Vector reinterpret cast operation"]
49686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
49687#[inline]
49688#[cfg(target_endian = "big")]
49689#[target_feature(enable = "neon,aes")]
49690#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49692#[cfg_attr(
49693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49694 assert_instr(nop)
49695)]
49696#[cfg_attr(
49697 not(target_arch = "arm"),
49698 stable(feature = "neon_intrinsics", since = "1.59.0")
49699)]
49700#[cfg_attr(
49701 target_arch = "arm",
49702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49703)]
49704pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
49705 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49706 unsafe { transmute(a) }
49707}
49708#[doc = "Vector reinterpret cast operation"]
49709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
49710#[inline]
49711#[cfg(target_endian = "little")]
49712#[target_feature(enable = "neon,aes")]
49713#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49714#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49715#[cfg_attr(
49716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49717 assert_instr(nop)
49718)]
49719#[cfg_attr(
49720 not(target_arch = "arm"),
49721 stable(feature = "neon_intrinsics", since = "1.59.0")
49722)]
49723#[cfg_attr(
49724 target_arch = "arm",
49725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49726)]
49727pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
49728 unsafe { transmute(a) }
49729}
49730#[doc = "Vector reinterpret cast operation"]
49731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
49732#[inline]
49733#[cfg(target_endian = "big")]
49734#[target_feature(enable = "neon,aes")]
49735#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49736#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49737#[cfg_attr(
49738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49739 assert_instr(nop)
49740)]
49741#[cfg_attr(
49742 not(target_arch = "arm"),
49743 stable(feature = "neon_intrinsics", since = "1.59.0")
49744)]
49745#[cfg_attr(
49746 target_arch = "arm",
49747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49748)]
49749pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
49750 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49751 unsafe { transmute(a) }
49752}
49753#[doc = "Vector reinterpret cast operation"]
49754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
49755#[inline]
49756#[cfg(target_endian = "little")]
49757#[target_feature(enable = "neon,aes")]
49758#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49760#[cfg_attr(
49761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49762 assert_instr(nop)
49763)]
49764#[cfg_attr(
49765 not(target_arch = "arm"),
49766 stable(feature = "neon_intrinsics", since = "1.59.0")
49767)]
49768#[cfg_attr(
49769 target_arch = "arm",
49770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49771)]
49772pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
49773 unsafe { transmute(a) }
49774}
49775#[doc = "Vector reinterpret cast operation"]
49776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
49777#[inline]
49778#[cfg(target_endian = "big")]
49779#[target_feature(enable = "neon,aes")]
49780#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49782#[cfg_attr(
49783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49784 assert_instr(nop)
49785)]
49786#[cfg_attr(
49787 not(target_arch = "arm"),
49788 stable(feature = "neon_intrinsics", since = "1.59.0")
49789)]
49790#[cfg_attr(
49791 target_arch = "arm",
49792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49793)]
49794pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
49795 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49796 unsafe {
49797 let ret_val: poly64x2_t = transmute(a);
49798 simd_shuffle!(ret_val, ret_val, [1, 0])
49799 }
49800}
49801#[doc = "Vector reinterpret cast operation"]
49802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
49803#[inline]
49804#[cfg(target_endian = "little")]
49805#[target_feature(enable = "neon,aes")]
49806#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49807#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49808#[cfg_attr(
49809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49810 assert_instr(nop)
49811)]
49812#[cfg_attr(
49813 not(target_arch = "arm"),
49814 stable(feature = "neon_intrinsics", since = "1.59.0")
49815)]
49816#[cfg_attr(
49817 target_arch = "arm",
49818 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49819)]
49820pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
49821 unsafe { transmute(a) }
49822}
49823#[doc = "Vector reinterpret cast operation"]
49824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
49825#[inline]
49826#[cfg(target_endian = "big")]
49827#[target_feature(enable = "neon,aes")]
49828#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49830#[cfg_attr(
49831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49832 assert_instr(nop)
49833)]
49834#[cfg_attr(
49835 not(target_arch = "arm"),
49836 stable(feature = "neon_intrinsics", since = "1.59.0")
49837)]
49838#[cfg_attr(
49839 target_arch = "arm",
49840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49841)]
49842pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
49843 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49844 unsafe { transmute(a) }
49845}
49846#[doc = "Vector reinterpret cast operation"]
49847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
49848#[inline]
49849#[cfg(target_endian = "little")]
49850#[target_feature(enable = "neon,aes")]
49851#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49853#[cfg_attr(
49854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49855 assert_instr(nop)
49856)]
49857#[cfg_attr(
49858 not(target_arch = "arm"),
49859 stable(feature = "neon_intrinsics", since = "1.59.0")
49860)]
49861#[cfg_attr(
49862 target_arch = "arm",
49863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49864)]
49865pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
49866 unsafe { transmute(a) }
49867}
49868#[doc = "Vector reinterpret cast operation"]
49869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
49870#[inline]
49871#[cfg(target_endian = "big")]
49872#[target_feature(enable = "neon,aes")]
49873#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49875#[cfg_attr(
49876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49877 assert_instr(nop)
49878)]
49879#[cfg_attr(
49880 not(target_arch = "arm"),
49881 stable(feature = "neon_intrinsics", since = "1.59.0")
49882)]
49883#[cfg_attr(
49884 target_arch = "arm",
49885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49886)]
49887pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
49888 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49889 unsafe { transmute(a) }
49890}
49891#[doc = "Vector reinterpret cast operation"]
49892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
49893#[inline]
49894#[cfg(target_endian = "little")]
49895#[target_feature(enable = "neon,aes")]
49896#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49897#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49898#[cfg_attr(
49899 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49900 assert_instr(nop)
49901)]
49902#[cfg_attr(
49903 not(target_arch = "arm"),
49904 stable(feature = "neon_intrinsics", since = "1.59.0")
49905)]
49906#[cfg_attr(
49907 target_arch = "arm",
49908 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49909)]
49910pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
49911 unsafe { transmute(a) }
49912}
49913#[doc = "Vector reinterpret cast operation"]
49914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
49915#[inline]
49916#[cfg(target_endian = "big")]
49917#[target_feature(enable = "neon,aes")]
49918#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49920#[cfg_attr(
49921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49922 assert_instr(nop)
49923)]
49924#[cfg_attr(
49925 not(target_arch = "arm"),
49926 stable(feature = "neon_intrinsics", since = "1.59.0")
49927)]
49928#[cfg_attr(
49929 target_arch = "arm",
49930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49931)]
49932pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
49933 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49934 unsafe {
49935 let ret_val: poly64x2_t = transmute(a);
49936 simd_shuffle!(ret_val, ret_val, [1, 0])
49937 }
49938}
49939#[doc = "Vector reinterpret cast operation"]
49940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
49941#[inline]
49942#[cfg(target_endian = "little")]
49943#[target_feature(enable = "neon,aes")]
49944#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49946#[cfg_attr(
49947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49948 assert_instr(nop)
49949)]
49950#[cfg_attr(
49951 not(target_arch = "arm"),
49952 stable(feature = "neon_intrinsics", since = "1.59.0")
49953)]
49954#[cfg_attr(
49955 target_arch = "arm",
49956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49957)]
49958pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
49959 unsafe { transmute(a) }
49960}
49961#[doc = "Vector reinterpret cast operation"]
49962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
49963#[inline]
49964#[cfg(target_endian = "big")]
49965#[target_feature(enable = "neon,aes")]
49966#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49968#[cfg_attr(
49969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49970 assert_instr(nop)
49971)]
49972#[cfg_attr(
49973 not(target_arch = "arm"),
49974 stable(feature = "neon_intrinsics", since = "1.59.0")
49975)]
49976#[cfg_attr(
49977 target_arch = "arm",
49978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49979)]
49980pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
49981 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49982 unsafe { transmute(a) }
49983}
49984#[doc = "Vector reinterpret cast operation"]
49985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
49986#[inline]
49987#[cfg(target_endian = "little")]
49988#[target_feature(enable = "neon,aes")]
49989#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
49990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49991#[cfg_attr(
49992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49993 assert_instr(nop)
49994)]
49995#[cfg_attr(
49996 not(target_arch = "arm"),
49997 stable(feature = "neon_intrinsics", since = "1.59.0")
49998)]
49999#[cfg_attr(
50000 target_arch = "arm",
50001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50002)]
50003pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
50004 unsafe { transmute(a) }
50005}
50006#[doc = "Vector reinterpret cast operation"]
50007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
50008#[inline]
50009#[cfg(target_endian = "big")]
50010#[target_feature(enable = "neon,aes")]
50011#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50013#[cfg_attr(
50014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50015 assert_instr(nop)
50016)]
50017#[cfg_attr(
50018 not(target_arch = "arm"),
50019 stable(feature = "neon_intrinsics", since = "1.59.0")
50020)]
50021#[cfg_attr(
50022 target_arch = "arm",
50023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50024)]
50025pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
50026 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50027 unsafe { transmute(a) }
50028}
50029#[doc = "Vector reinterpret cast operation"]
50030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
50031#[inline]
50032#[cfg(target_endian = "little")]
50033#[target_feature(enable = "neon,aes")]
50034#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50036#[cfg_attr(
50037 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50038 assert_instr(nop)
50039)]
50040#[cfg_attr(
50041 not(target_arch = "arm"),
50042 stable(feature = "neon_intrinsics", since = "1.59.0")
50043)]
50044#[cfg_attr(
50045 target_arch = "arm",
50046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50047)]
50048pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
50049 unsafe { transmute(a) }
50050}
50051#[doc = "Vector reinterpret cast operation"]
50052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
50053#[inline]
50054#[cfg(target_endian = "big")]
50055#[target_feature(enable = "neon,aes")]
50056#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50058#[cfg_attr(
50059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50060 assert_instr(nop)
50061)]
50062#[cfg_attr(
50063 not(target_arch = "arm"),
50064 stable(feature = "neon_intrinsics", since = "1.59.0")
50065)]
50066#[cfg_attr(
50067 target_arch = "arm",
50068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50069)]
50070pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
50071 let a: poly8x16_t =
50072 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50073 unsafe { transmute(a) }
50074}
50075#[doc = "Vector reinterpret cast operation"]
50076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
50077#[inline]
50078#[cfg(target_endian = "little")]
50079#[target_feature(enable = "neon,aes")]
50080#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50082#[cfg_attr(
50083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50084 assert_instr(nop)
50085)]
50086#[cfg_attr(
50087 not(target_arch = "arm"),
50088 stable(feature = "neon_intrinsics", since = "1.59.0")
50089)]
50090#[cfg_attr(
50091 target_arch = "arm",
50092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50093)]
50094pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
50095 unsafe { transmute(a) }
50096}
50097#[doc = "Vector reinterpret cast operation"]
50098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
50099#[inline]
50100#[cfg(target_endian = "big")]
50101#[target_feature(enable = "neon,aes")]
50102#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50104#[cfg_attr(
50105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50106 assert_instr(nop)
50107)]
50108#[cfg_attr(
50109 not(target_arch = "arm"),
50110 stable(feature = "neon_intrinsics", since = "1.59.0")
50111)]
50112#[cfg_attr(
50113 target_arch = "arm",
50114 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50115)]
50116pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
50117 let a: poly8x16_t =
50118 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50119 unsafe {
50120 let ret_val: poly64x2_t = transmute(a);
50121 simd_shuffle!(ret_val, ret_val, [1, 0])
50122 }
50123}
50124#[doc = "Vector reinterpret cast operation"]
50125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
50126#[inline]
50127#[cfg(target_endian = "little")]
50128#[target_feature(enable = "neon,aes")]
50129#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50130#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50131#[cfg_attr(
50132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50133 assert_instr(nop)
50134)]
50135#[cfg_attr(
50136 not(target_arch = "arm"),
50137 stable(feature = "neon_intrinsics", since = "1.59.0")
50138)]
50139#[cfg_attr(
50140 target_arch = "arm",
50141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50142)]
50143pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
50144 unsafe { transmute(a) }
50145}
50146#[doc = "Vector reinterpret cast operation"]
50147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
50148#[inline]
50149#[cfg(target_endian = "big")]
50150#[target_feature(enable = "neon,aes")]
50151#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50153#[cfg_attr(
50154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50155 assert_instr(nop)
50156)]
50157#[cfg_attr(
50158 not(target_arch = "arm"),
50159 stable(feature = "neon_intrinsics", since = "1.59.0")
50160)]
50161#[cfg_attr(
50162 target_arch = "arm",
50163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50164)]
50165pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
50166 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50167 unsafe { transmute(a) }
50168}
50169#[doc = "Vector reinterpret cast operation"]
50170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
50171#[inline]
50172#[cfg(target_endian = "little")]
50173#[target_feature(enable = "neon,aes")]
50174#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50176#[cfg_attr(
50177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50178 assert_instr(nop)
50179)]
50180#[cfg_attr(
50181 not(target_arch = "arm"),
50182 stable(feature = "neon_intrinsics", since = "1.59.0")
50183)]
50184#[cfg_attr(
50185 target_arch = "arm",
50186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50187)]
50188pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
50189 unsafe { transmute(a) }
50190}
50191#[doc = "Vector reinterpret cast operation"]
50192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
50193#[inline]
50194#[cfg(target_endian = "big")]
50195#[target_feature(enable = "neon,aes")]
50196#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50198#[cfg_attr(
50199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50200 assert_instr(nop)
50201)]
50202#[cfg_attr(
50203 not(target_arch = "arm"),
50204 stable(feature = "neon_intrinsics", since = "1.59.0")
50205)]
50206#[cfg_attr(
50207 target_arch = "arm",
50208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50209)]
50210pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
50211 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50212 unsafe { transmute(a) }
50213}
50214#[doc = "Vector reinterpret cast operation"]
50215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
50216#[inline]
50217#[cfg(target_endian = "little")]
50218#[target_feature(enable = "neon,aes")]
50219#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50221#[cfg_attr(
50222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50223 assert_instr(nop)
50224)]
50225#[cfg_attr(
50226 not(target_arch = "arm"),
50227 stable(feature = "neon_intrinsics", since = "1.59.0")
50228)]
50229#[cfg_attr(
50230 target_arch = "arm",
50231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50232)]
50233pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
50234 unsafe { transmute(a) }
50235}
50236#[doc = "Vector reinterpret cast operation"]
50237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
50238#[inline]
50239#[cfg(target_endian = "big")]
50240#[target_feature(enable = "neon,aes")]
50241#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50243#[cfg_attr(
50244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50245 assert_instr(nop)
50246)]
50247#[cfg_attr(
50248 not(target_arch = "arm"),
50249 stable(feature = "neon_intrinsics", since = "1.59.0")
50250)]
50251#[cfg_attr(
50252 target_arch = "arm",
50253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50254)]
50255pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
50256 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50257 unsafe {
50258 let ret_val: poly64x2_t = transmute(a);
50259 simd_shuffle!(ret_val, ret_val, [1, 0])
50260 }
50261}
50262#[doc = "Vector reinterpret cast operation"]
50263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
50264#[inline]
50265#[cfg(target_endian = "little")]
50266#[target_feature(enable = "neon,aes")]
50267#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50269#[cfg_attr(
50270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50271 assert_instr(nop)
50272)]
50273#[cfg_attr(
50274 not(target_arch = "arm"),
50275 stable(feature = "neon_intrinsics", since = "1.59.0")
50276)]
50277#[cfg_attr(
50278 target_arch = "arm",
50279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50280)]
50281pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
50282 unsafe { transmute(a) }
50283}
50284#[doc = "Vector reinterpret cast operation"]
50285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
50286#[inline]
50287#[cfg(target_endian = "big")]
50288#[target_feature(enable = "neon,aes")]
50289#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50290#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50291#[cfg_attr(
50292 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50293 assert_instr(nop)
50294)]
50295#[cfg_attr(
50296 not(target_arch = "arm"),
50297 stable(feature = "neon_intrinsics", since = "1.59.0")
50298)]
50299#[cfg_attr(
50300 target_arch = "arm",
50301 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50302)]
50303pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
50304 unsafe {
50305 let ret_val: int8x8_t = transmute(a);
50306 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50307 }
50308}
50309#[doc = "Vector reinterpret cast operation"]
50310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
50311#[inline]
50312#[cfg(target_endian = "little")]
50313#[target_feature(enable = "neon,aes")]
50314#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50316#[cfg_attr(
50317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50318 assert_instr(nop)
50319)]
50320#[cfg_attr(
50321 not(target_arch = "arm"),
50322 stable(feature = "neon_intrinsics", since = "1.59.0")
50323)]
50324#[cfg_attr(
50325 target_arch = "arm",
50326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50327)]
50328pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
50329 unsafe { transmute(a) }
50330}
50331#[doc = "Vector reinterpret cast operation"]
50332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
50333#[inline]
50334#[cfg(target_endian = "big")]
50335#[target_feature(enable = "neon,aes")]
50336#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50338#[cfg_attr(
50339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50340 assert_instr(nop)
50341)]
50342#[cfg_attr(
50343 not(target_arch = "arm"),
50344 stable(feature = "neon_intrinsics", since = "1.59.0")
50345)]
50346#[cfg_attr(
50347 target_arch = "arm",
50348 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50349)]
50350pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
50351 unsafe {
50352 let ret_val: int16x4_t = transmute(a);
50353 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50354 }
50355}
50356#[doc = "Vector reinterpret cast operation"]
50357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
50358#[inline]
50359#[cfg(target_endian = "little")]
50360#[target_feature(enable = "neon,aes")]
50361#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50363#[cfg_attr(
50364 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50365 assert_instr(nop)
50366)]
50367#[cfg_attr(
50368 not(target_arch = "arm"),
50369 stable(feature = "neon_intrinsics", since = "1.59.0")
50370)]
50371#[cfg_attr(
50372 target_arch = "arm",
50373 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50374)]
50375pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
50376 unsafe { transmute(a) }
50377}
50378#[doc = "Vector reinterpret cast operation"]
50379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
50380#[inline]
50381#[cfg(target_endian = "big")]
50382#[target_feature(enable = "neon,aes")]
50383#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50385#[cfg_attr(
50386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50387 assert_instr(nop)
50388)]
50389#[cfg_attr(
50390 not(target_arch = "arm"),
50391 stable(feature = "neon_intrinsics", since = "1.59.0")
50392)]
50393#[cfg_attr(
50394 target_arch = "arm",
50395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50396)]
50397pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
50398 unsafe {
50399 let ret_val: int32x2_t = transmute(a);
50400 simd_shuffle!(ret_val, ret_val, [1, 0])
50401 }
50402}
50403#[doc = "Vector reinterpret cast operation"]
50404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
50405#[inline]
50406#[cfg(target_endian = "little")]
50407#[target_feature(enable = "neon,aes")]
50408#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50410#[cfg_attr(
50411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50412 assert_instr(nop)
50413)]
50414#[cfg_attr(
50415 not(target_arch = "arm"),
50416 stable(feature = "neon_intrinsics", since = "1.59.0")
50417)]
50418#[cfg_attr(
50419 target_arch = "arm",
50420 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50421)]
50422pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
50423 unsafe { transmute(a) }
50424}
50425#[doc = "Vector reinterpret cast operation"]
50426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
50427#[inline]
50428#[cfg(target_endian = "big")]
50429#[target_feature(enable = "neon,aes")]
50430#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50432#[cfg_attr(
50433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50434 assert_instr(nop)
50435)]
50436#[cfg_attr(
50437 not(target_arch = "arm"),
50438 stable(feature = "neon_intrinsics", since = "1.59.0")
50439)]
50440#[cfg_attr(
50441 target_arch = "arm",
50442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50443)]
50444pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
50445 unsafe {
50446 let ret_val: uint8x8_t = transmute(a);
50447 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50448 }
50449}
50450#[doc = "Vector reinterpret cast operation"]
50451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
50452#[inline]
50453#[cfg(target_endian = "little")]
50454#[target_feature(enable = "neon,aes")]
50455#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50457#[cfg_attr(
50458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50459 assert_instr(nop)
50460)]
50461#[cfg_attr(
50462 not(target_arch = "arm"),
50463 stable(feature = "neon_intrinsics", since = "1.59.0")
50464)]
50465#[cfg_attr(
50466 target_arch = "arm",
50467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50468)]
50469pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
50470 unsafe { transmute(a) }
50471}
50472#[doc = "Vector reinterpret cast operation"]
50473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
50474#[inline]
50475#[cfg(target_endian = "big")]
50476#[target_feature(enable = "neon,aes")]
50477#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50479#[cfg_attr(
50480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50481 assert_instr(nop)
50482)]
50483#[cfg_attr(
50484 not(target_arch = "arm"),
50485 stable(feature = "neon_intrinsics", since = "1.59.0")
50486)]
50487#[cfg_attr(
50488 target_arch = "arm",
50489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50490)]
50491pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
50492 unsafe {
50493 let ret_val: uint16x4_t = transmute(a);
50494 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50495 }
50496}
50497#[doc = "Vector reinterpret cast operation"]
50498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
50499#[inline]
50500#[cfg(target_endian = "little")]
50501#[target_feature(enable = "neon,aes")]
50502#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50504#[cfg_attr(
50505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50506 assert_instr(nop)
50507)]
50508#[cfg_attr(
50509 not(target_arch = "arm"),
50510 stable(feature = "neon_intrinsics", since = "1.59.0")
50511)]
50512#[cfg_attr(
50513 target_arch = "arm",
50514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50515)]
50516pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
50517 unsafe { transmute(a) }
50518}
50519#[doc = "Vector reinterpret cast operation"]
50520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
50521#[inline]
50522#[cfg(target_endian = "big")]
50523#[target_feature(enable = "neon,aes")]
50524#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50526#[cfg_attr(
50527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50528 assert_instr(nop)
50529)]
50530#[cfg_attr(
50531 not(target_arch = "arm"),
50532 stable(feature = "neon_intrinsics", since = "1.59.0")
50533)]
50534#[cfg_attr(
50535 target_arch = "arm",
50536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50537)]
50538pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
50539 unsafe {
50540 let ret_val: uint32x2_t = transmute(a);
50541 simd_shuffle!(ret_val, ret_val, [1, 0])
50542 }
50543}
50544#[doc = "Vector reinterpret cast operation"]
50545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
50546#[inline]
50547#[cfg(target_endian = "little")]
50548#[target_feature(enable = "neon,aes")]
50549#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50551#[cfg_attr(
50552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50553 assert_instr(nop)
50554)]
50555#[cfg_attr(
50556 not(target_arch = "arm"),
50557 stable(feature = "neon_intrinsics", since = "1.59.0")
50558)]
50559#[cfg_attr(
50560 target_arch = "arm",
50561 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50562)]
50563pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
50564 unsafe { transmute(a) }
50565}
50566#[doc = "Vector reinterpret cast operation"]
50567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
50568#[inline]
50569#[cfg(target_endian = "big")]
50570#[target_feature(enable = "neon,aes")]
50571#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50573#[cfg_attr(
50574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50575 assert_instr(nop)
50576)]
50577#[cfg_attr(
50578 not(target_arch = "arm"),
50579 stable(feature = "neon_intrinsics", since = "1.59.0")
50580)]
50581#[cfg_attr(
50582 target_arch = "arm",
50583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50584)]
50585pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
50586 unsafe {
50587 let ret_val: poly8x8_t = transmute(a);
50588 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50589 }
50590}
50591#[doc = "Vector reinterpret cast operation"]
50592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
50593#[inline]
50594#[cfg(target_endian = "little")]
50595#[target_feature(enable = "neon,aes")]
50596#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50597#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50598#[cfg_attr(
50599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50600 assert_instr(nop)
50601)]
50602#[cfg_attr(
50603 not(target_arch = "arm"),
50604 stable(feature = "neon_intrinsics", since = "1.59.0")
50605)]
50606#[cfg_attr(
50607 target_arch = "arm",
50608 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50609)]
50610pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
50611 unsafe { transmute(a) }
50612}
50613#[doc = "Vector reinterpret cast operation"]
50614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
50615#[inline]
50616#[cfg(target_endian = "big")]
50617#[target_feature(enable = "neon,aes")]
50618#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50620#[cfg_attr(
50621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50622 assert_instr(nop)
50623)]
50624#[cfg_attr(
50625 not(target_arch = "arm"),
50626 stable(feature = "neon_intrinsics", since = "1.59.0")
50627)]
50628#[cfg_attr(
50629 target_arch = "arm",
50630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50631)]
50632pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
50633 unsafe {
50634 let ret_val: poly16x4_t = transmute(a);
50635 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50636 }
50637}
50638#[doc = "Vector reinterpret cast operation"]
50639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
50640#[inline]
50641#[cfg(target_endian = "little")]
50642#[target_feature(enable = "neon,aes")]
50643#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50645#[cfg_attr(
50646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50647 assert_instr(nop)
50648)]
50649#[cfg_attr(
50650 not(target_arch = "arm"),
50651 stable(feature = "neon_intrinsics", since = "1.59.0")
50652)]
50653#[cfg_attr(
50654 target_arch = "arm",
50655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50656)]
50657pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
50658 unsafe { transmute(a) }
50659}
50660#[doc = "Vector reinterpret cast operation"]
50661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
50662#[inline]
50663#[cfg(target_endian = "big")]
50664#[target_feature(enable = "neon,aes")]
50665#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50667#[cfg_attr(
50668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50669 assert_instr(nop)
50670)]
50671#[cfg_attr(
50672 not(target_arch = "arm"),
50673 stable(feature = "neon_intrinsics", since = "1.59.0")
50674)]
50675#[cfg_attr(
50676 target_arch = "arm",
50677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50678)]
50679pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
50680 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50681 unsafe { transmute(a) }
50682}
50683#[doc = "Vector reinterpret cast operation"]
50684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
50685#[inline]
50686#[cfg(target_endian = "little")]
50687#[target_feature(enable = "neon,aes")]
50688#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50690#[cfg_attr(
50691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50692 assert_instr(nop)
50693)]
50694#[cfg_attr(
50695 not(target_arch = "arm"),
50696 stable(feature = "neon_intrinsics", since = "1.59.0")
50697)]
50698#[cfg_attr(
50699 target_arch = "arm",
50700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50701)]
50702pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
50703 unsafe { transmute(a) }
50704}
50705#[doc = "Vector reinterpret cast operation"]
50706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
50707#[inline]
50708#[cfg(target_endian = "big")]
50709#[target_feature(enable = "neon,aes")]
50710#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50712#[cfg_attr(
50713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50714 assert_instr(nop)
50715)]
50716#[cfg_attr(
50717 not(target_arch = "arm"),
50718 stable(feature = "neon_intrinsics", since = "1.59.0")
50719)]
50720#[cfg_attr(
50721 target_arch = "arm",
50722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50723)]
50724pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
50725 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50726 unsafe {
50727 let ret_val: int8x16_t = transmute(a);
50728 simd_shuffle!(
50729 ret_val,
50730 ret_val,
50731 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50732 )
50733 }
50734}
50735#[doc = "Vector reinterpret cast operation"]
50736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
50737#[inline]
50738#[cfg(target_endian = "little")]
50739#[target_feature(enable = "neon,aes")]
50740#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50741#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50742#[cfg_attr(
50743 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50744 assert_instr(nop)
50745)]
50746#[cfg_attr(
50747 not(target_arch = "arm"),
50748 stable(feature = "neon_intrinsics", since = "1.59.0")
50749)]
50750#[cfg_attr(
50751 target_arch = "arm",
50752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50753)]
50754pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
50755 unsafe { transmute(a) }
50756}
50757#[doc = "Vector reinterpret cast operation"]
50758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
50759#[inline]
50760#[cfg(target_endian = "big")]
50761#[target_feature(enable = "neon,aes")]
50762#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50764#[cfg_attr(
50765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50766 assert_instr(nop)
50767)]
50768#[cfg_attr(
50769 not(target_arch = "arm"),
50770 stable(feature = "neon_intrinsics", since = "1.59.0")
50771)]
50772#[cfg_attr(
50773 target_arch = "arm",
50774 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50775)]
50776pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
50777 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50778 unsafe {
50779 let ret_val: int16x8_t = transmute(a);
50780 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50781 }
50782}
50783#[doc = "Vector reinterpret cast operation"]
50784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
50785#[inline]
50786#[cfg(target_endian = "little")]
50787#[target_feature(enable = "neon,aes")]
50788#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50789#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50790#[cfg_attr(
50791 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50792 assert_instr(nop)
50793)]
50794#[cfg_attr(
50795 not(target_arch = "arm"),
50796 stable(feature = "neon_intrinsics", since = "1.59.0")
50797)]
50798#[cfg_attr(
50799 target_arch = "arm",
50800 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50801)]
50802pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
50803 unsafe { transmute(a) }
50804}
50805#[doc = "Vector reinterpret cast operation"]
50806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
50807#[inline]
50808#[cfg(target_endian = "big")]
50809#[target_feature(enable = "neon,aes")]
50810#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50812#[cfg_attr(
50813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50814 assert_instr(nop)
50815)]
50816#[cfg_attr(
50817 not(target_arch = "arm"),
50818 stable(feature = "neon_intrinsics", since = "1.59.0")
50819)]
50820#[cfg_attr(
50821 target_arch = "arm",
50822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50823)]
50824pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
50825 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50826 unsafe {
50827 let ret_val: int32x4_t = transmute(a);
50828 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50829 }
50830}
50831#[doc = "Vector reinterpret cast operation"]
50832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
50833#[inline]
50834#[cfg(target_endian = "little")]
50835#[target_feature(enable = "neon,aes")]
50836#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50838#[cfg_attr(
50839 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50840 assert_instr(nop)
50841)]
50842#[cfg_attr(
50843 not(target_arch = "arm"),
50844 stable(feature = "neon_intrinsics", since = "1.59.0")
50845)]
50846#[cfg_attr(
50847 target_arch = "arm",
50848 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50849)]
50850pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
50851 unsafe { transmute(a) }
50852}
50853#[doc = "Vector reinterpret cast operation"]
50854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
50855#[inline]
50856#[cfg(target_endian = "big")]
50857#[target_feature(enable = "neon,aes")]
50858#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50860#[cfg_attr(
50861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50862 assert_instr(nop)
50863)]
50864#[cfg_attr(
50865 not(target_arch = "arm"),
50866 stable(feature = "neon_intrinsics", since = "1.59.0")
50867)]
50868#[cfg_attr(
50869 target_arch = "arm",
50870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50871)]
50872pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
50873 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50874 unsafe {
50875 let ret_val: uint8x16_t = transmute(a);
50876 simd_shuffle!(
50877 ret_val,
50878 ret_val,
50879 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50880 )
50881 }
50882}
50883#[doc = "Vector reinterpret cast operation"]
50884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
50885#[inline]
50886#[cfg(target_endian = "little")]
50887#[target_feature(enable = "neon,aes")]
50888#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50890#[cfg_attr(
50891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50892 assert_instr(nop)
50893)]
50894#[cfg_attr(
50895 not(target_arch = "arm"),
50896 stable(feature = "neon_intrinsics", since = "1.59.0")
50897)]
50898#[cfg_attr(
50899 target_arch = "arm",
50900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50901)]
50902pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
50903 unsafe { transmute(a) }
50904}
50905#[doc = "Vector reinterpret cast operation"]
50906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
50907#[inline]
50908#[cfg(target_endian = "big")]
50909#[target_feature(enable = "neon,aes")]
50910#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50912#[cfg_attr(
50913 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50914 assert_instr(nop)
50915)]
50916#[cfg_attr(
50917 not(target_arch = "arm"),
50918 stable(feature = "neon_intrinsics", since = "1.59.0")
50919)]
50920#[cfg_attr(
50921 target_arch = "arm",
50922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50923)]
50924pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
50925 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50926 unsafe {
50927 let ret_val: uint16x8_t = transmute(a);
50928 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50929 }
50930}
50931#[doc = "Vector reinterpret cast operation"]
50932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
50933#[inline]
50934#[cfg(target_endian = "little")]
50935#[target_feature(enable = "neon,aes")]
50936#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50938#[cfg_attr(
50939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50940 assert_instr(nop)
50941)]
50942#[cfg_attr(
50943 not(target_arch = "arm"),
50944 stable(feature = "neon_intrinsics", since = "1.59.0")
50945)]
50946#[cfg_attr(
50947 target_arch = "arm",
50948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50949)]
50950pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
50951 unsafe { transmute(a) }
50952}
50953#[doc = "Vector reinterpret cast operation"]
50954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
50955#[inline]
50956#[cfg(target_endian = "big")]
50957#[target_feature(enable = "neon,aes")]
50958#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50960#[cfg_attr(
50961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50962 assert_instr(nop)
50963)]
50964#[cfg_attr(
50965 not(target_arch = "arm"),
50966 stable(feature = "neon_intrinsics", since = "1.59.0")
50967)]
50968#[cfg_attr(
50969 target_arch = "arm",
50970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50971)]
50972pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
50973 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50974 unsafe {
50975 let ret_val: uint32x4_t = transmute(a);
50976 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50977 }
50978}
50979#[doc = "Vector reinterpret cast operation"]
50980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
50981#[inline]
50982#[cfg(target_endian = "little")]
50983#[target_feature(enable = "neon,aes")]
50984#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
50985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50986#[cfg_attr(
50987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50988 assert_instr(nop)
50989)]
50990#[cfg_attr(
50991 not(target_arch = "arm"),
50992 stable(feature = "neon_intrinsics", since = "1.59.0")
50993)]
50994#[cfg_attr(
50995 target_arch = "arm",
50996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50997)]
50998pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
50999 unsafe { transmute(a) }
51000}
51001#[doc = "Vector reinterpret cast operation"]
51002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
51003#[inline]
51004#[cfg(target_endian = "big")]
51005#[target_feature(enable = "neon,aes")]
51006#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
51007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51008#[cfg_attr(
51009 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51010 assert_instr(nop)
51011)]
51012#[cfg_attr(
51013 not(target_arch = "arm"),
51014 stable(feature = "neon_intrinsics", since = "1.59.0")
51015)]
51016#[cfg_attr(
51017 target_arch = "arm",
51018 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51019)]
51020pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
51021 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51022 unsafe {
51023 let ret_val: poly8x16_t = transmute(a);
51024 simd_shuffle!(
51025 ret_val,
51026 ret_val,
51027 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51028 )
51029 }
51030}
51031#[doc = "Vector reinterpret cast operation"]
51032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
51033#[inline]
51034#[cfg(target_endian = "little")]
51035#[target_feature(enable = "neon,aes")]
51036#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
51037#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51038#[cfg_attr(
51039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51040 assert_instr(nop)
51041)]
51042#[cfg_attr(
51043 not(target_arch = "arm"),
51044 stable(feature = "neon_intrinsics", since = "1.59.0")
51045)]
51046#[cfg_attr(
51047 target_arch = "arm",
51048 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51049)]
51050pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
51051 unsafe { transmute(a) }
51052}
51053#[doc = "Vector reinterpret cast operation"]
51054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
51055#[inline]
51056#[cfg(target_endian = "big")]
51057#[target_feature(enable = "neon,aes")]
51058#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
51059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51060#[cfg_attr(
51061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51062 assert_instr(nop)
51063)]
51064#[cfg_attr(
51065 not(target_arch = "arm"),
51066 stable(feature = "neon_intrinsics", since = "1.59.0")
51067)]
51068#[cfg_attr(
51069 target_arch = "arm",
51070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51071)]
51072pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
51073 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51074 unsafe {
51075 let ret_val: poly16x8_t = transmute(a);
51076 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51077 }
51078}
51079#[doc = "Reverse elements in 64-bit doublewords"]
51080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
51081#[inline]
51082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51083#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
51084#[cfg_attr(
51085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51086 assert_instr(rev64)
51087)]
51088#[target_feature(enable = "neon,fp16")]
51089#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
51090pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
51091 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
51092}
51093#[doc = "Reverse elements in 64-bit doublewords"]
51094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
51095#[inline]
51096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
51098#[cfg_attr(
51099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51100 assert_instr(rev64)
51101)]
51102#[target_feature(enable = "neon,fp16")]
51103#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
51104pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
51105 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
51106}
51107#[doc = "Rounding halving add"]
51108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
51109#[inline]
51110#[target_feature(enable = "neon")]
51111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51112#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
51113#[cfg_attr(
51114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51115 assert_instr(srhadd)
51116)]
51117#[cfg_attr(
51118 not(target_arch = "arm"),
51119 stable(feature = "neon_intrinsics", since = "1.59.0")
51120)]
51121#[cfg_attr(
51122 target_arch = "arm",
51123 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51124)]
51125pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
51126 unsafe extern "unadjusted" {
51127 #[cfg_attr(
51128 any(target_arch = "aarch64", target_arch = "arm64ec"),
51129 link_name = "llvm.aarch64.neon.srhadd.v8i8"
51130 )]
51131 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")]
51132 fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
51133 }
51134 unsafe { _vrhadd_s8(a, b) }
51135}
51136#[doc = "Rounding halving add"]
51137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
51138#[inline]
51139#[target_feature(enable = "neon")]
51140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
51142#[cfg_attr(
51143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51144 assert_instr(srhadd)
51145)]
51146#[cfg_attr(
51147 not(target_arch = "arm"),
51148 stable(feature = "neon_intrinsics", since = "1.59.0")
51149)]
51150#[cfg_attr(
51151 target_arch = "arm",
51152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51153)]
51154pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
51155 unsafe extern "unadjusted" {
51156 #[cfg_attr(
51157 any(target_arch = "aarch64", target_arch = "arm64ec"),
51158 link_name = "llvm.aarch64.neon.srhadd.v16i8"
51159 )]
51160 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")]
51161 fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
51162 }
51163 unsafe { _vrhaddq_s8(a, b) }
51164}
51165#[doc = "Rounding halving add"]
51166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
51167#[inline]
51168#[target_feature(enable = "neon")]
51169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
51171#[cfg_attr(
51172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51173 assert_instr(srhadd)
51174)]
51175#[cfg_attr(
51176 not(target_arch = "arm"),
51177 stable(feature = "neon_intrinsics", since = "1.59.0")
51178)]
51179#[cfg_attr(
51180 target_arch = "arm",
51181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51182)]
51183pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
51184 unsafe extern "unadjusted" {
51185 #[cfg_attr(
51186 any(target_arch = "aarch64", target_arch = "arm64ec"),
51187 link_name = "llvm.aarch64.neon.srhadd.v4i16"
51188 )]
51189 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")]
51190 fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
51191 }
51192 unsafe { _vrhadd_s16(a, b) }
51193}
51194#[doc = "Rounding halving add"]
51195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
51196#[inline]
51197#[target_feature(enable = "neon")]
51198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51199#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
51200#[cfg_attr(
51201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51202 assert_instr(srhadd)
51203)]
51204#[cfg_attr(
51205 not(target_arch = "arm"),
51206 stable(feature = "neon_intrinsics", since = "1.59.0")
51207)]
51208#[cfg_attr(
51209 target_arch = "arm",
51210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51211)]
51212pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
51213 unsafe extern "unadjusted" {
51214 #[cfg_attr(
51215 any(target_arch = "aarch64", target_arch = "arm64ec"),
51216 link_name = "llvm.aarch64.neon.srhadd.v8i16"
51217 )]
51218 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")]
51219 fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
51220 }
51221 unsafe { _vrhaddq_s16(a, b) }
51222}
51223#[doc = "Rounding halving add"]
51224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
51225#[inline]
51226#[target_feature(enable = "neon")]
51227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
51229#[cfg_attr(
51230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51231 assert_instr(srhadd)
51232)]
51233#[cfg_attr(
51234 not(target_arch = "arm"),
51235 stable(feature = "neon_intrinsics", since = "1.59.0")
51236)]
51237#[cfg_attr(
51238 target_arch = "arm",
51239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51240)]
51241pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
51242 unsafe extern "unadjusted" {
51243 #[cfg_attr(
51244 any(target_arch = "aarch64", target_arch = "arm64ec"),
51245 link_name = "llvm.aarch64.neon.srhadd.v2i32"
51246 )]
51247 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")]
51248 fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
51249 }
51250 unsafe { _vrhadd_s32(a, b) }
51251}
51252#[doc = "Rounding halving add"]
51253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
51254#[inline]
51255#[target_feature(enable = "neon")]
51256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51257#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
51258#[cfg_attr(
51259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51260 assert_instr(srhadd)
51261)]
51262#[cfg_attr(
51263 not(target_arch = "arm"),
51264 stable(feature = "neon_intrinsics", since = "1.59.0")
51265)]
51266#[cfg_attr(
51267 target_arch = "arm",
51268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51269)]
51270pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
51271 unsafe extern "unadjusted" {
51272 #[cfg_attr(
51273 any(target_arch = "aarch64", target_arch = "arm64ec"),
51274 link_name = "llvm.aarch64.neon.srhadd.v4i32"
51275 )]
51276 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")]
51277 fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
51278 }
51279 unsafe { _vrhaddq_s32(a, b) }
51280}
51281#[doc = "Rounding halving add"]
51282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
51283#[inline]
51284#[target_feature(enable = "neon")]
51285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51286#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
51287#[cfg_attr(
51288 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51289 assert_instr(urhadd)
51290)]
51291#[cfg_attr(
51292 not(target_arch = "arm"),
51293 stable(feature = "neon_intrinsics", since = "1.59.0")
51294)]
51295#[cfg_attr(
51296 target_arch = "arm",
51297 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51298)]
51299pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
51300 unsafe extern "unadjusted" {
51301 #[cfg_attr(
51302 any(target_arch = "aarch64", target_arch = "arm64ec"),
51303 link_name = "llvm.aarch64.neon.urhadd.v8i8"
51304 )]
51305 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")]
51306 fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
51307 }
51308 unsafe { _vrhadd_u8(a, b) }
51309}
51310#[doc = "Rounding halving add"]
51311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
51312#[inline]
51313#[target_feature(enable = "neon")]
51314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
51316#[cfg_attr(
51317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51318 assert_instr(urhadd)
51319)]
51320#[cfg_attr(
51321 not(target_arch = "arm"),
51322 stable(feature = "neon_intrinsics", since = "1.59.0")
51323)]
51324#[cfg_attr(
51325 target_arch = "arm",
51326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51327)]
51328pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
51329 unsafe extern "unadjusted" {
51330 #[cfg_attr(
51331 any(target_arch = "aarch64", target_arch = "arm64ec"),
51332 link_name = "llvm.aarch64.neon.urhadd.v16i8"
51333 )]
51334 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")]
51335 fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
51336 }
51337 unsafe { _vrhaddq_u8(a, b) }
51338}
51339#[doc = "Rounding halving add"]
51340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
51341#[inline]
51342#[target_feature(enable = "neon")]
51343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
51345#[cfg_attr(
51346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51347 assert_instr(urhadd)
51348)]
51349#[cfg_attr(
51350 not(target_arch = "arm"),
51351 stable(feature = "neon_intrinsics", since = "1.59.0")
51352)]
51353#[cfg_attr(
51354 target_arch = "arm",
51355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51356)]
51357pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
51358 unsafe extern "unadjusted" {
51359 #[cfg_attr(
51360 any(target_arch = "aarch64", target_arch = "arm64ec"),
51361 link_name = "llvm.aarch64.neon.urhadd.v4i16"
51362 )]
51363 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")]
51364 fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
51365 }
51366 unsafe { _vrhadd_u16(a, b) }
51367}
51368#[doc = "Rounding halving add"]
51369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
51370#[inline]
51371#[target_feature(enable = "neon")]
51372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51373#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
51374#[cfg_attr(
51375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51376 assert_instr(urhadd)
51377)]
51378#[cfg_attr(
51379 not(target_arch = "arm"),
51380 stable(feature = "neon_intrinsics", since = "1.59.0")
51381)]
51382#[cfg_attr(
51383 target_arch = "arm",
51384 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51385)]
51386pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
51387 unsafe extern "unadjusted" {
51388 #[cfg_attr(
51389 any(target_arch = "aarch64", target_arch = "arm64ec"),
51390 link_name = "llvm.aarch64.neon.urhadd.v8i16"
51391 )]
51392 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")]
51393 fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
51394 }
51395 unsafe { _vrhaddq_u16(a, b) }
51396}
51397#[doc = "Rounding halving add"]
51398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
51399#[inline]
51400#[target_feature(enable = "neon")]
51401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
51403#[cfg_attr(
51404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51405 assert_instr(urhadd)
51406)]
51407#[cfg_attr(
51408 not(target_arch = "arm"),
51409 stable(feature = "neon_intrinsics", since = "1.59.0")
51410)]
51411#[cfg_attr(
51412 target_arch = "arm",
51413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51414)]
51415pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
51416 unsafe extern "unadjusted" {
51417 #[cfg_attr(
51418 any(target_arch = "aarch64", target_arch = "arm64ec"),
51419 link_name = "llvm.aarch64.neon.urhadd.v2i32"
51420 )]
51421 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")]
51422 fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
51423 }
51424 unsafe { _vrhadd_u32(a, b) }
51425}
51426#[doc = "Rounding halving add"]
51427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
51428#[inline]
51429#[target_feature(enable = "neon")]
51430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51431#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
51432#[cfg_attr(
51433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51434 assert_instr(urhadd)
51435)]
51436#[cfg_attr(
51437 not(target_arch = "arm"),
51438 stable(feature = "neon_intrinsics", since = "1.59.0")
51439)]
51440#[cfg_attr(
51441 target_arch = "arm",
51442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51443)]
51444pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
51445 unsafe extern "unadjusted" {
51446 #[cfg_attr(
51447 any(target_arch = "aarch64", target_arch = "arm64ec"),
51448 link_name = "llvm.aarch64.neon.urhadd.v4i32"
51449 )]
51450 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")]
51451 fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
51452 }
51453 unsafe { _vrhaddq_u32(a, b) }
51454}
51455#[doc = "Floating-point round to integral, to nearest with ties to even"]
51456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
51457#[inline]
51458#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
51459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
51460#[cfg_attr(
51461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51462 assert_instr(frintn)
51463)]
51464#[target_feature(enable = "neon,fp16")]
51465#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
51466pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
51467 unsafe extern "unadjusted" {
51468 #[cfg_attr(
51469 any(target_arch = "aarch64", target_arch = "arm64ec"),
51470 link_name = "llvm.aarch64.neon.frintn.v4f16"
51471 )]
51472 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")]
51473 fn _vrndn_f16(a: float16x4_t) -> float16x4_t;
51474 }
51475 unsafe { _vrndn_f16(a) }
51476}
51477#[doc = "Floating-point round to integral, to nearest with ties to even"]
51478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
51479#[inline]
51480#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
51481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
51482#[cfg_attr(
51483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51484 assert_instr(frintn)
51485)]
51486#[target_feature(enable = "neon,fp16")]
51487#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
51488pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
51489 unsafe extern "unadjusted" {
51490 #[cfg_attr(
51491 any(target_arch = "aarch64", target_arch = "arm64ec"),
51492 link_name = "llvm.aarch64.neon.frintn.v8f16"
51493 )]
51494 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")]
51495 fn _vrndnq_f16(a: float16x8_t) -> float16x8_t;
51496 }
51497 unsafe { _vrndnq_f16(a) }
51498}
51499#[doc = "Floating-point round to integral, to nearest with ties to even"]
51500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
51501#[inline]
51502#[target_feature(enable = "neon")]
51503#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
51504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
51505#[cfg_attr(
51506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51507 assert_instr(frintn)
51508)]
51509#[cfg_attr(
51510 not(target_arch = "arm"),
51511 stable(feature = "neon_intrinsics", since = "1.59.0")
51512)]
51513#[cfg_attr(
51514 target_arch = "arm",
51515 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51516)]
51517pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
51518 unsafe extern "unadjusted" {
51519 #[cfg_attr(
51520 any(target_arch = "aarch64", target_arch = "arm64ec"),
51521 link_name = "llvm.aarch64.neon.frintn.v2f32"
51522 )]
51523 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")]
51524 fn _vrndn_f32(a: float32x2_t) -> float32x2_t;
51525 }
51526 unsafe { _vrndn_f32(a) }
51527}
51528#[doc = "Floating-point round to integral, to nearest with ties to even"]
51529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
51530#[inline]
51531#[target_feature(enable = "neon")]
51532#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
51533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
51534#[cfg_attr(
51535 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51536 assert_instr(frintn)
51537)]
51538#[cfg_attr(
51539 not(target_arch = "arm"),
51540 stable(feature = "neon_intrinsics", since = "1.59.0")
51541)]
51542#[cfg_attr(
51543 target_arch = "arm",
51544 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51545)]
51546pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
51547 unsafe extern "unadjusted" {
51548 #[cfg_attr(
51549 any(target_arch = "aarch64", target_arch = "arm64ec"),
51550 link_name = "llvm.aarch64.neon.frintn.v4f32"
51551 )]
51552 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")]
51553 fn _vrndnq_f32(a: float32x4_t) -> float32x4_t;
51554 }
51555 unsafe { _vrndnq_f32(a) }
51556}
51557#[doc = "Signed rounding shift left"]
51558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
51559#[inline]
51560#[target_feature(enable = "neon")]
51561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51563#[cfg_attr(
51564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51565 assert_instr(srshl)
51566)]
51567#[cfg_attr(
51568 not(target_arch = "arm"),
51569 stable(feature = "neon_intrinsics", since = "1.59.0")
51570)]
51571#[cfg_attr(
51572 target_arch = "arm",
51573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51574)]
51575pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
51576 unsafe extern "unadjusted" {
51577 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")]
51578 #[cfg_attr(
51579 any(target_arch = "aarch64", target_arch = "arm64ec"),
51580 link_name = "llvm.aarch64.neon.srshl.v8i8"
51581 )]
51582 fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
51583 }
51584 unsafe { _vrshl_s8(a, b) }
51585}
51586#[doc = "Signed rounding shift left"]
51587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
51588#[inline]
51589#[target_feature(enable = "neon")]
51590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51592#[cfg_attr(
51593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51594 assert_instr(srshl)
51595)]
51596#[cfg_attr(
51597 not(target_arch = "arm"),
51598 stable(feature = "neon_intrinsics", since = "1.59.0")
51599)]
51600#[cfg_attr(
51601 target_arch = "arm",
51602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51603)]
51604pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
51605 unsafe extern "unadjusted" {
51606 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")]
51607 #[cfg_attr(
51608 any(target_arch = "aarch64", target_arch = "arm64ec"),
51609 link_name = "llvm.aarch64.neon.srshl.v16i8"
51610 )]
51611 fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
51612 }
51613 unsafe { _vrshlq_s8(a, b) }
51614}
51615#[doc = "Signed rounding shift left"]
51616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
51617#[inline]
51618#[target_feature(enable = "neon")]
51619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51621#[cfg_attr(
51622 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51623 assert_instr(srshl)
51624)]
51625#[cfg_attr(
51626 not(target_arch = "arm"),
51627 stable(feature = "neon_intrinsics", since = "1.59.0")
51628)]
51629#[cfg_attr(
51630 target_arch = "arm",
51631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51632)]
51633pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
51634 unsafe extern "unadjusted" {
51635 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")]
51636 #[cfg_attr(
51637 any(target_arch = "aarch64", target_arch = "arm64ec"),
51638 link_name = "llvm.aarch64.neon.srshl.v4i16"
51639 )]
51640 fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
51641 }
51642 unsafe { _vrshl_s16(a, b) }
51643}
51644#[doc = "Signed rounding shift left"]
51645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
51646#[inline]
51647#[target_feature(enable = "neon")]
51648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51650#[cfg_attr(
51651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51652 assert_instr(srshl)
51653)]
51654#[cfg_attr(
51655 not(target_arch = "arm"),
51656 stable(feature = "neon_intrinsics", since = "1.59.0")
51657)]
51658#[cfg_attr(
51659 target_arch = "arm",
51660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51661)]
51662pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
51663 unsafe extern "unadjusted" {
51664 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")]
51665 #[cfg_attr(
51666 any(target_arch = "aarch64", target_arch = "arm64ec"),
51667 link_name = "llvm.aarch64.neon.srshl.v8i16"
51668 )]
51669 fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
51670 }
51671 unsafe { _vrshlq_s16(a, b) }
51672}
51673#[doc = "Signed rounding shift left"]
51674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
51675#[inline]
51676#[target_feature(enable = "neon")]
51677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51679#[cfg_attr(
51680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51681 assert_instr(srshl)
51682)]
51683#[cfg_attr(
51684 not(target_arch = "arm"),
51685 stable(feature = "neon_intrinsics", since = "1.59.0")
51686)]
51687#[cfg_attr(
51688 target_arch = "arm",
51689 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51690)]
51691pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
51692 unsafe extern "unadjusted" {
51693 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")]
51694 #[cfg_attr(
51695 any(target_arch = "aarch64", target_arch = "arm64ec"),
51696 link_name = "llvm.aarch64.neon.srshl.v2i32"
51697 )]
51698 fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
51699 }
51700 unsafe { _vrshl_s32(a, b) }
51701}
51702#[doc = "Signed rounding shift left"]
51703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
51704#[inline]
51705#[target_feature(enable = "neon")]
51706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51708#[cfg_attr(
51709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51710 assert_instr(srshl)
51711)]
51712#[cfg_attr(
51713 not(target_arch = "arm"),
51714 stable(feature = "neon_intrinsics", since = "1.59.0")
51715)]
51716#[cfg_attr(
51717 target_arch = "arm",
51718 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51719)]
51720pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
51721 unsafe extern "unadjusted" {
51722 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")]
51723 #[cfg_attr(
51724 any(target_arch = "aarch64", target_arch = "arm64ec"),
51725 link_name = "llvm.aarch64.neon.srshl.v4i32"
51726 )]
51727 fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
51728 }
51729 unsafe { _vrshlq_s32(a, b) }
51730}
51731#[doc = "Signed rounding shift left"]
51732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
51733#[inline]
51734#[target_feature(enable = "neon")]
51735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51736#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51737#[cfg_attr(
51738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51739 assert_instr(srshl)
51740)]
51741#[cfg_attr(
51742 not(target_arch = "arm"),
51743 stable(feature = "neon_intrinsics", since = "1.59.0")
51744)]
51745#[cfg_attr(
51746 target_arch = "arm",
51747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51748)]
51749pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
51750 unsafe extern "unadjusted" {
51751 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")]
51752 #[cfg_attr(
51753 any(target_arch = "aarch64", target_arch = "arm64ec"),
51754 link_name = "llvm.aarch64.neon.srshl.v1i64"
51755 )]
51756 fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
51757 }
51758 unsafe { _vrshl_s64(a, b) }
51759}
51760#[doc = "Signed rounding shift left"]
51761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
51762#[inline]
51763#[target_feature(enable = "neon")]
51764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51766#[cfg_attr(
51767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51768 assert_instr(srshl)
51769)]
51770#[cfg_attr(
51771 not(target_arch = "arm"),
51772 stable(feature = "neon_intrinsics", since = "1.59.0")
51773)]
51774#[cfg_attr(
51775 target_arch = "arm",
51776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51777)]
51778pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
51779 unsafe extern "unadjusted" {
51780 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")]
51781 #[cfg_attr(
51782 any(target_arch = "aarch64", target_arch = "arm64ec"),
51783 link_name = "llvm.aarch64.neon.srshl.v2i64"
51784 )]
51785 fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
51786 }
51787 unsafe { _vrshlq_s64(a, b) }
51788}
51789#[doc = "Unsigned rounding shift left"]
51790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
51791#[inline]
51792#[target_feature(enable = "neon")]
51793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51795#[cfg_attr(
51796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51797 assert_instr(urshl)
51798)]
51799#[cfg_attr(
51800 not(target_arch = "arm"),
51801 stable(feature = "neon_intrinsics", since = "1.59.0")
51802)]
51803#[cfg_attr(
51804 target_arch = "arm",
51805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51806)]
51807pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
51808 unsafe extern "unadjusted" {
51809 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")]
51810 #[cfg_attr(
51811 any(target_arch = "aarch64", target_arch = "arm64ec"),
51812 link_name = "llvm.aarch64.neon.urshl.v8i8"
51813 )]
51814 fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
51815 }
51816 unsafe { _vrshl_u8(a, b) }
51817}
51818#[doc = "Unsigned rounding shift left"]
51819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
51820#[inline]
51821#[target_feature(enable = "neon")]
51822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51824#[cfg_attr(
51825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51826 assert_instr(urshl)
51827)]
51828#[cfg_attr(
51829 not(target_arch = "arm"),
51830 stable(feature = "neon_intrinsics", since = "1.59.0")
51831)]
51832#[cfg_attr(
51833 target_arch = "arm",
51834 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51835)]
51836pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
51837 unsafe extern "unadjusted" {
51838 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")]
51839 #[cfg_attr(
51840 any(target_arch = "aarch64", target_arch = "arm64ec"),
51841 link_name = "llvm.aarch64.neon.urshl.v16i8"
51842 )]
51843 fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
51844 }
51845 unsafe { _vrshlq_u8(a, b) }
51846}
51847#[doc = "Unsigned rounding shift left"]
51848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
51849#[inline]
51850#[target_feature(enable = "neon")]
51851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51853#[cfg_attr(
51854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51855 assert_instr(urshl)
51856)]
51857#[cfg_attr(
51858 not(target_arch = "arm"),
51859 stable(feature = "neon_intrinsics", since = "1.59.0")
51860)]
51861#[cfg_attr(
51862 target_arch = "arm",
51863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51864)]
51865pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
51866 unsafe extern "unadjusted" {
51867 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")]
51868 #[cfg_attr(
51869 any(target_arch = "aarch64", target_arch = "arm64ec"),
51870 link_name = "llvm.aarch64.neon.urshl.v4i16"
51871 )]
51872 fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
51873 }
51874 unsafe { _vrshl_u16(a, b) }
51875}
51876#[doc = "Unsigned rounding shift left"]
51877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
51878#[inline]
51879#[target_feature(enable = "neon")]
51880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51882#[cfg_attr(
51883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51884 assert_instr(urshl)
51885)]
51886#[cfg_attr(
51887 not(target_arch = "arm"),
51888 stable(feature = "neon_intrinsics", since = "1.59.0")
51889)]
51890#[cfg_attr(
51891 target_arch = "arm",
51892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51893)]
51894pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
51895 unsafe extern "unadjusted" {
51896 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")]
51897 #[cfg_attr(
51898 any(target_arch = "aarch64", target_arch = "arm64ec"),
51899 link_name = "llvm.aarch64.neon.urshl.v8i16"
51900 )]
51901 fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
51902 }
51903 unsafe { _vrshlq_u16(a, b) }
51904}
51905#[doc = "Unsigned rounding shift left"]
51906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
51907#[inline]
51908#[target_feature(enable = "neon")]
51909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51910#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51911#[cfg_attr(
51912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51913 assert_instr(urshl)
51914)]
51915#[cfg_attr(
51916 not(target_arch = "arm"),
51917 stable(feature = "neon_intrinsics", since = "1.59.0")
51918)]
51919#[cfg_attr(
51920 target_arch = "arm",
51921 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51922)]
51923pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
51924 unsafe extern "unadjusted" {
51925 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")]
51926 #[cfg_attr(
51927 any(target_arch = "aarch64", target_arch = "arm64ec"),
51928 link_name = "llvm.aarch64.neon.urshl.v2i32"
51929 )]
51930 fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
51931 }
51932 unsafe { _vrshl_u32(a, b) }
51933}
51934#[doc = "Unsigned rounding shift left"]
51935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
51936#[inline]
51937#[target_feature(enable = "neon")]
51938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51940#[cfg_attr(
51941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51942 assert_instr(urshl)
51943)]
51944#[cfg_attr(
51945 not(target_arch = "arm"),
51946 stable(feature = "neon_intrinsics", since = "1.59.0")
51947)]
51948#[cfg_attr(
51949 target_arch = "arm",
51950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51951)]
51952pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
51953 unsafe extern "unadjusted" {
51954 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")]
51955 #[cfg_attr(
51956 any(target_arch = "aarch64", target_arch = "arm64ec"),
51957 link_name = "llvm.aarch64.neon.urshl.v4i32"
51958 )]
51959 fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
51960 }
51961 unsafe { _vrshlq_u32(a, b) }
51962}
51963#[doc = "Unsigned rounding shift left"]
51964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
51965#[inline]
51966#[target_feature(enable = "neon")]
51967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51969#[cfg_attr(
51970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51971 assert_instr(urshl)
51972)]
51973#[cfg_attr(
51974 not(target_arch = "arm"),
51975 stable(feature = "neon_intrinsics", since = "1.59.0")
51976)]
51977#[cfg_attr(
51978 target_arch = "arm",
51979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51980)]
51981pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
51982 unsafe extern "unadjusted" {
51983 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")]
51984 #[cfg_attr(
51985 any(target_arch = "aarch64", target_arch = "arm64ec"),
51986 link_name = "llvm.aarch64.neon.urshl.v1i64"
51987 )]
51988 fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
51989 }
51990 unsafe { _vrshl_u64(a, b) }
51991}
51992#[doc = "Unsigned rounding shift left"]
51993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
51994#[inline]
51995#[target_feature(enable = "neon")]
51996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
51998#[cfg_attr(
51999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52000 assert_instr(urshl)
52001)]
52002#[cfg_attr(
52003 not(target_arch = "arm"),
52004 stable(feature = "neon_intrinsics", since = "1.59.0")
52005)]
52006#[cfg_attr(
52007 target_arch = "arm",
52008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52009)]
52010pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
52011 unsafe extern "unadjusted" {
52012 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")]
52013 #[cfg_attr(
52014 any(target_arch = "aarch64", target_arch = "arm64ec"),
52015 link_name = "llvm.aarch64.neon.urshl.v2i64"
52016 )]
52017 fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
52018 }
52019 unsafe { _vrshlq_u64(a, b) }
52020}
52021#[doc = "Signed rounding shift right"]
52022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
52023#[inline]
52024#[target_feature(enable = "neon")]
52025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52027#[cfg_attr(
52028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52029 assert_instr(srshr, N = 2)
52030)]
52031#[rustc_legacy_const_generics(1)]
52032#[cfg_attr(
52033 not(target_arch = "arm"),
52034 stable(feature = "neon_intrinsics", since = "1.59.0")
52035)]
52036#[cfg_attr(
52037 target_arch = "arm",
52038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52039)]
52040pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
52041 static_assert!(N >= 1 && N <= 8);
52042 vrshl_s8(a, vdup_n_s8(-N as _))
52043}
52044#[doc = "Signed rounding shift right"]
52045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
52046#[inline]
52047#[target_feature(enable = "neon")]
52048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52049#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52050#[cfg_attr(
52051 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52052 assert_instr(srshr, N = 2)
52053)]
52054#[rustc_legacy_const_generics(1)]
52055#[cfg_attr(
52056 not(target_arch = "arm"),
52057 stable(feature = "neon_intrinsics", since = "1.59.0")
52058)]
52059#[cfg_attr(
52060 target_arch = "arm",
52061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52062)]
52063pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
52064 static_assert!(N >= 1 && N <= 8);
52065 vrshlq_s8(a, vdupq_n_s8(-N as _))
52066}
52067#[doc = "Signed rounding shift right"]
52068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
52069#[inline]
52070#[target_feature(enable = "neon")]
52071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52073#[cfg_attr(
52074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52075 assert_instr(srshr, N = 2)
52076)]
52077#[rustc_legacy_const_generics(1)]
52078#[cfg_attr(
52079 not(target_arch = "arm"),
52080 stable(feature = "neon_intrinsics", since = "1.59.0")
52081)]
52082#[cfg_attr(
52083 target_arch = "arm",
52084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52085)]
52086pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
52087 static_assert!(N >= 1 && N <= 16);
52088 vrshl_s16(a, vdup_n_s16(-N as _))
52089}
52090#[doc = "Signed rounding shift right"]
52091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
52092#[inline]
52093#[target_feature(enable = "neon")]
52094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52095#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52096#[cfg_attr(
52097 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52098 assert_instr(srshr, N = 2)
52099)]
52100#[rustc_legacy_const_generics(1)]
52101#[cfg_attr(
52102 not(target_arch = "arm"),
52103 stable(feature = "neon_intrinsics", since = "1.59.0")
52104)]
52105#[cfg_attr(
52106 target_arch = "arm",
52107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52108)]
52109pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
52110 static_assert!(N >= 1 && N <= 16);
52111 vrshlq_s16(a, vdupq_n_s16(-N as _))
52112}
52113#[doc = "Signed rounding shift right"]
52114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
52115#[inline]
52116#[target_feature(enable = "neon")]
52117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52119#[cfg_attr(
52120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52121 assert_instr(srshr, N = 2)
52122)]
52123#[rustc_legacy_const_generics(1)]
52124#[cfg_attr(
52125 not(target_arch = "arm"),
52126 stable(feature = "neon_intrinsics", since = "1.59.0")
52127)]
52128#[cfg_attr(
52129 target_arch = "arm",
52130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52131)]
52132pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
52133 static_assert!(N >= 1 && N <= 32);
52134 vrshl_s32(a, vdup_n_s32(-N as _))
52135}
52136#[doc = "Signed rounding shift right"]
52137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
52138#[inline]
52139#[target_feature(enable = "neon")]
52140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52142#[cfg_attr(
52143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52144 assert_instr(srshr, N = 2)
52145)]
52146#[rustc_legacy_const_generics(1)]
52147#[cfg_attr(
52148 not(target_arch = "arm"),
52149 stable(feature = "neon_intrinsics", since = "1.59.0")
52150)]
52151#[cfg_attr(
52152 target_arch = "arm",
52153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52154)]
52155pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
52156 static_assert!(N >= 1 && N <= 32);
52157 vrshlq_s32(a, vdupq_n_s32(-N as _))
52158}
52159#[doc = "Signed rounding shift right"]
52160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
52161#[inline]
52162#[target_feature(enable = "neon")]
52163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52165#[cfg_attr(
52166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52167 assert_instr(srshr, N = 2)
52168)]
52169#[rustc_legacy_const_generics(1)]
52170#[cfg_attr(
52171 not(target_arch = "arm"),
52172 stable(feature = "neon_intrinsics", since = "1.59.0")
52173)]
52174#[cfg_attr(
52175 target_arch = "arm",
52176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52177)]
52178pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
52179 static_assert!(N >= 1 && N <= 64);
52180 vrshl_s64(a, vdup_n_s64(-N as _))
52181}
52182#[doc = "Signed rounding shift right"]
52183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
52184#[inline]
52185#[target_feature(enable = "neon")]
52186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52188#[cfg_attr(
52189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52190 assert_instr(srshr, N = 2)
52191)]
52192#[rustc_legacy_const_generics(1)]
52193#[cfg_attr(
52194 not(target_arch = "arm"),
52195 stable(feature = "neon_intrinsics", since = "1.59.0")
52196)]
52197#[cfg_attr(
52198 target_arch = "arm",
52199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52200)]
52201pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
52202 static_assert!(N >= 1 && N <= 64);
52203 vrshlq_s64(a, vdupq_n_s64(-N as _))
52204}
52205#[doc = "Unsigned rounding shift right"]
52206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
52207#[inline]
52208#[target_feature(enable = "neon")]
52209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52211#[cfg_attr(
52212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52213 assert_instr(urshr, N = 2)
52214)]
52215#[rustc_legacy_const_generics(1)]
52216#[cfg_attr(
52217 not(target_arch = "arm"),
52218 stable(feature = "neon_intrinsics", since = "1.59.0")
52219)]
52220#[cfg_attr(
52221 target_arch = "arm",
52222 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52223)]
52224pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
52225 static_assert!(N >= 1 && N <= 8);
52226 vrshl_u8(a, vdup_n_s8(-N as _))
52227}
52228#[doc = "Unsigned rounding shift right"]
52229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
52230#[inline]
52231#[target_feature(enable = "neon")]
52232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52234#[cfg_attr(
52235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52236 assert_instr(urshr, N = 2)
52237)]
52238#[rustc_legacy_const_generics(1)]
52239#[cfg_attr(
52240 not(target_arch = "arm"),
52241 stable(feature = "neon_intrinsics", since = "1.59.0")
52242)]
52243#[cfg_attr(
52244 target_arch = "arm",
52245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52246)]
52247pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
52248 static_assert!(N >= 1 && N <= 8);
52249 vrshlq_u8(a, vdupq_n_s8(-N as _))
52250}
52251#[doc = "Unsigned rounding shift right"]
52252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
52253#[inline]
52254#[target_feature(enable = "neon")]
52255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52257#[cfg_attr(
52258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52259 assert_instr(urshr, N = 2)
52260)]
52261#[rustc_legacy_const_generics(1)]
52262#[cfg_attr(
52263 not(target_arch = "arm"),
52264 stable(feature = "neon_intrinsics", since = "1.59.0")
52265)]
52266#[cfg_attr(
52267 target_arch = "arm",
52268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52269)]
52270pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
52271 static_assert!(N >= 1 && N <= 16);
52272 vrshl_u16(a, vdup_n_s16(-N as _))
52273}
52274#[doc = "Unsigned rounding shift right"]
52275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
52276#[inline]
52277#[target_feature(enable = "neon")]
52278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52280#[cfg_attr(
52281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52282 assert_instr(urshr, N = 2)
52283)]
52284#[rustc_legacy_const_generics(1)]
52285#[cfg_attr(
52286 not(target_arch = "arm"),
52287 stable(feature = "neon_intrinsics", since = "1.59.0")
52288)]
52289#[cfg_attr(
52290 target_arch = "arm",
52291 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52292)]
52293pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
52294 static_assert!(N >= 1 && N <= 16);
52295 vrshlq_u16(a, vdupq_n_s16(-N as _))
52296}
52297#[doc = "Unsigned rounding shift right"]
52298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
52299#[inline]
52300#[target_feature(enable = "neon")]
52301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52303#[cfg_attr(
52304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52305 assert_instr(urshr, N = 2)
52306)]
52307#[rustc_legacy_const_generics(1)]
52308#[cfg_attr(
52309 not(target_arch = "arm"),
52310 stable(feature = "neon_intrinsics", since = "1.59.0")
52311)]
52312#[cfg_attr(
52313 target_arch = "arm",
52314 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52315)]
52316pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
52317 static_assert!(N >= 1 && N <= 32);
52318 vrshl_u32(a, vdup_n_s32(-N as _))
52319}
52320#[doc = "Unsigned rounding shift right"]
52321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
52322#[inline]
52323#[target_feature(enable = "neon")]
52324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52326#[cfg_attr(
52327 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52328 assert_instr(urshr, N = 2)
52329)]
52330#[rustc_legacy_const_generics(1)]
52331#[cfg_attr(
52332 not(target_arch = "arm"),
52333 stable(feature = "neon_intrinsics", since = "1.59.0")
52334)]
52335#[cfg_attr(
52336 target_arch = "arm",
52337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52338)]
52339pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
52340 static_assert!(N >= 1 && N <= 32);
52341 vrshlq_u32(a, vdupq_n_s32(-N as _))
52342}
52343#[doc = "Unsigned rounding shift right"]
52344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
52345#[inline]
52346#[target_feature(enable = "neon")]
52347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52349#[cfg_attr(
52350 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52351 assert_instr(urshr, N = 2)
52352)]
52353#[rustc_legacy_const_generics(1)]
52354#[cfg_attr(
52355 not(target_arch = "arm"),
52356 stable(feature = "neon_intrinsics", since = "1.59.0")
52357)]
52358#[cfg_attr(
52359 target_arch = "arm",
52360 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52361)]
52362pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
52363 static_assert!(N >= 1 && N <= 64);
52364 vrshl_u64(a, vdup_n_s64(-N as _))
52365}
52366#[doc = "Unsigned rounding shift right"]
52367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
52368#[inline]
52369#[target_feature(enable = "neon")]
52370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
52372#[cfg_attr(
52373 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52374 assert_instr(urshr, N = 2)
52375)]
52376#[rustc_legacy_const_generics(1)]
52377#[cfg_attr(
52378 not(target_arch = "arm"),
52379 stable(feature = "neon_intrinsics", since = "1.59.0")
52380)]
52381#[cfg_attr(
52382 target_arch = "arm",
52383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52384)]
52385pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
52386 static_assert!(N >= 1 && N <= 64);
52387 vrshlq_u64(a, vdupq_n_s64(-N as _))
52388}
52389#[doc = "Rounding shift right narrow"]
52390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
52391#[inline]
52392#[cfg(target_arch = "arm")]
52393#[target_feature(enable = "neon,v7")]
52394#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
52395#[rustc_legacy_const_generics(1)]
52396#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
52397pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
52398 static_assert!(N >= 1 && N <= 8);
52399 unsafe extern "unadjusted" {
52400 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")]
52401 fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
52402 }
52403 unsafe {
52404 _vrshrn_n_s16(
52405 a,
52406 const {
52407 int16x8_t([
52408 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
52409 -N as i16,
52410 ])
52411 },
52412 )
52413 }
52414}
52415#[doc = "Rounding shift right narrow"]
52416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
52417#[inline]
52418#[cfg(target_arch = "arm")]
52419#[target_feature(enable = "neon,v7")]
52420#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
52421#[rustc_legacy_const_generics(1)]
52422#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
52423pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
52424 static_assert!(N >= 1 && N <= 16);
52425 unsafe extern "unadjusted" {
52426 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")]
52427 fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
52428 }
52429 unsafe {
52430 _vrshrn_n_s32(
52431 a,
52432 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
52433 )
52434 }
52435}
52436#[doc = "Rounding shift right narrow"]
52437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
52438#[inline]
52439#[cfg(target_arch = "arm")]
52440#[target_feature(enable = "neon,v7")]
52441#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
52442#[rustc_legacy_const_generics(1)]
52443#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
52444pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
52445 static_assert!(N >= 1 && N <= 32);
52446 unsafe extern "unadjusted" {
52447 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")]
52448 fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
52449 }
52450 unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
52451}
52452#[doc = "Rounding shift right narrow"]
52453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
52454#[inline]
52455#[target_feature(enable = "neon")]
52456#[cfg(not(target_arch = "arm"))]
52457#[cfg_attr(test, assert_instr(rshrn, N = 2))]
52458#[rustc_legacy_const_generics(1)]
52459#[stable(feature = "neon_intrinsics", since = "1.59.0")]
52460pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
52461 static_assert!(N >= 1 && N <= 8);
52462 unsafe extern "unadjusted" {
52463 #[cfg_attr(
52464 any(target_arch = "aarch64", target_arch = "arm64ec"),
52465 link_name = "llvm.aarch64.neon.rshrn.v8i8"
52466 )]
52467 fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
52468 }
52469 unsafe { _vrshrn_n_s16(a, N) }
52470}
52471#[doc = "Rounding shift right narrow"]
52472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
52473#[inline]
52474#[target_feature(enable = "neon")]
52475#[cfg(not(target_arch = "arm"))]
52476#[cfg_attr(test, assert_instr(rshrn, N = 2))]
52477#[rustc_legacy_const_generics(1)]
52478#[stable(feature = "neon_intrinsics", since = "1.59.0")]
52479pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
52480 static_assert!(N >= 1 && N <= 16);
52481 unsafe extern "unadjusted" {
52482 #[cfg_attr(
52483 any(target_arch = "aarch64", target_arch = "arm64ec"),
52484 link_name = "llvm.aarch64.neon.rshrn.v4i16"
52485 )]
52486 fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
52487 }
52488 unsafe { _vrshrn_n_s32(a, N) }
52489}
52490#[doc = "Rounding shift right narrow"]
52491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
52492#[inline]
52493#[target_feature(enable = "neon")]
52494#[cfg(not(target_arch = "arm"))]
52495#[cfg_attr(test, assert_instr(rshrn, N = 2))]
52496#[rustc_legacy_const_generics(1)]
52497#[stable(feature = "neon_intrinsics", since = "1.59.0")]
52498pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
52499 static_assert!(N >= 1 && N <= 32);
52500 unsafe extern "unadjusted" {
52501 #[cfg_attr(
52502 any(target_arch = "aarch64", target_arch = "arm64ec"),
52503 link_name = "llvm.aarch64.neon.rshrn.v2i32"
52504 )]
52505 fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
52506 }
52507 unsafe { _vrshrn_n_s64(a, N) }
52508}
52509#[doc = "Rounding shift right narrow"]
52510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
52511#[inline]
52512#[target_feature(enable = "neon")]
52513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
52515#[cfg_attr(
52516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52517 assert_instr(rshrn, N = 2)
52518)]
52519#[rustc_legacy_const_generics(1)]
52520#[cfg_attr(
52521 not(target_arch = "arm"),
52522 stable(feature = "neon_intrinsics", since = "1.59.0")
52523)]
52524#[cfg_attr(
52525 target_arch = "arm",
52526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52527)]
52528pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
52529 static_assert!(N >= 1 && N <= 8);
52530 unsafe { transmute(vrshrn_n_s16::<N>(transmute(a))) }
52531}
52532#[doc = "Rounding shift right narrow"]
52533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
52534#[inline]
52535#[target_feature(enable = "neon")]
52536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
52538#[cfg_attr(
52539 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52540 assert_instr(rshrn, N = 2)
52541)]
52542#[rustc_legacy_const_generics(1)]
52543#[cfg_attr(
52544 not(target_arch = "arm"),
52545 stable(feature = "neon_intrinsics", since = "1.59.0")
52546)]
52547#[cfg_attr(
52548 target_arch = "arm",
52549 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52550)]
52551pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
52552 static_assert!(N >= 1 && N <= 16);
52553 unsafe { transmute(vrshrn_n_s32::<N>(transmute(a))) }
52554}
52555#[doc = "Rounding shift right narrow"]
52556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
52557#[inline]
52558#[target_feature(enable = "neon")]
52559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52560#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
52561#[cfg_attr(
52562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52563 assert_instr(rshrn, N = 2)
52564)]
52565#[rustc_legacy_const_generics(1)]
52566#[cfg_attr(
52567 not(target_arch = "arm"),
52568 stable(feature = "neon_intrinsics", since = "1.59.0")
52569)]
52570#[cfg_attr(
52571 target_arch = "arm",
52572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52573)]
52574pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
52575 static_assert!(N >= 1 && N <= 32);
52576 unsafe { transmute(vrshrn_n_s64::<N>(transmute(a))) }
52577}
52578#[doc = "Reciprocal square-root estimate."]
52579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
52580#[inline]
52581#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
52582#[target_feature(enable = "neon,fp16")]
52583#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
52584#[cfg_attr(
52585 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52586 assert_instr(frsqrte)
52587)]
52588#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
52589pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
52590 unsafe extern "unadjusted" {
52591 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")]
52592 #[cfg_attr(
52593 any(target_arch = "aarch64", target_arch = "arm64ec"),
52594 link_name = "llvm.aarch64.neon.frsqrte.v4f16"
52595 )]
52596 fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t;
52597 }
52598 unsafe { _vrsqrte_f16(a) }
52599}
52600#[doc = "Reciprocal square-root estimate."]
52601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
52602#[inline]
52603#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
52604#[target_feature(enable = "neon,fp16")]
52605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
52606#[cfg_attr(
52607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52608 assert_instr(frsqrte)
52609)]
52610#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
52611pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
52612 unsafe extern "unadjusted" {
52613 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")]
52614 #[cfg_attr(
52615 any(target_arch = "aarch64", target_arch = "arm64ec"),
52616 link_name = "llvm.aarch64.neon.frsqrte.v8f16"
52617 )]
52618 fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t;
52619 }
52620 unsafe { _vrsqrteq_f16(a) }
52621}
52622#[doc = "Reciprocal square-root estimate."]
52623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
52624#[inline]
52625#[target_feature(enable = "neon")]
52626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
52628#[cfg_attr(
52629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52630 assert_instr(frsqrte)
52631)]
52632#[cfg_attr(
52633 not(target_arch = "arm"),
52634 stable(feature = "neon_intrinsics", since = "1.59.0")
52635)]
52636#[cfg_attr(
52637 target_arch = "arm",
52638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52639)]
52640pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
52641 unsafe extern "unadjusted" {
52642 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
52643 #[cfg_attr(
52644 any(target_arch = "aarch64", target_arch = "arm64ec"),
52645 link_name = "llvm.aarch64.neon.frsqrte.v2f32"
52646 )]
52647 fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t;
52648 }
52649 unsafe { _vrsqrte_f32(a) }
52650}
52651#[doc = "Reciprocal square-root estimate."]
52652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
52653#[inline]
52654#[target_feature(enable = "neon")]
52655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
52657#[cfg_attr(
52658 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52659 assert_instr(frsqrte)
52660)]
52661#[cfg_attr(
52662 not(target_arch = "arm"),
52663 stable(feature = "neon_intrinsics", since = "1.59.0")
52664)]
52665#[cfg_attr(
52666 target_arch = "arm",
52667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52668)]
52669pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
52670 unsafe extern "unadjusted" {
52671 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")]
52672 #[cfg_attr(
52673 any(target_arch = "aarch64", target_arch = "arm64ec"),
52674 link_name = "llvm.aarch64.neon.frsqrte.v4f32"
52675 )]
52676 fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t;
52677 }
52678 unsafe { _vrsqrteq_f32(a) }
52679}
52680#[doc = "Unsigned reciprocal square root estimate"]
52681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
52682#[inline]
52683#[target_feature(enable = "neon")]
52684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
52686#[cfg_attr(
52687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52688 assert_instr(ursqrte)
52689)]
52690#[cfg_attr(
52691 not(target_arch = "arm"),
52692 stable(feature = "neon_intrinsics", since = "1.59.0")
52693)]
52694#[cfg_attr(
52695 target_arch = "arm",
52696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52697)]
52698pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
52699 unsafe extern "unadjusted" {
52700 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")]
52701 #[cfg_attr(
52702 any(target_arch = "aarch64", target_arch = "arm64ec"),
52703 link_name = "llvm.aarch64.neon.ursqrte.v2i32"
52704 )]
52705 fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t;
52706 }
52707 unsafe { _vrsqrte_u32(a) }
52708}
52709#[doc = "Unsigned reciprocal square root estimate"]
52710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
52711#[inline]
52712#[target_feature(enable = "neon")]
52713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52714#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
52715#[cfg_attr(
52716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52717 assert_instr(ursqrte)
52718)]
52719#[cfg_attr(
52720 not(target_arch = "arm"),
52721 stable(feature = "neon_intrinsics", since = "1.59.0")
52722)]
52723#[cfg_attr(
52724 target_arch = "arm",
52725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52726)]
52727pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
52728 unsafe extern "unadjusted" {
52729 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")]
52730 #[cfg_attr(
52731 any(target_arch = "aarch64", target_arch = "arm64ec"),
52732 link_name = "llvm.aarch64.neon.ursqrte.v4i32"
52733 )]
52734 fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t;
52735 }
52736 unsafe { _vrsqrteq_u32(a) }
52737}
52738#[doc = "Floating-point reciprocal square root step"]
52739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
52740#[inline]
52741#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
52742#[target_feature(enable = "neon,fp16")]
52743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
52744#[cfg_attr(
52745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52746 assert_instr(frsqrts)
52747)]
52748#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
52749pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
52750 unsafe extern "unadjusted" {
52751 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")]
52752 #[cfg_attr(
52753 any(target_arch = "aarch64", target_arch = "arm64ec"),
52754 link_name = "llvm.aarch64.neon.frsqrts.v4f16"
52755 )]
52756 fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
52757 }
52758 unsafe { _vrsqrts_f16(a, b) }
52759}
52760#[doc = "Floating-point reciprocal square root step"]
52761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
52762#[inline]
52763#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
52764#[target_feature(enable = "neon,fp16")]
52765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
52766#[cfg_attr(
52767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52768 assert_instr(frsqrts)
52769)]
52770#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
52771pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
52772 unsafe extern "unadjusted" {
52773 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")]
52774 #[cfg_attr(
52775 any(target_arch = "aarch64", target_arch = "arm64ec"),
52776 link_name = "llvm.aarch64.neon.frsqrts.v8f16"
52777 )]
52778 fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
52779 }
52780 unsafe { _vrsqrtsq_f16(a, b) }
52781}
52782#[doc = "Floating-point reciprocal square root step"]
52783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
52784#[inline]
52785#[target_feature(enable = "neon")]
52786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
52788#[cfg_attr(
52789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52790 assert_instr(frsqrts)
52791)]
52792#[cfg_attr(
52793 not(target_arch = "arm"),
52794 stable(feature = "neon_intrinsics", since = "1.59.0")
52795)]
52796#[cfg_attr(
52797 target_arch = "arm",
52798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52799)]
52800pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
52801 unsafe extern "unadjusted" {
52802 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")]
52803 #[cfg_attr(
52804 any(target_arch = "aarch64", target_arch = "arm64ec"),
52805 link_name = "llvm.aarch64.neon.frsqrts.v2f32"
52806 )]
52807 fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
52808 }
52809 unsafe { _vrsqrts_f32(a, b) }
52810}
52811#[doc = "Floating-point reciprocal square root step"]
52812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
52813#[inline]
52814#[target_feature(enable = "neon")]
52815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
52817#[cfg_attr(
52818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52819 assert_instr(frsqrts)
52820)]
52821#[cfg_attr(
52822 not(target_arch = "arm"),
52823 stable(feature = "neon_intrinsics", since = "1.59.0")
52824)]
52825#[cfg_attr(
52826 target_arch = "arm",
52827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52828)]
52829pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
52830 unsafe extern "unadjusted" {
52831 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")]
52832 #[cfg_attr(
52833 any(target_arch = "aarch64", target_arch = "arm64ec"),
52834 link_name = "llvm.aarch64.neon.frsqrts.v4f32"
52835 )]
52836 fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
52837 }
52838 unsafe { _vrsqrtsq_f32(a, b) }
52839}
52840#[doc = "Signed rounding shift right and accumulate"]
52841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
52842#[inline]
52843#[target_feature(enable = "neon")]
52844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52845#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52846#[cfg_attr(
52847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52848 assert_instr(srsra, N = 2)
52849)]
52850#[rustc_legacy_const_generics(2)]
52851#[cfg_attr(
52852 not(target_arch = "arm"),
52853 stable(feature = "neon_intrinsics", since = "1.59.0")
52854)]
52855#[cfg_attr(
52856 target_arch = "arm",
52857 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52858)]
52859pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
52860 static_assert!(N >= 1 && N <= 8);
52861 unsafe { simd_add(a, vrshr_n_s8::<N>(b)) }
52862}
52863#[doc = "Signed rounding shift right and accumulate"]
52864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
52865#[inline]
52866#[target_feature(enable = "neon")]
52867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52869#[cfg_attr(
52870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52871 assert_instr(srsra, N = 2)
52872)]
52873#[rustc_legacy_const_generics(2)]
52874#[cfg_attr(
52875 not(target_arch = "arm"),
52876 stable(feature = "neon_intrinsics", since = "1.59.0")
52877)]
52878#[cfg_attr(
52879 target_arch = "arm",
52880 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52881)]
52882pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
52883 static_assert!(N >= 1 && N <= 8);
52884 unsafe { simd_add(a, vrshrq_n_s8::<N>(b)) }
52885}
52886#[doc = "Signed rounding shift right and accumulate"]
52887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
52888#[inline]
52889#[target_feature(enable = "neon")]
52890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52892#[cfg_attr(
52893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52894 assert_instr(srsra, N = 2)
52895)]
52896#[rustc_legacy_const_generics(2)]
52897#[cfg_attr(
52898 not(target_arch = "arm"),
52899 stable(feature = "neon_intrinsics", since = "1.59.0")
52900)]
52901#[cfg_attr(
52902 target_arch = "arm",
52903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52904)]
52905pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
52906 static_assert!(N >= 1 && N <= 16);
52907 unsafe { simd_add(a, vrshr_n_s16::<N>(b)) }
52908}
52909#[doc = "Signed rounding shift right and accumulate"]
52910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
52911#[inline]
52912#[target_feature(enable = "neon")]
52913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52915#[cfg_attr(
52916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52917 assert_instr(srsra, N = 2)
52918)]
52919#[rustc_legacy_const_generics(2)]
52920#[cfg_attr(
52921 not(target_arch = "arm"),
52922 stable(feature = "neon_intrinsics", since = "1.59.0")
52923)]
52924#[cfg_attr(
52925 target_arch = "arm",
52926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52927)]
52928pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
52929 static_assert!(N >= 1 && N <= 16);
52930 unsafe { simd_add(a, vrshrq_n_s16::<N>(b)) }
52931}
52932#[doc = "Signed rounding shift right and accumulate"]
52933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
52934#[inline]
52935#[target_feature(enable = "neon")]
52936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52938#[cfg_attr(
52939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52940 assert_instr(srsra, N = 2)
52941)]
52942#[rustc_legacy_const_generics(2)]
52943#[cfg_attr(
52944 not(target_arch = "arm"),
52945 stable(feature = "neon_intrinsics", since = "1.59.0")
52946)]
52947#[cfg_attr(
52948 target_arch = "arm",
52949 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52950)]
52951pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
52952 static_assert!(N >= 1 && N <= 32);
52953 unsafe { simd_add(a, vrshr_n_s32::<N>(b)) }
52954}
52955#[doc = "Signed rounding shift right and accumulate"]
52956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
52957#[inline]
52958#[target_feature(enable = "neon")]
52959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52961#[cfg_attr(
52962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52963 assert_instr(srsra, N = 2)
52964)]
52965#[rustc_legacy_const_generics(2)]
52966#[cfg_attr(
52967 not(target_arch = "arm"),
52968 stable(feature = "neon_intrinsics", since = "1.59.0")
52969)]
52970#[cfg_attr(
52971 target_arch = "arm",
52972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52973)]
52974pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
52975 static_assert!(N >= 1 && N <= 32);
52976 unsafe { simd_add(a, vrshrq_n_s32::<N>(b)) }
52977}
52978#[doc = "Signed rounding shift right and accumulate"]
52979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
52980#[inline]
52981#[target_feature(enable = "neon")]
52982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
52984#[cfg_attr(
52985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52986 assert_instr(srsra, N = 2)
52987)]
52988#[rustc_legacy_const_generics(2)]
52989#[cfg_attr(
52990 not(target_arch = "arm"),
52991 stable(feature = "neon_intrinsics", since = "1.59.0")
52992)]
52993#[cfg_attr(
52994 target_arch = "arm",
52995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52996)]
52997pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
52998 static_assert!(N >= 1 && N <= 64);
52999 unsafe { simd_add(a, vrshr_n_s64::<N>(b)) }
53000}
53001#[doc = "Signed rounding shift right and accumulate"]
53002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
53003#[inline]
53004#[target_feature(enable = "neon")]
53005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53007#[cfg_attr(
53008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53009 assert_instr(srsra, N = 2)
53010)]
53011#[rustc_legacy_const_generics(2)]
53012#[cfg_attr(
53013 not(target_arch = "arm"),
53014 stable(feature = "neon_intrinsics", since = "1.59.0")
53015)]
53016#[cfg_attr(
53017 target_arch = "arm",
53018 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53019)]
53020pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
53021 static_assert!(N >= 1 && N <= 64);
53022 unsafe { simd_add(a, vrshrq_n_s64::<N>(b)) }
53023}
53024#[doc = "Unsigned rounding shift right and accumulate"]
53025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
53026#[inline]
53027#[target_feature(enable = "neon")]
53028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53030#[cfg_attr(
53031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53032 assert_instr(ursra, N = 2)
53033)]
53034#[rustc_legacy_const_generics(2)]
53035#[cfg_attr(
53036 not(target_arch = "arm"),
53037 stable(feature = "neon_intrinsics", since = "1.59.0")
53038)]
53039#[cfg_attr(
53040 target_arch = "arm",
53041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53042)]
53043pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
53044 static_assert!(N >= 1 && N <= 8);
53045 unsafe { simd_add(a, vrshr_n_u8::<N>(b)) }
53046}
53047#[doc = "Unsigned rounding shift right and accumulate"]
53048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
53049#[inline]
53050#[target_feature(enable = "neon")]
53051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53053#[cfg_attr(
53054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53055 assert_instr(ursra, N = 2)
53056)]
53057#[rustc_legacy_const_generics(2)]
53058#[cfg_attr(
53059 not(target_arch = "arm"),
53060 stable(feature = "neon_intrinsics", since = "1.59.0")
53061)]
53062#[cfg_attr(
53063 target_arch = "arm",
53064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53065)]
53066pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
53067 static_assert!(N >= 1 && N <= 8);
53068 unsafe { simd_add(a, vrshrq_n_u8::<N>(b)) }
53069}
53070#[doc = "Unsigned rounding shift right and accumulate"]
53071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
53072#[inline]
53073#[target_feature(enable = "neon")]
53074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53076#[cfg_attr(
53077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53078 assert_instr(ursra, N = 2)
53079)]
53080#[rustc_legacy_const_generics(2)]
53081#[cfg_attr(
53082 not(target_arch = "arm"),
53083 stable(feature = "neon_intrinsics", since = "1.59.0")
53084)]
53085#[cfg_attr(
53086 target_arch = "arm",
53087 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53088)]
53089pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
53090 static_assert!(N >= 1 && N <= 16);
53091 unsafe { simd_add(a, vrshr_n_u16::<N>(b)) }
53092}
53093#[doc = "Unsigned rounding shift right and accumulate"]
53094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
53095#[inline]
53096#[target_feature(enable = "neon")]
53097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53099#[cfg_attr(
53100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53101 assert_instr(ursra, N = 2)
53102)]
53103#[rustc_legacy_const_generics(2)]
53104#[cfg_attr(
53105 not(target_arch = "arm"),
53106 stable(feature = "neon_intrinsics", since = "1.59.0")
53107)]
53108#[cfg_attr(
53109 target_arch = "arm",
53110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53111)]
53112pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
53113 static_assert!(N >= 1 && N <= 16);
53114 unsafe { simd_add(a, vrshrq_n_u16::<N>(b)) }
53115}
53116#[doc = "Unsigned rounding shift right and accumulate"]
53117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
53118#[inline]
53119#[target_feature(enable = "neon")]
53120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53122#[cfg_attr(
53123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53124 assert_instr(ursra, N = 2)
53125)]
53126#[rustc_legacy_const_generics(2)]
53127#[cfg_attr(
53128 not(target_arch = "arm"),
53129 stable(feature = "neon_intrinsics", since = "1.59.0")
53130)]
53131#[cfg_attr(
53132 target_arch = "arm",
53133 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53134)]
53135pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
53136 static_assert!(N >= 1 && N <= 32);
53137 unsafe { simd_add(a, vrshr_n_u32::<N>(b)) }
53138}
53139#[doc = "Unsigned rounding shift right and accumulate"]
53140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
53141#[inline]
53142#[target_feature(enable = "neon")]
53143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53145#[cfg_attr(
53146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53147 assert_instr(ursra, N = 2)
53148)]
53149#[rustc_legacy_const_generics(2)]
53150#[cfg_attr(
53151 not(target_arch = "arm"),
53152 stable(feature = "neon_intrinsics", since = "1.59.0")
53153)]
53154#[cfg_attr(
53155 target_arch = "arm",
53156 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53157)]
53158pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
53159 static_assert!(N >= 1 && N <= 32);
53160 unsafe { simd_add(a, vrshrq_n_u32::<N>(b)) }
53161}
53162#[doc = "Unsigned rounding shift right and accumulate"]
53163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
53164#[inline]
53165#[target_feature(enable = "neon")]
53166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53168#[cfg_attr(
53169 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53170 assert_instr(ursra, N = 2)
53171)]
53172#[rustc_legacy_const_generics(2)]
53173#[cfg_attr(
53174 not(target_arch = "arm"),
53175 stable(feature = "neon_intrinsics", since = "1.59.0")
53176)]
53177#[cfg_attr(
53178 target_arch = "arm",
53179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53180)]
53181pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
53182 static_assert!(N >= 1 && N <= 64);
53183 unsafe { simd_add(a, vrshr_n_u64::<N>(b)) }
53184}
53185#[doc = "Unsigned rounding shift right and accumulate"]
53186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
53187#[inline]
53188#[target_feature(enable = "neon")]
53189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
53191#[cfg_attr(
53192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53193 assert_instr(ursra, N = 2)
53194)]
53195#[rustc_legacy_const_generics(2)]
53196#[cfg_attr(
53197 not(target_arch = "arm"),
53198 stable(feature = "neon_intrinsics", since = "1.59.0")
53199)]
53200#[cfg_attr(
53201 target_arch = "arm",
53202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53203)]
53204pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
53205 static_assert!(N >= 1 && N <= 64);
53206 unsafe { simd_add(a, vrshrq_n_u64::<N>(b)) }
53207}
53208#[doc = "Rounding subtract returning high narrow"]
53209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
53210#[inline]
53211#[target_feature(enable = "neon")]
53212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53214#[cfg_attr(
53215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53216 assert_instr(rsubhn)
53217)]
53218#[cfg_attr(
53219 not(target_arch = "arm"),
53220 stable(feature = "neon_intrinsics", since = "1.59.0")
53221)]
53222#[cfg_attr(
53223 target_arch = "arm",
53224 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53225)]
53226pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
53227 unsafe extern "unadjusted" {
53228 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")]
53229 #[cfg_attr(
53230 any(target_arch = "aarch64", target_arch = "arm64ec"),
53231 link_name = "llvm.aarch64.neon.rsubhn.v8i8"
53232 )]
53233 fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
53234 }
53235 unsafe { _vrsubhn_s16(a, b) }
53236}
53237#[doc = "Rounding subtract returning high narrow"]
53238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
53239#[inline]
53240#[target_feature(enable = "neon")]
53241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53243#[cfg_attr(
53244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53245 assert_instr(rsubhn)
53246)]
53247#[cfg_attr(
53248 not(target_arch = "arm"),
53249 stable(feature = "neon_intrinsics", since = "1.59.0")
53250)]
53251#[cfg_attr(
53252 target_arch = "arm",
53253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53254)]
53255pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
53256 unsafe extern "unadjusted" {
53257 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")]
53258 #[cfg_attr(
53259 any(target_arch = "aarch64", target_arch = "arm64ec"),
53260 link_name = "llvm.aarch64.neon.rsubhn.v4i16"
53261 )]
53262 fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
53263 }
53264 unsafe { _vrsubhn_s32(a, b) }
53265}
53266#[doc = "Rounding subtract returning high narrow"]
53267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
53268#[inline]
53269#[target_feature(enable = "neon")]
53270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53272#[cfg_attr(
53273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53274 assert_instr(rsubhn)
53275)]
53276#[cfg_attr(
53277 not(target_arch = "arm"),
53278 stable(feature = "neon_intrinsics", since = "1.59.0")
53279)]
53280#[cfg_attr(
53281 target_arch = "arm",
53282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53283)]
53284pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
53285 unsafe extern "unadjusted" {
53286 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")]
53287 #[cfg_attr(
53288 any(target_arch = "aarch64", target_arch = "arm64ec"),
53289 link_name = "llvm.aarch64.neon.rsubhn.v2i32"
53290 )]
53291 fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
53292 }
53293 unsafe { _vrsubhn_s64(a, b) }
53294}
53295#[doc = "Rounding subtract returning high narrow"]
53296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
53297#[inline]
53298#[cfg(target_endian = "little")]
53299#[target_feature(enable = "neon")]
53300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53302#[cfg_attr(
53303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53304 assert_instr(rsubhn)
53305)]
53306#[cfg_attr(
53307 not(target_arch = "arm"),
53308 stable(feature = "neon_intrinsics", since = "1.59.0")
53309)]
53310#[cfg_attr(
53311 target_arch = "arm",
53312 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53313)]
53314pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
53315 unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) }
53316}
53317#[doc = "Rounding subtract returning high narrow"]
53318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
53319#[inline]
53320#[cfg(target_endian = "big")]
53321#[target_feature(enable = "neon")]
53322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53324#[cfg_attr(
53325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53326 assert_instr(rsubhn)
53327)]
53328#[cfg_attr(
53329 not(target_arch = "arm"),
53330 stable(feature = "neon_intrinsics", since = "1.59.0")
53331)]
53332#[cfg_attr(
53333 target_arch = "arm",
53334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53335)]
53336pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
53337 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53338 let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
53339 unsafe {
53340 let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
53341 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53342 }
53343}
53344#[doc = "Rounding subtract returning high narrow"]
53345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
53346#[inline]
53347#[cfg(target_endian = "little")]
53348#[target_feature(enable = "neon")]
53349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53351#[cfg_attr(
53352 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53353 assert_instr(rsubhn)
53354)]
53355#[cfg_attr(
53356 not(target_arch = "arm"),
53357 stable(feature = "neon_intrinsics", since = "1.59.0")
53358)]
53359#[cfg_attr(
53360 target_arch = "arm",
53361 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53362)]
53363pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
53364 unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) }
53365}
53366#[doc = "Rounding subtract returning high narrow"]
53367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
53368#[inline]
53369#[cfg(target_endian = "big")]
53370#[target_feature(enable = "neon")]
53371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53373#[cfg_attr(
53374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53375 assert_instr(rsubhn)
53376)]
53377#[cfg_attr(
53378 not(target_arch = "arm"),
53379 stable(feature = "neon_intrinsics", since = "1.59.0")
53380)]
53381#[cfg_attr(
53382 target_arch = "arm",
53383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53384)]
53385pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
53386 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53387 let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
53388 unsafe {
53389 let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
53390 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53391 }
53392}
53393#[doc = "Rounding subtract returning high narrow"]
53394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
53395#[inline]
53396#[cfg(target_endian = "little")]
53397#[target_feature(enable = "neon")]
53398#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53399#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53400#[cfg_attr(
53401 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53402 assert_instr(rsubhn)
53403)]
53404#[cfg_attr(
53405 not(target_arch = "arm"),
53406 stable(feature = "neon_intrinsics", since = "1.59.0")
53407)]
53408#[cfg_attr(
53409 target_arch = "arm",
53410 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53411)]
53412pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
53413 unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) }
53414}
53415#[doc = "Rounding subtract returning high narrow"]
53416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
53417#[inline]
53418#[cfg(target_endian = "big")]
53419#[target_feature(enable = "neon")]
53420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
53422#[cfg_attr(
53423 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53424 assert_instr(rsubhn)
53425)]
53426#[cfg_attr(
53427 not(target_arch = "arm"),
53428 stable(feature = "neon_intrinsics", since = "1.59.0")
53429)]
53430#[cfg_attr(
53431 target_arch = "arm",
53432 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53433)]
53434pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
53435 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
53436 let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
53437 unsafe {
53438 let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
53439 simd_shuffle!(ret_val, ret_val, [1, 0])
53440 }
53441}
53442#[doc = "Insert vector element from another vector element"]
53443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
53444#[inline]
53445#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
53446#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53447#[cfg_attr(
53448 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53449 assert_instr(nop, LANE = 0)
53450)]
53451#[rustc_legacy_const_generics(2)]
53452#[target_feature(enable = "neon,fp16")]
53453#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
53454pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
53455 static_assert_uimm_bits!(LANE, 2);
53456 unsafe { simd_insert!(b, LANE as u32, a) }
53457}
53458#[doc = "Insert vector element from another vector element"]
53459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
53460#[inline]
53461#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
53462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53463#[cfg_attr(
53464 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53465 assert_instr(nop, LANE = 0)
53466)]
53467#[rustc_legacy_const_generics(2)]
53468#[target_feature(enable = "neon,fp16")]
53469#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
53470pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
53471 static_assert_uimm_bits!(LANE, 3);
53472 unsafe { simd_insert!(b, LANE as u32, a) }
53473}
53474#[doc = "Insert vector element from another vector element"]
53475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
53476#[inline]
53477#[target_feature(enable = "neon")]
53478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53480#[cfg_attr(
53481 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53482 assert_instr(nop, LANE = 0)
53483)]
53484#[rustc_legacy_const_generics(2)]
53485#[cfg_attr(
53486 not(target_arch = "arm"),
53487 stable(feature = "neon_intrinsics", since = "1.59.0")
53488)]
53489#[cfg_attr(
53490 target_arch = "arm",
53491 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53492)]
53493pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
53494 static_assert_uimm_bits!(LANE, 1);
53495 unsafe { simd_insert!(b, LANE as u32, a) }
53496}
53497#[doc = "Insert vector element from another vector element"]
53498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
53499#[inline]
53500#[target_feature(enable = "neon")]
53501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53503#[cfg_attr(
53504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53505 assert_instr(nop, LANE = 0)
53506)]
53507#[rustc_legacy_const_generics(2)]
53508#[cfg_attr(
53509 not(target_arch = "arm"),
53510 stable(feature = "neon_intrinsics", since = "1.59.0")
53511)]
53512#[cfg_attr(
53513 target_arch = "arm",
53514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53515)]
53516pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
53517 static_assert_uimm_bits!(LANE, 2);
53518 unsafe { simd_insert!(b, LANE as u32, a) }
53519}
53520#[doc = "Insert vector element from another vector element"]
53521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
53522#[inline]
53523#[target_feature(enable = "neon")]
53524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53526#[cfg_attr(
53527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53528 assert_instr(nop, LANE = 0)
53529)]
53530#[rustc_legacy_const_generics(2)]
53531#[cfg_attr(
53532 not(target_arch = "arm"),
53533 stable(feature = "neon_intrinsics", since = "1.59.0")
53534)]
53535#[cfg_attr(
53536 target_arch = "arm",
53537 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53538)]
53539pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
53540 static_assert_uimm_bits!(LANE, 3);
53541 unsafe { simd_insert!(b, LANE as u32, a) }
53542}
53543#[doc = "Insert vector element from another vector element"]
53544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
53545#[inline]
53546#[target_feature(enable = "neon")]
53547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53549#[cfg_attr(
53550 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53551 assert_instr(nop, LANE = 0)
53552)]
53553#[rustc_legacy_const_generics(2)]
53554#[cfg_attr(
53555 not(target_arch = "arm"),
53556 stable(feature = "neon_intrinsics", since = "1.59.0")
53557)]
53558#[cfg_attr(
53559 target_arch = "arm",
53560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53561)]
53562pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
53563 static_assert_uimm_bits!(LANE, 4);
53564 unsafe { simd_insert!(b, LANE as u32, a) }
53565}
53566#[doc = "Insert vector element from another vector element"]
53567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
53568#[inline]
53569#[target_feature(enable = "neon")]
53570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53572#[cfg_attr(
53573 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53574 assert_instr(nop, LANE = 0)
53575)]
53576#[rustc_legacy_const_generics(2)]
53577#[cfg_attr(
53578 not(target_arch = "arm"),
53579 stable(feature = "neon_intrinsics", since = "1.59.0")
53580)]
53581#[cfg_attr(
53582 target_arch = "arm",
53583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53584)]
53585pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
53586 static_assert_uimm_bits!(LANE, 2);
53587 unsafe { simd_insert!(b, LANE as u32, a) }
53588}
53589#[doc = "Insert vector element from another vector element"]
53590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
53591#[inline]
53592#[target_feature(enable = "neon")]
53593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53594#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53595#[cfg_attr(
53596 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53597 assert_instr(nop, LANE = 0)
53598)]
53599#[rustc_legacy_const_generics(2)]
53600#[cfg_attr(
53601 not(target_arch = "arm"),
53602 stable(feature = "neon_intrinsics", since = "1.59.0")
53603)]
53604#[cfg_attr(
53605 target_arch = "arm",
53606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53607)]
53608pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
53609 static_assert_uimm_bits!(LANE, 3);
53610 unsafe { simd_insert!(b, LANE as u32, a) }
53611}
53612#[doc = "Insert vector element from another vector element"]
53613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
53614#[inline]
53615#[target_feature(enable = "neon")]
53616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53618#[cfg_attr(
53619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53620 assert_instr(nop, LANE = 0)
53621)]
53622#[rustc_legacy_const_generics(2)]
53623#[cfg_attr(
53624 not(target_arch = "arm"),
53625 stable(feature = "neon_intrinsics", since = "1.59.0")
53626)]
53627#[cfg_attr(
53628 target_arch = "arm",
53629 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53630)]
53631pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
53632 static_assert_uimm_bits!(LANE, 1);
53633 unsafe { simd_insert!(b, LANE as u32, a) }
53634}
53635#[doc = "Insert vector element from another vector element"]
53636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
53637#[inline]
53638#[target_feature(enable = "neon")]
53639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53641#[cfg_attr(
53642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53643 assert_instr(nop, LANE = 0)
53644)]
53645#[rustc_legacy_const_generics(2)]
53646#[cfg_attr(
53647 not(target_arch = "arm"),
53648 stable(feature = "neon_intrinsics", since = "1.59.0")
53649)]
53650#[cfg_attr(
53651 target_arch = "arm",
53652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53653)]
53654pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
53655 static_assert_uimm_bits!(LANE, 2);
53656 unsafe { simd_insert!(b, LANE as u32, a) }
53657}
53658#[doc = "Insert vector element from another vector element"]
53659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
53660#[inline]
53661#[target_feature(enable = "neon")]
53662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53664#[cfg_attr(
53665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53666 assert_instr(nop, LANE = 0)
53667)]
53668#[rustc_legacy_const_generics(2)]
53669#[cfg_attr(
53670 not(target_arch = "arm"),
53671 stable(feature = "neon_intrinsics", since = "1.59.0")
53672)]
53673#[cfg_attr(
53674 target_arch = "arm",
53675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53676)]
53677pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
53678 static_assert_uimm_bits!(LANE, 1);
53679 unsafe { simd_insert!(b, LANE as u32, a) }
53680}
53681#[doc = "Insert vector element from another vector element"]
53682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
53683#[inline]
53684#[target_feature(enable = "neon")]
53685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53687#[cfg_attr(
53688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53689 assert_instr(nop, LANE = 0)
53690)]
53691#[rustc_legacy_const_generics(2)]
53692#[cfg_attr(
53693 not(target_arch = "arm"),
53694 stable(feature = "neon_intrinsics", since = "1.59.0")
53695)]
53696#[cfg_attr(
53697 target_arch = "arm",
53698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53699)]
53700pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
53701 static_assert_uimm_bits!(LANE, 3);
53702 unsafe { simd_insert!(b, LANE as u32, a) }
53703}
53704#[doc = "Insert vector element from another vector element"]
53705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
53706#[inline]
53707#[target_feature(enable = "neon")]
53708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53710#[cfg_attr(
53711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53712 assert_instr(nop, LANE = 0)
53713)]
53714#[rustc_legacy_const_generics(2)]
53715#[cfg_attr(
53716 not(target_arch = "arm"),
53717 stable(feature = "neon_intrinsics", since = "1.59.0")
53718)]
53719#[cfg_attr(
53720 target_arch = "arm",
53721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53722)]
53723pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
53724 static_assert_uimm_bits!(LANE, 4);
53725 unsafe { simd_insert!(b, LANE as u32, a) }
53726}
53727#[doc = "Insert vector element from another vector element"]
53728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
53729#[inline]
53730#[target_feature(enable = "neon")]
53731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53733#[cfg_attr(
53734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53735 assert_instr(nop, LANE = 0)
53736)]
53737#[rustc_legacy_const_generics(2)]
53738#[cfg_attr(
53739 not(target_arch = "arm"),
53740 stable(feature = "neon_intrinsics", since = "1.59.0")
53741)]
53742#[cfg_attr(
53743 target_arch = "arm",
53744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53745)]
53746pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
53747 static_assert_uimm_bits!(LANE, 2);
53748 unsafe { simd_insert!(b, LANE as u32, a) }
53749}
53750#[doc = "Insert vector element from another vector element"]
53751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
53752#[inline]
53753#[target_feature(enable = "neon")]
53754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53756#[cfg_attr(
53757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53758 assert_instr(nop, LANE = 0)
53759)]
53760#[rustc_legacy_const_generics(2)]
53761#[cfg_attr(
53762 not(target_arch = "arm"),
53763 stable(feature = "neon_intrinsics", since = "1.59.0")
53764)]
53765#[cfg_attr(
53766 target_arch = "arm",
53767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53768)]
53769pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
53770 static_assert_uimm_bits!(LANE, 3);
53771 unsafe { simd_insert!(b, LANE as u32, a) }
53772}
53773#[doc = "Insert vector element from another vector element"]
53774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
53775#[inline]
53776#[target_feature(enable = "neon")]
53777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53779#[cfg_attr(
53780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53781 assert_instr(nop, LANE = 0)
53782)]
53783#[rustc_legacy_const_generics(2)]
53784#[cfg_attr(
53785 not(target_arch = "arm"),
53786 stable(feature = "neon_intrinsics", since = "1.59.0")
53787)]
53788#[cfg_attr(
53789 target_arch = "arm",
53790 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53791)]
53792pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
53793 static_assert_uimm_bits!(LANE, 1);
53794 unsafe { simd_insert!(b, LANE as u32, a) }
53795}
53796#[doc = "Insert vector element from another vector element"]
53797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
53798#[inline]
53799#[target_feature(enable = "neon")]
53800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53802#[cfg_attr(
53803 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53804 assert_instr(nop, LANE = 0)
53805)]
53806#[rustc_legacy_const_generics(2)]
53807#[cfg_attr(
53808 not(target_arch = "arm"),
53809 stable(feature = "neon_intrinsics", since = "1.59.0")
53810)]
53811#[cfg_attr(
53812 target_arch = "arm",
53813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53814)]
53815pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
53816 static_assert_uimm_bits!(LANE, 2);
53817 unsafe { simd_insert!(b, LANE as u32, a) }
53818}
53819#[doc = "Insert vector element from another vector element"]
53820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
53821#[inline]
53822#[target_feature(enable = "neon")]
53823#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53824#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53825#[cfg_attr(
53826 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53827 assert_instr(nop, LANE = 0)
53828)]
53829#[rustc_legacy_const_generics(2)]
53830#[cfg_attr(
53831 not(target_arch = "arm"),
53832 stable(feature = "neon_intrinsics", since = "1.59.0")
53833)]
53834#[cfg_attr(
53835 target_arch = "arm",
53836 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53837)]
53838pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
53839 static_assert_uimm_bits!(LANE, 1);
53840 unsafe { simd_insert!(b, LANE as u32, a) }
53841}
53842#[doc = "Insert vector element from another vector element"]
53843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
53844#[inline]
53845#[target_feature(enable = "neon")]
53846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53848#[cfg_attr(
53849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53850 assert_instr(nop, LANE = 0)
53851)]
53852#[rustc_legacy_const_generics(2)]
53853#[cfg_attr(
53854 not(target_arch = "arm"),
53855 stable(feature = "neon_intrinsics", since = "1.59.0")
53856)]
53857#[cfg_attr(
53858 target_arch = "arm",
53859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53860)]
53861pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
53862 static_assert_uimm_bits!(LANE, 3);
53863 unsafe { simd_insert!(b, LANE as u32, a) }
53864}
53865#[doc = "Insert vector element from another vector element"]
53866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
53867#[inline]
53868#[target_feature(enable = "neon")]
53869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53871#[cfg_attr(
53872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53873 assert_instr(nop, LANE = 0)
53874)]
53875#[rustc_legacy_const_generics(2)]
53876#[cfg_attr(
53877 not(target_arch = "arm"),
53878 stable(feature = "neon_intrinsics", since = "1.59.0")
53879)]
53880#[cfg_attr(
53881 target_arch = "arm",
53882 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53883)]
53884pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
53885 static_assert_uimm_bits!(LANE, 4);
53886 unsafe { simd_insert!(b, LANE as u32, a) }
53887}
53888#[doc = "Insert vector element from another vector element"]
53889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
53890#[inline]
53891#[target_feature(enable = "neon")]
53892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53893#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53894#[cfg_attr(
53895 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53896 assert_instr(nop, LANE = 0)
53897)]
53898#[rustc_legacy_const_generics(2)]
53899#[cfg_attr(
53900 not(target_arch = "arm"),
53901 stable(feature = "neon_intrinsics", since = "1.59.0")
53902)]
53903#[cfg_attr(
53904 target_arch = "arm",
53905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53906)]
53907pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
53908 static_assert_uimm_bits!(LANE, 2);
53909 unsafe { simd_insert!(b, LANE as u32, a) }
53910}
53911#[doc = "Insert vector element from another vector element"]
53912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
53913#[inline]
53914#[target_feature(enable = "neon")]
53915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53917#[cfg_attr(
53918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53919 assert_instr(nop, LANE = 0)
53920)]
53921#[rustc_legacy_const_generics(2)]
53922#[cfg_attr(
53923 not(target_arch = "arm"),
53924 stable(feature = "neon_intrinsics", since = "1.59.0")
53925)]
53926#[cfg_attr(
53927 target_arch = "arm",
53928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53929)]
53930pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
53931 static_assert_uimm_bits!(LANE, 3);
53932 unsafe { simd_insert!(b, LANE as u32, a) }
53933}
53934#[doc = "Insert vector element from another vector element"]
53935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
53936#[inline]
53937#[target_feature(enable = "neon,aes")]
53938#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
53939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53940#[cfg_attr(
53941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53942 assert_instr(nop, LANE = 0)
53943)]
53944#[rustc_legacy_const_generics(2)]
53945#[cfg_attr(
53946 not(target_arch = "arm"),
53947 stable(feature = "neon_intrinsics", since = "1.59.0")
53948)]
53949#[cfg_attr(
53950 target_arch = "arm",
53951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53952)]
53953pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
53954 static_assert!(LANE == 0);
53955 unsafe { simd_insert!(b, LANE as u32, a) }
53956}
53957#[doc = "Insert vector element from another vector element"]
53958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
53959#[inline]
53960#[target_feature(enable = "neon")]
53961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53963#[cfg_attr(
53964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53965 assert_instr(nop, LANE = 0)
53966)]
53967#[rustc_legacy_const_generics(2)]
53968#[cfg_attr(
53969 not(target_arch = "arm"),
53970 stable(feature = "neon_intrinsics", since = "1.59.0")
53971)]
53972#[cfg_attr(
53973 target_arch = "arm",
53974 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53975)]
53976pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
53977 static_assert!(LANE == 0);
53978 unsafe { simd_insert!(b, LANE as u32, a) }
53979}
53980#[doc = "Insert vector element from another vector element"]
53981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
53982#[inline]
53983#[target_feature(enable = "neon")]
53984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
53986#[cfg_attr(
53987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53988 assert_instr(nop, LANE = 0)
53989)]
53990#[rustc_legacy_const_generics(2)]
53991#[cfg_attr(
53992 not(target_arch = "arm"),
53993 stable(feature = "neon_intrinsics", since = "1.59.0")
53994)]
53995#[cfg_attr(
53996 target_arch = "arm",
53997 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53998)]
53999pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
54000 static_assert!(LANE == 0);
54001 unsafe { simd_insert!(b, LANE as u32, a) }
54002}
54003#[doc = "Insert vector element from another vector element"]
54004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
54005#[inline]
54006#[target_feature(enable = "neon,aes")]
54007#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
54009#[cfg_attr(
54010 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54011 assert_instr(nop, LANE = 0)
54012)]
54013#[rustc_legacy_const_generics(2)]
54014#[cfg_attr(
54015 not(target_arch = "arm"),
54016 stable(feature = "neon_intrinsics", since = "1.59.0")
54017)]
54018#[cfg_attr(
54019 target_arch = "arm",
54020 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54021)]
54022pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
54023 static_assert_uimm_bits!(LANE, 1);
54024 unsafe { simd_insert!(b, LANE as u32, a) }
54025}
54026#[doc = "SHA1 hash update accelerator, choose."]
54027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
54028#[inline]
54029#[target_feature(enable = "sha2")]
54030#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54031#[cfg_attr(test, assert_instr(sha1c))]
54032#[cfg_attr(
54033 target_arch = "arm",
54034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54035)]
54036#[cfg_attr(
54037 not(target_arch = "arm"),
54038 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54039)]
54040pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
54041 unsafe extern "unadjusted" {
54042 #[cfg_attr(
54043 any(target_arch = "aarch64", target_arch = "arm64ec"),
54044 link_name = "llvm.aarch64.crypto.sha1c"
54045 )]
54046 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
54047 fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
54048 }
54049 unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) }
54050}
54051#[doc = "SHA1 fixed rotate."]
54052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
54053#[inline]
54054#[target_feature(enable = "sha2")]
54055#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54056#[cfg_attr(test, assert_instr(sha1h))]
54057#[cfg_attr(
54058 target_arch = "arm",
54059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54060)]
54061#[cfg_attr(
54062 not(target_arch = "arm"),
54063 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54064)]
54065pub fn vsha1h_u32(hash_e: u32) -> u32 {
54066 unsafe extern "unadjusted" {
54067 #[cfg_attr(
54068 any(target_arch = "aarch64", target_arch = "arm64ec"),
54069 link_name = "llvm.aarch64.crypto.sha1h"
54070 )]
54071 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
54072 fn _vsha1h_u32(hash_e: u32) -> u32;
54073 }
54074 unsafe { _vsha1h_u32(hash_e) }
54075}
54076#[doc = "SHA1 hash update accelerator, majority"]
54077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
54078#[inline]
54079#[target_feature(enable = "sha2")]
54080#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54081#[cfg_attr(test, assert_instr(sha1m))]
54082#[cfg_attr(
54083 target_arch = "arm",
54084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54085)]
54086#[cfg_attr(
54087 not(target_arch = "arm"),
54088 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54089)]
54090pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
54091 unsafe extern "unadjusted" {
54092 #[cfg_attr(
54093 any(target_arch = "aarch64", target_arch = "arm64ec"),
54094 link_name = "llvm.aarch64.crypto.sha1m"
54095 )]
54096 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
54097 fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
54098 }
54099 unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) }
54100}
54101#[doc = "SHA1 hash update accelerator, parity"]
54102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
54103#[inline]
54104#[target_feature(enable = "sha2")]
54105#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54106#[cfg_attr(test, assert_instr(sha1p))]
54107#[cfg_attr(
54108 target_arch = "arm",
54109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54110)]
54111#[cfg_attr(
54112 not(target_arch = "arm"),
54113 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54114)]
54115pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
54116 unsafe extern "unadjusted" {
54117 #[cfg_attr(
54118 any(target_arch = "aarch64", target_arch = "arm64ec"),
54119 link_name = "llvm.aarch64.crypto.sha1p"
54120 )]
54121 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
54122 fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
54123 }
54124 unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) }
54125}
54126#[doc = "SHA1 schedule update accelerator, first part."]
54127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
54128#[inline]
54129#[target_feature(enable = "sha2")]
54130#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54131#[cfg_attr(test, assert_instr(sha1su0))]
54132#[cfg_attr(
54133 target_arch = "arm",
54134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54135)]
54136#[cfg_attr(
54137 not(target_arch = "arm"),
54138 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54139)]
54140pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
54141 unsafe extern "unadjusted" {
54142 #[cfg_attr(
54143 any(target_arch = "aarch64", target_arch = "arm64ec"),
54144 link_name = "llvm.aarch64.crypto.sha1su0"
54145 )]
54146 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
54147 fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
54148 }
54149 unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) }
54150}
54151#[doc = "SHA1 schedule update accelerator, second part."]
54152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
54153#[inline]
54154#[target_feature(enable = "sha2")]
54155#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54156#[cfg_attr(test, assert_instr(sha1su1))]
54157#[cfg_attr(
54158 target_arch = "arm",
54159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54160)]
54161#[cfg_attr(
54162 not(target_arch = "arm"),
54163 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54164)]
54165pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
54166 unsafe extern "unadjusted" {
54167 #[cfg_attr(
54168 any(target_arch = "aarch64", target_arch = "arm64ec"),
54169 link_name = "llvm.aarch64.crypto.sha1su1"
54170 )]
54171 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
54172 fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
54173 }
54174 unsafe { _vsha1su1q_u32(tw0_3, w12_15) }
54175}
54176#[doc = "SHA1 schedule update accelerator, upper part."]
54177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
54178#[inline]
54179#[target_feature(enable = "sha2")]
54180#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54181#[cfg_attr(test, assert_instr(sha256h2))]
54182#[cfg_attr(
54183 target_arch = "arm",
54184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54185)]
54186#[cfg_attr(
54187 not(target_arch = "arm"),
54188 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54189)]
54190pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
54191 unsafe extern "unadjusted" {
54192 #[cfg_attr(
54193 any(target_arch = "aarch64", target_arch = "arm64ec"),
54194 link_name = "llvm.aarch64.crypto.sha256h2"
54195 )]
54196 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
54197 fn _vsha256h2q_u32(
54198 hash_abcd: uint32x4_t,
54199 hash_efgh: uint32x4_t,
54200 wk: uint32x4_t,
54201 ) -> uint32x4_t;
54202 }
54203 unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) }
54204}
54205#[doc = "SHA1 schedule update accelerator, first part."]
54206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
54207#[inline]
54208#[target_feature(enable = "sha2")]
54209#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54210#[cfg_attr(test, assert_instr(sha256h))]
54211#[cfg_attr(
54212 target_arch = "arm",
54213 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54214)]
54215#[cfg_attr(
54216 not(target_arch = "arm"),
54217 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54218)]
54219pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
54220 unsafe extern "unadjusted" {
54221 #[cfg_attr(
54222 any(target_arch = "aarch64", target_arch = "arm64ec"),
54223 link_name = "llvm.aarch64.crypto.sha256h"
54224 )]
54225 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
54226 fn _vsha256hq_u32(
54227 hash_abcd: uint32x4_t,
54228 hash_efgh: uint32x4_t,
54229 wk: uint32x4_t,
54230 ) -> uint32x4_t;
54231 }
54232 unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) }
54233}
54234#[doc = "SHA256 schedule update accelerator, first part."]
54235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
54236#[inline]
54237#[target_feature(enable = "sha2")]
54238#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54239#[cfg_attr(test, assert_instr(sha256su0))]
54240#[cfg_attr(
54241 target_arch = "arm",
54242 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54243)]
54244#[cfg_attr(
54245 not(target_arch = "arm"),
54246 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54247)]
54248pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
54249 unsafe extern "unadjusted" {
54250 #[cfg_attr(
54251 any(target_arch = "aarch64", target_arch = "arm64ec"),
54252 link_name = "llvm.aarch64.crypto.sha256su0"
54253 )]
54254 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
54255 fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
54256 }
54257 unsafe { _vsha256su0q_u32(w0_3, w4_7) }
54258}
54259#[doc = "SHA256 schedule update accelerator, second part."]
54260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
54261#[inline]
54262#[target_feature(enable = "sha2")]
54263#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54264#[cfg_attr(test, assert_instr(sha256su1))]
54265#[cfg_attr(
54266 target_arch = "arm",
54267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54268)]
54269#[cfg_attr(
54270 not(target_arch = "arm"),
54271 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
54272)]
54273pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
54274 unsafe extern "unadjusted" {
54275 #[cfg_attr(
54276 any(target_arch = "aarch64", target_arch = "arm64ec"),
54277 link_name = "llvm.aarch64.crypto.sha256su1"
54278 )]
54279 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
54280 fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
54281 -> uint32x4_t;
54282 }
54283 unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
54284}
54285#[doc = "Shift Right and Insert (immediate)"]
54286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
54287#[inline]
54288#[target_feature(enable = "neon")]
54289#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54290fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
54291 unsafe extern "unadjusted" {
54292 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
54293 fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
54294 }
54295 unsafe { _vshiftins_v16i8(a, b, c) }
54296}
54297#[doc = "Shift Right and Insert (immediate)"]
54298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
54299#[inline]
54300#[target_feature(enable = "neon")]
54301#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54302fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
54303 unsafe extern "unadjusted" {
54304 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
54305 fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
54306 }
54307 unsafe { _vshiftins_v1i64(a, b, c) }
54308}
54309#[doc = "Shift Right and Insert (immediate)"]
54310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
54311#[inline]
54312#[target_feature(enable = "neon")]
54313#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54314fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
54315 unsafe extern "unadjusted" {
54316 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
54317 fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
54318 }
54319 unsafe { _vshiftins_v2i32(a, b, c) }
54320}
54321#[doc = "Shift Right and Insert (immediate)"]
54322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
54323#[inline]
54324#[target_feature(enable = "neon")]
54325#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54326fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
54327 unsafe extern "unadjusted" {
54328 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
54329 fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
54330 }
54331 unsafe { _vshiftins_v2i64(a, b, c) }
54332}
54333#[doc = "Shift Right and Insert (immediate)"]
54334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
54335#[inline]
54336#[target_feature(enable = "neon")]
54337#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54338fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
54339 unsafe extern "unadjusted" {
54340 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
54341 fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
54342 }
54343 unsafe { _vshiftins_v4i16(a, b, c) }
54344}
54345#[doc = "Shift Right and Insert (immediate)"]
54346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
54347#[inline]
54348#[target_feature(enable = "neon")]
54349#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54350fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
54351 unsafe extern "unadjusted" {
54352 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
54353 fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
54354 }
54355 unsafe { _vshiftins_v4i32(a, b, c) }
54356}
54357#[doc = "Shift Right and Insert (immediate)"]
54358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
54359#[inline]
54360#[target_feature(enable = "neon")]
54361#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54362fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
54363 unsafe extern "unadjusted" {
54364 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
54365 fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
54366 }
54367 unsafe { _vshiftins_v8i16(a, b, c) }
54368}
54369#[doc = "Shift Right and Insert (immediate)"]
54370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
54371#[inline]
54372#[target_feature(enable = "neon")]
54373#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
54374fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
54375 unsafe extern "unadjusted" {
54376 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
54377 fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
54378 }
54379 unsafe { _vshiftins_v8i8(a, b, c) }
54380}
54381#[doc = "Shift left"]
54382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
54383#[inline]
54384#[target_feature(enable = "neon")]
54385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54387#[cfg_attr(
54388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54389 assert_instr(shl, N = 2)
54390)]
54391#[rustc_legacy_const_generics(1)]
54392#[cfg_attr(
54393 not(target_arch = "arm"),
54394 stable(feature = "neon_intrinsics", since = "1.59.0")
54395)]
54396#[cfg_attr(
54397 target_arch = "arm",
54398 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54399)]
54400pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
54401 static_assert_uimm_bits!(N, 3);
54402 unsafe { simd_shl(a, vdup_n_s8(N as _)) }
54403}
54404#[doc = "Shift left"]
54405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
54406#[inline]
54407#[target_feature(enable = "neon")]
54408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54410#[cfg_attr(
54411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54412 assert_instr(shl, N = 2)
54413)]
54414#[rustc_legacy_const_generics(1)]
54415#[cfg_attr(
54416 not(target_arch = "arm"),
54417 stable(feature = "neon_intrinsics", since = "1.59.0")
54418)]
54419#[cfg_attr(
54420 target_arch = "arm",
54421 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54422)]
54423pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
54424 static_assert_uimm_bits!(N, 3);
54425 unsafe { simd_shl(a, vdupq_n_s8(N as _)) }
54426}
54427#[doc = "Shift left"]
54428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
54429#[inline]
54430#[target_feature(enable = "neon")]
54431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54433#[cfg_attr(
54434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54435 assert_instr(shl, N = 2)
54436)]
54437#[rustc_legacy_const_generics(1)]
54438#[cfg_attr(
54439 not(target_arch = "arm"),
54440 stable(feature = "neon_intrinsics", since = "1.59.0")
54441)]
54442#[cfg_attr(
54443 target_arch = "arm",
54444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54445)]
54446pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
54447 static_assert_uimm_bits!(N, 4);
54448 unsafe { simd_shl(a, vdup_n_s16(N as _)) }
54449}
54450#[doc = "Shift left"]
54451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
54452#[inline]
54453#[target_feature(enable = "neon")]
54454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54456#[cfg_attr(
54457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54458 assert_instr(shl, N = 2)
54459)]
54460#[rustc_legacy_const_generics(1)]
54461#[cfg_attr(
54462 not(target_arch = "arm"),
54463 stable(feature = "neon_intrinsics", since = "1.59.0")
54464)]
54465#[cfg_attr(
54466 target_arch = "arm",
54467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54468)]
54469pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
54470 static_assert_uimm_bits!(N, 4);
54471 unsafe { simd_shl(a, vdupq_n_s16(N as _)) }
54472}
54473#[doc = "Shift left"]
54474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
54475#[inline]
54476#[target_feature(enable = "neon")]
54477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54479#[cfg_attr(
54480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54481 assert_instr(shl, N = 2)
54482)]
54483#[rustc_legacy_const_generics(1)]
54484#[cfg_attr(
54485 not(target_arch = "arm"),
54486 stable(feature = "neon_intrinsics", since = "1.59.0")
54487)]
54488#[cfg_attr(
54489 target_arch = "arm",
54490 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54491)]
54492pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
54493 static_assert_uimm_bits!(N, 5);
54494 unsafe { simd_shl(a, vdup_n_s32(N as _)) }
54495}
54496#[doc = "Shift left"]
54497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
54498#[inline]
54499#[target_feature(enable = "neon")]
54500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54502#[cfg_attr(
54503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54504 assert_instr(shl, N = 2)
54505)]
54506#[rustc_legacy_const_generics(1)]
54507#[cfg_attr(
54508 not(target_arch = "arm"),
54509 stable(feature = "neon_intrinsics", since = "1.59.0")
54510)]
54511#[cfg_attr(
54512 target_arch = "arm",
54513 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54514)]
54515pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
54516 static_assert_uimm_bits!(N, 5);
54517 unsafe { simd_shl(a, vdupq_n_s32(N as _)) }
54518}
54519#[doc = "Shift left"]
54520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
54521#[inline]
54522#[target_feature(enable = "neon")]
54523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54525#[cfg_attr(
54526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54527 assert_instr(shl, N = 2)
54528)]
54529#[rustc_legacy_const_generics(1)]
54530#[cfg_attr(
54531 not(target_arch = "arm"),
54532 stable(feature = "neon_intrinsics", since = "1.59.0")
54533)]
54534#[cfg_attr(
54535 target_arch = "arm",
54536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54537)]
54538pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
54539 static_assert_uimm_bits!(N, 6);
54540 unsafe { simd_shl(a, vdup_n_s64(N as _)) }
54541}
54542#[doc = "Shift left"]
54543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
54544#[inline]
54545#[target_feature(enable = "neon")]
54546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54548#[cfg_attr(
54549 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54550 assert_instr(shl, N = 2)
54551)]
54552#[rustc_legacy_const_generics(1)]
54553#[cfg_attr(
54554 not(target_arch = "arm"),
54555 stable(feature = "neon_intrinsics", since = "1.59.0")
54556)]
54557#[cfg_attr(
54558 target_arch = "arm",
54559 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54560)]
54561pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
54562 static_assert_uimm_bits!(N, 6);
54563 unsafe { simd_shl(a, vdupq_n_s64(N as _)) }
54564}
54565#[doc = "Shift left"]
54566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
54567#[inline]
54568#[target_feature(enable = "neon")]
54569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54571#[cfg_attr(
54572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54573 assert_instr(shl, N = 2)
54574)]
54575#[rustc_legacy_const_generics(1)]
54576#[cfg_attr(
54577 not(target_arch = "arm"),
54578 stable(feature = "neon_intrinsics", since = "1.59.0")
54579)]
54580#[cfg_attr(
54581 target_arch = "arm",
54582 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54583)]
54584pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
54585 static_assert_uimm_bits!(N, 3);
54586 unsafe { simd_shl(a, vdup_n_u8(N as _)) }
54587}
54588#[doc = "Shift left"]
54589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
54590#[inline]
54591#[target_feature(enable = "neon")]
54592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54594#[cfg_attr(
54595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54596 assert_instr(shl, N = 2)
54597)]
54598#[rustc_legacy_const_generics(1)]
54599#[cfg_attr(
54600 not(target_arch = "arm"),
54601 stable(feature = "neon_intrinsics", since = "1.59.0")
54602)]
54603#[cfg_attr(
54604 target_arch = "arm",
54605 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54606)]
54607pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
54608 static_assert_uimm_bits!(N, 3);
54609 unsafe { simd_shl(a, vdupq_n_u8(N as _)) }
54610}
54611#[doc = "Shift left"]
54612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
54613#[inline]
54614#[target_feature(enable = "neon")]
54615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54617#[cfg_attr(
54618 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54619 assert_instr(shl, N = 2)
54620)]
54621#[rustc_legacy_const_generics(1)]
54622#[cfg_attr(
54623 not(target_arch = "arm"),
54624 stable(feature = "neon_intrinsics", since = "1.59.0")
54625)]
54626#[cfg_attr(
54627 target_arch = "arm",
54628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54629)]
54630pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
54631 static_assert_uimm_bits!(N, 4);
54632 unsafe { simd_shl(a, vdup_n_u16(N as _)) }
54633}
54634#[doc = "Shift left"]
54635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
54636#[inline]
54637#[target_feature(enable = "neon")]
54638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54640#[cfg_attr(
54641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54642 assert_instr(shl, N = 2)
54643)]
54644#[rustc_legacy_const_generics(1)]
54645#[cfg_attr(
54646 not(target_arch = "arm"),
54647 stable(feature = "neon_intrinsics", since = "1.59.0")
54648)]
54649#[cfg_attr(
54650 target_arch = "arm",
54651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54652)]
54653pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
54654 static_assert_uimm_bits!(N, 4);
54655 unsafe { simd_shl(a, vdupq_n_u16(N as _)) }
54656}
54657#[doc = "Shift left"]
54658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
54659#[inline]
54660#[target_feature(enable = "neon")]
54661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54662#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54663#[cfg_attr(
54664 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54665 assert_instr(shl, N = 2)
54666)]
54667#[rustc_legacy_const_generics(1)]
54668#[cfg_attr(
54669 not(target_arch = "arm"),
54670 stable(feature = "neon_intrinsics", since = "1.59.0")
54671)]
54672#[cfg_attr(
54673 target_arch = "arm",
54674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54675)]
54676pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
54677 static_assert_uimm_bits!(N, 5);
54678 unsafe { simd_shl(a, vdup_n_u32(N as _)) }
54679}
54680#[doc = "Shift left"]
54681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
54682#[inline]
54683#[target_feature(enable = "neon")]
54684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54686#[cfg_attr(
54687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54688 assert_instr(shl, N = 2)
54689)]
54690#[rustc_legacy_const_generics(1)]
54691#[cfg_attr(
54692 not(target_arch = "arm"),
54693 stable(feature = "neon_intrinsics", since = "1.59.0")
54694)]
54695#[cfg_attr(
54696 target_arch = "arm",
54697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54698)]
54699pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
54700 static_assert_uimm_bits!(N, 5);
54701 unsafe { simd_shl(a, vdupq_n_u32(N as _)) }
54702}
54703#[doc = "Shift left"]
54704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
54705#[inline]
54706#[target_feature(enable = "neon")]
54707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54709#[cfg_attr(
54710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54711 assert_instr(shl, N = 2)
54712)]
54713#[rustc_legacy_const_generics(1)]
54714#[cfg_attr(
54715 not(target_arch = "arm"),
54716 stable(feature = "neon_intrinsics", since = "1.59.0")
54717)]
54718#[cfg_attr(
54719 target_arch = "arm",
54720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54721)]
54722pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
54723 static_assert_uimm_bits!(N, 6);
54724 unsafe { simd_shl(a, vdup_n_u64(N as _)) }
54725}
54726#[doc = "Shift left"]
54727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
54728#[inline]
54729#[target_feature(enable = "neon")]
54730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
54732#[cfg_attr(
54733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54734 assert_instr(shl, N = 2)
54735)]
54736#[rustc_legacy_const_generics(1)]
54737#[cfg_attr(
54738 not(target_arch = "arm"),
54739 stable(feature = "neon_intrinsics", since = "1.59.0")
54740)]
54741#[cfg_attr(
54742 target_arch = "arm",
54743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54744)]
54745pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
54746 static_assert_uimm_bits!(N, 6);
54747 unsafe { simd_shl(a, vdupq_n_u64(N as _)) }
54748}
54749#[doc = "Signed Shift left"]
54750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
54751#[inline]
54752#[target_feature(enable = "neon")]
54753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54755#[cfg_attr(
54756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54757 assert_instr(sshl)
54758)]
54759#[cfg_attr(
54760 not(target_arch = "arm"),
54761 stable(feature = "neon_intrinsics", since = "1.59.0")
54762)]
54763#[cfg_attr(
54764 target_arch = "arm",
54765 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54766)]
54767pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
54768 unsafe extern "unadjusted" {
54769 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")]
54770 #[cfg_attr(
54771 any(target_arch = "aarch64", target_arch = "arm64ec"),
54772 link_name = "llvm.aarch64.neon.sshl.v8i8"
54773 )]
54774 fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
54775 }
54776 unsafe { _vshl_s8(a, b) }
54777}
54778#[doc = "Signed Shift left"]
54779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
54780#[inline]
54781#[target_feature(enable = "neon")]
54782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54784#[cfg_attr(
54785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54786 assert_instr(sshl)
54787)]
54788#[cfg_attr(
54789 not(target_arch = "arm"),
54790 stable(feature = "neon_intrinsics", since = "1.59.0")
54791)]
54792#[cfg_attr(
54793 target_arch = "arm",
54794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54795)]
54796pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
54797 unsafe extern "unadjusted" {
54798 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")]
54799 #[cfg_attr(
54800 any(target_arch = "aarch64", target_arch = "arm64ec"),
54801 link_name = "llvm.aarch64.neon.sshl.v16i8"
54802 )]
54803 fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
54804 }
54805 unsafe { _vshlq_s8(a, b) }
54806}
54807#[doc = "Signed Shift left"]
54808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
54809#[inline]
54810#[target_feature(enable = "neon")]
54811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54813#[cfg_attr(
54814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54815 assert_instr(sshl)
54816)]
54817#[cfg_attr(
54818 not(target_arch = "arm"),
54819 stable(feature = "neon_intrinsics", since = "1.59.0")
54820)]
54821#[cfg_attr(
54822 target_arch = "arm",
54823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54824)]
54825pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
54826 unsafe extern "unadjusted" {
54827 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")]
54828 #[cfg_attr(
54829 any(target_arch = "aarch64", target_arch = "arm64ec"),
54830 link_name = "llvm.aarch64.neon.sshl.v4i16"
54831 )]
54832 fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
54833 }
54834 unsafe { _vshl_s16(a, b) }
54835}
54836#[doc = "Signed Shift left"]
54837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
54838#[inline]
54839#[target_feature(enable = "neon")]
54840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54841#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54842#[cfg_attr(
54843 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54844 assert_instr(sshl)
54845)]
54846#[cfg_attr(
54847 not(target_arch = "arm"),
54848 stable(feature = "neon_intrinsics", since = "1.59.0")
54849)]
54850#[cfg_attr(
54851 target_arch = "arm",
54852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54853)]
54854pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
54855 unsafe extern "unadjusted" {
54856 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")]
54857 #[cfg_attr(
54858 any(target_arch = "aarch64", target_arch = "arm64ec"),
54859 link_name = "llvm.aarch64.neon.sshl.v8i16"
54860 )]
54861 fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
54862 }
54863 unsafe { _vshlq_s16(a, b) }
54864}
54865#[doc = "Signed Shift left"]
54866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
54867#[inline]
54868#[target_feature(enable = "neon")]
54869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54871#[cfg_attr(
54872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54873 assert_instr(sshl)
54874)]
54875#[cfg_attr(
54876 not(target_arch = "arm"),
54877 stable(feature = "neon_intrinsics", since = "1.59.0")
54878)]
54879#[cfg_attr(
54880 target_arch = "arm",
54881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54882)]
54883pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
54884 unsafe extern "unadjusted" {
54885 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")]
54886 #[cfg_attr(
54887 any(target_arch = "aarch64", target_arch = "arm64ec"),
54888 link_name = "llvm.aarch64.neon.sshl.v2i32"
54889 )]
54890 fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
54891 }
54892 unsafe { _vshl_s32(a, b) }
54893}
54894#[doc = "Signed Shift left"]
54895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
54896#[inline]
54897#[target_feature(enable = "neon")]
54898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54900#[cfg_attr(
54901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54902 assert_instr(sshl)
54903)]
54904#[cfg_attr(
54905 not(target_arch = "arm"),
54906 stable(feature = "neon_intrinsics", since = "1.59.0")
54907)]
54908#[cfg_attr(
54909 target_arch = "arm",
54910 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54911)]
54912pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
54913 unsafe extern "unadjusted" {
54914 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")]
54915 #[cfg_attr(
54916 any(target_arch = "aarch64", target_arch = "arm64ec"),
54917 link_name = "llvm.aarch64.neon.sshl.v4i32"
54918 )]
54919 fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
54920 }
54921 unsafe { _vshlq_s32(a, b) }
54922}
54923#[doc = "Signed Shift left"]
54924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
54925#[inline]
54926#[target_feature(enable = "neon")]
54927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54929#[cfg_attr(
54930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54931 assert_instr(sshl)
54932)]
54933#[cfg_attr(
54934 not(target_arch = "arm"),
54935 stable(feature = "neon_intrinsics", since = "1.59.0")
54936)]
54937#[cfg_attr(
54938 target_arch = "arm",
54939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54940)]
54941pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
54942 unsafe extern "unadjusted" {
54943 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")]
54944 #[cfg_attr(
54945 any(target_arch = "aarch64", target_arch = "arm64ec"),
54946 link_name = "llvm.aarch64.neon.sshl.v1i64"
54947 )]
54948 fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
54949 }
54950 unsafe { _vshl_s64(a, b) }
54951}
54952#[doc = "Signed Shift left"]
54953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
54954#[inline]
54955#[target_feature(enable = "neon")]
54956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54957#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54958#[cfg_attr(
54959 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54960 assert_instr(sshl)
54961)]
54962#[cfg_attr(
54963 not(target_arch = "arm"),
54964 stable(feature = "neon_intrinsics", since = "1.59.0")
54965)]
54966#[cfg_attr(
54967 target_arch = "arm",
54968 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54969)]
54970pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
54971 unsafe extern "unadjusted" {
54972 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")]
54973 #[cfg_attr(
54974 any(target_arch = "aarch64", target_arch = "arm64ec"),
54975 link_name = "llvm.aarch64.neon.sshl.v2i64"
54976 )]
54977 fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
54978 }
54979 unsafe { _vshlq_s64(a, b) }
54980}
54981#[doc = "Unsigned Shift left"]
54982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
54983#[inline]
54984#[target_feature(enable = "neon")]
54985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
54987#[cfg_attr(
54988 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54989 assert_instr(ushl)
54990)]
54991#[cfg_attr(
54992 not(target_arch = "arm"),
54993 stable(feature = "neon_intrinsics", since = "1.59.0")
54994)]
54995#[cfg_attr(
54996 target_arch = "arm",
54997 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54998)]
54999pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
55000 unsafe extern "unadjusted" {
55001 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")]
55002 #[cfg_attr(
55003 any(target_arch = "aarch64", target_arch = "arm64ec"),
55004 link_name = "llvm.aarch64.neon.ushl.v8i8"
55005 )]
55006 fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
55007 }
55008 unsafe { _vshl_u8(a, b) }
55009}
55010#[doc = "Unsigned Shift left"]
55011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
55012#[inline]
55013#[target_feature(enable = "neon")]
55014#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55015#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55016#[cfg_attr(
55017 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55018 assert_instr(ushl)
55019)]
55020#[cfg_attr(
55021 not(target_arch = "arm"),
55022 stable(feature = "neon_intrinsics", since = "1.59.0")
55023)]
55024#[cfg_attr(
55025 target_arch = "arm",
55026 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55027)]
55028pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
55029 unsafe extern "unadjusted" {
55030 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")]
55031 #[cfg_attr(
55032 any(target_arch = "aarch64", target_arch = "arm64ec"),
55033 link_name = "llvm.aarch64.neon.ushl.v16i8"
55034 )]
55035 fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
55036 }
55037 unsafe { _vshlq_u8(a, b) }
55038}
55039#[doc = "Unsigned Shift left"]
55040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
55041#[inline]
55042#[target_feature(enable = "neon")]
55043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55044#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55045#[cfg_attr(
55046 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55047 assert_instr(ushl)
55048)]
55049#[cfg_attr(
55050 not(target_arch = "arm"),
55051 stable(feature = "neon_intrinsics", since = "1.59.0")
55052)]
55053#[cfg_attr(
55054 target_arch = "arm",
55055 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55056)]
55057pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
55058 unsafe extern "unadjusted" {
55059 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")]
55060 #[cfg_attr(
55061 any(target_arch = "aarch64", target_arch = "arm64ec"),
55062 link_name = "llvm.aarch64.neon.ushl.v4i16"
55063 )]
55064 fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
55065 }
55066 unsafe { _vshl_u16(a, b) }
55067}
55068#[doc = "Unsigned Shift left"]
55069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
55070#[inline]
55071#[target_feature(enable = "neon")]
55072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55074#[cfg_attr(
55075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55076 assert_instr(ushl)
55077)]
55078#[cfg_attr(
55079 not(target_arch = "arm"),
55080 stable(feature = "neon_intrinsics", since = "1.59.0")
55081)]
55082#[cfg_attr(
55083 target_arch = "arm",
55084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55085)]
55086pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
55087 unsafe extern "unadjusted" {
55088 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")]
55089 #[cfg_attr(
55090 any(target_arch = "aarch64", target_arch = "arm64ec"),
55091 link_name = "llvm.aarch64.neon.ushl.v8i16"
55092 )]
55093 fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
55094 }
55095 unsafe { _vshlq_u16(a, b) }
55096}
55097#[doc = "Unsigned Shift left"]
55098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
55099#[inline]
55100#[target_feature(enable = "neon")]
55101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55103#[cfg_attr(
55104 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55105 assert_instr(ushl)
55106)]
55107#[cfg_attr(
55108 not(target_arch = "arm"),
55109 stable(feature = "neon_intrinsics", since = "1.59.0")
55110)]
55111#[cfg_attr(
55112 target_arch = "arm",
55113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55114)]
55115pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
55116 unsafe extern "unadjusted" {
55117 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")]
55118 #[cfg_attr(
55119 any(target_arch = "aarch64", target_arch = "arm64ec"),
55120 link_name = "llvm.aarch64.neon.ushl.v2i32"
55121 )]
55122 fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
55123 }
55124 unsafe { _vshl_u32(a, b) }
55125}
55126#[doc = "Unsigned Shift left"]
55127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
55128#[inline]
55129#[target_feature(enable = "neon")]
55130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55132#[cfg_attr(
55133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55134 assert_instr(ushl)
55135)]
55136#[cfg_attr(
55137 not(target_arch = "arm"),
55138 stable(feature = "neon_intrinsics", since = "1.59.0")
55139)]
55140#[cfg_attr(
55141 target_arch = "arm",
55142 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55143)]
55144pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
55145 unsafe extern "unadjusted" {
55146 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")]
55147 #[cfg_attr(
55148 any(target_arch = "aarch64", target_arch = "arm64ec"),
55149 link_name = "llvm.aarch64.neon.ushl.v4i32"
55150 )]
55151 fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
55152 }
55153 unsafe { _vshlq_u32(a, b) }
55154}
55155#[doc = "Unsigned Shift left"]
55156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
55157#[inline]
55158#[target_feature(enable = "neon")]
55159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55161#[cfg_attr(
55162 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55163 assert_instr(ushl)
55164)]
55165#[cfg_attr(
55166 not(target_arch = "arm"),
55167 stable(feature = "neon_intrinsics", since = "1.59.0")
55168)]
55169#[cfg_attr(
55170 target_arch = "arm",
55171 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55172)]
55173pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
55174 unsafe extern "unadjusted" {
55175 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")]
55176 #[cfg_attr(
55177 any(target_arch = "aarch64", target_arch = "arm64ec"),
55178 link_name = "llvm.aarch64.neon.ushl.v1i64"
55179 )]
55180 fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
55181 }
55182 unsafe { _vshl_u64(a, b) }
55183}
55184#[doc = "Unsigned Shift left"]
55185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
55186#[inline]
55187#[target_feature(enable = "neon")]
55188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
55190#[cfg_attr(
55191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55192 assert_instr(ushl)
55193)]
55194#[cfg_attr(
55195 not(target_arch = "arm"),
55196 stable(feature = "neon_intrinsics", since = "1.59.0")
55197)]
55198#[cfg_attr(
55199 target_arch = "arm",
55200 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55201)]
55202pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
55203 unsafe extern "unadjusted" {
55204 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")]
55205 #[cfg_attr(
55206 any(target_arch = "aarch64", target_arch = "arm64ec"),
55207 link_name = "llvm.aarch64.neon.ushl.v2i64"
55208 )]
55209 fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
55210 }
55211 unsafe { _vshlq_u64(a, b) }
55212}
55213#[doc = "Signed shift left long"]
55214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
55215#[inline]
55216#[target_feature(enable = "neon")]
55217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55218#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
55219#[cfg_attr(
55220 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55221 assert_instr(sshll, N = 2)
55222)]
55223#[rustc_legacy_const_generics(1)]
55224#[cfg_attr(
55225 not(target_arch = "arm"),
55226 stable(feature = "neon_intrinsics", since = "1.59.0")
55227)]
55228#[cfg_attr(
55229 target_arch = "arm",
55230 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55231)]
55232pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
55233 static_assert!(N >= 0 && N <= 16);
55234 unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) }
55235}
55236#[doc = "Signed shift left long"]
55237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
55238#[inline]
55239#[target_feature(enable = "neon")]
55240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55241#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
55242#[cfg_attr(
55243 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55244 assert_instr(sshll, N = 2)
55245)]
55246#[rustc_legacy_const_generics(1)]
55247#[cfg_attr(
55248 not(target_arch = "arm"),
55249 stable(feature = "neon_intrinsics", since = "1.59.0")
55250)]
55251#[cfg_attr(
55252 target_arch = "arm",
55253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55254)]
55255pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
55256 static_assert!(N >= 0 && N <= 32);
55257 unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) }
55258}
55259#[doc = "Signed shift left long"]
55260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
55261#[inline]
55262#[target_feature(enable = "neon")]
55263#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55264#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
55265#[cfg_attr(
55266 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55267 assert_instr(sshll, N = 2)
55268)]
55269#[rustc_legacy_const_generics(1)]
55270#[cfg_attr(
55271 not(target_arch = "arm"),
55272 stable(feature = "neon_intrinsics", since = "1.59.0")
55273)]
55274#[cfg_attr(
55275 target_arch = "arm",
55276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55277)]
55278pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
55279 static_assert!(N >= 0 && N <= 8);
55280 unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) }
55281}
55282#[doc = "Signed shift left long"]
55283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
55284#[inline]
55285#[target_feature(enable = "neon")]
55286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55287#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
55288#[cfg_attr(
55289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55290 assert_instr(ushll, N = 2)
55291)]
55292#[rustc_legacy_const_generics(1)]
55293#[cfg_attr(
55294 not(target_arch = "arm"),
55295 stable(feature = "neon_intrinsics", since = "1.59.0")
55296)]
55297#[cfg_attr(
55298 target_arch = "arm",
55299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55300)]
55301pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
55302 static_assert!(N >= 0 && N <= 16);
55303 unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) }
55304}
55305#[doc = "Signed shift left long"]
55306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
55307#[inline]
55308#[target_feature(enable = "neon")]
55309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
55311#[cfg_attr(
55312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55313 assert_instr(ushll, N = 2)
55314)]
55315#[rustc_legacy_const_generics(1)]
55316#[cfg_attr(
55317 not(target_arch = "arm"),
55318 stable(feature = "neon_intrinsics", since = "1.59.0")
55319)]
55320#[cfg_attr(
55321 target_arch = "arm",
55322 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55323)]
55324pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
55325 static_assert!(N >= 0 && N <= 32);
55326 unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) }
55327}
55328#[doc = "Signed shift left long"]
55329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
55330#[inline]
55331#[target_feature(enable = "neon")]
55332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55333#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
55334#[cfg_attr(
55335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55336 assert_instr(ushll, N = 2)
55337)]
55338#[rustc_legacy_const_generics(1)]
55339#[cfg_attr(
55340 not(target_arch = "arm"),
55341 stable(feature = "neon_intrinsics", since = "1.59.0")
55342)]
55343#[cfg_attr(
55344 target_arch = "arm",
55345 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55346)]
55347pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
55348 static_assert!(N >= 0 && N <= 8);
55349 unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) }
55350}
55351#[doc = "Shift right"]
55352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
55353#[inline]
55354#[target_feature(enable = "neon")]
55355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55356#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
55357#[cfg_attr(
55358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55359 assert_instr(sshr, N = 2)
55360)]
55361#[rustc_legacy_const_generics(1)]
55362#[cfg_attr(
55363 not(target_arch = "arm"),
55364 stable(feature = "neon_intrinsics", since = "1.59.0")
55365)]
55366#[cfg_attr(
55367 target_arch = "arm",
55368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55369)]
55370pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
55371 static_assert!(N >= 1 && N <= 8);
55372 let n: i32 = if N == 8 { 7 } else { N };
55373 unsafe { simd_shr(a, vdup_n_s8(n as _)) }
55374}
55375#[doc = "Shift right"]
55376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
55377#[inline]
55378#[target_feature(enable = "neon")]
55379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55380#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
55381#[cfg_attr(
55382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55383 assert_instr(sshr, N = 2)
55384)]
55385#[rustc_legacy_const_generics(1)]
55386#[cfg_attr(
55387 not(target_arch = "arm"),
55388 stable(feature = "neon_intrinsics", since = "1.59.0")
55389)]
55390#[cfg_attr(
55391 target_arch = "arm",
55392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55393)]
55394pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
55395 static_assert!(N >= 1 && N <= 8);
55396 let n: i32 = if N == 8 { 7 } else { N };
55397 unsafe { simd_shr(a, vdupq_n_s8(n as _)) }
55398}
55399#[doc = "Shift right"]
55400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
55401#[inline]
55402#[target_feature(enable = "neon")]
55403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55404#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
55405#[cfg_attr(
55406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55407 assert_instr(sshr, N = 2)
55408)]
55409#[rustc_legacy_const_generics(1)]
55410#[cfg_attr(
55411 not(target_arch = "arm"),
55412 stable(feature = "neon_intrinsics", since = "1.59.0")
55413)]
55414#[cfg_attr(
55415 target_arch = "arm",
55416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55417)]
55418pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
55419 static_assert!(N >= 1 && N <= 16);
55420 let n: i32 = if N == 16 { 15 } else { N };
55421 unsafe { simd_shr(a, vdup_n_s16(n as _)) }
55422}
55423#[doc = "Shift right"]
55424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
55425#[inline]
55426#[target_feature(enable = "neon")]
55427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55428#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
55429#[cfg_attr(
55430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55431 assert_instr(sshr, N = 2)
55432)]
55433#[rustc_legacy_const_generics(1)]
55434#[cfg_attr(
55435 not(target_arch = "arm"),
55436 stable(feature = "neon_intrinsics", since = "1.59.0")
55437)]
55438#[cfg_attr(
55439 target_arch = "arm",
55440 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55441)]
55442pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
55443 static_assert!(N >= 1 && N <= 16);
55444 let n: i32 = if N == 16 { 15 } else { N };
55445 unsafe { simd_shr(a, vdupq_n_s16(n as _)) }
55446}
55447#[doc = "Shift right"]
55448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
55449#[inline]
55450#[target_feature(enable = "neon")]
55451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
55453#[cfg_attr(
55454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55455 assert_instr(sshr, N = 2)
55456)]
55457#[rustc_legacy_const_generics(1)]
55458#[cfg_attr(
55459 not(target_arch = "arm"),
55460 stable(feature = "neon_intrinsics", since = "1.59.0")
55461)]
55462#[cfg_attr(
55463 target_arch = "arm",
55464 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55465)]
55466pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
55467 static_assert!(N >= 1 && N <= 32);
55468 let n: i32 = if N == 32 { 31 } else { N };
55469 unsafe { simd_shr(a, vdup_n_s32(n as _)) }
55470}
55471#[doc = "Shift right"]
55472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
55473#[inline]
55474#[target_feature(enable = "neon")]
55475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55476#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
55477#[cfg_attr(
55478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55479 assert_instr(sshr, N = 2)
55480)]
55481#[rustc_legacy_const_generics(1)]
55482#[cfg_attr(
55483 not(target_arch = "arm"),
55484 stable(feature = "neon_intrinsics", since = "1.59.0")
55485)]
55486#[cfg_attr(
55487 target_arch = "arm",
55488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55489)]
55490pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
55491 static_assert!(N >= 1 && N <= 32);
55492 let n: i32 = if N == 32 { 31 } else { N };
55493 unsafe { simd_shr(a, vdupq_n_s32(n as _)) }
55494}
55495#[doc = "Shift right"]
55496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
55497#[inline]
55498#[target_feature(enable = "neon")]
55499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55500#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
55501#[cfg_attr(
55502 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55503 assert_instr(sshr, N = 2)
55504)]
55505#[rustc_legacy_const_generics(1)]
55506#[cfg_attr(
55507 not(target_arch = "arm"),
55508 stable(feature = "neon_intrinsics", since = "1.59.0")
55509)]
55510#[cfg_attr(
55511 target_arch = "arm",
55512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55513)]
55514pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
55515 static_assert!(N >= 1 && N <= 64);
55516 let n: i32 = if N == 64 { 63 } else { N };
55517 unsafe { simd_shr(a, vdup_n_s64(n as _)) }
55518}
55519#[doc = "Shift right"]
55520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
55521#[inline]
55522#[target_feature(enable = "neon")]
55523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55524#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
55525#[cfg_attr(
55526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55527 assert_instr(sshr, N = 2)
55528)]
55529#[rustc_legacy_const_generics(1)]
55530#[cfg_attr(
55531 not(target_arch = "arm"),
55532 stable(feature = "neon_intrinsics", since = "1.59.0")
55533)]
55534#[cfg_attr(
55535 target_arch = "arm",
55536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55537)]
55538pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
55539 static_assert!(N >= 1 && N <= 64);
55540 let n: i32 = if N == 64 { 63 } else { N };
55541 unsafe { simd_shr(a, vdupq_n_s64(n as _)) }
55542}
55543#[doc = "Shift right"]
55544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
55545#[inline]
55546#[target_feature(enable = "neon")]
55547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55548#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
55549#[cfg_attr(
55550 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55551 assert_instr(ushr, N = 2)
55552)]
55553#[rustc_legacy_const_generics(1)]
55554#[cfg_attr(
55555 not(target_arch = "arm"),
55556 stable(feature = "neon_intrinsics", since = "1.59.0")
55557)]
55558#[cfg_attr(
55559 target_arch = "arm",
55560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55561)]
55562pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
55563 static_assert!(N >= 1 && N <= 8);
55564 let n: i32 = if N == 8 {
55565 return vdup_n_u8(0);
55566 } else {
55567 N
55568 };
55569 unsafe { simd_shr(a, vdup_n_u8(n as _)) }
55570}
55571#[doc = "Shift right"]
55572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
55573#[inline]
55574#[target_feature(enable = "neon")]
55575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55576#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
55577#[cfg_attr(
55578 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55579 assert_instr(ushr, N = 2)
55580)]
55581#[rustc_legacy_const_generics(1)]
55582#[cfg_attr(
55583 not(target_arch = "arm"),
55584 stable(feature = "neon_intrinsics", since = "1.59.0")
55585)]
55586#[cfg_attr(
55587 target_arch = "arm",
55588 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55589)]
55590pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
55591 static_assert!(N >= 1 && N <= 8);
55592 let n: i32 = if N == 8 {
55593 return vdupq_n_u8(0);
55594 } else {
55595 N
55596 };
55597 unsafe { simd_shr(a, vdupq_n_u8(n as _)) }
55598}
55599#[doc = "Shift right"]
55600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
55601#[inline]
55602#[target_feature(enable = "neon")]
55603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55604#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
55605#[cfg_attr(
55606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55607 assert_instr(ushr, N = 2)
55608)]
55609#[rustc_legacy_const_generics(1)]
55610#[cfg_attr(
55611 not(target_arch = "arm"),
55612 stable(feature = "neon_intrinsics", since = "1.59.0")
55613)]
55614#[cfg_attr(
55615 target_arch = "arm",
55616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55617)]
55618pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
55619 static_assert!(N >= 1 && N <= 16);
55620 let n: i32 = if N == 16 {
55621 return vdup_n_u16(0);
55622 } else {
55623 N
55624 };
55625 unsafe { simd_shr(a, vdup_n_u16(n as _)) }
55626}
55627#[doc = "Shift right"]
55628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
55629#[inline]
55630#[target_feature(enable = "neon")]
55631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55632#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
55633#[cfg_attr(
55634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55635 assert_instr(ushr, N = 2)
55636)]
55637#[rustc_legacy_const_generics(1)]
55638#[cfg_attr(
55639 not(target_arch = "arm"),
55640 stable(feature = "neon_intrinsics", since = "1.59.0")
55641)]
55642#[cfg_attr(
55643 target_arch = "arm",
55644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55645)]
55646pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
55647 static_assert!(N >= 1 && N <= 16);
55648 let n: i32 = if N == 16 {
55649 return vdupq_n_u16(0);
55650 } else {
55651 N
55652 };
55653 unsafe { simd_shr(a, vdupq_n_u16(n as _)) }
55654}
55655#[doc = "Shift right"]
55656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
55657#[inline]
55658#[target_feature(enable = "neon")]
55659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55660#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
55661#[cfg_attr(
55662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55663 assert_instr(ushr, N = 2)
55664)]
55665#[rustc_legacy_const_generics(1)]
55666#[cfg_attr(
55667 not(target_arch = "arm"),
55668 stable(feature = "neon_intrinsics", since = "1.59.0")
55669)]
55670#[cfg_attr(
55671 target_arch = "arm",
55672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55673)]
55674pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
55675 static_assert!(N >= 1 && N <= 32);
55676 let n: i32 = if N == 32 {
55677 return vdup_n_u32(0);
55678 } else {
55679 N
55680 };
55681 unsafe { simd_shr(a, vdup_n_u32(n as _)) }
55682}
55683#[doc = "Shift right"]
55684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
55685#[inline]
55686#[target_feature(enable = "neon")]
55687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55688#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
55689#[cfg_attr(
55690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55691 assert_instr(ushr, N = 2)
55692)]
55693#[rustc_legacy_const_generics(1)]
55694#[cfg_attr(
55695 not(target_arch = "arm"),
55696 stable(feature = "neon_intrinsics", since = "1.59.0")
55697)]
55698#[cfg_attr(
55699 target_arch = "arm",
55700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55701)]
55702pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
55703 static_assert!(N >= 1 && N <= 32);
55704 let n: i32 = if N == 32 {
55705 return vdupq_n_u32(0);
55706 } else {
55707 N
55708 };
55709 unsafe { simd_shr(a, vdupq_n_u32(n as _)) }
55710}
55711#[doc = "Shift right"]
55712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
55713#[inline]
55714#[target_feature(enable = "neon")]
55715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55716#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
55717#[cfg_attr(
55718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55719 assert_instr(ushr, N = 2)
55720)]
55721#[rustc_legacy_const_generics(1)]
55722#[cfg_attr(
55723 not(target_arch = "arm"),
55724 stable(feature = "neon_intrinsics", since = "1.59.0")
55725)]
55726#[cfg_attr(
55727 target_arch = "arm",
55728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55729)]
55730pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
55731 static_assert!(N >= 1 && N <= 64);
55732 let n: i32 = if N == 64 {
55733 return vdup_n_u64(0);
55734 } else {
55735 N
55736 };
55737 unsafe { simd_shr(a, vdup_n_u64(n as _)) }
55738}
55739#[doc = "Shift right"]
55740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
55741#[inline]
55742#[target_feature(enable = "neon")]
55743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
55745#[cfg_attr(
55746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55747 assert_instr(ushr, N = 2)
55748)]
55749#[rustc_legacy_const_generics(1)]
55750#[cfg_attr(
55751 not(target_arch = "arm"),
55752 stable(feature = "neon_intrinsics", since = "1.59.0")
55753)]
55754#[cfg_attr(
55755 target_arch = "arm",
55756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55757)]
55758pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
55759 static_assert!(N >= 1 && N <= 64);
55760 let n: i32 = if N == 64 {
55761 return vdupq_n_u64(0);
55762 } else {
55763 N
55764 };
55765 unsafe { simd_shr(a, vdupq_n_u64(n as _)) }
55766}
55767#[doc = "Shift right narrow"]
55768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
55769#[inline]
55770#[target_feature(enable = "neon")]
55771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55772#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
55773#[cfg_attr(
55774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55775 assert_instr(shrn, N = 2)
55776)]
55777#[rustc_legacy_const_generics(1)]
55778#[cfg_attr(
55779 not(target_arch = "arm"),
55780 stable(feature = "neon_intrinsics", since = "1.59.0")
55781)]
55782#[cfg_attr(
55783 target_arch = "arm",
55784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55785)]
55786pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
55787 static_assert!(N >= 1 && N <= 8);
55788 unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) }
55789}
55790#[doc = "Shift right narrow"]
55791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
55792#[inline]
55793#[target_feature(enable = "neon")]
55794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55795#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
55796#[cfg_attr(
55797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55798 assert_instr(shrn, N = 2)
55799)]
55800#[rustc_legacy_const_generics(1)]
55801#[cfg_attr(
55802 not(target_arch = "arm"),
55803 stable(feature = "neon_intrinsics", since = "1.59.0")
55804)]
55805#[cfg_attr(
55806 target_arch = "arm",
55807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55808)]
55809pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
55810 static_assert!(N >= 1 && N <= 16);
55811 unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) }
55812}
55813#[doc = "Shift right narrow"]
55814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
55815#[inline]
55816#[target_feature(enable = "neon")]
55817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55818#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
55819#[cfg_attr(
55820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55821 assert_instr(shrn, N = 2)
55822)]
55823#[rustc_legacy_const_generics(1)]
55824#[cfg_attr(
55825 not(target_arch = "arm"),
55826 stable(feature = "neon_intrinsics", since = "1.59.0")
55827)]
55828#[cfg_attr(
55829 target_arch = "arm",
55830 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55831)]
55832pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
55833 static_assert!(N >= 1 && N <= 32);
55834 unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) }
55835}
55836#[doc = "Shift right narrow"]
55837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
55838#[inline]
55839#[target_feature(enable = "neon")]
55840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55841#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
55842#[cfg_attr(
55843 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55844 assert_instr(shrn, N = 2)
55845)]
55846#[rustc_legacy_const_generics(1)]
55847#[cfg_attr(
55848 not(target_arch = "arm"),
55849 stable(feature = "neon_intrinsics", since = "1.59.0")
55850)]
55851#[cfg_attr(
55852 target_arch = "arm",
55853 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55854)]
55855pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
55856 static_assert!(N >= 1 && N <= 8);
55857 unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) }
55858}
55859#[doc = "Shift right narrow"]
55860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
55861#[inline]
55862#[target_feature(enable = "neon")]
55863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
55865#[cfg_attr(
55866 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55867 assert_instr(shrn, N = 2)
55868)]
55869#[rustc_legacy_const_generics(1)]
55870#[cfg_attr(
55871 not(target_arch = "arm"),
55872 stable(feature = "neon_intrinsics", since = "1.59.0")
55873)]
55874#[cfg_attr(
55875 target_arch = "arm",
55876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55877)]
55878pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
55879 static_assert!(N >= 1 && N <= 16);
55880 unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) }
55881}
55882#[doc = "Shift right narrow"]
55883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
55884#[inline]
55885#[target_feature(enable = "neon")]
55886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
55887#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
55888#[cfg_attr(
55889 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55890 assert_instr(shrn, N = 2)
55891)]
55892#[rustc_legacy_const_generics(1)]
55893#[cfg_attr(
55894 not(target_arch = "arm"),
55895 stable(feature = "neon_intrinsics", since = "1.59.0")
55896)]
55897#[cfg_attr(
55898 target_arch = "arm",
55899 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55900)]
55901pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
55902 static_assert!(N >= 1 && N <= 32);
55903 unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) }
55904}
55905#[doc = "Shift Left and Insert (immediate)"]
55906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
55907#[inline]
55908#[cfg(target_arch = "arm")]
55909#[target_feature(enable = "neon,v7")]
55910#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55911#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
55912#[rustc_legacy_const_generics(2)]
55913pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
55914 static_assert_uimm_bits!(N, 3);
55915 vshiftins_v8i8(a, b, int8x8_t::splat(N as i8))
55916}
55917#[doc = "Shift Left and Insert (immediate)"]
55918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
55919#[inline]
55920#[cfg(target_arch = "arm")]
55921#[target_feature(enable = "neon,v7")]
55922#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55923#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
55924#[rustc_legacy_const_generics(2)]
55925pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
55926 static_assert_uimm_bits!(N, 3);
55927 vshiftins_v16i8(a, b, int8x16_t::splat(N as i8))
55928}
55929#[doc = "Shift Left and Insert (immediate)"]
55930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
55931#[inline]
55932#[cfg(target_arch = "arm")]
55933#[target_feature(enable = "neon,v7")]
55934#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55935#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
55936#[rustc_legacy_const_generics(2)]
55937pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
55938 static_assert_uimm_bits!(N, 4);
55939 vshiftins_v4i16(a, b, int16x4_t::splat(N as i16))
55940}
55941#[doc = "Shift Left and Insert (immediate)"]
55942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
55943#[inline]
55944#[cfg(target_arch = "arm")]
55945#[target_feature(enable = "neon,v7")]
55946#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
55948#[rustc_legacy_const_generics(2)]
55949pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
55950 static_assert_uimm_bits!(N, 4);
55951 vshiftins_v8i16(a, b, int16x8_t::splat(N as i16))
55952}
55953#[doc = "Shift Left and Insert (immediate)"]
55954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
55955#[inline]
55956#[cfg(target_arch = "arm")]
55957#[target_feature(enable = "neon,v7")]
55958#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55959#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
55960#[rustc_legacy_const_generics(2)]
55961pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
55962 static_assert!(N >= 0 && N <= 31);
55963 vshiftins_v2i32(a, b, int32x2_t::splat(N))
55964}
55965#[doc = "Shift Left and Insert (immediate)"]
55966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
55967#[inline]
55968#[cfg(target_arch = "arm")]
55969#[target_feature(enable = "neon,v7")]
55970#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55971#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
55972#[rustc_legacy_const_generics(2)]
55973pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
55974 static_assert!(N >= 0 && N <= 31);
55975 vshiftins_v4i32(a, b, int32x4_t::splat(N))
55976}
55977#[doc = "Shift Left and Insert (immediate)"]
55978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
55979#[inline]
55980#[cfg(target_arch = "arm")]
55981#[target_feature(enable = "neon,v7")]
55982#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55983#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
55984#[rustc_legacy_const_generics(2)]
55985pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
55986 static_assert!(N >= 0 && N <= 63);
55987 vshiftins_v1i64(a, b, int64x1_t::splat(N as i64))
55988}
55989#[doc = "Shift Left and Insert (immediate)"]
55990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
55991#[inline]
55992#[cfg(target_arch = "arm")]
55993#[target_feature(enable = "neon,v7")]
55994#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
55995#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
55996#[rustc_legacy_const_generics(2)]
55997pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
55998 static_assert!(N >= 0 && N <= 63);
55999 vshiftins_v2i64(a, b, int64x2_t::splat(N as i64))
56000}
56001#[doc = "Shift Left and Insert (immediate)"]
56002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
56003#[inline]
56004#[cfg(target_arch = "arm")]
56005#[target_feature(enable = "neon,v7")]
56006#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
56008#[rustc_legacy_const_generics(2)]
56009pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
56010 static_assert_uimm_bits!(N, 3);
56011 unsafe {
56012 transmute(vshiftins_v8i8(
56013 transmute(a),
56014 transmute(b),
56015 int8x8_t::splat(N as i8),
56016 ))
56017 }
56018}
56019#[doc = "Shift Left and Insert (immediate)"]
56020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
56021#[inline]
56022#[cfg(target_arch = "arm")]
56023#[target_feature(enable = "neon,v7")]
56024#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56025#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
56026#[rustc_legacy_const_generics(2)]
56027pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
56028 static_assert_uimm_bits!(N, 3);
56029 unsafe {
56030 transmute(vshiftins_v16i8(
56031 transmute(a),
56032 transmute(b),
56033 int8x16_t::splat(N as i8),
56034 ))
56035 }
56036}
56037#[doc = "Shift Left and Insert (immediate)"]
56038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
56039#[inline]
56040#[cfg(target_arch = "arm")]
56041#[target_feature(enable = "neon,v7")]
56042#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56043#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
56044#[rustc_legacy_const_generics(2)]
56045pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
56046 static_assert_uimm_bits!(N, 4);
56047 unsafe {
56048 transmute(vshiftins_v4i16(
56049 transmute(a),
56050 transmute(b),
56051 int16x4_t::splat(N as i16),
56052 ))
56053 }
56054}
56055#[doc = "Shift Left and Insert (immediate)"]
56056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
56057#[inline]
56058#[cfg(target_arch = "arm")]
56059#[target_feature(enable = "neon,v7")]
56060#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56061#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
56062#[rustc_legacy_const_generics(2)]
56063pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
56064 static_assert_uimm_bits!(N, 4);
56065 unsafe {
56066 transmute(vshiftins_v8i16(
56067 transmute(a),
56068 transmute(b),
56069 int16x8_t::splat(N as i16),
56070 ))
56071 }
56072}
56073#[doc = "Shift Left and Insert (immediate)"]
56074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
56075#[inline]
56076#[cfg(target_arch = "arm")]
56077#[target_feature(enable = "neon,v7")]
56078#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56079#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
56080#[rustc_legacy_const_generics(2)]
56081pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
56082 static_assert!(N >= 0 && N <= 31);
56083 unsafe {
56084 transmute(vshiftins_v2i32(
56085 transmute(a),
56086 transmute(b),
56087 int32x2_t::splat(N as i32),
56088 ))
56089 }
56090}
56091#[doc = "Shift Left and Insert (immediate)"]
56092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
56093#[inline]
56094#[cfg(target_arch = "arm")]
56095#[target_feature(enable = "neon,v7")]
56096#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56097#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
56098#[rustc_legacy_const_generics(2)]
56099pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
56100 static_assert!(N >= 0 && N <= 31);
56101 unsafe {
56102 transmute(vshiftins_v4i32(
56103 transmute(a),
56104 transmute(b),
56105 int32x4_t::splat(N as i32),
56106 ))
56107 }
56108}
56109#[doc = "Shift Left and Insert (immediate)"]
56110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
56111#[inline]
56112#[cfg(target_arch = "arm")]
56113#[target_feature(enable = "neon,v7")]
56114#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56115#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
56116#[rustc_legacy_const_generics(2)]
56117pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
56118 static_assert!(N >= 0 && N <= 63);
56119 unsafe {
56120 transmute(vshiftins_v1i64(
56121 transmute(a),
56122 transmute(b),
56123 int64x1_t::splat(N as i64),
56124 ))
56125 }
56126}
56127#[doc = "Shift Left and Insert (immediate)"]
56128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
56129#[inline]
56130#[cfg(target_arch = "arm")]
56131#[target_feature(enable = "neon,v7")]
56132#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56133#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
56134#[rustc_legacy_const_generics(2)]
56135pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
56136 static_assert!(N >= 0 && N <= 63);
56137 unsafe {
56138 transmute(vshiftins_v2i64(
56139 transmute(a),
56140 transmute(b),
56141 int64x2_t::splat(N as i64),
56142 ))
56143 }
56144}
56145#[doc = "Shift Left and Insert (immediate)"]
56146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
56147#[inline]
56148#[cfg(target_arch = "arm")]
56149#[target_feature(enable = "neon,v7")]
56150#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
56152#[rustc_legacy_const_generics(2)]
56153pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
56154 static_assert_uimm_bits!(N, 3);
56155 unsafe {
56156 transmute(vshiftins_v8i8(
56157 transmute(a),
56158 transmute(b),
56159 int8x8_t::splat(N as i8),
56160 ))
56161 }
56162}
56163#[doc = "Shift Left and Insert (immediate)"]
56164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
56165#[inline]
56166#[cfg(target_arch = "arm")]
56167#[target_feature(enable = "neon,v7")]
56168#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56169#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
56170#[rustc_legacy_const_generics(2)]
56171pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
56172 static_assert_uimm_bits!(N, 3);
56173 unsafe {
56174 transmute(vshiftins_v16i8(
56175 transmute(a),
56176 transmute(b),
56177 int8x16_t::splat(N as i8),
56178 ))
56179 }
56180}
56181#[doc = "Shift Left and Insert (immediate)"]
56182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
56183#[inline]
56184#[cfg(target_arch = "arm")]
56185#[target_feature(enable = "neon,v7")]
56186#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56187#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
56188#[rustc_legacy_const_generics(2)]
56189pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
56190 static_assert_uimm_bits!(N, 4);
56191 unsafe {
56192 transmute(vshiftins_v4i16(
56193 transmute(a),
56194 transmute(b),
56195 int16x4_t::splat(N as i16),
56196 ))
56197 }
56198}
56199#[doc = "Shift Left and Insert (immediate)"]
56200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
56201#[inline]
56202#[cfg(target_arch = "arm")]
56203#[target_feature(enable = "neon,v7")]
56204#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56205#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
56206#[rustc_legacy_const_generics(2)]
56207pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
56208 static_assert_uimm_bits!(N, 4);
56209 unsafe {
56210 transmute(vshiftins_v8i16(
56211 transmute(a),
56212 transmute(b),
56213 int16x8_t::splat(N as i16),
56214 ))
56215 }
56216}
56217#[doc = "Signed shift right and accumulate"]
56218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
56219#[inline]
56220#[target_feature(enable = "neon")]
56221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56223#[cfg_attr(
56224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56225 assert_instr(ssra, N = 2)
56226)]
56227#[rustc_legacy_const_generics(2)]
56228#[cfg_attr(
56229 not(target_arch = "arm"),
56230 stable(feature = "neon_intrinsics", since = "1.59.0")
56231)]
56232#[cfg_attr(
56233 target_arch = "arm",
56234 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56235)]
56236pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
56237 static_assert!(N >= 1 && N <= 8);
56238 unsafe { simd_add(a, vshr_n_s8::<N>(b)) }
56239}
56240#[doc = "Signed shift right and accumulate"]
56241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
56242#[inline]
56243#[target_feature(enable = "neon")]
56244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56246#[cfg_attr(
56247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56248 assert_instr(ssra, N = 2)
56249)]
56250#[rustc_legacy_const_generics(2)]
56251#[cfg_attr(
56252 not(target_arch = "arm"),
56253 stable(feature = "neon_intrinsics", since = "1.59.0")
56254)]
56255#[cfg_attr(
56256 target_arch = "arm",
56257 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56258)]
56259pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
56260 static_assert!(N >= 1 && N <= 8);
56261 unsafe { simd_add(a, vshrq_n_s8::<N>(b)) }
56262}
56263#[doc = "Signed shift right and accumulate"]
56264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
56265#[inline]
56266#[target_feature(enable = "neon")]
56267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56269#[cfg_attr(
56270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56271 assert_instr(ssra, N = 2)
56272)]
56273#[rustc_legacy_const_generics(2)]
56274#[cfg_attr(
56275 not(target_arch = "arm"),
56276 stable(feature = "neon_intrinsics", since = "1.59.0")
56277)]
56278#[cfg_attr(
56279 target_arch = "arm",
56280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56281)]
56282pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
56283 static_assert!(N >= 1 && N <= 16);
56284 unsafe { simd_add(a, vshr_n_s16::<N>(b)) }
56285}
56286#[doc = "Signed shift right and accumulate"]
56287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
56288#[inline]
56289#[target_feature(enable = "neon")]
56290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56292#[cfg_attr(
56293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56294 assert_instr(ssra, N = 2)
56295)]
56296#[rustc_legacy_const_generics(2)]
56297#[cfg_attr(
56298 not(target_arch = "arm"),
56299 stable(feature = "neon_intrinsics", since = "1.59.0")
56300)]
56301#[cfg_attr(
56302 target_arch = "arm",
56303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56304)]
56305pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
56306 static_assert!(N >= 1 && N <= 16);
56307 unsafe { simd_add(a, vshrq_n_s16::<N>(b)) }
56308}
56309#[doc = "Signed shift right and accumulate"]
56310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
56311#[inline]
56312#[target_feature(enable = "neon")]
56313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56315#[cfg_attr(
56316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56317 assert_instr(ssra, N = 2)
56318)]
56319#[rustc_legacy_const_generics(2)]
56320#[cfg_attr(
56321 not(target_arch = "arm"),
56322 stable(feature = "neon_intrinsics", since = "1.59.0")
56323)]
56324#[cfg_attr(
56325 target_arch = "arm",
56326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56327)]
56328pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
56329 static_assert!(N >= 1 && N <= 32);
56330 unsafe { simd_add(a, vshr_n_s32::<N>(b)) }
56331}
56332#[doc = "Signed shift right and accumulate"]
56333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
56334#[inline]
56335#[target_feature(enable = "neon")]
56336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56338#[cfg_attr(
56339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56340 assert_instr(ssra, N = 2)
56341)]
56342#[rustc_legacy_const_generics(2)]
56343#[cfg_attr(
56344 not(target_arch = "arm"),
56345 stable(feature = "neon_intrinsics", since = "1.59.0")
56346)]
56347#[cfg_attr(
56348 target_arch = "arm",
56349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56350)]
56351pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
56352 static_assert!(N >= 1 && N <= 32);
56353 unsafe { simd_add(a, vshrq_n_s32::<N>(b)) }
56354}
56355#[doc = "Signed shift right and accumulate"]
56356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
56357#[inline]
56358#[target_feature(enable = "neon")]
56359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56361#[cfg_attr(
56362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56363 assert_instr(ssra, N = 2)
56364)]
56365#[rustc_legacy_const_generics(2)]
56366#[cfg_attr(
56367 not(target_arch = "arm"),
56368 stable(feature = "neon_intrinsics", since = "1.59.0")
56369)]
56370#[cfg_attr(
56371 target_arch = "arm",
56372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56373)]
56374pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
56375 static_assert!(N >= 1 && N <= 64);
56376 unsafe { simd_add(a, vshr_n_s64::<N>(b)) }
56377}
56378#[doc = "Signed shift right and accumulate"]
56379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
56380#[inline]
56381#[target_feature(enable = "neon")]
56382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56384#[cfg_attr(
56385 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56386 assert_instr(ssra, N = 2)
56387)]
56388#[rustc_legacy_const_generics(2)]
56389#[cfg_attr(
56390 not(target_arch = "arm"),
56391 stable(feature = "neon_intrinsics", since = "1.59.0")
56392)]
56393#[cfg_attr(
56394 target_arch = "arm",
56395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56396)]
56397pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
56398 static_assert!(N >= 1 && N <= 64);
56399 unsafe { simd_add(a, vshrq_n_s64::<N>(b)) }
56400}
56401#[doc = "Unsigned shift right and accumulate"]
56402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
56403#[inline]
56404#[target_feature(enable = "neon")]
56405#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56406#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56407#[cfg_attr(
56408 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56409 assert_instr(usra, N = 2)
56410)]
56411#[rustc_legacy_const_generics(2)]
56412#[cfg_attr(
56413 not(target_arch = "arm"),
56414 stable(feature = "neon_intrinsics", since = "1.59.0")
56415)]
56416#[cfg_attr(
56417 target_arch = "arm",
56418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56419)]
56420pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
56421 static_assert!(N >= 1 && N <= 8);
56422 unsafe { simd_add(a, vshr_n_u8::<N>(b)) }
56423}
56424#[doc = "Unsigned shift right and accumulate"]
56425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
56426#[inline]
56427#[target_feature(enable = "neon")]
56428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56430#[cfg_attr(
56431 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56432 assert_instr(usra, N = 2)
56433)]
56434#[rustc_legacy_const_generics(2)]
56435#[cfg_attr(
56436 not(target_arch = "arm"),
56437 stable(feature = "neon_intrinsics", since = "1.59.0")
56438)]
56439#[cfg_attr(
56440 target_arch = "arm",
56441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56442)]
56443pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
56444 static_assert!(N >= 1 && N <= 8);
56445 unsafe { simd_add(a, vshrq_n_u8::<N>(b)) }
56446}
56447#[doc = "Unsigned shift right and accumulate"]
56448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
56449#[inline]
56450#[target_feature(enable = "neon")]
56451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56453#[cfg_attr(
56454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56455 assert_instr(usra, N = 2)
56456)]
56457#[rustc_legacy_const_generics(2)]
56458#[cfg_attr(
56459 not(target_arch = "arm"),
56460 stable(feature = "neon_intrinsics", since = "1.59.0")
56461)]
56462#[cfg_attr(
56463 target_arch = "arm",
56464 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56465)]
56466pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
56467 static_assert!(N >= 1 && N <= 16);
56468 unsafe { simd_add(a, vshr_n_u16::<N>(b)) }
56469}
56470#[doc = "Unsigned shift right and accumulate"]
56471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
56472#[inline]
56473#[target_feature(enable = "neon")]
56474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56476#[cfg_attr(
56477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56478 assert_instr(usra, N = 2)
56479)]
56480#[rustc_legacy_const_generics(2)]
56481#[cfg_attr(
56482 not(target_arch = "arm"),
56483 stable(feature = "neon_intrinsics", since = "1.59.0")
56484)]
56485#[cfg_attr(
56486 target_arch = "arm",
56487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56488)]
56489pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
56490 static_assert!(N >= 1 && N <= 16);
56491 unsafe { simd_add(a, vshrq_n_u16::<N>(b)) }
56492}
56493#[doc = "Unsigned shift right and accumulate"]
56494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
56495#[inline]
56496#[target_feature(enable = "neon")]
56497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56499#[cfg_attr(
56500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56501 assert_instr(usra, N = 2)
56502)]
56503#[rustc_legacy_const_generics(2)]
56504#[cfg_attr(
56505 not(target_arch = "arm"),
56506 stable(feature = "neon_intrinsics", since = "1.59.0")
56507)]
56508#[cfg_attr(
56509 target_arch = "arm",
56510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56511)]
56512pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
56513 static_assert!(N >= 1 && N <= 32);
56514 unsafe { simd_add(a, vshr_n_u32::<N>(b)) }
56515}
56516#[doc = "Unsigned shift right and accumulate"]
56517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
56518#[inline]
56519#[target_feature(enable = "neon")]
56520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56522#[cfg_attr(
56523 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56524 assert_instr(usra, N = 2)
56525)]
56526#[rustc_legacy_const_generics(2)]
56527#[cfg_attr(
56528 not(target_arch = "arm"),
56529 stable(feature = "neon_intrinsics", since = "1.59.0")
56530)]
56531#[cfg_attr(
56532 target_arch = "arm",
56533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56534)]
56535pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
56536 static_assert!(N >= 1 && N <= 32);
56537 unsafe { simd_add(a, vshrq_n_u32::<N>(b)) }
56538}
56539#[doc = "Unsigned shift right and accumulate"]
56540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
56541#[inline]
56542#[target_feature(enable = "neon")]
56543#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56544#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56545#[cfg_attr(
56546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56547 assert_instr(usra, N = 2)
56548)]
56549#[rustc_legacy_const_generics(2)]
56550#[cfg_attr(
56551 not(target_arch = "arm"),
56552 stable(feature = "neon_intrinsics", since = "1.59.0")
56553)]
56554#[cfg_attr(
56555 target_arch = "arm",
56556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56557)]
56558pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
56559 static_assert!(N >= 1 && N <= 64);
56560 unsafe { simd_add(a, vshr_n_u64::<N>(b)) }
56561}
56562#[doc = "Unsigned shift right and accumulate"]
56563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
56564#[inline]
56565#[target_feature(enable = "neon")]
56566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
56568#[cfg_attr(
56569 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56570 assert_instr(usra, N = 2)
56571)]
56572#[rustc_legacy_const_generics(2)]
56573#[cfg_attr(
56574 not(target_arch = "arm"),
56575 stable(feature = "neon_intrinsics", since = "1.59.0")
56576)]
56577#[cfg_attr(
56578 target_arch = "arm",
56579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56580)]
56581pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
56582 static_assert!(N >= 1 && N <= 64);
56583 unsafe { simd_add(a, vshrq_n_u64::<N>(b)) }
56584}
56585#[doc = "Shift Right and Insert (immediate)"]
56586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
56587#[inline]
56588#[target_feature(enable = "neon,v7")]
56589#[cfg(target_arch = "arm")]
56590#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
56592#[rustc_legacy_const_generics(2)]
56593pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
56594 static_assert!(1 <= N && N <= 8);
56595 vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8))
56596}
56597#[doc = "Shift Right and Insert (immediate)"]
56598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
56599#[inline]
56600#[target_feature(enable = "neon,v7")]
56601#[cfg(target_arch = "arm")]
56602#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56603#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
56604#[rustc_legacy_const_generics(2)]
56605pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
56606 static_assert!(1 <= N && N <= 8);
56607 vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8))
56608}
56609#[doc = "Shift Right and Insert (immediate)"]
56610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
56611#[inline]
56612#[target_feature(enable = "neon,v7")]
56613#[cfg(target_arch = "arm")]
56614#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56615#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
56616#[rustc_legacy_const_generics(2)]
56617pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
56618 static_assert!(1 <= N && N <= 16);
56619 vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16))
56620}
56621#[doc = "Shift Right and Insert (immediate)"]
56622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
56623#[inline]
56624#[target_feature(enable = "neon,v7")]
56625#[cfg(target_arch = "arm")]
56626#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
56628#[rustc_legacy_const_generics(2)]
56629pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
56630 static_assert!(1 <= N && N <= 16);
56631 vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16))
56632}
56633#[doc = "Shift Right and Insert (immediate)"]
56634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
56635#[inline]
56636#[target_feature(enable = "neon,v7")]
56637#[cfg(target_arch = "arm")]
56638#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56639#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
56640#[rustc_legacy_const_generics(2)]
56641pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
56642 static_assert!(1 <= N && N <= 32);
56643 vshiftins_v2i32(a, b, int32x2_t::splat(-N as i32))
56644}
56645#[doc = "Shift Right and Insert (immediate)"]
56646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
56647#[inline]
56648#[target_feature(enable = "neon,v7")]
56649#[cfg(target_arch = "arm")]
56650#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56651#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
56652#[rustc_legacy_const_generics(2)]
56653pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
56654 static_assert!(1 <= N && N <= 32);
56655 vshiftins_v4i32(a, b, int32x4_t::splat(-N as i32))
56656}
56657#[doc = "Shift Right and Insert (immediate)"]
56658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
56659#[inline]
56660#[target_feature(enable = "neon,v7")]
56661#[cfg(target_arch = "arm")]
56662#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56663#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
56664#[rustc_legacy_const_generics(2)]
56665pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
56666 static_assert!(1 <= N && N <= 64);
56667 vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64))
56668}
56669#[doc = "Shift Right and Insert (immediate)"]
56670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
56671#[inline]
56672#[target_feature(enable = "neon,v7")]
56673#[cfg(target_arch = "arm")]
56674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
56676#[rustc_legacy_const_generics(2)]
56677pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
56678 static_assert!(1 <= N && N <= 64);
56679 vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64))
56680}
56681#[doc = "Shift Right and Insert (immediate)"]
56682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
56683#[inline]
56684#[cfg(target_arch = "arm")]
56685#[target_feature(enable = "neon,v7")]
56686#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56687#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
56688#[rustc_legacy_const_generics(2)]
56689pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
56690 static_assert!(1 <= N && N <= 8);
56691 unsafe {
56692 transmute(vshiftins_v8i8(
56693 transmute(a),
56694 transmute(b),
56695 int8x8_t::splat(-N as i8),
56696 ))
56697 }
56698}
56699#[doc = "Shift Right and Insert (immediate)"]
56700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
56701#[inline]
56702#[cfg(target_arch = "arm")]
56703#[target_feature(enable = "neon,v7")]
56704#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56705#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
56706#[rustc_legacy_const_generics(2)]
56707pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
56708 static_assert!(1 <= N && N <= 8);
56709 unsafe {
56710 transmute(vshiftins_v16i8(
56711 transmute(a),
56712 transmute(b),
56713 int8x16_t::splat(-N as i8),
56714 ))
56715 }
56716}
56717#[doc = "Shift Right and Insert (immediate)"]
56718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
56719#[inline]
56720#[cfg(target_arch = "arm")]
56721#[target_feature(enable = "neon,v7")]
56722#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56723#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
56724#[rustc_legacy_const_generics(2)]
56725pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
56726 static_assert!(1 <= N && N <= 16);
56727 unsafe {
56728 transmute(vshiftins_v4i16(
56729 transmute(a),
56730 transmute(b),
56731 int16x4_t::splat(-N as i16),
56732 ))
56733 }
56734}
56735#[doc = "Shift Right and Insert (immediate)"]
56736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
56737#[inline]
56738#[cfg(target_arch = "arm")]
56739#[target_feature(enable = "neon,v7")]
56740#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56741#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
56742#[rustc_legacy_const_generics(2)]
56743pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
56744 static_assert!(1 <= N && N <= 16);
56745 unsafe {
56746 transmute(vshiftins_v8i16(
56747 transmute(a),
56748 transmute(b),
56749 int16x8_t::splat(-N as i16),
56750 ))
56751 }
56752}
56753#[doc = "Shift Right and Insert (immediate)"]
56754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
56755#[inline]
56756#[cfg(target_arch = "arm")]
56757#[target_feature(enable = "neon,v7")]
56758#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56759#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
56760#[rustc_legacy_const_generics(2)]
56761pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
56762 static_assert!(1 <= N && N <= 32);
56763 unsafe {
56764 transmute(vshiftins_v2i32(
56765 transmute(a),
56766 transmute(b),
56767 int32x2_t::splat(-N),
56768 ))
56769 }
56770}
56771#[doc = "Shift Right and Insert (immediate)"]
56772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
56773#[inline]
56774#[cfg(target_arch = "arm")]
56775#[target_feature(enable = "neon,v7")]
56776#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56777#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
56778#[rustc_legacy_const_generics(2)]
56779pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
56780 static_assert!(1 <= N && N <= 32);
56781 unsafe {
56782 transmute(vshiftins_v4i32(
56783 transmute(a),
56784 transmute(b),
56785 int32x4_t::splat(-N),
56786 ))
56787 }
56788}
56789#[doc = "Shift Right and Insert (immediate)"]
56790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
56791#[inline]
56792#[cfg(target_arch = "arm")]
56793#[target_feature(enable = "neon,v7")]
56794#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56795#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
56796#[rustc_legacy_const_generics(2)]
56797pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
56798 static_assert!(1 <= N && N <= 64);
56799 unsafe {
56800 transmute(vshiftins_v1i64(
56801 transmute(a),
56802 transmute(b),
56803 int64x1_t::splat(-N as i64),
56804 ))
56805 }
56806}
56807#[doc = "Shift Right and Insert (immediate)"]
56808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
56809#[inline]
56810#[cfg(target_arch = "arm")]
56811#[target_feature(enable = "neon,v7")]
56812#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56813#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
56814#[rustc_legacy_const_generics(2)]
56815pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
56816 static_assert!(1 <= N && N <= 64);
56817 unsafe {
56818 transmute(vshiftins_v2i64(
56819 transmute(a),
56820 transmute(b),
56821 int64x2_t::splat(-N as i64),
56822 ))
56823 }
56824}
56825#[doc = "Shift Right and Insert (immediate)"]
56826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
56827#[inline]
56828#[cfg(target_arch = "arm")]
56829#[target_feature(enable = "neon,v7")]
56830#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56831#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
56832#[rustc_legacy_const_generics(2)]
56833pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
56834 static_assert!(1 <= N && N <= 8);
56835 unsafe {
56836 transmute(vshiftins_v8i8(
56837 transmute(a),
56838 transmute(b),
56839 int8x8_t::splat(-N as i8),
56840 ))
56841 }
56842}
56843#[doc = "Shift Right and Insert (immediate)"]
56844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
56845#[inline]
56846#[cfg(target_arch = "arm")]
56847#[target_feature(enable = "neon,v7")]
56848#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56849#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
56850#[rustc_legacy_const_generics(2)]
56851pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
56852 static_assert!(1 <= N && N <= 8);
56853 unsafe {
56854 transmute(vshiftins_v16i8(
56855 transmute(a),
56856 transmute(b),
56857 int8x16_t::splat(-N as i8),
56858 ))
56859 }
56860}
56861#[doc = "Shift Right and Insert (immediate)"]
56862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
56863#[inline]
56864#[cfg(target_arch = "arm")]
56865#[target_feature(enable = "neon,v7")]
56866#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56867#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
56868#[rustc_legacy_const_generics(2)]
56869pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
56870 static_assert!(1 <= N && N <= 16);
56871 unsafe {
56872 transmute(vshiftins_v4i16(
56873 transmute(a),
56874 transmute(b),
56875 int16x4_t::splat(-N as i16),
56876 ))
56877 }
56878}
56879#[doc = "Shift Right and Insert (immediate)"]
56880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
56881#[inline]
56882#[cfg(target_arch = "arm")]
56883#[target_feature(enable = "neon,v7")]
56884#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
56885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
56886#[rustc_legacy_const_generics(2)]
56887pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
56888 static_assert!(1 <= N && N <= 16);
56889 unsafe {
56890 transmute(vshiftins_v8i16(
56891 transmute(a),
56892 transmute(b),
56893 int16x8_t::splat(-N as i16),
56894 ))
56895 }
56896}
56897#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
56898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
56899#[doc = "## Safety"]
56900#[doc = " * Neon instrinsic unsafe"]
56901#[inline]
56902#[cfg(target_arch = "arm")]
56903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56904#[target_feature(enable = "neon,fp16")]
56905#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
56906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
56907pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
56908 vst1_v4f16(
56909 ptr as *const i8,
56910 transmute(a),
56911 crate::mem::align_of::<f16>() as i32,
56912 )
56913}
56914#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
56915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
56916#[doc = "## Safety"]
56917#[doc = " * Neon instrinsic unsafe"]
56918#[inline]
56919#[cfg(target_arch = "arm")]
56920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56921#[target_feature(enable = "neon,fp16")]
56922#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
56923#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
56924pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
56925 vst1q_v8f16(
56926 ptr as *const i8,
56927 transmute(a),
56928 crate::mem::align_of::<f16>() as i32,
56929 )
56930}
56931#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
56932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
56933#[doc = "## Safety"]
56934#[doc = " * Neon instrinsic unsafe"]
56935#[inline]
56936#[cfg(target_arch = "arm")]
56937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56938#[cfg_attr(test, assert_instr(vst1))]
56939#[target_feature(enable = "neon,fp16")]
56940#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
56941pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
56942 unsafe extern "unadjusted" {
56943 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f16.v4f16")]
56944 fn _vst1_f16_x2(ptr: *mut f16, a: float16x4_t, b: float16x4_t);
56945 }
56946 _vst1_f16_x2(a, b.0, b.1)
56947}
56948#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
56949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
56950#[doc = "## Safety"]
56951#[doc = " * Neon instrinsic unsafe"]
56952#[inline]
56953#[cfg(target_arch = "arm")]
56954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
56955#[cfg_attr(test, assert_instr(vst1))]
56956#[target_feature(enable = "neon,fp16")]
56957#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
56958pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
56959 unsafe extern "unadjusted" {
56960 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f16.v8f16")]
56961 fn _vst1q_f16_x2(ptr: *mut f16, a: float16x8_t, b: float16x8_t);
56962 }
56963 _vst1q_f16_x2(a, b.0, b.1)
56964}
56965#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
56966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
56967#[doc = "## Safety"]
56968#[doc = " * Neon instrinsic unsafe"]
56969#[inline]
56970#[cfg(not(target_arch = "arm"))]
56971#[cfg_attr(test, assert_instr(st1))]
56972#[target_feature(enable = "neon,fp16")]
56973#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
56974pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
56975 unsafe extern "unadjusted" {
56976 #[cfg_attr(
56977 any(target_arch = "aarch64", target_arch = "arm64ec"),
56978 link_name = "llvm.aarch64.neon.st1x2.v4f16.p0f16"
56979 )]
56980 fn _vst1_f16_x2(a: float16x4_t, b: float16x4_t, ptr: *mut f16);
56981 }
56982 _vst1_f16_x2(b.0, b.1, a)
56983}
56984#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
56985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
56986#[doc = "## Safety"]
56987#[doc = " * Neon instrinsic unsafe"]
56988#[inline]
56989#[cfg(not(target_arch = "arm"))]
56990#[cfg_attr(test, assert_instr(st1))]
56991#[target_feature(enable = "neon,fp16")]
56992#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
56993pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
56994 unsafe extern "unadjusted" {
56995 #[cfg_attr(
56996 any(target_arch = "aarch64", target_arch = "arm64ec"),
56997 link_name = "llvm.aarch64.neon.st1x2.v8f16.p0f16"
56998 )]
56999 fn _vst1q_f16_x2(a: float16x8_t, b: float16x8_t, ptr: *mut f16);
57000 }
57001 _vst1q_f16_x2(b.0, b.1, a)
57002}
57003#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
57005#[doc = "## Safety"]
57006#[doc = " * Neon instrinsic unsafe"]
57007#[inline]
57008#[cfg(target_arch = "arm")]
57009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57010#[cfg_attr(test, assert_instr(vst1))]
57011#[target_feature(enable = "neon,fp16")]
57012#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57013pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
57014 unsafe extern "unadjusted" {
57015 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f16.v4f16")]
57016 fn _vst1_f16_x3(ptr: *mut f16, a: float16x4_t, b: float16x4_t, c: float16x4_t);
57017 }
57018 _vst1_f16_x3(a, b.0, b.1, b.2)
57019}
57020#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
57022#[doc = "## Safety"]
57023#[doc = " * Neon instrinsic unsafe"]
57024#[inline]
57025#[cfg(target_arch = "arm")]
57026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57027#[cfg_attr(test, assert_instr(vst1))]
57028#[target_feature(enable = "neon,fp16")]
57029#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57030pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
57031 unsafe extern "unadjusted" {
57032 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f16.v8f16")]
57033 fn _vst1q_f16_x3(ptr: *mut f16, a: float16x8_t, b: float16x8_t, c: float16x8_t);
57034 }
57035 _vst1q_f16_x3(a, b.0, b.1, b.2)
57036}
57037#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
57039#[doc = "## Safety"]
57040#[doc = " * Neon instrinsic unsafe"]
57041#[inline]
57042#[cfg(not(target_arch = "arm"))]
57043#[cfg_attr(test, assert_instr(st1))]
57044#[target_feature(enable = "neon,fp16")]
57045#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57046pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
57047 unsafe extern "unadjusted" {
57048 #[cfg_attr(
57049 any(target_arch = "aarch64", target_arch = "arm64ec"),
57050 link_name = "llvm.aarch64.neon.st1x3.v4f16.p0f16"
57051 )]
57052 fn _vst1_f16_x3(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut f16);
57053 }
57054 _vst1_f16_x3(b.0, b.1, b.2, a)
57055}
57056#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
57058#[doc = "## Safety"]
57059#[doc = " * Neon instrinsic unsafe"]
57060#[inline]
57061#[cfg(not(target_arch = "arm"))]
57062#[cfg_attr(test, assert_instr(st1))]
57063#[target_feature(enable = "neon,fp16")]
57064#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57065pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
57066 unsafe extern "unadjusted" {
57067 #[cfg_attr(
57068 any(target_arch = "aarch64", target_arch = "arm64ec"),
57069 link_name = "llvm.aarch64.neon.st1x3.v8f16.p0f16"
57070 )]
57071 fn _vst1q_f16_x3(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut f16);
57072 }
57073 _vst1q_f16_x3(b.0, b.1, b.2, a)
57074}
57075#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
57077#[doc = "## Safety"]
57078#[doc = " * Neon instrinsic unsafe"]
57079#[inline]
57080#[cfg(target_arch = "arm")]
57081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57082#[target_feature(enable = "neon,fp16")]
57083#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57084#[cfg_attr(test, assert_instr(vst1))]
57085pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
57086 unsafe extern "unadjusted" {
57087 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f16.v4f16")]
57088 fn _vst1_f16_x4(
57089 ptr: *mut f16,
57090 a: float16x4_t,
57091 b: float16x4_t,
57092 c: float16x4_t,
57093 d: float16x4_t,
57094 );
57095 }
57096 _vst1_f16_x4(a, b.0, b.1, b.2, b.3)
57097}
57098#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
57100#[doc = "## Safety"]
57101#[doc = " * Neon instrinsic unsafe"]
57102#[inline]
57103#[cfg(target_arch = "arm")]
57104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57105#[target_feature(enable = "neon,fp16")]
57106#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57107#[cfg_attr(test, assert_instr(vst1))]
57108pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
57109 unsafe extern "unadjusted" {
57110 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f16.v8f16")]
57111 fn _vst1q_f16_x4(
57112 ptr: *mut f16,
57113 a: float16x8_t,
57114 b: float16x8_t,
57115 c: float16x8_t,
57116 d: float16x8_t,
57117 );
57118 }
57119 _vst1q_f16_x4(a, b.0, b.1, b.2, b.3)
57120}
57121#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
57123#[doc = "## Safety"]
57124#[doc = " * Neon instrinsic unsafe"]
57125#[inline]
57126#[cfg(not(target_arch = "arm"))]
57127#[cfg_attr(test, assert_instr(st1))]
57128#[target_feature(enable = "neon,fp16")]
57129#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57130pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
57131 unsafe extern "unadjusted" {
57132 #[cfg_attr(
57133 any(target_arch = "aarch64", target_arch = "arm64ec"),
57134 link_name = "llvm.aarch64.neon.st1x4.v4f16.p0f16"
57135 )]
57136 fn _vst1_f16_x4(
57137 a: float16x4_t,
57138 b: float16x4_t,
57139 c: float16x4_t,
57140 d: float16x4_t,
57141 ptr: *mut f16,
57142 );
57143 }
57144 _vst1_f16_x4(b.0, b.1, b.2, b.3, a)
57145}
57146#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
57148#[doc = "## Safety"]
57149#[doc = " * Neon instrinsic unsafe"]
57150#[inline]
57151#[cfg(not(target_arch = "arm"))]
57152#[cfg_attr(test, assert_instr(st1))]
57153#[target_feature(enable = "neon,fp16")]
57154#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57155pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
57156 unsafe extern "unadjusted" {
57157 #[cfg_attr(
57158 any(target_arch = "aarch64", target_arch = "arm64ec"),
57159 link_name = "llvm.aarch64.neon.st1x4.v8f16.p0f16"
57160 )]
57161 fn _vst1q_f16_x4(
57162 a: float16x8_t,
57163 b: float16x8_t,
57164 c: float16x8_t,
57165 d: float16x8_t,
57166 ptr: *mut f16,
57167 );
57168 }
57169 _vst1q_f16_x4(b.0, b.1, b.2, b.3, a)
57170}
57171#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
57173#[doc = "## Safety"]
57174#[doc = " * Neon instrinsic unsafe"]
57175#[inline]
57176#[target_feature(enable = "neon")]
57177#[cfg(target_arch = "arm")]
57178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57179#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
57181pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
57182 vst1_v2f32(
57183 ptr as *const i8,
57184 transmute(a),
57185 crate::mem::align_of::<f32>() as i32,
57186 )
57187}
57188#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
57190#[doc = "## Safety"]
57191#[doc = " * Neon instrinsic unsafe"]
57192#[inline]
57193#[target_feature(enable = "neon")]
57194#[cfg(target_arch = "arm")]
57195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57196#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57197#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
57198pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
57199 vst1q_v4f32(
57200 ptr as *const i8,
57201 transmute(a),
57202 crate::mem::align_of::<f32>() as i32,
57203 )
57204}
57205#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
57207#[doc = "## Safety"]
57208#[doc = " * Neon instrinsic unsafe"]
57209#[inline]
57210#[target_feature(enable = "neon")]
57211#[cfg(target_arch = "arm")]
57212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57213#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57214#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
57215pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
57216 vst1_v8i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
57217}
57218#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
57220#[doc = "## Safety"]
57221#[doc = " * Neon instrinsic unsafe"]
57222#[inline]
57223#[target_feature(enable = "neon")]
57224#[cfg(target_arch = "arm")]
57225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57226#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
57228pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
57229 vst1q_v16i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
57230}
57231#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
57233#[doc = "## Safety"]
57234#[doc = " * Neon instrinsic unsafe"]
57235#[inline]
57236#[target_feature(enable = "neon")]
57237#[cfg(target_arch = "arm")]
57238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57239#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57240#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
57241pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
57242 vst1_v4i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
57243}
57244#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
57246#[doc = "## Safety"]
57247#[doc = " * Neon instrinsic unsafe"]
57248#[inline]
57249#[target_feature(enable = "neon")]
57250#[cfg(target_arch = "arm")]
57251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57252#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57253#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
57254pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
57255 vst1q_v8i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
57256}
57257#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
57259#[doc = "## Safety"]
57260#[doc = " * Neon instrinsic unsafe"]
57261#[inline]
57262#[target_feature(enable = "neon")]
57263#[cfg(target_arch = "arm")]
57264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57265#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57266#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
57267pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
57268 vst1_v2i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
57269}
57270#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
57272#[doc = "## Safety"]
57273#[doc = " * Neon instrinsic unsafe"]
57274#[inline]
57275#[target_feature(enable = "neon")]
57276#[cfg(target_arch = "arm")]
57277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57278#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
57280pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
57281 vst1q_v4i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
57282}
57283#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
57285#[doc = "## Safety"]
57286#[doc = " * Neon instrinsic unsafe"]
57287#[inline]
57288#[target_feature(enable = "neon")]
57289#[cfg(target_arch = "arm")]
57290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57291#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57292#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
57293pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
57294 vst1_v1i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
57295}
57296#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
57298#[doc = "## Safety"]
57299#[doc = " * Neon instrinsic unsafe"]
57300#[inline]
57301#[target_feature(enable = "neon")]
57302#[cfg(target_arch = "arm")]
57303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57304#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57305#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
57306pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
57307 vst1q_v2i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
57308}
57309#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
57311#[doc = "## Safety"]
57312#[doc = " * Neon instrinsic unsafe"]
57313#[inline]
57314#[target_feature(enable = "neon")]
57315#[cfg(target_arch = "arm")]
57316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57317#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57318#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
57319pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
57320 vst1_v8i8(
57321 ptr as *const i8,
57322 transmute(a),
57323 crate::mem::align_of::<u8>() as i32,
57324 )
57325}
57326#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
57328#[doc = "## Safety"]
57329#[doc = " * Neon instrinsic unsafe"]
57330#[inline]
57331#[target_feature(enable = "neon")]
57332#[cfg(target_arch = "arm")]
57333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57334#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57335#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
57336pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
57337 vst1q_v16i8(
57338 ptr as *const i8,
57339 transmute(a),
57340 crate::mem::align_of::<u8>() as i32,
57341 )
57342}
57343#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
57345#[doc = "## Safety"]
57346#[doc = " * Neon instrinsic unsafe"]
57347#[inline]
57348#[target_feature(enable = "neon")]
57349#[cfg(target_arch = "arm")]
57350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57351#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57352#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
57353pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
57354 vst1_v4i16(
57355 ptr as *const i8,
57356 transmute(a),
57357 crate::mem::align_of::<u16>() as i32,
57358 )
57359}
57360#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
57362#[doc = "## Safety"]
57363#[doc = " * Neon instrinsic unsafe"]
57364#[inline]
57365#[target_feature(enable = "neon")]
57366#[cfg(target_arch = "arm")]
57367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57368#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
57370pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
57371 vst1q_v8i16(
57372 ptr as *const i8,
57373 transmute(a),
57374 crate::mem::align_of::<u16>() as i32,
57375 )
57376}
57377#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
57379#[doc = "## Safety"]
57380#[doc = " * Neon instrinsic unsafe"]
57381#[inline]
57382#[target_feature(enable = "neon")]
57383#[cfg(target_arch = "arm")]
57384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57385#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57386#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
57387pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
57388 vst1_v2i32(
57389 ptr as *const i8,
57390 transmute(a),
57391 crate::mem::align_of::<u32>() as i32,
57392 )
57393}
57394#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
57396#[doc = "## Safety"]
57397#[doc = " * Neon instrinsic unsafe"]
57398#[inline]
57399#[target_feature(enable = "neon")]
57400#[cfg(target_arch = "arm")]
57401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57402#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57403#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
57404pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
57405 vst1q_v4i32(
57406 ptr as *const i8,
57407 transmute(a),
57408 crate::mem::align_of::<u32>() as i32,
57409 )
57410}
57411#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
57413#[doc = "## Safety"]
57414#[doc = " * Neon instrinsic unsafe"]
57415#[inline]
57416#[target_feature(enable = "neon")]
57417#[cfg(target_arch = "arm")]
57418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57419#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57420#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
57421pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
57422 vst1_v1i64(
57423 ptr as *const i8,
57424 transmute(a),
57425 crate::mem::align_of::<u64>() as i32,
57426 )
57427}
57428#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
57430#[doc = "## Safety"]
57431#[doc = " * Neon instrinsic unsafe"]
57432#[inline]
57433#[target_feature(enable = "neon")]
57434#[cfg(target_arch = "arm")]
57435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57436#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57437#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
57438pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
57439 vst1q_v2i64(
57440 ptr as *const i8,
57441 transmute(a),
57442 crate::mem::align_of::<u64>() as i32,
57443 )
57444}
57445#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
57447#[doc = "## Safety"]
57448#[doc = " * Neon instrinsic unsafe"]
57449#[inline]
57450#[target_feature(enable = "neon")]
57451#[cfg(target_arch = "arm")]
57452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57453#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
57455pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
57456 vst1_v8i8(
57457 ptr as *const i8,
57458 transmute(a),
57459 crate::mem::align_of::<p8>() as i32,
57460 )
57461}
57462#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
57464#[doc = "## Safety"]
57465#[doc = " * Neon instrinsic unsafe"]
57466#[inline]
57467#[target_feature(enable = "neon")]
57468#[cfg(target_arch = "arm")]
57469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
57472pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
57473 vst1q_v16i8(
57474 ptr as *const i8,
57475 transmute(a),
57476 crate::mem::align_of::<p8>() as i32,
57477 )
57478}
57479#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
57481#[doc = "## Safety"]
57482#[doc = " * Neon instrinsic unsafe"]
57483#[inline]
57484#[target_feature(enable = "neon")]
57485#[cfg(target_arch = "arm")]
57486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57487#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57488#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
57489pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
57490 vst1_v4i16(
57491 ptr as *const i8,
57492 transmute(a),
57493 crate::mem::align_of::<p16>() as i32,
57494 )
57495}
57496#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
57498#[doc = "## Safety"]
57499#[doc = " * Neon instrinsic unsafe"]
57500#[inline]
57501#[target_feature(enable = "neon")]
57502#[cfg(target_arch = "arm")]
57503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57505#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
57506pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
57507 vst1q_v8i16(
57508 ptr as *const i8,
57509 transmute(a),
57510 crate::mem::align_of::<p16>() as i32,
57511 )
57512}
57513#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
57515#[doc = "## Safety"]
57516#[doc = " * Neon instrinsic unsafe"]
57517#[inline]
57518#[target_feature(enable = "neon")]
57519#[cfg(target_arch = "arm")]
57520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57521#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57522#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
57523pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
57524 vst1_v1i64(
57525 ptr as *const i8,
57526 transmute(a),
57527 crate::mem::align_of::<p64>() as i32,
57528 )
57529}
57530#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
57531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
57532#[doc = "## Safety"]
57533#[doc = " * Neon instrinsic unsafe"]
57534#[inline]
57535#[target_feature(enable = "neon")]
57536#[cfg(target_arch = "arm")]
57537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57538#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
57540pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
57541 vst1q_v2i64(
57542 ptr as *const i8,
57543 transmute(a),
57544 crate::mem::align_of::<p64>() as i32,
57545 )
57546}
57547#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
57549#[doc = "## Safety"]
57550#[doc = " * Neon instrinsic unsafe"]
57551#[inline]
57552#[cfg(target_arch = "arm")]
57553#[target_feature(enable = "neon,v7")]
57554#[cfg_attr(test, assert_instr(vst1))]
57555#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57556pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
57557 unsafe extern "unadjusted" {
57558 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2f32.p0")]
57559 fn _vst1_f32_x2(ptr: *mut f32, a: float32x2_t, b: float32x2_t);
57560 }
57561 _vst1_f32_x2(a, b.0, b.1)
57562}
57563#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
57565#[doc = "## Safety"]
57566#[doc = " * Neon instrinsic unsafe"]
57567#[inline]
57568#[cfg(target_arch = "arm")]
57569#[target_feature(enable = "neon,v7")]
57570#[cfg_attr(test, assert_instr(vst1))]
57571#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57572pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
57573 unsafe extern "unadjusted" {
57574 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4f32.p0")]
57575 fn _vst1q_f32_x2(ptr: *mut f32, a: float32x4_t, b: float32x4_t);
57576 }
57577 _vst1q_f32_x2(a, b.0, b.1)
57578}
57579#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
57581#[doc = "## Safety"]
57582#[doc = " * Neon instrinsic unsafe"]
57583#[inline]
57584#[target_feature(enable = "neon")]
57585#[cfg(not(target_arch = "arm"))]
57586#[cfg_attr(test, assert_instr(st1))]
57587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
57588pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
57589 unsafe extern "unadjusted" {
57590 #[cfg_attr(
57591 any(target_arch = "aarch64", target_arch = "arm64ec"),
57592 link_name = "llvm.aarch64.neon.st1x2.v2f32.p0f32"
57593 )]
57594 fn _vst1_f32_x2(a: float32x2_t, b: float32x2_t, ptr: *mut f32);
57595 }
57596 _vst1_f32_x2(b.0, b.1, a)
57597}
57598#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
57600#[doc = "## Safety"]
57601#[doc = " * Neon instrinsic unsafe"]
57602#[inline]
57603#[target_feature(enable = "neon")]
57604#[cfg(not(target_arch = "arm"))]
57605#[cfg_attr(test, assert_instr(st1))]
57606#[stable(feature = "neon_intrinsics", since = "1.59.0")]
57607pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
57608 unsafe extern "unadjusted" {
57609 #[cfg_attr(
57610 any(target_arch = "aarch64", target_arch = "arm64ec"),
57611 link_name = "llvm.aarch64.neon.st1x2.v4f32.p0f32"
57612 )]
57613 fn _vst1q_f32_x2(a: float32x4_t, b: float32x4_t, ptr: *mut f32);
57614 }
57615 _vst1q_f32_x2(b.0, b.1, a)
57616}
57617#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
57619#[doc = "## Safety"]
57620#[doc = " * Neon instrinsic unsafe"]
57621#[inline]
57622#[target_feature(enable = "neon")]
57623#[cfg(not(target_arch = "arm"))]
57624#[cfg_attr(test, assert_instr(st1))]
57625#[stable(feature = "neon_intrinsics", since = "1.59.0")]
57626pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
57627 unsafe extern "unadjusted" {
57628 #[cfg_attr(
57629 any(target_arch = "aarch64", target_arch = "arm64ec"),
57630 link_name = "llvm.aarch64.neon.st1x3.v2f32.p0f32"
57631 )]
57632 fn _vst1_f32_x3(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32);
57633 }
57634 _vst1_f32_x3(b.0, b.1, b.2, a)
57635}
57636#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
57638#[doc = "## Safety"]
57639#[doc = " * Neon instrinsic unsafe"]
57640#[inline]
57641#[target_feature(enable = "neon")]
57642#[cfg(not(target_arch = "arm"))]
57643#[cfg_attr(test, assert_instr(st1))]
57644#[stable(feature = "neon_intrinsics", since = "1.59.0")]
57645pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
57646 unsafe extern "unadjusted" {
57647 #[cfg_attr(
57648 any(target_arch = "aarch64", target_arch = "arm64ec"),
57649 link_name = "llvm.aarch64.neon.st1x3.v4f32.p0f32"
57650 )]
57651 fn _vst1q_f32_x3(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32);
57652 }
57653 _vst1q_f32_x3(b.0, b.1, b.2, a)
57654}
57655#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
57657#[doc = "## Safety"]
57658#[doc = " * Neon instrinsic unsafe"]
57659#[inline]
57660#[cfg(target_arch = "arm")]
57661#[target_feature(enable = "neon,v7")]
57662#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57663#[cfg_attr(test, assert_instr(vst1))]
57664pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
57665 unsafe extern "unadjusted" {
57666 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v2f32.p0")]
57667 fn _vst1_f32_x4(
57668 ptr: *mut f32,
57669 a: float32x2_t,
57670 b: float32x2_t,
57671 c: float32x2_t,
57672 d: float32x2_t,
57673 );
57674 }
57675 _vst1_f32_x4(a, b.0, b.1, b.2, b.3)
57676}
57677#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
57679#[doc = "## Safety"]
57680#[doc = " * Neon instrinsic unsafe"]
57681#[inline]
57682#[cfg(target_arch = "arm")]
57683#[target_feature(enable = "neon,v7")]
57684#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
57685#[cfg_attr(test, assert_instr(vst1))]
57686pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
57687 unsafe extern "unadjusted" {
57688 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v4f32.p0")]
57689 fn _vst1q_f32_x4(
57690 ptr: *mut f32,
57691 a: float32x4_t,
57692 b: float32x4_t,
57693 c: float32x4_t,
57694 d: float32x4_t,
57695 );
57696 }
57697 _vst1q_f32_x4(a, b.0, b.1, b.2, b.3)
57698}
57699#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
57701#[doc = "## Safety"]
57702#[doc = " * Neon instrinsic unsafe"]
57703#[inline]
57704#[target_feature(enable = "neon")]
57705#[cfg(not(target_arch = "arm"))]
57706#[cfg_attr(test, assert_instr(st1))]
57707#[stable(feature = "neon_intrinsics", since = "1.59.0")]
57708pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
57709 unsafe extern "unadjusted" {
57710 #[cfg_attr(
57711 any(target_arch = "aarch64", target_arch = "arm64ec"),
57712 link_name = "llvm.aarch64.neon.st1x4.v2f32.p0f32"
57713 )]
57714 fn _vst1_f32_x4(
57715 a: float32x2_t,
57716 b: float32x2_t,
57717 c: float32x2_t,
57718 d: float32x2_t,
57719 ptr: *mut f32,
57720 );
57721 }
57722 _vst1_f32_x4(b.0, b.1, b.2, b.3, a)
57723}
57724#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
57725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
57726#[doc = "## Safety"]
57727#[doc = " * Neon instrinsic unsafe"]
57728#[inline]
57729#[target_feature(enable = "neon")]
57730#[cfg(not(target_arch = "arm"))]
57731#[cfg_attr(test, assert_instr(st1))]
57732#[stable(feature = "neon_intrinsics", since = "1.59.0")]
57733pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
57734 unsafe extern "unadjusted" {
57735 #[cfg_attr(
57736 any(target_arch = "aarch64", target_arch = "arm64ec"),
57737 link_name = "llvm.aarch64.neon.st1x4.v4f32.p0f32"
57738 )]
57739 fn _vst1q_f32_x4(
57740 a: float32x4_t,
57741 b: float32x4_t,
57742 c: float32x4_t,
57743 d: float32x4_t,
57744 ptr: *mut f32,
57745 );
57746 }
57747 _vst1q_f32_x4(b.0, b.1, b.2, b.3, a)
57748}
57749#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
57751#[doc = "## Safety"]
57752#[doc = " * Neon instrinsic unsafe"]
57753#[inline]
57754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57756#[cfg_attr(
57757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57758 assert_instr(nop, LANE = 0)
57759)]
57760#[rustc_legacy_const_generics(2)]
57761#[target_feature(enable = "neon,fp16")]
57762#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57763pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
57764 static_assert_uimm_bits!(LANE, 2);
57765 *a = simd_extract!(b, LANE as u32);
57766}
57767#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
57769#[doc = "## Safety"]
57770#[doc = " * Neon instrinsic unsafe"]
57771#[inline]
57772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57773#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57774#[cfg_attr(
57775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57776 assert_instr(nop, LANE = 0)
57777)]
57778#[rustc_legacy_const_generics(2)]
57779#[target_feature(enable = "neon,fp16")]
57780#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57781pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
57782 static_assert_uimm_bits!(LANE, 3);
57783 *a = simd_extract!(b, LANE as u32);
57784}
57785#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
57787#[doc = "## Safety"]
57788#[doc = " * Neon instrinsic unsafe"]
57789#[inline]
57790#[target_feature(enable = "neon")]
57791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57793#[cfg_attr(
57794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57795 assert_instr(nop, LANE = 0)
57796)]
57797#[rustc_legacy_const_generics(2)]
57798#[cfg_attr(
57799 not(target_arch = "arm"),
57800 stable(feature = "neon_intrinsics", since = "1.59.0")
57801)]
57802#[cfg_attr(
57803 target_arch = "arm",
57804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57805)]
57806pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
57807 static_assert_uimm_bits!(LANE, 1);
57808 *a = simd_extract!(b, LANE as u32);
57809}
57810#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
57812#[doc = "## Safety"]
57813#[doc = " * Neon instrinsic unsafe"]
57814#[inline]
57815#[target_feature(enable = "neon")]
57816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57817#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57818#[cfg_attr(
57819 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57820 assert_instr(nop, LANE = 0)
57821)]
57822#[rustc_legacy_const_generics(2)]
57823#[cfg_attr(
57824 not(target_arch = "arm"),
57825 stable(feature = "neon_intrinsics", since = "1.59.0")
57826)]
57827#[cfg_attr(
57828 target_arch = "arm",
57829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57830)]
57831pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
57832 static_assert_uimm_bits!(LANE, 2);
57833 *a = simd_extract!(b, LANE as u32);
57834}
57835#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
57837#[doc = "## Safety"]
57838#[doc = " * Neon instrinsic unsafe"]
57839#[inline]
57840#[target_feature(enable = "neon")]
57841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57843#[cfg_attr(
57844 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57845 assert_instr(nop, LANE = 0)
57846)]
57847#[rustc_legacy_const_generics(2)]
57848#[cfg_attr(
57849 not(target_arch = "arm"),
57850 stable(feature = "neon_intrinsics", since = "1.59.0")
57851)]
57852#[cfg_attr(
57853 target_arch = "arm",
57854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57855)]
57856pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
57857 static_assert_uimm_bits!(LANE, 3);
57858 *a = simd_extract!(b, LANE as u32);
57859}
57860#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
57862#[doc = "## Safety"]
57863#[doc = " * Neon instrinsic unsafe"]
57864#[inline]
57865#[target_feature(enable = "neon")]
57866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57868#[cfg_attr(
57869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57870 assert_instr(nop, LANE = 0)
57871)]
57872#[rustc_legacy_const_generics(2)]
57873#[cfg_attr(
57874 not(target_arch = "arm"),
57875 stable(feature = "neon_intrinsics", since = "1.59.0")
57876)]
57877#[cfg_attr(
57878 target_arch = "arm",
57879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57880)]
57881pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
57882 static_assert_uimm_bits!(LANE, 4);
57883 *a = simd_extract!(b, LANE as u32);
57884}
57885#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
57887#[doc = "## Safety"]
57888#[doc = " * Neon instrinsic unsafe"]
57889#[inline]
57890#[target_feature(enable = "neon")]
57891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57893#[cfg_attr(
57894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57895 assert_instr(nop, LANE = 0)
57896)]
57897#[rustc_legacy_const_generics(2)]
57898#[cfg_attr(
57899 not(target_arch = "arm"),
57900 stable(feature = "neon_intrinsics", since = "1.59.0")
57901)]
57902#[cfg_attr(
57903 target_arch = "arm",
57904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57905)]
57906pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
57907 static_assert_uimm_bits!(LANE, 2);
57908 *a = simd_extract!(b, LANE as u32);
57909}
57910#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
57912#[doc = "## Safety"]
57913#[doc = " * Neon instrinsic unsafe"]
57914#[inline]
57915#[target_feature(enable = "neon")]
57916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57918#[cfg_attr(
57919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57920 assert_instr(nop, LANE = 0)
57921)]
57922#[rustc_legacy_const_generics(2)]
57923#[cfg_attr(
57924 not(target_arch = "arm"),
57925 stable(feature = "neon_intrinsics", since = "1.59.0")
57926)]
57927#[cfg_attr(
57928 target_arch = "arm",
57929 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57930)]
57931pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
57932 static_assert_uimm_bits!(LANE, 3);
57933 *a = simd_extract!(b, LANE as u32);
57934}
57935#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
57937#[doc = "## Safety"]
57938#[doc = " * Neon instrinsic unsafe"]
57939#[inline]
57940#[target_feature(enable = "neon")]
57941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57943#[cfg_attr(
57944 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57945 assert_instr(nop, LANE = 0)
57946)]
57947#[rustc_legacy_const_generics(2)]
57948#[cfg_attr(
57949 not(target_arch = "arm"),
57950 stable(feature = "neon_intrinsics", since = "1.59.0")
57951)]
57952#[cfg_attr(
57953 target_arch = "arm",
57954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57955)]
57956pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
57957 static_assert_uimm_bits!(LANE, 1);
57958 *a = simd_extract!(b, LANE as u32);
57959}
57960#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
57962#[doc = "## Safety"]
57963#[doc = " * Neon instrinsic unsafe"]
57964#[inline]
57965#[target_feature(enable = "neon")]
57966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57968#[cfg_attr(
57969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57970 assert_instr(nop, LANE = 0)
57971)]
57972#[rustc_legacy_const_generics(2)]
57973#[cfg_attr(
57974 not(target_arch = "arm"),
57975 stable(feature = "neon_intrinsics", since = "1.59.0")
57976)]
57977#[cfg_attr(
57978 target_arch = "arm",
57979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57980)]
57981pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
57982 static_assert_uimm_bits!(LANE, 2);
57983 *a = simd_extract!(b, LANE as u32);
57984}
57985#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
57986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
57987#[doc = "## Safety"]
57988#[doc = " * Neon instrinsic unsafe"]
57989#[inline]
57990#[target_feature(enable = "neon")]
57991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
57993#[cfg_attr(
57994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57995 assert_instr(nop, LANE = 0)
57996)]
57997#[rustc_legacy_const_generics(2)]
57998#[cfg_attr(
57999 not(target_arch = "arm"),
58000 stable(feature = "neon_intrinsics", since = "1.59.0")
58001)]
58002#[cfg_attr(
58003 target_arch = "arm",
58004 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58005)]
58006pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
58007 static_assert_uimm_bits!(LANE, 1);
58008 *a = simd_extract!(b, LANE as u32);
58009}
58010#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
58012#[doc = "## Safety"]
58013#[doc = " * Neon instrinsic unsafe"]
58014#[inline]
58015#[target_feature(enable = "neon")]
58016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58018#[cfg_attr(
58019 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58020 assert_instr(nop, LANE = 0)
58021)]
58022#[rustc_legacy_const_generics(2)]
58023#[cfg_attr(
58024 not(target_arch = "arm"),
58025 stable(feature = "neon_intrinsics", since = "1.59.0")
58026)]
58027#[cfg_attr(
58028 target_arch = "arm",
58029 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58030)]
58031pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
58032 static_assert_uimm_bits!(LANE, 3);
58033 *a = simd_extract!(b, LANE as u32);
58034}
58035#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
58037#[doc = "## Safety"]
58038#[doc = " * Neon instrinsic unsafe"]
58039#[inline]
58040#[target_feature(enable = "neon")]
58041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58043#[cfg_attr(
58044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58045 assert_instr(nop, LANE = 0)
58046)]
58047#[rustc_legacy_const_generics(2)]
58048#[cfg_attr(
58049 not(target_arch = "arm"),
58050 stable(feature = "neon_intrinsics", since = "1.59.0")
58051)]
58052#[cfg_attr(
58053 target_arch = "arm",
58054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58055)]
58056pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
58057 static_assert_uimm_bits!(LANE, 4);
58058 *a = simd_extract!(b, LANE as u32);
58059}
58060#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
58062#[doc = "## Safety"]
58063#[doc = " * Neon instrinsic unsafe"]
58064#[inline]
58065#[target_feature(enable = "neon")]
58066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58068#[cfg_attr(
58069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58070 assert_instr(nop, LANE = 0)
58071)]
58072#[rustc_legacy_const_generics(2)]
58073#[cfg_attr(
58074 not(target_arch = "arm"),
58075 stable(feature = "neon_intrinsics", since = "1.59.0")
58076)]
58077#[cfg_attr(
58078 target_arch = "arm",
58079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58080)]
58081pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
58082 static_assert_uimm_bits!(LANE, 2);
58083 *a = simd_extract!(b, LANE as u32);
58084}
58085#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
58087#[doc = "## Safety"]
58088#[doc = " * Neon instrinsic unsafe"]
58089#[inline]
58090#[target_feature(enable = "neon")]
58091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58093#[cfg_attr(
58094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58095 assert_instr(nop, LANE = 0)
58096)]
58097#[rustc_legacy_const_generics(2)]
58098#[cfg_attr(
58099 not(target_arch = "arm"),
58100 stable(feature = "neon_intrinsics", since = "1.59.0")
58101)]
58102#[cfg_attr(
58103 target_arch = "arm",
58104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58105)]
58106pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
58107 static_assert_uimm_bits!(LANE, 3);
58108 *a = simd_extract!(b, LANE as u32);
58109}
58110#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
58112#[doc = "## Safety"]
58113#[doc = " * Neon instrinsic unsafe"]
58114#[inline]
58115#[target_feature(enable = "neon")]
58116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58118#[cfg_attr(
58119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58120 assert_instr(nop, LANE = 0)
58121)]
58122#[rustc_legacy_const_generics(2)]
58123#[cfg_attr(
58124 not(target_arch = "arm"),
58125 stable(feature = "neon_intrinsics", since = "1.59.0")
58126)]
58127#[cfg_attr(
58128 target_arch = "arm",
58129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58130)]
58131pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
58132 static_assert_uimm_bits!(LANE, 1);
58133 *a = simd_extract!(b, LANE as u32);
58134}
58135#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
58137#[doc = "## Safety"]
58138#[doc = " * Neon instrinsic unsafe"]
58139#[inline]
58140#[target_feature(enable = "neon")]
58141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58143#[cfg_attr(
58144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58145 assert_instr(nop, LANE = 0)
58146)]
58147#[rustc_legacy_const_generics(2)]
58148#[cfg_attr(
58149 not(target_arch = "arm"),
58150 stable(feature = "neon_intrinsics", since = "1.59.0")
58151)]
58152#[cfg_attr(
58153 target_arch = "arm",
58154 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58155)]
58156pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
58157 static_assert_uimm_bits!(LANE, 2);
58158 *a = simd_extract!(b, LANE as u32);
58159}
58160#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
58162#[doc = "## Safety"]
58163#[doc = " * Neon instrinsic unsafe"]
58164#[inline]
58165#[target_feature(enable = "neon")]
58166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58168#[cfg_attr(
58169 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58170 assert_instr(nop, LANE = 0)
58171)]
58172#[rustc_legacy_const_generics(2)]
58173#[cfg_attr(
58174 not(target_arch = "arm"),
58175 stable(feature = "neon_intrinsics", since = "1.59.0")
58176)]
58177#[cfg_attr(
58178 target_arch = "arm",
58179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58180)]
58181pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
58182 static_assert_uimm_bits!(LANE, 1);
58183 *a = simd_extract!(b, LANE as u32);
58184}
58185#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
58187#[doc = "## Safety"]
58188#[doc = " * Neon instrinsic unsafe"]
58189#[inline]
58190#[target_feature(enable = "neon")]
58191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58193#[cfg_attr(
58194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58195 assert_instr(nop, LANE = 0)
58196)]
58197#[rustc_legacy_const_generics(2)]
58198#[cfg_attr(
58199 not(target_arch = "arm"),
58200 stable(feature = "neon_intrinsics", since = "1.59.0")
58201)]
58202#[cfg_attr(
58203 target_arch = "arm",
58204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58205)]
58206pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
58207 static_assert_uimm_bits!(LANE, 3);
58208 *a = simd_extract!(b, LANE as u32);
58209}
58210#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
58212#[doc = "## Safety"]
58213#[doc = " * Neon instrinsic unsafe"]
58214#[inline]
58215#[target_feature(enable = "neon")]
58216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58218#[cfg_attr(
58219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58220 assert_instr(nop, LANE = 0)
58221)]
58222#[rustc_legacy_const_generics(2)]
58223#[cfg_attr(
58224 not(target_arch = "arm"),
58225 stable(feature = "neon_intrinsics", since = "1.59.0")
58226)]
58227#[cfg_attr(
58228 target_arch = "arm",
58229 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58230)]
58231pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
58232 static_assert_uimm_bits!(LANE, 4);
58233 *a = simd_extract!(b, LANE as u32);
58234}
58235#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
58237#[doc = "## Safety"]
58238#[doc = " * Neon instrinsic unsafe"]
58239#[inline]
58240#[target_feature(enable = "neon")]
58241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58243#[cfg_attr(
58244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58245 assert_instr(nop, LANE = 0)
58246)]
58247#[rustc_legacy_const_generics(2)]
58248#[cfg_attr(
58249 not(target_arch = "arm"),
58250 stable(feature = "neon_intrinsics", since = "1.59.0")
58251)]
58252#[cfg_attr(
58253 target_arch = "arm",
58254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58255)]
58256pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
58257 static_assert_uimm_bits!(LANE, 2);
58258 *a = simd_extract!(b, LANE as u32);
58259}
58260#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
58262#[doc = "## Safety"]
58263#[doc = " * Neon instrinsic unsafe"]
58264#[inline]
58265#[target_feature(enable = "neon")]
58266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58268#[cfg_attr(
58269 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58270 assert_instr(nop, LANE = 0)
58271)]
58272#[rustc_legacy_const_generics(2)]
58273#[cfg_attr(
58274 not(target_arch = "arm"),
58275 stable(feature = "neon_intrinsics", since = "1.59.0")
58276)]
58277#[cfg_attr(
58278 target_arch = "arm",
58279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58280)]
58281pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
58282 static_assert_uimm_bits!(LANE, 3);
58283 *a = simd_extract!(b, LANE as u32);
58284}
58285#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
58287#[doc = "## Safety"]
58288#[doc = " * Neon instrinsic unsafe"]
58289#[inline]
58290#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58291#[target_feature(enable = "neon,aes")]
58292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58293#[cfg_attr(
58294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58295 assert_instr(nop, LANE = 0)
58296)]
58297#[rustc_legacy_const_generics(2)]
58298#[cfg_attr(
58299 not(target_arch = "arm"),
58300 stable(feature = "neon_intrinsics", since = "1.59.0")
58301)]
58302#[cfg_attr(
58303 target_arch = "arm",
58304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58305)]
58306pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
58307 static_assert!(LANE == 0);
58308 *a = simd_extract!(b, LANE as u32);
58309}
58310#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
58312#[doc = "## Safety"]
58313#[doc = " * Neon instrinsic unsafe"]
58314#[inline]
58315#[target_feature(enable = "neon")]
58316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58318#[cfg_attr(
58319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58320 assert_instr(nop, LANE = 0)
58321)]
58322#[rustc_legacy_const_generics(2)]
58323#[cfg_attr(
58324 not(target_arch = "arm"),
58325 stable(feature = "neon_intrinsics", since = "1.59.0")
58326)]
58327#[cfg_attr(
58328 target_arch = "arm",
58329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58330)]
58331pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
58332 static_assert!(LANE == 0);
58333 *a = simd_extract!(b, LANE as u32);
58334}
58335#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
58337#[doc = "## Safety"]
58338#[doc = " * Neon instrinsic unsafe"]
58339#[inline]
58340#[target_feature(enable = "neon")]
58341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58342#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
58343#[cfg_attr(
58344 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58345 assert_instr(nop, LANE = 0)
58346)]
58347#[rustc_legacy_const_generics(2)]
58348#[cfg_attr(
58349 not(target_arch = "arm"),
58350 stable(feature = "neon_intrinsics", since = "1.59.0")
58351)]
58352#[cfg_attr(
58353 target_arch = "arm",
58354 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58355)]
58356pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
58357 static_assert!(LANE == 0);
58358 *a = simd_extract!(b, LANE as u32);
58359}
58360#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
58361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
58362#[doc = "## Safety"]
58363#[doc = " * Neon instrinsic unsafe"]
58364#[inline]
58365#[target_feature(enable = "neon,aes")]
58366#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
58368#[cfg_attr(
58369 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58370 assert_instr(st1)
58371)]
58372#[cfg_attr(
58373 not(target_arch = "arm"),
58374 stable(feature = "neon_intrinsics", since = "1.59.0")
58375)]
58376#[cfg_attr(
58377 target_arch = "arm",
58378 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58379)]
58380pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
58381 vst1_s64_x2(transmute(a), transmute(b))
58382}
58383#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
58384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
58385#[doc = "## Safety"]
58386#[doc = " * Neon instrinsic unsafe"]
58387#[inline]
58388#[target_feature(enable = "neon,aes")]
58389#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
58391#[cfg_attr(
58392 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58393 assert_instr(st1)
58394)]
58395#[cfg_attr(
58396 not(target_arch = "arm"),
58397 stable(feature = "neon_intrinsics", since = "1.59.0")
58398)]
58399#[cfg_attr(
58400 target_arch = "arm",
58401 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58402)]
58403pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
58404 vst1_s64_x3(transmute(a), transmute(b))
58405}
58406#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
58407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
58408#[doc = "## Safety"]
58409#[doc = " * Neon instrinsic unsafe"]
58410#[inline]
58411#[target_feature(enable = "neon,aes")]
58412#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
58414#[cfg_attr(
58415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58416 assert_instr(st1)
58417)]
58418#[cfg_attr(
58419 not(target_arch = "arm"),
58420 stable(feature = "neon_intrinsics", since = "1.59.0")
58421)]
58422#[cfg_attr(
58423 target_arch = "arm",
58424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58425)]
58426pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
58427 vst1_s64_x4(transmute(a), transmute(b))
58428}
58429#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
58430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
58431#[doc = "## Safety"]
58432#[doc = " * Neon instrinsic unsafe"]
58433#[inline]
58434#[target_feature(enable = "neon,aes")]
58435#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
58437#[cfg_attr(
58438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58439 assert_instr(st1)
58440)]
58441#[cfg_attr(
58442 not(target_arch = "arm"),
58443 stable(feature = "neon_intrinsics", since = "1.59.0")
58444)]
58445#[cfg_attr(
58446 target_arch = "arm",
58447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58448)]
58449pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
58450 vst1q_s64_x2(transmute(a), transmute(b))
58451}
58452#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
58453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
58454#[doc = "## Safety"]
58455#[doc = " * Neon instrinsic unsafe"]
58456#[inline]
58457#[target_feature(enable = "neon,aes")]
58458#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
58460#[cfg_attr(
58461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58462 assert_instr(st1)
58463)]
58464#[cfg_attr(
58465 not(target_arch = "arm"),
58466 stable(feature = "neon_intrinsics", since = "1.59.0")
58467)]
58468#[cfg_attr(
58469 target_arch = "arm",
58470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58471)]
58472pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
58473 vst1q_s64_x3(transmute(a), transmute(b))
58474}
58475#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
58476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
58477#[doc = "## Safety"]
58478#[doc = " * Neon instrinsic unsafe"]
58479#[inline]
58480#[target_feature(enable = "neon,aes")]
58481#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
58483#[cfg_attr(
58484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58485 assert_instr(st1)
58486)]
58487#[cfg_attr(
58488 not(target_arch = "arm"),
58489 stable(feature = "neon_intrinsics", since = "1.59.0")
58490)]
58491#[cfg_attr(
58492 target_arch = "arm",
58493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58494)]
58495pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
58496 vst1q_s64_x4(transmute(a), transmute(b))
58497}
58498#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
58500#[doc = "## Safety"]
58501#[doc = " * Neon instrinsic unsafe"]
58502#[inline]
58503#[target_feature(enable = "neon")]
58504#[cfg(not(target_arch = "arm"))]
58505#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58506#[cfg_attr(test, assert_instr(st1))]
58507pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
58508 unsafe extern "unadjusted" {
58509 #[cfg_attr(
58510 any(target_arch = "aarch64", target_arch = "arm64ec"),
58511 link_name = "llvm.aarch64.neon.st1x2.v8i8.p0i8"
58512 )]
58513 fn _vst1_s8_x2(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
58514 }
58515 _vst1_s8_x2(b.0, b.1, a)
58516}
58517#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
58519#[doc = "## Safety"]
58520#[doc = " * Neon instrinsic unsafe"]
58521#[inline]
58522#[target_feature(enable = "neon")]
58523#[cfg(not(target_arch = "arm"))]
58524#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58525#[cfg_attr(test, assert_instr(st1))]
58526pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
58527 unsafe extern "unadjusted" {
58528 #[cfg_attr(
58529 any(target_arch = "aarch64", target_arch = "arm64ec"),
58530 link_name = "llvm.aarch64.neon.st1x2.v16i8.p0i8"
58531 )]
58532 fn _vst1q_s8_x2(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
58533 }
58534 _vst1q_s8_x2(b.0, b.1, a)
58535}
58536#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
58538#[doc = "## Safety"]
58539#[doc = " * Neon instrinsic unsafe"]
58540#[inline]
58541#[target_feature(enable = "neon")]
58542#[cfg(not(target_arch = "arm"))]
58543#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58544#[cfg_attr(test, assert_instr(st1))]
58545pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
58546 unsafe extern "unadjusted" {
58547 #[cfg_attr(
58548 any(target_arch = "aarch64", target_arch = "arm64ec"),
58549 link_name = "llvm.aarch64.neon.st1x2.v4i16.p0i16"
58550 )]
58551 fn _vst1_s16_x2(a: int16x4_t, b: int16x4_t, ptr: *mut i16);
58552 }
58553 _vst1_s16_x2(b.0, b.1, a)
58554}
58555#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
58557#[doc = "## Safety"]
58558#[doc = " * Neon instrinsic unsafe"]
58559#[inline]
58560#[target_feature(enable = "neon")]
58561#[cfg(not(target_arch = "arm"))]
58562#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58563#[cfg_attr(test, assert_instr(st1))]
58564pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
58565 unsafe extern "unadjusted" {
58566 #[cfg_attr(
58567 any(target_arch = "aarch64", target_arch = "arm64ec"),
58568 link_name = "llvm.aarch64.neon.st1x2.v8i16.p0i16"
58569 )]
58570 fn _vst1q_s16_x2(a: int16x8_t, b: int16x8_t, ptr: *mut i16);
58571 }
58572 _vst1q_s16_x2(b.0, b.1, a)
58573}
58574#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
58576#[doc = "## Safety"]
58577#[doc = " * Neon instrinsic unsafe"]
58578#[inline]
58579#[target_feature(enable = "neon")]
58580#[cfg(not(target_arch = "arm"))]
58581#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58582#[cfg_attr(test, assert_instr(st1))]
58583pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
58584 unsafe extern "unadjusted" {
58585 #[cfg_attr(
58586 any(target_arch = "aarch64", target_arch = "arm64ec"),
58587 link_name = "llvm.aarch64.neon.st1x2.v2i32.p0i32"
58588 )]
58589 fn _vst1_s32_x2(a: int32x2_t, b: int32x2_t, ptr: *mut i32);
58590 }
58591 _vst1_s32_x2(b.0, b.1, a)
58592}
58593#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
58595#[doc = "## Safety"]
58596#[doc = " * Neon instrinsic unsafe"]
58597#[inline]
58598#[target_feature(enable = "neon")]
58599#[cfg(not(target_arch = "arm"))]
58600#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58601#[cfg_attr(test, assert_instr(st1))]
58602pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
58603 unsafe extern "unadjusted" {
58604 #[cfg_attr(
58605 any(target_arch = "aarch64", target_arch = "arm64ec"),
58606 link_name = "llvm.aarch64.neon.st1x2.v4i32.p0i32"
58607 )]
58608 fn _vst1q_s32_x2(a: int32x4_t, b: int32x4_t, ptr: *mut i32);
58609 }
58610 _vst1q_s32_x2(b.0, b.1, a)
58611}
58612#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
58614#[doc = "## Safety"]
58615#[doc = " * Neon instrinsic unsafe"]
58616#[inline]
58617#[target_feature(enable = "neon")]
58618#[cfg(not(target_arch = "arm"))]
58619#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58620#[cfg_attr(test, assert_instr(st1))]
58621pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
58622 unsafe extern "unadjusted" {
58623 #[cfg_attr(
58624 any(target_arch = "aarch64", target_arch = "arm64ec"),
58625 link_name = "llvm.aarch64.neon.st1x2.v1i64.p0i64"
58626 )]
58627 fn _vst1_s64_x2(a: int64x1_t, b: int64x1_t, ptr: *mut i64);
58628 }
58629 _vst1_s64_x2(b.0, b.1, a)
58630}
58631#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
58633#[doc = "## Safety"]
58634#[doc = " * Neon instrinsic unsafe"]
58635#[inline]
58636#[target_feature(enable = "neon")]
58637#[cfg(not(target_arch = "arm"))]
58638#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58639#[cfg_attr(test, assert_instr(st1))]
58640pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
58641 unsafe extern "unadjusted" {
58642 #[cfg_attr(
58643 any(target_arch = "aarch64", target_arch = "arm64ec"),
58644 link_name = "llvm.aarch64.neon.st1x2.v2i64.p0i64"
58645 )]
58646 fn _vst1q_s64_x2(a: int64x2_t, b: int64x2_t, ptr: *mut i64);
58647 }
58648 _vst1q_s64_x2(b.0, b.1, a)
58649}
58650#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
58652#[doc = "## Safety"]
58653#[doc = " * Neon instrinsic unsafe"]
58654#[inline]
58655#[target_feature(enable = "neon,v7")]
58656#[cfg(target_arch = "arm")]
58657#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58658#[cfg_attr(test, assert_instr(vst1))]
58659pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
58660 unsafe extern "unadjusted" {
58661 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i8.p0")]
58662 fn _vst1_s8_x2(ptr: *mut i8, a: int8x8_t, b: int8x8_t);
58663 }
58664 _vst1_s8_x2(a, b.0, b.1)
58665}
58666#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
58668#[doc = "## Safety"]
58669#[doc = " * Neon instrinsic unsafe"]
58670#[inline]
58671#[target_feature(enable = "neon,v7")]
58672#[cfg(target_arch = "arm")]
58673#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58674#[cfg_attr(test, assert_instr(vst1))]
58675pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
58676 unsafe extern "unadjusted" {
58677 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v16i8.p0")]
58678 fn _vst1q_s8_x2(ptr: *mut i8, a: int8x16_t, b: int8x16_t);
58679 }
58680 _vst1q_s8_x2(a, b.0, b.1)
58681}
58682#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
58684#[doc = "## Safety"]
58685#[doc = " * Neon instrinsic unsafe"]
58686#[inline]
58687#[target_feature(enable = "neon,v7")]
58688#[cfg(target_arch = "arm")]
58689#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58690#[cfg_attr(test, assert_instr(vst1))]
58691pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
58692 unsafe extern "unadjusted" {
58693 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i16.p0")]
58694 fn _vst1_s16_x2(ptr: *mut i16, a: int16x4_t, b: int16x4_t);
58695 }
58696 _vst1_s16_x2(a, b.0, b.1)
58697}
58698#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
58700#[doc = "## Safety"]
58701#[doc = " * Neon instrinsic unsafe"]
58702#[inline]
58703#[target_feature(enable = "neon,v7")]
58704#[cfg(target_arch = "arm")]
58705#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58706#[cfg_attr(test, assert_instr(vst1))]
58707pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
58708 unsafe extern "unadjusted" {
58709 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i16.p0")]
58710 fn _vst1q_s16_x2(ptr: *mut i16, a: int16x8_t, b: int16x8_t);
58711 }
58712 _vst1q_s16_x2(a, b.0, b.1)
58713}
58714#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
58716#[doc = "## Safety"]
58717#[doc = " * Neon instrinsic unsafe"]
58718#[inline]
58719#[target_feature(enable = "neon,v7")]
58720#[cfg(target_arch = "arm")]
58721#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58722#[cfg_attr(test, assert_instr(vst1))]
58723pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
58724 unsafe extern "unadjusted" {
58725 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i32.p0")]
58726 fn _vst1_s32_x2(ptr: *mut i32, a: int32x2_t, b: int32x2_t);
58727 }
58728 _vst1_s32_x2(a, b.0, b.1)
58729}
58730#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
58732#[doc = "## Safety"]
58733#[doc = " * Neon instrinsic unsafe"]
58734#[inline]
58735#[target_feature(enable = "neon,v7")]
58736#[cfg(target_arch = "arm")]
58737#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58738#[cfg_attr(test, assert_instr(vst1))]
58739pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
58740 unsafe extern "unadjusted" {
58741 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i32.p0")]
58742 fn _vst1q_s32_x2(ptr: *mut i32, a: int32x4_t, b: int32x4_t);
58743 }
58744 _vst1q_s32_x2(a, b.0, b.1)
58745}
58746#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
58748#[doc = "## Safety"]
58749#[doc = " * Neon instrinsic unsafe"]
58750#[inline]
58751#[target_feature(enable = "neon,v7")]
58752#[cfg(target_arch = "arm")]
58753#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58754#[cfg_attr(test, assert_instr(vst1))]
58755pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
58756 unsafe extern "unadjusted" {
58757 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v1i64.p0")]
58758 fn _vst1_s64_x2(ptr: *mut i64, a: int64x1_t, b: int64x1_t);
58759 }
58760 _vst1_s64_x2(a, b.0, b.1)
58761}
58762#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
58764#[doc = "## Safety"]
58765#[doc = " * Neon instrinsic unsafe"]
58766#[inline]
58767#[target_feature(enable = "neon,v7")]
58768#[cfg(target_arch = "arm")]
58769#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58770#[cfg_attr(test, assert_instr(vst1))]
58771pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
58772 unsafe extern "unadjusted" {
58773 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i64.p0")]
58774 fn _vst1q_s64_x2(ptr: *mut i64, a: int64x2_t, b: int64x2_t);
58775 }
58776 _vst1q_s64_x2(a, b.0, b.1)
58777}
58778#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
58780#[doc = "## Safety"]
58781#[doc = " * Neon instrinsic unsafe"]
58782#[inline]
58783#[target_feature(enable = "neon")]
58784#[cfg(not(target_arch = "arm"))]
58785#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58786#[cfg_attr(test, assert_instr(st1))]
58787pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
58788 unsafe extern "unadjusted" {
58789 #[cfg_attr(
58790 any(target_arch = "aarch64", target_arch = "arm64ec"),
58791 link_name = "llvm.aarch64.neon.st1x3.v8i8.p0i8"
58792 )]
58793 fn _vst1_s8_x3(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
58794 }
58795 _vst1_s8_x3(b.0, b.1, b.2, a)
58796}
58797#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
58799#[doc = "## Safety"]
58800#[doc = " * Neon instrinsic unsafe"]
58801#[inline]
58802#[target_feature(enable = "neon")]
58803#[cfg(not(target_arch = "arm"))]
58804#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58805#[cfg_attr(test, assert_instr(st1))]
58806pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
58807 unsafe extern "unadjusted" {
58808 #[cfg_attr(
58809 any(target_arch = "aarch64", target_arch = "arm64ec"),
58810 link_name = "llvm.aarch64.neon.st1x3.v16i8.p0i8"
58811 )]
58812 fn _vst1q_s8_x3(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
58813 }
58814 _vst1q_s8_x3(b.0, b.1, b.2, a)
58815}
58816#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
58818#[doc = "## Safety"]
58819#[doc = " * Neon instrinsic unsafe"]
58820#[inline]
58821#[target_feature(enable = "neon")]
58822#[cfg(not(target_arch = "arm"))]
58823#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58824#[cfg_attr(test, assert_instr(st1))]
58825pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
58826 unsafe extern "unadjusted" {
58827 #[cfg_attr(
58828 any(target_arch = "aarch64", target_arch = "arm64ec"),
58829 link_name = "llvm.aarch64.neon.st1x3.v4i16.p0i16"
58830 )]
58831 fn _vst1_s16_x3(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16);
58832 }
58833 _vst1_s16_x3(b.0, b.1, b.2, a)
58834}
58835#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
58837#[doc = "## Safety"]
58838#[doc = " * Neon instrinsic unsafe"]
58839#[inline]
58840#[target_feature(enable = "neon")]
58841#[cfg(not(target_arch = "arm"))]
58842#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58843#[cfg_attr(test, assert_instr(st1))]
58844pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
58845 unsafe extern "unadjusted" {
58846 #[cfg_attr(
58847 any(target_arch = "aarch64", target_arch = "arm64ec"),
58848 link_name = "llvm.aarch64.neon.st1x3.v8i16.p0i16"
58849 )]
58850 fn _vst1q_s16_x3(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16);
58851 }
58852 _vst1q_s16_x3(b.0, b.1, b.2, a)
58853}
58854#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
58856#[doc = "## Safety"]
58857#[doc = " * Neon instrinsic unsafe"]
58858#[inline]
58859#[target_feature(enable = "neon")]
58860#[cfg(not(target_arch = "arm"))]
58861#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58862#[cfg_attr(test, assert_instr(st1))]
58863pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
58864 unsafe extern "unadjusted" {
58865 #[cfg_attr(
58866 any(target_arch = "aarch64", target_arch = "arm64ec"),
58867 link_name = "llvm.aarch64.neon.st1x3.v2i32.p0i32"
58868 )]
58869 fn _vst1_s32_x3(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32);
58870 }
58871 _vst1_s32_x3(b.0, b.1, b.2, a)
58872}
58873#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
58875#[doc = "## Safety"]
58876#[doc = " * Neon instrinsic unsafe"]
58877#[inline]
58878#[target_feature(enable = "neon")]
58879#[cfg(not(target_arch = "arm"))]
58880#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58881#[cfg_attr(test, assert_instr(st1))]
58882pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
58883 unsafe extern "unadjusted" {
58884 #[cfg_attr(
58885 any(target_arch = "aarch64", target_arch = "arm64ec"),
58886 link_name = "llvm.aarch64.neon.st1x3.v4i32.p0i32"
58887 )]
58888 fn _vst1q_s32_x3(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32);
58889 }
58890 _vst1q_s32_x3(b.0, b.1, b.2, a)
58891}
58892#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
58894#[doc = "## Safety"]
58895#[doc = " * Neon instrinsic unsafe"]
58896#[inline]
58897#[target_feature(enable = "neon")]
58898#[cfg(not(target_arch = "arm"))]
58899#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58900#[cfg_attr(test, assert_instr(st1))]
58901pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
58902 unsafe extern "unadjusted" {
58903 #[cfg_attr(
58904 any(target_arch = "aarch64", target_arch = "arm64ec"),
58905 link_name = "llvm.aarch64.neon.st1x3.v1i64.p0i64"
58906 )]
58907 fn _vst1_s64_x3(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64);
58908 }
58909 _vst1_s64_x3(b.0, b.1, b.2, a)
58910}
58911#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
58913#[doc = "## Safety"]
58914#[doc = " * Neon instrinsic unsafe"]
58915#[inline]
58916#[target_feature(enable = "neon")]
58917#[cfg(not(target_arch = "arm"))]
58918#[stable(feature = "neon_intrinsics", since = "1.59.0")]
58919#[cfg_attr(test, assert_instr(st1))]
58920pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
58921 unsafe extern "unadjusted" {
58922 #[cfg_attr(
58923 any(target_arch = "aarch64", target_arch = "arm64ec"),
58924 link_name = "llvm.aarch64.neon.st1x3.v2i64.p0i64"
58925 )]
58926 fn _vst1q_s64_x3(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64);
58927 }
58928 _vst1q_s64_x3(b.0, b.1, b.2, a)
58929}
58930#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
58932#[doc = "## Safety"]
58933#[doc = " * Neon instrinsic unsafe"]
58934#[inline]
58935#[target_feature(enable = "neon,v7")]
58936#[cfg(target_arch = "arm")]
58937#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58938#[cfg_attr(test, assert_instr(vst1))]
58939pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
58940 unsafe extern "unadjusted" {
58941 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v8i8.p0")]
58942 fn _vst1_s8_x3(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t);
58943 }
58944 _vst1_s8_x3(a, b.0, b.1, b.2)
58945}
58946#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
58948#[doc = "## Safety"]
58949#[doc = " * Neon instrinsic unsafe"]
58950#[inline]
58951#[target_feature(enable = "neon,v7")]
58952#[cfg(target_arch = "arm")]
58953#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58954#[cfg_attr(test, assert_instr(vst1))]
58955pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
58956 unsafe extern "unadjusted" {
58957 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v16i8.p0")]
58958 fn _vst1q_s8_x3(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t);
58959 }
58960 _vst1q_s8_x3(a, b.0, b.1, b.2)
58961}
58962#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
58964#[doc = "## Safety"]
58965#[doc = " * Neon instrinsic unsafe"]
58966#[inline]
58967#[target_feature(enable = "neon,v7")]
58968#[cfg(target_arch = "arm")]
58969#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58970#[cfg_attr(test, assert_instr(vst1))]
58971pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
58972 unsafe extern "unadjusted" {
58973 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v4i16.p0")]
58974 fn _vst1_s16_x3(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t);
58975 }
58976 _vst1_s16_x3(a, b.0, b.1, b.2)
58977}
58978#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
58980#[doc = "## Safety"]
58981#[doc = " * Neon instrinsic unsafe"]
58982#[inline]
58983#[target_feature(enable = "neon,v7")]
58984#[cfg(target_arch = "arm")]
58985#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
58986#[cfg_attr(test, assert_instr(vst1))]
58987pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
58988 unsafe extern "unadjusted" {
58989 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v8i16.p0")]
58990 fn _vst1q_s16_x3(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t);
58991 }
58992 _vst1q_s16_x3(a, b.0, b.1, b.2)
58993}
58994#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
58995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
58996#[doc = "## Safety"]
58997#[doc = " * Neon instrinsic unsafe"]
58998#[inline]
58999#[target_feature(enable = "neon,v7")]
59000#[cfg(target_arch = "arm")]
59001#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59002#[cfg_attr(test, assert_instr(vst1))]
59003pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
59004 unsafe extern "unadjusted" {
59005 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v2i32.p0")]
59006 fn _vst1_s32_x3(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t);
59007 }
59008 _vst1_s32_x3(a, b.0, b.1, b.2)
59009}
59010#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
59012#[doc = "## Safety"]
59013#[doc = " * Neon instrinsic unsafe"]
59014#[inline]
59015#[target_feature(enable = "neon,v7")]
59016#[cfg(target_arch = "arm")]
59017#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59018#[cfg_attr(test, assert_instr(vst1))]
59019pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
59020 unsafe extern "unadjusted" {
59021 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v4i32.p0")]
59022 fn _vst1q_s32_x3(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t);
59023 }
59024 _vst1q_s32_x3(a, b.0, b.1, b.2)
59025}
59026#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
59028#[doc = "## Safety"]
59029#[doc = " * Neon instrinsic unsafe"]
59030#[inline]
59031#[target_feature(enable = "neon,v7")]
59032#[cfg(target_arch = "arm")]
59033#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59034#[cfg_attr(test, assert_instr(vst1))]
59035pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
59036 unsafe extern "unadjusted" {
59037 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v1i64.p0")]
59038 fn _vst1_s64_x3(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t);
59039 }
59040 _vst1_s64_x3(a, b.0, b.1, b.2)
59041}
59042#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
59044#[doc = "## Safety"]
59045#[doc = " * Neon instrinsic unsafe"]
59046#[inline]
59047#[target_feature(enable = "neon,v7")]
59048#[cfg(target_arch = "arm")]
59049#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59050#[cfg_attr(test, assert_instr(vst1))]
59051pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
59052 unsafe extern "unadjusted" {
59053 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v2i64.p0")]
59054 fn _vst1q_s64_x3(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t);
59055 }
59056 _vst1q_s64_x3(a, b.0, b.1, b.2)
59057}
59058#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
59060#[doc = "## Safety"]
59061#[doc = " * Neon instrinsic unsafe"]
59062#[inline]
59063#[target_feature(enable = "neon")]
59064#[cfg(not(target_arch = "arm"))]
59065#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59066#[cfg_attr(test, assert_instr(st1))]
59067pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
59068 unsafe extern "unadjusted" {
59069 #[cfg_attr(
59070 any(target_arch = "aarch64", target_arch = "arm64ec"),
59071 link_name = "llvm.aarch64.neon.st1x4.v8i8.p0i8"
59072 )]
59073 fn _vst1_s8_x4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
59074 }
59075 _vst1_s8_x4(b.0, b.1, b.2, b.3, a)
59076}
59077#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
59079#[doc = "## Safety"]
59080#[doc = " * Neon instrinsic unsafe"]
59081#[inline]
59082#[target_feature(enable = "neon")]
59083#[cfg(not(target_arch = "arm"))]
59084#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59085#[cfg_attr(test, assert_instr(st1))]
59086pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
59087 unsafe extern "unadjusted" {
59088 #[cfg_attr(
59089 any(target_arch = "aarch64", target_arch = "arm64ec"),
59090 link_name = "llvm.aarch64.neon.st1x4.v16i8.p0i8"
59091 )]
59092 fn _vst1q_s8_x4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
59093 }
59094 _vst1q_s8_x4(b.0, b.1, b.2, b.3, a)
59095}
59096#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
59098#[doc = "## Safety"]
59099#[doc = " * Neon instrinsic unsafe"]
59100#[inline]
59101#[target_feature(enable = "neon")]
59102#[cfg(not(target_arch = "arm"))]
59103#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59104#[cfg_attr(test, assert_instr(st1))]
59105pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
59106 unsafe extern "unadjusted" {
59107 #[cfg_attr(
59108 any(target_arch = "aarch64", target_arch = "arm64ec"),
59109 link_name = "llvm.aarch64.neon.st1x4.v4i16.p0i16"
59110 )]
59111 fn _vst1_s16_x4(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16);
59112 }
59113 _vst1_s16_x4(b.0, b.1, b.2, b.3, a)
59114}
59115#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
59117#[doc = "## Safety"]
59118#[doc = " * Neon instrinsic unsafe"]
59119#[inline]
59120#[target_feature(enable = "neon")]
59121#[cfg(not(target_arch = "arm"))]
59122#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59123#[cfg_attr(test, assert_instr(st1))]
59124pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
59125 unsafe extern "unadjusted" {
59126 #[cfg_attr(
59127 any(target_arch = "aarch64", target_arch = "arm64ec"),
59128 link_name = "llvm.aarch64.neon.st1x4.v8i16.p0i16"
59129 )]
59130 fn _vst1q_s16_x4(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16);
59131 }
59132 _vst1q_s16_x4(b.0, b.1, b.2, b.3, a)
59133}
59134#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
59136#[doc = "## Safety"]
59137#[doc = " * Neon instrinsic unsafe"]
59138#[inline]
59139#[target_feature(enable = "neon")]
59140#[cfg(not(target_arch = "arm"))]
59141#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59142#[cfg_attr(test, assert_instr(st1))]
59143pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
59144 unsafe extern "unadjusted" {
59145 #[cfg_attr(
59146 any(target_arch = "aarch64", target_arch = "arm64ec"),
59147 link_name = "llvm.aarch64.neon.st1x4.v2i32.p0i32"
59148 )]
59149 fn _vst1_s32_x4(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32);
59150 }
59151 _vst1_s32_x4(b.0, b.1, b.2, b.3, a)
59152}
59153#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
59155#[doc = "## Safety"]
59156#[doc = " * Neon instrinsic unsafe"]
59157#[inline]
59158#[target_feature(enable = "neon")]
59159#[cfg(not(target_arch = "arm"))]
59160#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59161#[cfg_attr(test, assert_instr(st1))]
59162pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
59163 unsafe extern "unadjusted" {
59164 #[cfg_attr(
59165 any(target_arch = "aarch64", target_arch = "arm64ec"),
59166 link_name = "llvm.aarch64.neon.st1x4.v4i32.p0i32"
59167 )]
59168 fn _vst1q_s32_x4(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32);
59169 }
59170 _vst1q_s32_x4(b.0, b.1, b.2, b.3, a)
59171}
59172#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
59174#[doc = "## Safety"]
59175#[doc = " * Neon instrinsic unsafe"]
59176#[inline]
59177#[target_feature(enable = "neon")]
59178#[cfg(not(target_arch = "arm"))]
59179#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59180#[cfg_attr(test, assert_instr(st1))]
59181pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
59182 unsafe extern "unadjusted" {
59183 #[cfg_attr(
59184 any(target_arch = "aarch64", target_arch = "arm64ec"),
59185 link_name = "llvm.aarch64.neon.st1x4.v1i64.p0i64"
59186 )]
59187 fn _vst1_s64_x4(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64);
59188 }
59189 _vst1_s64_x4(b.0, b.1, b.2, b.3, a)
59190}
59191#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
59193#[doc = "## Safety"]
59194#[doc = " * Neon instrinsic unsafe"]
59195#[inline]
59196#[target_feature(enable = "neon")]
59197#[cfg(not(target_arch = "arm"))]
59198#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59199#[cfg_attr(test, assert_instr(st1))]
59200pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
59201 unsafe extern "unadjusted" {
59202 #[cfg_attr(
59203 any(target_arch = "aarch64", target_arch = "arm64ec"),
59204 link_name = "llvm.aarch64.neon.st1x4.v2i64.p0i64"
59205 )]
59206 fn _vst1q_s64_x4(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64);
59207 }
59208 _vst1q_s64_x4(b.0, b.1, b.2, b.3, a)
59209}
59210#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
59212#[doc = "## Safety"]
59213#[doc = " * Neon instrinsic unsafe"]
59214#[inline]
59215#[cfg(target_arch = "arm")]
59216#[target_feature(enable = "neon,v7")]
59217#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59218#[cfg_attr(test, assert_instr(vst1))]
59219pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
59220 unsafe extern "unadjusted" {
59221 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v8i8.p0")]
59222 fn _vst1_s8_x4(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t);
59223 }
59224 _vst1_s8_x4(a, b.0, b.1, b.2, b.3)
59225}
59226#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
59228#[doc = "## Safety"]
59229#[doc = " * Neon instrinsic unsafe"]
59230#[inline]
59231#[cfg(target_arch = "arm")]
59232#[target_feature(enable = "neon,v7")]
59233#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59234#[cfg_attr(test, assert_instr(vst1))]
59235pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
59236 unsafe extern "unadjusted" {
59237 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v16i8.p0")]
59238 fn _vst1q_s8_x4(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t);
59239 }
59240 _vst1q_s8_x4(a, b.0, b.1, b.2, b.3)
59241}
59242#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
59244#[doc = "## Safety"]
59245#[doc = " * Neon instrinsic unsafe"]
59246#[inline]
59247#[cfg(target_arch = "arm")]
59248#[target_feature(enable = "neon,v7")]
59249#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59250#[cfg_attr(test, assert_instr(vst1))]
59251pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
59252 unsafe extern "unadjusted" {
59253 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v4i16.p0")]
59254 fn _vst1_s16_x4(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t);
59255 }
59256 _vst1_s16_x4(a, b.0, b.1, b.2, b.3)
59257}
59258#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
59260#[doc = "## Safety"]
59261#[doc = " * Neon instrinsic unsafe"]
59262#[inline]
59263#[cfg(target_arch = "arm")]
59264#[target_feature(enable = "neon,v7")]
59265#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59266#[cfg_attr(test, assert_instr(vst1))]
59267pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
59268 unsafe extern "unadjusted" {
59269 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v8i16.p0")]
59270 fn _vst1q_s16_x4(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t);
59271 }
59272 _vst1q_s16_x4(a, b.0, b.1, b.2, b.3)
59273}
59274#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
59276#[doc = "## Safety"]
59277#[doc = " * Neon instrinsic unsafe"]
59278#[inline]
59279#[cfg(target_arch = "arm")]
59280#[target_feature(enable = "neon,v7")]
59281#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59282#[cfg_attr(test, assert_instr(vst1))]
59283pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
59284 unsafe extern "unadjusted" {
59285 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v2i32.p0")]
59286 fn _vst1_s32_x4(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t);
59287 }
59288 _vst1_s32_x4(a, b.0, b.1, b.2, b.3)
59289}
59290#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
59292#[doc = "## Safety"]
59293#[doc = " * Neon instrinsic unsafe"]
59294#[inline]
59295#[cfg(target_arch = "arm")]
59296#[target_feature(enable = "neon,v7")]
59297#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59298#[cfg_attr(test, assert_instr(vst1))]
59299pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
59300 unsafe extern "unadjusted" {
59301 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v4i32.p0")]
59302 fn _vst1q_s32_x4(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t);
59303 }
59304 _vst1q_s32_x4(a, b.0, b.1, b.2, b.3)
59305}
59306#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
59308#[doc = "## Safety"]
59309#[doc = " * Neon instrinsic unsafe"]
59310#[inline]
59311#[cfg(target_arch = "arm")]
59312#[target_feature(enable = "neon,v7")]
59313#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59314#[cfg_attr(test, assert_instr(vst1))]
59315pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
59316 unsafe extern "unadjusted" {
59317 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v1i64.p0")]
59318 fn _vst1_s64_x4(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t);
59319 }
59320 _vst1_s64_x4(a, b.0, b.1, b.2, b.3)
59321}
59322#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
59323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
59324#[doc = "## Safety"]
59325#[doc = " * Neon instrinsic unsafe"]
59326#[inline]
59327#[cfg(target_arch = "arm")]
59328#[target_feature(enable = "neon,v7")]
59329#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59330#[cfg_attr(test, assert_instr(vst1))]
59331pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
59332 unsafe extern "unadjusted" {
59333 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v2i64.p0")]
59334 fn _vst1q_s64_x4(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t);
59335 }
59336 _vst1q_s64_x4(a, b.0, b.1, b.2, b.3)
59337}
59338#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
59340#[doc = "## Safety"]
59341#[doc = " * Neon instrinsic unsafe"]
59342#[inline]
59343#[target_feature(enable = "neon")]
59344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59346#[cfg_attr(
59347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59348 assert_instr(st1)
59349)]
59350#[cfg_attr(
59351 not(target_arch = "arm"),
59352 stable(feature = "neon_intrinsics", since = "1.59.0")
59353)]
59354#[cfg_attr(
59355 target_arch = "arm",
59356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59357)]
59358pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
59359 vst1_s8_x2(transmute(a), transmute(b))
59360}
59361#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
59363#[doc = "## Safety"]
59364#[doc = " * Neon instrinsic unsafe"]
59365#[inline]
59366#[target_feature(enable = "neon")]
59367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59369#[cfg_attr(
59370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59371 assert_instr(st1)
59372)]
59373#[cfg_attr(
59374 not(target_arch = "arm"),
59375 stable(feature = "neon_intrinsics", since = "1.59.0")
59376)]
59377#[cfg_attr(
59378 target_arch = "arm",
59379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59380)]
59381pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
59382 vst1_s8_x3(transmute(a), transmute(b))
59383}
59384#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
59386#[doc = "## Safety"]
59387#[doc = " * Neon instrinsic unsafe"]
59388#[inline]
59389#[target_feature(enable = "neon")]
59390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59392#[cfg_attr(
59393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59394 assert_instr(st1)
59395)]
59396#[cfg_attr(
59397 not(target_arch = "arm"),
59398 stable(feature = "neon_intrinsics", since = "1.59.0")
59399)]
59400#[cfg_attr(
59401 target_arch = "arm",
59402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59403)]
59404pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
59405 vst1_s8_x4(transmute(a), transmute(b))
59406}
59407#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
59409#[doc = "## Safety"]
59410#[doc = " * Neon instrinsic unsafe"]
59411#[inline]
59412#[target_feature(enable = "neon")]
59413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59415#[cfg_attr(
59416 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59417 assert_instr(st1)
59418)]
59419#[cfg_attr(
59420 not(target_arch = "arm"),
59421 stable(feature = "neon_intrinsics", since = "1.59.0")
59422)]
59423#[cfg_attr(
59424 target_arch = "arm",
59425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59426)]
59427pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
59428 vst1q_s8_x2(transmute(a), transmute(b))
59429}
59430#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
59432#[doc = "## Safety"]
59433#[doc = " * Neon instrinsic unsafe"]
59434#[inline]
59435#[target_feature(enable = "neon")]
59436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59438#[cfg_attr(
59439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59440 assert_instr(st1)
59441)]
59442#[cfg_attr(
59443 not(target_arch = "arm"),
59444 stable(feature = "neon_intrinsics", since = "1.59.0")
59445)]
59446#[cfg_attr(
59447 target_arch = "arm",
59448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59449)]
59450pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
59451 vst1q_s8_x3(transmute(a), transmute(b))
59452}
59453#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
59455#[doc = "## Safety"]
59456#[doc = " * Neon instrinsic unsafe"]
59457#[inline]
59458#[target_feature(enable = "neon")]
59459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59461#[cfg_attr(
59462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59463 assert_instr(st1)
59464)]
59465#[cfg_attr(
59466 not(target_arch = "arm"),
59467 stable(feature = "neon_intrinsics", since = "1.59.0")
59468)]
59469#[cfg_attr(
59470 target_arch = "arm",
59471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59472)]
59473pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
59474 vst1q_s8_x4(transmute(a), transmute(b))
59475}
59476#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
59478#[doc = "## Safety"]
59479#[doc = " * Neon instrinsic unsafe"]
59480#[inline]
59481#[target_feature(enable = "neon")]
59482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59484#[cfg_attr(
59485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59486 assert_instr(st1)
59487)]
59488#[cfg_attr(
59489 not(target_arch = "arm"),
59490 stable(feature = "neon_intrinsics", since = "1.59.0")
59491)]
59492#[cfg_attr(
59493 target_arch = "arm",
59494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59495)]
59496pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
59497 vst1_s16_x2(transmute(a), transmute(b))
59498}
59499#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
59501#[doc = "## Safety"]
59502#[doc = " * Neon instrinsic unsafe"]
59503#[inline]
59504#[target_feature(enable = "neon")]
59505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59507#[cfg_attr(
59508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59509 assert_instr(st1)
59510)]
59511#[cfg_attr(
59512 not(target_arch = "arm"),
59513 stable(feature = "neon_intrinsics", since = "1.59.0")
59514)]
59515#[cfg_attr(
59516 target_arch = "arm",
59517 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59518)]
59519pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
59520 vst1_s16_x3(transmute(a), transmute(b))
59521}
59522#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
59524#[doc = "## Safety"]
59525#[doc = " * Neon instrinsic unsafe"]
59526#[inline]
59527#[target_feature(enable = "neon")]
59528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59530#[cfg_attr(
59531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59532 assert_instr(st1)
59533)]
59534#[cfg_attr(
59535 not(target_arch = "arm"),
59536 stable(feature = "neon_intrinsics", since = "1.59.0")
59537)]
59538#[cfg_attr(
59539 target_arch = "arm",
59540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59541)]
59542pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
59543 vst1_s16_x4(transmute(a), transmute(b))
59544}
59545#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
59547#[doc = "## Safety"]
59548#[doc = " * Neon instrinsic unsafe"]
59549#[inline]
59550#[target_feature(enable = "neon")]
59551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59553#[cfg_attr(
59554 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59555 assert_instr(st1)
59556)]
59557#[cfg_attr(
59558 not(target_arch = "arm"),
59559 stable(feature = "neon_intrinsics", since = "1.59.0")
59560)]
59561#[cfg_attr(
59562 target_arch = "arm",
59563 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59564)]
59565pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
59566 vst1q_s16_x2(transmute(a), transmute(b))
59567}
59568#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
59570#[doc = "## Safety"]
59571#[doc = " * Neon instrinsic unsafe"]
59572#[inline]
59573#[target_feature(enable = "neon")]
59574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59576#[cfg_attr(
59577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59578 assert_instr(st1)
59579)]
59580#[cfg_attr(
59581 not(target_arch = "arm"),
59582 stable(feature = "neon_intrinsics", since = "1.59.0")
59583)]
59584#[cfg_attr(
59585 target_arch = "arm",
59586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59587)]
59588pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
59589 vst1q_s16_x3(transmute(a), transmute(b))
59590}
59591#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
59593#[doc = "## Safety"]
59594#[doc = " * Neon instrinsic unsafe"]
59595#[inline]
59596#[target_feature(enable = "neon")]
59597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59599#[cfg_attr(
59600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59601 assert_instr(st1)
59602)]
59603#[cfg_attr(
59604 not(target_arch = "arm"),
59605 stable(feature = "neon_intrinsics", since = "1.59.0")
59606)]
59607#[cfg_attr(
59608 target_arch = "arm",
59609 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59610)]
59611pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
59612 vst1q_s16_x4(transmute(a), transmute(b))
59613}
59614#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
59616#[doc = "## Safety"]
59617#[doc = " * Neon instrinsic unsafe"]
59618#[inline]
59619#[target_feature(enable = "neon")]
59620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59622#[cfg_attr(
59623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59624 assert_instr(st1)
59625)]
59626#[cfg_attr(
59627 not(target_arch = "arm"),
59628 stable(feature = "neon_intrinsics", since = "1.59.0")
59629)]
59630#[cfg_attr(
59631 target_arch = "arm",
59632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59633)]
59634pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
59635 vst1_s32_x2(transmute(a), transmute(b))
59636}
59637#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
59639#[doc = "## Safety"]
59640#[doc = " * Neon instrinsic unsafe"]
59641#[inline]
59642#[target_feature(enable = "neon")]
59643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59645#[cfg_attr(
59646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59647 assert_instr(st1)
59648)]
59649#[cfg_attr(
59650 not(target_arch = "arm"),
59651 stable(feature = "neon_intrinsics", since = "1.59.0")
59652)]
59653#[cfg_attr(
59654 target_arch = "arm",
59655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59656)]
59657pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
59658 vst1_s32_x3(transmute(a), transmute(b))
59659}
59660#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
59662#[doc = "## Safety"]
59663#[doc = " * Neon instrinsic unsafe"]
59664#[inline]
59665#[target_feature(enable = "neon")]
59666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59668#[cfg_attr(
59669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59670 assert_instr(st1)
59671)]
59672#[cfg_attr(
59673 not(target_arch = "arm"),
59674 stable(feature = "neon_intrinsics", since = "1.59.0")
59675)]
59676#[cfg_attr(
59677 target_arch = "arm",
59678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59679)]
59680pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
59681 vst1_s32_x4(transmute(a), transmute(b))
59682}
59683#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
59685#[doc = "## Safety"]
59686#[doc = " * Neon instrinsic unsafe"]
59687#[inline]
59688#[target_feature(enable = "neon")]
59689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59691#[cfg_attr(
59692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59693 assert_instr(st1)
59694)]
59695#[cfg_attr(
59696 not(target_arch = "arm"),
59697 stable(feature = "neon_intrinsics", since = "1.59.0")
59698)]
59699#[cfg_attr(
59700 target_arch = "arm",
59701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59702)]
59703pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
59704 vst1q_s32_x2(transmute(a), transmute(b))
59705}
59706#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
59708#[doc = "## Safety"]
59709#[doc = " * Neon instrinsic unsafe"]
59710#[inline]
59711#[target_feature(enable = "neon")]
59712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59714#[cfg_attr(
59715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59716 assert_instr(st1)
59717)]
59718#[cfg_attr(
59719 not(target_arch = "arm"),
59720 stable(feature = "neon_intrinsics", since = "1.59.0")
59721)]
59722#[cfg_attr(
59723 target_arch = "arm",
59724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59725)]
59726pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
59727 vst1q_s32_x3(transmute(a), transmute(b))
59728}
59729#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
59731#[doc = "## Safety"]
59732#[doc = " * Neon instrinsic unsafe"]
59733#[inline]
59734#[target_feature(enable = "neon")]
59735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59736#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59737#[cfg_attr(
59738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59739 assert_instr(st1)
59740)]
59741#[cfg_attr(
59742 not(target_arch = "arm"),
59743 stable(feature = "neon_intrinsics", since = "1.59.0")
59744)]
59745#[cfg_attr(
59746 target_arch = "arm",
59747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59748)]
59749pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
59750 vst1q_s32_x4(transmute(a), transmute(b))
59751}
59752#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
59754#[doc = "## Safety"]
59755#[doc = " * Neon instrinsic unsafe"]
59756#[inline]
59757#[target_feature(enable = "neon")]
59758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59760#[cfg_attr(
59761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59762 assert_instr(st1)
59763)]
59764#[cfg_attr(
59765 not(target_arch = "arm"),
59766 stable(feature = "neon_intrinsics", since = "1.59.0")
59767)]
59768#[cfg_attr(
59769 target_arch = "arm",
59770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59771)]
59772pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
59773 vst1_s64_x2(transmute(a), transmute(b))
59774}
59775#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
59777#[doc = "## Safety"]
59778#[doc = " * Neon instrinsic unsafe"]
59779#[inline]
59780#[target_feature(enable = "neon")]
59781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59783#[cfg_attr(
59784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59785 assert_instr(st1)
59786)]
59787#[cfg_attr(
59788 not(target_arch = "arm"),
59789 stable(feature = "neon_intrinsics", since = "1.59.0")
59790)]
59791#[cfg_attr(
59792 target_arch = "arm",
59793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59794)]
59795pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
59796 vst1_s64_x3(transmute(a), transmute(b))
59797}
59798#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
59800#[doc = "## Safety"]
59801#[doc = " * Neon instrinsic unsafe"]
59802#[inline]
59803#[target_feature(enable = "neon")]
59804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59806#[cfg_attr(
59807 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59808 assert_instr(st1)
59809)]
59810#[cfg_attr(
59811 not(target_arch = "arm"),
59812 stable(feature = "neon_intrinsics", since = "1.59.0")
59813)]
59814#[cfg_attr(
59815 target_arch = "arm",
59816 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59817)]
59818pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
59819 vst1_s64_x4(transmute(a), transmute(b))
59820}
59821#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
59823#[doc = "## Safety"]
59824#[doc = " * Neon instrinsic unsafe"]
59825#[inline]
59826#[target_feature(enable = "neon")]
59827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59829#[cfg_attr(
59830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59831 assert_instr(st1)
59832)]
59833#[cfg_attr(
59834 not(target_arch = "arm"),
59835 stable(feature = "neon_intrinsics", since = "1.59.0")
59836)]
59837#[cfg_attr(
59838 target_arch = "arm",
59839 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59840)]
59841pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
59842 vst1q_s64_x2(transmute(a), transmute(b))
59843}
59844#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
59846#[doc = "## Safety"]
59847#[doc = " * Neon instrinsic unsafe"]
59848#[inline]
59849#[target_feature(enable = "neon")]
59850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59852#[cfg_attr(
59853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59854 assert_instr(st1)
59855)]
59856#[cfg_attr(
59857 not(target_arch = "arm"),
59858 stable(feature = "neon_intrinsics", since = "1.59.0")
59859)]
59860#[cfg_attr(
59861 target_arch = "arm",
59862 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59863)]
59864pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
59865 vst1q_s64_x3(transmute(a), transmute(b))
59866}
59867#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
59869#[doc = "## Safety"]
59870#[doc = " * Neon instrinsic unsafe"]
59871#[inline]
59872#[target_feature(enable = "neon")]
59873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59875#[cfg_attr(
59876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59877 assert_instr(st1)
59878)]
59879#[cfg_attr(
59880 not(target_arch = "arm"),
59881 stable(feature = "neon_intrinsics", since = "1.59.0")
59882)]
59883#[cfg_attr(
59884 target_arch = "arm",
59885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59886)]
59887pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
59888 vst1q_s64_x4(transmute(a), transmute(b))
59889}
59890#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
59892#[doc = "## Safety"]
59893#[doc = " * Neon instrinsic unsafe"]
59894#[inline]
59895#[target_feature(enable = "neon")]
59896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59897#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59898#[cfg_attr(
59899 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59900 assert_instr(st1)
59901)]
59902#[cfg_attr(
59903 not(target_arch = "arm"),
59904 stable(feature = "neon_intrinsics", since = "1.59.0")
59905)]
59906#[cfg_attr(
59907 target_arch = "arm",
59908 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59909)]
59910pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
59911 vst1_s8_x2(transmute(a), transmute(b))
59912}
59913#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
59915#[doc = "## Safety"]
59916#[doc = " * Neon instrinsic unsafe"]
59917#[inline]
59918#[target_feature(enable = "neon")]
59919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59921#[cfg_attr(
59922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59923 assert_instr(st1)
59924)]
59925#[cfg_attr(
59926 not(target_arch = "arm"),
59927 stable(feature = "neon_intrinsics", since = "1.59.0")
59928)]
59929#[cfg_attr(
59930 target_arch = "arm",
59931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59932)]
59933pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
59934 vst1_s8_x3(transmute(a), transmute(b))
59935}
59936#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
59938#[doc = "## Safety"]
59939#[doc = " * Neon instrinsic unsafe"]
59940#[inline]
59941#[target_feature(enable = "neon")]
59942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59944#[cfg_attr(
59945 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59946 assert_instr(st1)
59947)]
59948#[cfg_attr(
59949 not(target_arch = "arm"),
59950 stable(feature = "neon_intrinsics", since = "1.59.0")
59951)]
59952#[cfg_attr(
59953 target_arch = "arm",
59954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59955)]
59956pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
59957 vst1_s8_x4(transmute(a), transmute(b))
59958}
59959#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
59961#[doc = "## Safety"]
59962#[doc = " * Neon instrinsic unsafe"]
59963#[inline]
59964#[target_feature(enable = "neon")]
59965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59967#[cfg_attr(
59968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59969 assert_instr(st1)
59970)]
59971#[cfg_attr(
59972 not(target_arch = "arm"),
59973 stable(feature = "neon_intrinsics", since = "1.59.0")
59974)]
59975#[cfg_attr(
59976 target_arch = "arm",
59977 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59978)]
59979pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
59980 vst1q_s8_x2(transmute(a), transmute(b))
59981}
59982#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
59983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
59984#[doc = "## Safety"]
59985#[doc = " * Neon instrinsic unsafe"]
59986#[inline]
59987#[target_feature(enable = "neon")]
59988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
59990#[cfg_attr(
59991 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59992 assert_instr(st1)
59993)]
59994#[cfg_attr(
59995 not(target_arch = "arm"),
59996 stable(feature = "neon_intrinsics", since = "1.59.0")
59997)]
59998#[cfg_attr(
59999 target_arch = "arm",
60000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60001)]
60002pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
60003 vst1q_s8_x3(transmute(a), transmute(b))
60004}
60005#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
60007#[doc = "## Safety"]
60008#[doc = " * Neon instrinsic unsafe"]
60009#[inline]
60010#[target_feature(enable = "neon")]
60011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60013#[cfg_attr(
60014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60015 assert_instr(st1)
60016)]
60017#[cfg_attr(
60018 not(target_arch = "arm"),
60019 stable(feature = "neon_intrinsics", since = "1.59.0")
60020)]
60021#[cfg_attr(
60022 target_arch = "arm",
60023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60024)]
60025pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
60026 vst1q_s8_x4(transmute(a), transmute(b))
60027}
60028#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
60030#[doc = "## Safety"]
60031#[doc = " * Neon instrinsic unsafe"]
60032#[inline]
60033#[target_feature(enable = "neon")]
60034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60036#[cfg_attr(
60037 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60038 assert_instr(st1)
60039)]
60040#[cfg_attr(
60041 not(target_arch = "arm"),
60042 stable(feature = "neon_intrinsics", since = "1.59.0")
60043)]
60044#[cfg_attr(
60045 target_arch = "arm",
60046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60047)]
60048pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
60049 vst1_s16_x2(transmute(a), transmute(b))
60050}
60051#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
60053#[doc = "## Safety"]
60054#[doc = " * Neon instrinsic unsafe"]
60055#[inline]
60056#[target_feature(enable = "neon")]
60057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60058#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60059#[cfg_attr(
60060 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60061 assert_instr(st1)
60062)]
60063#[cfg_attr(
60064 not(target_arch = "arm"),
60065 stable(feature = "neon_intrinsics", since = "1.59.0")
60066)]
60067#[cfg_attr(
60068 target_arch = "arm",
60069 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60070)]
60071pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
60072 vst1_s16_x3(transmute(a), transmute(b))
60073}
60074#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
60076#[doc = "## Safety"]
60077#[doc = " * Neon instrinsic unsafe"]
60078#[inline]
60079#[target_feature(enable = "neon")]
60080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60082#[cfg_attr(
60083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60084 assert_instr(st1)
60085)]
60086#[cfg_attr(
60087 not(target_arch = "arm"),
60088 stable(feature = "neon_intrinsics", since = "1.59.0")
60089)]
60090#[cfg_attr(
60091 target_arch = "arm",
60092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60093)]
60094pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
60095 vst1_s16_x4(transmute(a), transmute(b))
60096}
60097#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
60099#[doc = "## Safety"]
60100#[doc = " * Neon instrinsic unsafe"]
60101#[inline]
60102#[target_feature(enable = "neon")]
60103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60105#[cfg_attr(
60106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60107 assert_instr(st1)
60108)]
60109#[cfg_attr(
60110 not(target_arch = "arm"),
60111 stable(feature = "neon_intrinsics", since = "1.59.0")
60112)]
60113#[cfg_attr(
60114 target_arch = "arm",
60115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60116)]
60117pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
60118 vst1q_s16_x2(transmute(a), transmute(b))
60119}
60120#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
60122#[doc = "## Safety"]
60123#[doc = " * Neon instrinsic unsafe"]
60124#[inline]
60125#[target_feature(enable = "neon")]
60126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60128#[cfg_attr(
60129 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60130 assert_instr(st1)
60131)]
60132#[cfg_attr(
60133 not(target_arch = "arm"),
60134 stable(feature = "neon_intrinsics", since = "1.59.0")
60135)]
60136#[cfg_attr(
60137 target_arch = "arm",
60138 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60139)]
60140pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
60141 vst1q_s16_x3(transmute(a), transmute(b))
60142}
60143#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
60144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
60145#[doc = "## Safety"]
60146#[doc = " * Neon instrinsic unsafe"]
60147#[inline]
60148#[target_feature(enable = "neon")]
60149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
60151#[cfg_attr(
60152 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60153 assert_instr(st1)
60154)]
60155#[cfg_attr(
60156 not(target_arch = "arm"),
60157 stable(feature = "neon_intrinsics", since = "1.59.0")
60158)]
60159#[cfg_attr(
60160 target_arch = "arm",
60161 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60162)]
60163pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
60164 vst1q_s16_x4(transmute(a), transmute(b))
60165}
60166#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v1i64)"]
60168#[doc = "## Safety"]
60169#[doc = " * Neon instrinsic unsafe"]
60170#[inline]
60171#[target_feature(enable = "neon")]
60172#[cfg(target_arch = "arm")]
60173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60174#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60175#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
60176unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32) {
60177 unsafe extern "unadjusted" {
60178 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v1i64.p0")]
60179 fn _vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32);
60180 }
60181 _vst1_v1i64(addr, val, align)
60182}
60183#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2f32)"]
60185#[doc = "## Safety"]
60186#[doc = " * Neon instrinsic unsafe"]
60187#[inline]
60188#[target_feature(enable = "neon")]
60189#[cfg(target_arch = "arm")]
60190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60191#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
60193unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32) {
60194 unsafe extern "unadjusted" {
60195 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2f32.p0")]
60196 fn _vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32);
60197 }
60198 _vst1_v2f32(addr, val, align)
60199}
60200#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2i32)"]
60202#[doc = "## Safety"]
60203#[doc = " * Neon instrinsic unsafe"]
60204#[inline]
60205#[target_feature(enable = "neon")]
60206#[cfg(target_arch = "arm")]
60207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60208#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
60210unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32) {
60211 unsafe extern "unadjusted" {
60212 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i32.p0")]
60213 fn _vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32);
60214 }
60215 _vst1_v2i32(addr, val, align)
60216}
60217#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4i16)"]
60219#[doc = "## Safety"]
60220#[doc = " * Neon instrinsic unsafe"]
60221#[inline]
60222#[target_feature(enable = "neon")]
60223#[cfg(target_arch = "arm")]
60224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60225#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
60227unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32) {
60228 unsafe extern "unadjusted" {
60229 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i16.p0")]
60230 fn _vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32);
60231 }
60232 _vst1_v4i16(addr, val, align)
60233}
60234#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v8i8)"]
60236#[doc = "## Safety"]
60237#[doc = " * Neon instrinsic unsafe"]
60238#[inline]
60239#[target_feature(enable = "neon")]
60240#[cfg(target_arch = "arm")]
60241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60242#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60243#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
60244unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32) {
60245 unsafe extern "unadjusted" {
60246 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i8.p0")]
60247 fn _vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32);
60248 }
60249 _vst1_v8i8(addr, val, align)
60250}
60251#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v16i8)"]
60253#[doc = "## Safety"]
60254#[doc = " * Neon instrinsic unsafe"]
60255#[inline]
60256#[target_feature(enable = "neon")]
60257#[cfg(target_arch = "arm")]
60258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60259#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60260#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
60261unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32) {
60262 unsafe extern "unadjusted" {
60263 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v16i8.p0")]
60264 fn _vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32);
60265 }
60266 _vst1q_v16i8(addr, val, align)
60267}
60268#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v2i64)"]
60270#[doc = "## Safety"]
60271#[doc = " * Neon instrinsic unsafe"]
60272#[inline]
60273#[target_feature(enable = "neon")]
60274#[cfg(target_arch = "arm")]
60275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60276#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60277#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
60278unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32) {
60279 unsafe extern "unadjusted" {
60280 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i64.p0")]
60281 fn _vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32);
60282 }
60283 _vst1q_v2i64(addr, val, align)
60284}
60285#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4f32)"]
60287#[doc = "## Safety"]
60288#[doc = " * Neon instrinsic unsafe"]
60289#[inline]
60290#[target_feature(enable = "neon")]
60291#[cfg(target_arch = "arm")]
60292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60293#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60294#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
60295unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32) {
60296 unsafe extern "unadjusted" {
60297 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f32.p0")]
60298 fn _vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32);
60299 }
60300 _vst1q_v4f32(addr, val, align)
60301}
60302#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4i32)"]
60304#[doc = "## Safety"]
60305#[doc = " * Neon instrinsic unsafe"]
60306#[inline]
60307#[target_feature(enable = "neon")]
60308#[cfg(target_arch = "arm")]
60309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60310#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
60312unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32) {
60313 unsafe extern "unadjusted" {
60314 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i32.p0")]
60315 fn _vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32);
60316 }
60317 _vst1q_v4i32(addr, val, align)
60318}
60319#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8i16)"]
60321#[doc = "## Safety"]
60322#[doc = " * Neon instrinsic unsafe"]
60323#[inline]
60324#[target_feature(enable = "neon")]
60325#[cfg(target_arch = "arm")]
60326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60327#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60328#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
60329unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32) {
60330 unsafe extern "unadjusted" {
60331 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i16.p0")]
60332 fn _vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32);
60333 }
60334 _vst1q_v8i16(addr, val, align)
60335}
60336#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
60338#[doc = "## Safety"]
60339#[doc = " * Neon instrinsic unsafe"]
60340#[inline]
60341#[cfg(target_arch = "arm")]
60342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60343#[target_feature(enable = "neon,fp16")]
60344#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60345#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
60346unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
60347 unsafe extern "unadjusted" {
60348 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f16.p0")]
60349 fn _vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32);
60350 }
60351 _vst1_v4f16(addr, val, align)
60352}
60353#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
60354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
60355#[doc = "## Safety"]
60356#[doc = " * Neon instrinsic unsafe"]
60357#[inline]
60358#[cfg(target_arch = "arm")]
60359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60360#[target_feature(enable = "neon,fp16")]
60361#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60362#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
60363unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
60364 unsafe extern "unadjusted" {
60365 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8f16.p0")]
60366 fn _vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32);
60367 }
60368 _vst1q_v8f16(addr, val, align)
60369}
60370#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
60371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
60372#[doc = "## Safety"]
60373#[doc = " * Neon instrinsic unsafe"]
60374#[inline]
60375#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60376#[target_feature(enable = "neon,aes")]
60377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60378#[cfg_attr(
60379 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60380 assert_instr(nop, LANE = 0)
60381)]
60382#[rustc_legacy_const_generics(2)]
60383#[cfg_attr(
60384 not(target_arch = "arm"),
60385 stable(feature = "neon_intrinsics", since = "1.59.0")
60386)]
60387#[cfg_attr(
60388 target_arch = "arm",
60389 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60390)]
60391pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
60392 static_assert_uimm_bits!(LANE, 1);
60393 *a = simd_extract!(b, LANE as u32);
60394}
60395#[doc = "Store multiple 2-element structures from two registers"]
60396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
60397#[doc = "## Safety"]
60398#[doc = " * Neon instrinsic unsafe"]
60399#[inline]
60400#[cfg(not(target_arch = "arm"))]
60401#[target_feature(enable = "neon,fp16")]
60402#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60403#[cfg_attr(test, assert_instr(st2))]
60404pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
60405 unsafe extern "unadjusted" {
60406 #[cfg_attr(
60407 any(target_arch = "aarch64", target_arch = "arm64ec"),
60408 link_name = "llvm.aarch64.neon.st2.v4f16.p0i8"
60409 )]
60410 fn _vst2_f16(a: float16x4_t, b: float16x4_t, ptr: *mut i8);
60411 }
60412 _vst2_f16(b.0, b.1, a as _)
60413}
60414#[doc = "Store multiple 2-element structures from two registers"]
60415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
60416#[doc = "## Safety"]
60417#[doc = " * Neon instrinsic unsafe"]
60418#[inline]
60419#[cfg(not(target_arch = "arm"))]
60420#[target_feature(enable = "neon,fp16")]
60421#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60422#[cfg_attr(test, assert_instr(st2))]
60423pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
60424 unsafe extern "unadjusted" {
60425 #[cfg_attr(
60426 any(target_arch = "aarch64", target_arch = "arm64ec"),
60427 link_name = "llvm.aarch64.neon.st2.v8f16.p0i8"
60428 )]
60429 fn _vst2q_f16(a: float16x8_t, b: float16x8_t, ptr: *mut i8);
60430 }
60431 _vst2q_f16(b.0, b.1, a as _)
60432}
60433#[doc = "Store multiple 2-element structures from two registers"]
60434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
60435#[doc = "## Safety"]
60436#[doc = " * Neon instrinsic unsafe"]
60437#[inline]
60438#[cfg(target_arch = "arm")]
60439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60440#[target_feature(enable = "neon,fp16")]
60441#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60442#[cfg_attr(test, assert_instr(vst2))]
60443pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
60444 unsafe extern "unadjusted" {
60445 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4f16")]
60446 fn _vst2_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, size: i32);
60447 }
60448 _vst2_f16(a as _, b.0, b.1, 2)
60449}
60450#[doc = "Store multiple 2-element structures from two registers"]
60451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
60452#[doc = "## Safety"]
60453#[doc = " * Neon instrinsic unsafe"]
60454#[inline]
60455#[cfg(target_arch = "arm")]
60456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60457#[target_feature(enable = "neon,fp16")]
60458#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60459#[cfg_attr(test, assert_instr(vst2))]
60460pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
60461 unsafe extern "unadjusted" {
60462 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8f16")]
60463 fn _vst2q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, size: i32);
60464 }
60465 _vst2q_f16(a as _, b.0, b.1, 2)
60466}
60467#[doc = "Store multiple 2-element structures from two registers"]
60468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
60469#[doc = "## Safety"]
60470#[doc = " * Neon instrinsic unsafe"]
60471#[inline]
60472#[target_feature(enable = "neon")]
60473#[cfg(not(target_arch = "arm"))]
60474#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60475#[cfg_attr(test, assert_instr(st2))]
60476pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
60477 unsafe extern "unadjusted" {
60478 #[cfg_attr(
60479 any(target_arch = "aarch64", target_arch = "arm64ec"),
60480 link_name = "llvm.aarch64.neon.st2.v2f32.p0i8"
60481 )]
60482 fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8);
60483 }
60484 _vst2_f32(b.0, b.1, a as _)
60485}
60486#[doc = "Store multiple 2-element structures from two registers"]
60487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
60488#[doc = "## Safety"]
60489#[doc = " * Neon instrinsic unsafe"]
60490#[inline]
60491#[target_feature(enable = "neon")]
60492#[cfg(not(target_arch = "arm"))]
60493#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60494#[cfg_attr(test, assert_instr(st2))]
60495pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
60496 unsafe extern "unadjusted" {
60497 #[cfg_attr(
60498 any(target_arch = "aarch64", target_arch = "arm64ec"),
60499 link_name = "llvm.aarch64.neon.st2.v4f32.p0i8"
60500 )]
60501 fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8);
60502 }
60503 _vst2q_f32(b.0, b.1, a as _)
60504}
60505#[doc = "Store multiple 2-element structures from two registers"]
60506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
60507#[doc = "## Safety"]
60508#[doc = " * Neon instrinsic unsafe"]
60509#[inline]
60510#[target_feature(enable = "neon")]
60511#[cfg(not(target_arch = "arm"))]
60512#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60513#[cfg_attr(test, assert_instr(st2))]
60514pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
60515 unsafe extern "unadjusted" {
60516 #[cfg_attr(
60517 any(target_arch = "aarch64", target_arch = "arm64ec"),
60518 link_name = "llvm.aarch64.neon.st2.v8i8.p0i8"
60519 )]
60520 fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
60521 }
60522 _vst2_s8(b.0, b.1, a as _)
60523}
60524#[doc = "Store multiple 2-element structures from two registers"]
60525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
60526#[doc = "## Safety"]
60527#[doc = " * Neon instrinsic unsafe"]
60528#[inline]
60529#[target_feature(enable = "neon")]
60530#[cfg(not(target_arch = "arm"))]
60531#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60532#[cfg_attr(test, assert_instr(st2))]
60533pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
60534 unsafe extern "unadjusted" {
60535 #[cfg_attr(
60536 any(target_arch = "aarch64", target_arch = "arm64ec"),
60537 link_name = "llvm.aarch64.neon.st2.v16i8.p0i8"
60538 )]
60539 fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
60540 }
60541 _vst2q_s8(b.0, b.1, a as _)
60542}
60543#[doc = "Store multiple 2-element structures from two registers"]
60544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
60545#[doc = "## Safety"]
60546#[doc = " * Neon instrinsic unsafe"]
60547#[inline]
60548#[target_feature(enable = "neon")]
60549#[cfg(not(target_arch = "arm"))]
60550#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60551#[cfg_attr(test, assert_instr(st2))]
60552pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
60553 unsafe extern "unadjusted" {
60554 #[cfg_attr(
60555 any(target_arch = "aarch64", target_arch = "arm64ec"),
60556 link_name = "llvm.aarch64.neon.st2.v4i16.p0i8"
60557 )]
60558 fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8);
60559 }
60560 _vst2_s16(b.0, b.1, a as _)
60561}
60562#[doc = "Store multiple 2-element structures from two registers"]
60563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
60564#[doc = "## Safety"]
60565#[doc = " * Neon instrinsic unsafe"]
60566#[inline]
60567#[target_feature(enable = "neon")]
60568#[cfg(not(target_arch = "arm"))]
60569#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60570#[cfg_attr(test, assert_instr(st2))]
60571pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
60572 unsafe extern "unadjusted" {
60573 #[cfg_attr(
60574 any(target_arch = "aarch64", target_arch = "arm64ec"),
60575 link_name = "llvm.aarch64.neon.st2.v8i16.p0i8"
60576 )]
60577 fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8);
60578 }
60579 _vst2q_s16(b.0, b.1, a as _)
60580}
60581#[doc = "Store multiple 2-element structures from two registers"]
60582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
60583#[doc = "## Safety"]
60584#[doc = " * Neon instrinsic unsafe"]
60585#[inline]
60586#[target_feature(enable = "neon")]
60587#[cfg(not(target_arch = "arm"))]
60588#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60589#[cfg_attr(test, assert_instr(st2))]
60590pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
60591 unsafe extern "unadjusted" {
60592 #[cfg_attr(
60593 any(target_arch = "aarch64", target_arch = "arm64ec"),
60594 link_name = "llvm.aarch64.neon.st2.v2i32.p0i8"
60595 )]
60596 fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8);
60597 }
60598 _vst2_s32(b.0, b.1, a as _)
60599}
60600#[doc = "Store multiple 2-element structures from two registers"]
60601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
60602#[doc = "## Safety"]
60603#[doc = " * Neon instrinsic unsafe"]
60604#[inline]
60605#[target_feature(enable = "neon")]
60606#[cfg(not(target_arch = "arm"))]
60607#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60608#[cfg_attr(test, assert_instr(st2))]
60609pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
60610 unsafe extern "unadjusted" {
60611 #[cfg_attr(
60612 any(target_arch = "aarch64", target_arch = "arm64ec"),
60613 link_name = "llvm.aarch64.neon.st2.v4i32.p0i8"
60614 )]
60615 fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8);
60616 }
60617 _vst2q_s32(b.0, b.1, a as _)
60618}
60619#[doc = "Store multiple 2-element structures from two registers"]
60620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
60621#[doc = "## Safety"]
60622#[doc = " * Neon instrinsic unsafe"]
60623#[inline]
60624#[cfg(target_arch = "arm")]
60625#[target_feature(enable = "neon,v7")]
60626#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60627#[cfg_attr(test, assert_instr(vst2))]
60628pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
60629 unsafe extern "unadjusted" {
60630 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2f32.p0")]
60631 fn _vst2_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32);
60632 }
60633 _vst2_f32(a as _, b.0, b.1, 4)
60634}
60635#[doc = "Store multiple 2-element structures from two registers"]
60636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
60637#[doc = "## Safety"]
60638#[doc = " * Neon instrinsic unsafe"]
60639#[inline]
60640#[cfg(target_arch = "arm")]
60641#[target_feature(enable = "neon,v7")]
60642#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60643#[cfg_attr(test, assert_instr(vst2))]
60644pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
60645 unsafe extern "unadjusted" {
60646 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4f32.p0")]
60647 fn _vst2q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32);
60648 }
60649 _vst2q_f32(a as _, b.0, b.1, 4)
60650}
60651#[doc = "Store multiple 2-element structures from two registers"]
60652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
60653#[doc = "## Safety"]
60654#[doc = " * Neon instrinsic unsafe"]
60655#[inline]
60656#[cfg(target_arch = "arm")]
60657#[target_feature(enable = "neon,v7")]
60658#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60659#[cfg_attr(test, assert_instr(vst2))]
60660pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
60661 unsafe extern "unadjusted" {
60662 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i8.p0")]
60663 fn _vst2_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32);
60664 }
60665 _vst2_s8(a as _, b.0, b.1, 1)
60666}
60667#[doc = "Store multiple 2-element structures from two registers"]
60668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
60669#[doc = "## Safety"]
60670#[doc = " * Neon instrinsic unsafe"]
60671#[inline]
60672#[cfg(target_arch = "arm")]
60673#[target_feature(enable = "neon,v7")]
60674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60675#[cfg_attr(test, assert_instr(vst2))]
60676pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
60677 unsafe extern "unadjusted" {
60678 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v16i8.p0")]
60679 fn _vst2q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32);
60680 }
60681 _vst2q_s8(a as _, b.0, b.1, 1)
60682}
60683#[doc = "Store multiple 2-element structures from two registers"]
60684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
60685#[doc = "## Safety"]
60686#[doc = " * Neon instrinsic unsafe"]
60687#[inline]
60688#[cfg(target_arch = "arm")]
60689#[target_feature(enable = "neon,v7")]
60690#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60691#[cfg_attr(test, assert_instr(vst2))]
60692pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
60693 unsafe extern "unadjusted" {
60694 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i16.p0")]
60695 fn _vst2_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32);
60696 }
60697 _vst2_s16(a as _, b.0, b.1, 2)
60698}
60699#[doc = "Store multiple 2-element structures from two registers"]
60700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
60701#[doc = "## Safety"]
60702#[doc = " * Neon instrinsic unsafe"]
60703#[inline]
60704#[cfg(target_arch = "arm")]
60705#[target_feature(enable = "neon,v7")]
60706#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60707#[cfg_attr(test, assert_instr(vst2))]
60708pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
60709 unsafe extern "unadjusted" {
60710 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i16.p0")]
60711 fn _vst2q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32);
60712 }
60713 _vst2q_s16(a as _, b.0, b.1, 2)
60714}
60715#[doc = "Store multiple 2-element structures from two registers"]
60716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
60717#[doc = "## Safety"]
60718#[doc = " * Neon instrinsic unsafe"]
60719#[inline]
60720#[cfg(target_arch = "arm")]
60721#[target_feature(enable = "neon,v7")]
60722#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60723#[cfg_attr(test, assert_instr(vst2))]
60724pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
60725 unsafe extern "unadjusted" {
60726 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2i32.p0")]
60727 fn _vst2_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32);
60728 }
60729 _vst2_s32(a as _, b.0, b.1, 4)
60730}
60731#[doc = "Store multiple 2-element structures from two registers"]
60732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
60733#[doc = "## Safety"]
60734#[doc = " * Neon instrinsic unsafe"]
60735#[inline]
60736#[cfg(target_arch = "arm")]
60737#[target_feature(enable = "neon,v7")]
60738#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60739#[cfg_attr(test, assert_instr(vst2))]
60740pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
60741 unsafe extern "unadjusted" {
60742 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i32.p0")]
60743 fn _vst2q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32);
60744 }
60745 _vst2q_s32(a as _, b.0, b.1, 4)
60746}
60747#[doc = "Store multiple 2-element structures from two registers"]
60748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
60749#[doc = "## Safety"]
60750#[doc = " * Neon instrinsic unsafe"]
60751#[inline]
60752#[cfg(not(target_arch = "arm"))]
60753#[rustc_legacy_const_generics(2)]
60754#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60755#[target_feature(enable = "neon,fp16")]
60756#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60757pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
60758 static_assert_uimm_bits!(LANE, 2);
60759 unsafe extern "unadjusted" {
60760 #[cfg_attr(
60761 any(target_arch = "aarch64", target_arch = "arm64ec"),
60762 link_name = "llvm.aarch64.neon.st2lane.v4f16.p0i8"
60763 )]
60764 fn _vst2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *mut i8);
60765 }
60766 _vst2_lane_f16(b.0, b.1, LANE as i64, a as _)
60767}
60768#[doc = "Store multiple 2-element structures from two registers"]
60769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
60770#[doc = "## Safety"]
60771#[doc = " * Neon instrinsic unsafe"]
60772#[inline]
60773#[cfg(not(target_arch = "arm"))]
60774#[rustc_legacy_const_generics(2)]
60775#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60776#[target_feature(enable = "neon,fp16")]
60777#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60778pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
60779 static_assert_uimm_bits!(LANE, 3);
60780 unsafe extern "unadjusted" {
60781 #[cfg_attr(
60782 any(target_arch = "aarch64", target_arch = "arm64ec"),
60783 link_name = "llvm.aarch64.neon.st2lane.v8f16.p0i8"
60784 )]
60785 fn _vst2q_lane_f16(a: float16x8_t, b: float16x8_t, n: i64, ptr: *mut i8);
60786 }
60787 _vst2q_lane_f16(b.0, b.1, LANE as i64, a as _)
60788}
60789#[doc = "Store multiple 2-element structures from two registers"]
60790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
60791#[doc = "## Safety"]
60792#[doc = " * Neon instrinsic unsafe"]
60793#[inline]
60794#[cfg(target_arch = "arm")]
60795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60796#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
60797#[rustc_legacy_const_generics(2)]
60798#[target_feature(enable = "neon,fp16")]
60799#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60800pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
60801 static_assert_uimm_bits!(LANE, 2);
60802 unsafe extern "unadjusted" {
60803 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f16")]
60804 fn _vst2_lane_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, n: i32, size: i32);
60805 }
60806 _vst2_lane_f16(a as _, b.0, b.1, LANE, 2)
60807}
60808#[doc = "Store multiple 2-element structures from two registers"]
60809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
60810#[doc = "## Safety"]
60811#[doc = " * Neon instrinsic unsafe"]
60812#[inline]
60813#[cfg(target_arch = "arm")]
60814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60815#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
60816#[rustc_legacy_const_generics(2)]
60817#[target_feature(enable = "neon,fp16")]
60818#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60819pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
60820 static_assert_uimm_bits!(LANE, 1);
60821 unsafe extern "unadjusted" {
60822 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8f16")]
60823 fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32);
60824 }
60825 _vst2q_lane_f16(a as _, b.0, b.1, LANE, 2)
60826}
60827#[doc = "Store multiple 2-element structures from two registers"]
60828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
60829#[doc = "## Safety"]
60830#[doc = " * Neon instrinsic unsafe"]
60831#[inline]
60832#[target_feature(enable = "neon")]
60833#[cfg(not(target_arch = "arm"))]
60834#[rustc_legacy_const_generics(2)]
60835#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60837pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
60838 static_assert_uimm_bits!(LANE, 1);
60839 unsafe extern "unadjusted" {
60840 #[cfg_attr(
60841 any(target_arch = "aarch64", target_arch = "arm64ec"),
60842 link_name = "llvm.aarch64.neon.st2lane.v2f32.p0i8"
60843 )]
60844 fn _vst2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8);
60845 }
60846 _vst2_lane_f32(b.0, b.1, LANE as i64, a as _)
60847}
60848#[doc = "Store multiple 2-element structures from two registers"]
60849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
60850#[doc = "## Safety"]
60851#[doc = " * Neon instrinsic unsafe"]
60852#[inline]
60853#[target_feature(enable = "neon")]
60854#[cfg(not(target_arch = "arm"))]
60855#[rustc_legacy_const_generics(2)]
60856#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60857#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60858pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
60859 static_assert_uimm_bits!(LANE, 2);
60860 unsafe extern "unadjusted" {
60861 #[cfg_attr(
60862 any(target_arch = "aarch64", target_arch = "arm64ec"),
60863 link_name = "llvm.aarch64.neon.st2lane.v4f32.p0i8"
60864 )]
60865 fn _vst2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8);
60866 }
60867 _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _)
60868}
60869#[doc = "Store multiple 2-element structures from two registers"]
60870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
60871#[doc = "## Safety"]
60872#[doc = " * Neon instrinsic unsafe"]
60873#[inline]
60874#[target_feature(enable = "neon")]
60875#[cfg(not(target_arch = "arm"))]
60876#[rustc_legacy_const_generics(2)]
60877#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60878#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60879pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
60880 static_assert_uimm_bits!(LANE, 3);
60881 unsafe extern "unadjusted" {
60882 #[cfg_attr(
60883 any(target_arch = "aarch64", target_arch = "arm64ec"),
60884 link_name = "llvm.aarch64.neon.st2lane.v8i8.p0i8"
60885 )]
60886 fn _vst2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8);
60887 }
60888 _vst2_lane_s8(b.0, b.1, LANE as i64, a as _)
60889}
60890#[doc = "Store multiple 2-element structures from two registers"]
60891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
60892#[doc = "## Safety"]
60893#[doc = " * Neon instrinsic unsafe"]
60894#[inline]
60895#[target_feature(enable = "neon")]
60896#[cfg(not(target_arch = "arm"))]
60897#[rustc_legacy_const_generics(2)]
60898#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60899#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60900pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
60901 static_assert_uimm_bits!(LANE, 2);
60902 unsafe extern "unadjusted" {
60903 #[cfg_attr(
60904 any(target_arch = "aarch64", target_arch = "arm64ec"),
60905 link_name = "llvm.aarch64.neon.st2lane.v4i16.p0i8"
60906 )]
60907 fn _vst2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8);
60908 }
60909 _vst2_lane_s16(b.0, b.1, LANE as i64, a as _)
60910}
60911#[doc = "Store multiple 2-element structures from two registers"]
60912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
60913#[doc = "## Safety"]
60914#[doc = " * Neon instrinsic unsafe"]
60915#[inline]
60916#[target_feature(enable = "neon")]
60917#[cfg(not(target_arch = "arm"))]
60918#[rustc_legacy_const_generics(2)]
60919#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60920#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60921pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
60922 static_assert_uimm_bits!(LANE, 3);
60923 unsafe extern "unadjusted" {
60924 #[cfg_attr(
60925 any(target_arch = "aarch64", target_arch = "arm64ec"),
60926 link_name = "llvm.aarch64.neon.st2lane.v8i16.p0i8"
60927 )]
60928 fn _vst2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8);
60929 }
60930 _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _)
60931}
60932#[doc = "Store multiple 2-element structures from two registers"]
60933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
60934#[doc = "## Safety"]
60935#[doc = " * Neon instrinsic unsafe"]
60936#[inline]
60937#[target_feature(enable = "neon")]
60938#[cfg(not(target_arch = "arm"))]
60939#[rustc_legacy_const_generics(2)]
60940#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60941#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60942pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
60943 static_assert_uimm_bits!(LANE, 1);
60944 unsafe extern "unadjusted" {
60945 #[cfg_attr(
60946 any(target_arch = "aarch64", target_arch = "arm64ec"),
60947 link_name = "llvm.aarch64.neon.st2lane.v2i32.p0i8"
60948 )]
60949 fn _vst2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8);
60950 }
60951 _vst2_lane_s32(b.0, b.1, LANE as i64, a as _)
60952}
60953#[doc = "Store multiple 2-element structures from two registers"]
60954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
60955#[doc = "## Safety"]
60956#[doc = " * Neon instrinsic unsafe"]
60957#[inline]
60958#[target_feature(enable = "neon")]
60959#[cfg(not(target_arch = "arm"))]
60960#[rustc_legacy_const_generics(2)]
60961#[cfg_attr(test, assert_instr(st2, LANE = 0))]
60962#[stable(feature = "neon_intrinsics", since = "1.59.0")]
60963pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
60964 static_assert_uimm_bits!(LANE, 2);
60965 unsafe extern "unadjusted" {
60966 #[cfg_attr(
60967 any(target_arch = "aarch64", target_arch = "arm64ec"),
60968 link_name = "llvm.aarch64.neon.st2lane.v4i32.p0i8"
60969 )]
60970 fn _vst2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8);
60971 }
60972 _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _)
60973}
60974#[doc = "Store multiple 2-element structures from two registers"]
60975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
60976#[doc = "## Safety"]
60977#[doc = " * Neon instrinsic unsafe"]
60978#[inline]
60979#[cfg(target_arch = "arm")]
60980#[target_feature(enable = "neon,v7")]
60981#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
60982#[rustc_legacy_const_generics(2)]
60983#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
60984pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
60985 static_assert_uimm_bits!(LANE, 1);
60986 unsafe extern "unadjusted" {
60987 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2f32.p0")]
60988 fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32);
60989 }
60990 _vst2_lane_f32(a as _, b.0, b.1, LANE, 4)
60991}
60992#[doc = "Store multiple 2-element structures from two registers"]
60993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
60994#[doc = "## Safety"]
60995#[doc = " * Neon instrinsic unsafe"]
60996#[inline]
60997#[cfg(target_arch = "arm")]
60998#[target_feature(enable = "neon,v7")]
60999#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
61000#[rustc_legacy_const_generics(2)]
61001#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61002pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
61003 static_assert_uimm_bits!(LANE, 2);
61004 unsafe extern "unadjusted" {
61005 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4f32.p0")]
61006 fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32);
61007 }
61008 _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4)
61009}
61010#[doc = "Store multiple 2-element structures from two registers"]
61011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
61012#[doc = "## Safety"]
61013#[doc = " * Neon instrinsic unsafe"]
61014#[inline]
61015#[cfg(target_arch = "arm")]
61016#[target_feature(enable = "neon,v7")]
61017#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
61018#[rustc_legacy_const_generics(2)]
61019#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61020pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
61021 static_assert_uimm_bits!(LANE, 3);
61022 unsafe extern "unadjusted" {
61023 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i8.p0")]
61024 fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32);
61025 }
61026 _vst2_lane_s8(a as _, b.0, b.1, LANE, 1)
61027}
61028#[doc = "Store multiple 2-element structures from two registers"]
61029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
61030#[doc = "## Safety"]
61031#[doc = " * Neon instrinsic unsafe"]
61032#[inline]
61033#[cfg(target_arch = "arm")]
61034#[target_feature(enable = "neon,v7")]
61035#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
61036#[rustc_legacy_const_generics(2)]
61037#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61038pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
61039 static_assert_uimm_bits!(LANE, 2);
61040 unsafe extern "unadjusted" {
61041 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i16.p0")]
61042 fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32);
61043 }
61044 _vst2_lane_s16(a as _, b.0, b.1, LANE, 2)
61045}
61046#[doc = "Store multiple 2-element structures from two registers"]
61047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
61048#[doc = "## Safety"]
61049#[doc = " * Neon instrinsic unsafe"]
61050#[inline]
61051#[cfg(target_arch = "arm")]
61052#[target_feature(enable = "neon,v7")]
61053#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
61054#[rustc_legacy_const_generics(2)]
61055#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61056pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
61057 static_assert_uimm_bits!(LANE, 3);
61058 unsafe extern "unadjusted" {
61059 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i16.p0")]
61060 fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32);
61061 }
61062 _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2)
61063}
61064#[doc = "Store multiple 2-element structures from two registers"]
61065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
61066#[doc = "## Safety"]
61067#[doc = " * Neon instrinsic unsafe"]
61068#[inline]
61069#[cfg(target_arch = "arm")]
61070#[target_feature(enable = "neon,v7")]
61071#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
61072#[rustc_legacy_const_generics(2)]
61073#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61074pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
61075 static_assert_uimm_bits!(LANE, 1);
61076 unsafe extern "unadjusted" {
61077 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2i32.p0")]
61078 fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32);
61079 }
61080 _vst2_lane_s32(a as _, b.0, b.1, LANE, 4)
61081}
61082#[doc = "Store multiple 2-element structures from two registers"]
61083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
61084#[doc = "## Safety"]
61085#[doc = " * Neon instrinsic unsafe"]
61086#[inline]
61087#[cfg(target_arch = "arm")]
61088#[target_feature(enable = "neon,v7")]
61089#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
61090#[rustc_legacy_const_generics(2)]
61091#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61092pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
61093 static_assert_uimm_bits!(LANE, 2);
61094 unsafe extern "unadjusted" {
61095 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i32.p0")]
61096 fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32);
61097 }
61098 _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4)
61099}
61100#[doc = "Store multiple 2-element structures from two registers"]
61101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
61102#[doc = "## Safety"]
61103#[doc = " * Neon instrinsic unsafe"]
61104#[inline]
61105#[target_feature(enable = "neon")]
61106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61108#[cfg_attr(
61109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61110 assert_instr(st2, LANE = 0)
61111)]
61112#[rustc_legacy_const_generics(2)]
61113#[cfg_attr(
61114 not(target_arch = "arm"),
61115 stable(feature = "neon_intrinsics", since = "1.59.0")
61116)]
61117#[cfg_attr(
61118 target_arch = "arm",
61119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61120)]
61121pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
61122 static_assert_uimm_bits!(LANE, 3);
61123 vst2_lane_s8::<LANE>(transmute(a), transmute(b))
61124}
61125#[doc = "Store multiple 2-element structures from two registers"]
61126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
61127#[doc = "## Safety"]
61128#[doc = " * Neon instrinsic unsafe"]
61129#[inline]
61130#[target_feature(enable = "neon")]
61131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61133#[cfg_attr(
61134 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61135 assert_instr(st2, LANE = 0)
61136)]
61137#[rustc_legacy_const_generics(2)]
61138#[cfg_attr(
61139 not(target_arch = "arm"),
61140 stable(feature = "neon_intrinsics", since = "1.59.0")
61141)]
61142#[cfg_attr(
61143 target_arch = "arm",
61144 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61145)]
61146pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
61147 static_assert_uimm_bits!(LANE, 2);
61148 vst2_lane_s16::<LANE>(transmute(a), transmute(b))
61149}
61150#[doc = "Store multiple 2-element structures from two registers"]
61151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
61152#[doc = "## Safety"]
61153#[doc = " * Neon instrinsic unsafe"]
61154#[inline]
61155#[target_feature(enable = "neon")]
61156#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61157#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61158#[cfg_attr(
61159 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61160 assert_instr(st2, LANE = 0)
61161)]
61162#[rustc_legacy_const_generics(2)]
61163#[cfg_attr(
61164 not(target_arch = "arm"),
61165 stable(feature = "neon_intrinsics", since = "1.59.0")
61166)]
61167#[cfg_attr(
61168 target_arch = "arm",
61169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61170)]
61171pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
61172 static_assert_uimm_bits!(LANE, 3);
61173 vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
61174}
61175#[doc = "Store multiple 2-element structures from two registers"]
61176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
61177#[doc = "## Safety"]
61178#[doc = " * Neon instrinsic unsafe"]
61179#[inline]
61180#[target_feature(enable = "neon")]
61181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61183#[cfg_attr(
61184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61185 assert_instr(st2, LANE = 0)
61186)]
61187#[rustc_legacy_const_generics(2)]
61188#[cfg_attr(
61189 not(target_arch = "arm"),
61190 stable(feature = "neon_intrinsics", since = "1.59.0")
61191)]
61192#[cfg_attr(
61193 target_arch = "arm",
61194 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61195)]
61196pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
61197 static_assert_uimm_bits!(LANE, 1);
61198 vst2_lane_s32::<LANE>(transmute(a), transmute(b))
61199}
61200#[doc = "Store multiple 2-element structures from two registers"]
61201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
61202#[doc = "## Safety"]
61203#[doc = " * Neon instrinsic unsafe"]
61204#[inline]
61205#[target_feature(enable = "neon")]
61206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61208#[cfg_attr(
61209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61210 assert_instr(st2, LANE = 0)
61211)]
61212#[rustc_legacy_const_generics(2)]
61213#[cfg_attr(
61214 not(target_arch = "arm"),
61215 stable(feature = "neon_intrinsics", since = "1.59.0")
61216)]
61217#[cfg_attr(
61218 target_arch = "arm",
61219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61220)]
61221pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
61222 static_assert_uimm_bits!(LANE, 2);
61223 vst2q_lane_s32::<LANE>(transmute(a), transmute(b))
61224}
61225#[doc = "Store multiple 2-element structures from two registers"]
61226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
61227#[doc = "## Safety"]
61228#[doc = " * Neon instrinsic unsafe"]
61229#[inline]
61230#[target_feature(enable = "neon")]
61231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61233#[cfg_attr(
61234 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61235 assert_instr(st2, LANE = 0)
61236)]
61237#[rustc_legacy_const_generics(2)]
61238#[cfg_attr(
61239 not(target_arch = "arm"),
61240 stable(feature = "neon_intrinsics", since = "1.59.0")
61241)]
61242#[cfg_attr(
61243 target_arch = "arm",
61244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61245)]
61246pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
61247 static_assert_uimm_bits!(LANE, 3);
61248 vst2_lane_s8::<LANE>(transmute(a), transmute(b))
61249}
61250#[doc = "Store multiple 2-element structures from two registers"]
61251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
61252#[doc = "## Safety"]
61253#[doc = " * Neon instrinsic unsafe"]
61254#[inline]
61255#[target_feature(enable = "neon")]
61256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61258#[cfg_attr(
61259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61260 assert_instr(st2, LANE = 0)
61261)]
61262#[rustc_legacy_const_generics(2)]
61263#[cfg_attr(
61264 not(target_arch = "arm"),
61265 stable(feature = "neon_intrinsics", since = "1.59.0")
61266)]
61267#[cfg_attr(
61268 target_arch = "arm",
61269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61270)]
61271pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
61272 static_assert_uimm_bits!(LANE, 2);
61273 vst2_lane_s16::<LANE>(transmute(a), transmute(b))
61274}
61275#[doc = "Store multiple 2-element structures from two registers"]
61276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
61277#[doc = "## Safety"]
61278#[doc = " * Neon instrinsic unsafe"]
61279#[inline]
61280#[target_feature(enable = "neon")]
61281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
61283#[cfg_attr(
61284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61285 assert_instr(st2, LANE = 0)
61286)]
61287#[rustc_legacy_const_generics(2)]
61288#[cfg_attr(
61289 not(target_arch = "arm"),
61290 stable(feature = "neon_intrinsics", since = "1.59.0")
61291)]
61292#[cfg_attr(
61293 target_arch = "arm",
61294 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61295)]
61296pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
61297 static_assert_uimm_bits!(LANE, 3);
61298 vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
61299}
61300#[doc = "Store multiple 2-element structures from two registers"]
61301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
61302#[doc = "## Safety"]
61303#[doc = " * Neon instrinsic unsafe"]
61304#[inline]
61305#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61306#[target_feature(enable = "neon,aes")]
61307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
61308#[cfg_attr(
61309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61310 assert_instr(nop)
61311)]
61312#[cfg_attr(
61313 not(target_arch = "arm"),
61314 stable(feature = "neon_intrinsics", since = "1.59.0")
61315)]
61316#[cfg_attr(
61317 target_arch = "arm",
61318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61319)]
61320pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
61321 vst2_s64(transmute(a), transmute(b))
61322}
61323#[doc = "Store multiple 2-element structures from two registers"]
61324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
61325#[doc = "## Safety"]
61326#[doc = " * Neon instrinsic unsafe"]
61327#[inline]
61328#[cfg(target_arch = "arm")]
61329#[target_feature(enable = "neon,v7")]
61330#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61331#[cfg_attr(test, assert_instr(nop))]
61332pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
61333 unsafe extern "unadjusted" {
61334 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")]
61335 fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32);
61336 }
61337 _vst2_s64(a as _, b.0, b.1, 8)
61338}
61339#[doc = "Store multiple 2-element structures from two registers"]
61340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
61341#[doc = "## Safety"]
61342#[doc = " * Neon instrinsic unsafe"]
61343#[inline]
61344#[target_feature(enable = "neon")]
61345#[cfg(not(target_arch = "arm"))]
61346#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61347#[cfg_attr(test, assert_instr(nop))]
61348pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
61349 unsafe extern "unadjusted" {
61350 #[cfg_attr(
61351 any(target_arch = "aarch64", target_arch = "arm64ec"),
61352 link_name = "llvm.aarch64.neon.st2.v1i64.p0i8"
61353 )]
61354 fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8);
61355 }
61356 _vst2_s64(b.0, b.1, a as _)
61357}
61358#[doc = "Store multiple 2-element structures from two registers"]
61359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
61360#[doc = "## Safety"]
61361#[doc = " * Neon instrinsic unsafe"]
61362#[inline]
61363#[target_feature(enable = "neon")]
61364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
61366#[cfg_attr(
61367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61368 assert_instr(nop)
61369)]
61370#[cfg_attr(
61371 not(target_arch = "arm"),
61372 stable(feature = "neon_intrinsics", since = "1.59.0")
61373)]
61374#[cfg_attr(
61375 target_arch = "arm",
61376 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61377)]
61378pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
61379 vst2_s64(transmute(a), transmute(b))
61380}
61381#[doc = "Store multiple 2-element structures from two registers"]
61382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
61383#[doc = "## Safety"]
61384#[doc = " * Neon instrinsic unsafe"]
61385#[inline]
61386#[target_feature(enable = "neon")]
61387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61389#[cfg_attr(
61390 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61391 assert_instr(st2)
61392)]
61393#[cfg_attr(
61394 not(target_arch = "arm"),
61395 stable(feature = "neon_intrinsics", since = "1.59.0")
61396)]
61397#[cfg_attr(
61398 target_arch = "arm",
61399 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61400)]
61401pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
61402 vst2_s8(transmute(a), transmute(b))
61403}
61404#[doc = "Store multiple 2-element structures from two registers"]
61405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
61406#[doc = "## Safety"]
61407#[doc = " * Neon instrinsic unsafe"]
61408#[inline]
61409#[target_feature(enable = "neon")]
61410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61412#[cfg_attr(
61413 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61414 assert_instr(st2)
61415)]
61416#[cfg_attr(
61417 not(target_arch = "arm"),
61418 stable(feature = "neon_intrinsics", since = "1.59.0")
61419)]
61420#[cfg_attr(
61421 target_arch = "arm",
61422 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61423)]
61424pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
61425 vst2q_s8(transmute(a), transmute(b))
61426}
61427#[doc = "Store multiple 2-element structures from two registers"]
61428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
61429#[doc = "## Safety"]
61430#[doc = " * Neon instrinsic unsafe"]
61431#[inline]
61432#[target_feature(enable = "neon")]
61433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61435#[cfg_attr(
61436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61437 assert_instr(st2)
61438)]
61439#[cfg_attr(
61440 not(target_arch = "arm"),
61441 stable(feature = "neon_intrinsics", since = "1.59.0")
61442)]
61443#[cfg_attr(
61444 target_arch = "arm",
61445 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61446)]
61447pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
61448 vst2_s16(transmute(a), transmute(b))
61449}
61450#[doc = "Store multiple 2-element structures from two registers"]
61451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
61452#[doc = "## Safety"]
61453#[doc = " * Neon instrinsic unsafe"]
61454#[inline]
61455#[target_feature(enable = "neon")]
61456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61458#[cfg_attr(
61459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61460 assert_instr(st2)
61461)]
61462#[cfg_attr(
61463 not(target_arch = "arm"),
61464 stable(feature = "neon_intrinsics", since = "1.59.0")
61465)]
61466#[cfg_attr(
61467 target_arch = "arm",
61468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61469)]
61470pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
61471 vst2q_s16(transmute(a), transmute(b))
61472}
61473#[doc = "Store multiple 2-element structures from two registers"]
61474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
61475#[doc = "## Safety"]
61476#[doc = " * Neon instrinsic unsafe"]
61477#[inline]
61478#[target_feature(enable = "neon")]
61479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61481#[cfg_attr(
61482 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61483 assert_instr(st2)
61484)]
61485#[cfg_attr(
61486 not(target_arch = "arm"),
61487 stable(feature = "neon_intrinsics", since = "1.59.0")
61488)]
61489#[cfg_attr(
61490 target_arch = "arm",
61491 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61492)]
61493pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
61494 vst2_s32(transmute(a), transmute(b))
61495}
61496#[doc = "Store multiple 2-element structures from two registers"]
61497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
61498#[doc = "## Safety"]
61499#[doc = " * Neon instrinsic unsafe"]
61500#[inline]
61501#[target_feature(enable = "neon")]
61502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61504#[cfg_attr(
61505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61506 assert_instr(st2)
61507)]
61508#[cfg_attr(
61509 not(target_arch = "arm"),
61510 stable(feature = "neon_intrinsics", since = "1.59.0")
61511)]
61512#[cfg_attr(
61513 target_arch = "arm",
61514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61515)]
61516pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
61517 vst2q_s32(transmute(a), transmute(b))
61518}
61519#[doc = "Store multiple 2-element structures from two registers"]
61520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
61521#[doc = "## Safety"]
61522#[doc = " * Neon instrinsic unsafe"]
61523#[inline]
61524#[target_feature(enable = "neon")]
61525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61527#[cfg_attr(
61528 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61529 assert_instr(st2)
61530)]
61531#[cfg_attr(
61532 not(target_arch = "arm"),
61533 stable(feature = "neon_intrinsics", since = "1.59.0")
61534)]
61535#[cfg_attr(
61536 target_arch = "arm",
61537 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61538)]
61539pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
61540 vst2_s8(transmute(a), transmute(b))
61541}
61542#[doc = "Store multiple 2-element structures from two registers"]
61543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
61544#[doc = "## Safety"]
61545#[doc = " * Neon instrinsic unsafe"]
61546#[inline]
61547#[target_feature(enable = "neon")]
61548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61550#[cfg_attr(
61551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61552 assert_instr(st2)
61553)]
61554#[cfg_attr(
61555 not(target_arch = "arm"),
61556 stable(feature = "neon_intrinsics", since = "1.59.0")
61557)]
61558#[cfg_attr(
61559 target_arch = "arm",
61560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61561)]
61562pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
61563 vst2q_s8(transmute(a), transmute(b))
61564}
61565#[doc = "Store multiple 2-element structures from two registers"]
61566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
61567#[doc = "## Safety"]
61568#[doc = " * Neon instrinsic unsafe"]
61569#[inline]
61570#[target_feature(enable = "neon")]
61571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61573#[cfg_attr(
61574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61575 assert_instr(st2)
61576)]
61577#[cfg_attr(
61578 not(target_arch = "arm"),
61579 stable(feature = "neon_intrinsics", since = "1.59.0")
61580)]
61581#[cfg_attr(
61582 target_arch = "arm",
61583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61584)]
61585pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
61586 vst2_s16(transmute(a), transmute(b))
61587}
61588#[doc = "Store multiple 2-element structures from two registers"]
61589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
61590#[doc = "## Safety"]
61591#[doc = " * Neon instrinsic unsafe"]
61592#[inline]
61593#[target_feature(enable = "neon")]
61594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
61596#[cfg_attr(
61597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61598 assert_instr(st2)
61599)]
61600#[cfg_attr(
61601 not(target_arch = "arm"),
61602 stable(feature = "neon_intrinsics", since = "1.59.0")
61603)]
61604#[cfg_attr(
61605 target_arch = "arm",
61606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61607)]
61608pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
61609 vst2q_s16(transmute(a), transmute(b))
61610}
61611#[doc = "Store multiple 3-element structures from three registers"]
61612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
61613#[doc = "## Safety"]
61614#[doc = " * Neon instrinsic unsafe"]
61615#[inline]
61616#[cfg(target_arch = "arm")]
61617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61618#[target_feature(enable = "neon,fp16")]
61619#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
61620#[cfg_attr(test, assert_instr(vst3))]
61621pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
61622 unsafe extern "unadjusted" {
61623 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f16")]
61624 fn _vst3_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, c: float16x4_t, size: i32);
61625 }
61626 _vst3_f16(a as _, b.0, b.1, b.2, 2)
61627}
61628#[doc = "Store multiple 3-element structures from three registers"]
61629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
61630#[doc = "## Safety"]
61631#[doc = " * Neon instrinsic unsafe"]
61632#[inline]
61633#[cfg(target_arch = "arm")]
61634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61635#[target_feature(enable = "neon,fp16")]
61636#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
61637#[cfg_attr(test, assert_instr(vst3))]
61638pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
61639 unsafe extern "unadjusted" {
61640 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8f16")]
61641 fn _vst3q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, c: float16x8_t, size: i32);
61642 }
61643 _vst3q_f16(a as _, b.0, b.1, b.2, 2)
61644}
61645#[doc = "Store multiple 3-element structures from three registers"]
61646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
61647#[doc = "## Safety"]
61648#[doc = " * Neon instrinsic unsafe"]
61649#[inline]
61650#[cfg(not(target_arch = "arm"))]
61651#[target_feature(enable = "neon,fp16")]
61652#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
61653#[cfg_attr(test, assert_instr(st3))]
61654pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
61655 unsafe extern "unadjusted" {
61656 #[cfg_attr(
61657 any(target_arch = "aarch64", target_arch = "arm64ec"),
61658 link_name = "llvm.aarch64.neon.st3.v4f16.p0i8"
61659 )]
61660 fn _vst3_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut i8);
61661 }
61662 _vst3_f16(b.0, b.1, b.2, a as _)
61663}
61664#[doc = "Store multiple 3-element structures from three registers"]
61665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
61666#[doc = "## Safety"]
61667#[doc = " * Neon instrinsic unsafe"]
61668#[inline]
61669#[cfg(not(target_arch = "arm"))]
61670#[target_feature(enable = "neon,fp16")]
61671#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
61672#[cfg_attr(test, assert_instr(st3))]
61673pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
61674 unsafe extern "unadjusted" {
61675 #[cfg_attr(
61676 any(target_arch = "aarch64", target_arch = "arm64ec"),
61677 link_name = "llvm.aarch64.neon.st3.v8f16.p0i8"
61678 )]
61679 fn _vst3q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut i8);
61680 }
61681 _vst3q_f16(b.0, b.1, b.2, a as _)
61682}
61683#[doc = "Store multiple 3-element structures from three registers"]
61684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
61685#[doc = "## Safety"]
61686#[doc = " * Neon instrinsic unsafe"]
61687#[inline]
61688#[cfg(target_arch = "arm")]
61689#[target_feature(enable = "neon,v7")]
61690#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61691#[cfg_attr(test, assert_instr(vst3))]
61692pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
61693 unsafe extern "unadjusted" {
61694 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2f32")]
61695 fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32);
61696 }
61697 _vst3_f32(a as _, b.0, b.1, b.2, 4)
61698}
61699#[doc = "Store multiple 3-element structures from three registers"]
61700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
61701#[doc = "## Safety"]
61702#[doc = " * Neon instrinsic unsafe"]
61703#[inline]
61704#[cfg(target_arch = "arm")]
61705#[target_feature(enable = "neon,v7")]
61706#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61707#[cfg_attr(test, assert_instr(vst3))]
61708pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
61709 unsafe extern "unadjusted" {
61710 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f32")]
61711 fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32);
61712 }
61713 _vst3q_f32(a as _, b.0, b.1, b.2, 4)
61714}
61715#[doc = "Store multiple 3-element structures from three registers"]
61716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
61717#[doc = "## Safety"]
61718#[doc = " * Neon instrinsic unsafe"]
61719#[inline]
61720#[cfg(target_arch = "arm")]
61721#[target_feature(enable = "neon,v7")]
61722#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61723#[cfg_attr(test, assert_instr(vst3))]
61724pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
61725 unsafe extern "unadjusted" {
61726 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i8")]
61727 fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32);
61728 }
61729 _vst3_s8(a as _, b.0, b.1, b.2, 1)
61730}
61731#[doc = "Store multiple 3-element structures from three registers"]
61732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
61733#[doc = "## Safety"]
61734#[doc = " * Neon instrinsic unsafe"]
61735#[inline]
61736#[cfg(target_arch = "arm")]
61737#[target_feature(enable = "neon,v7")]
61738#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61739#[cfg_attr(test, assert_instr(vst3))]
61740pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
61741 unsafe extern "unadjusted" {
61742 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v16i8")]
61743 fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32);
61744 }
61745 _vst3q_s8(a as _, b.0, b.1, b.2, 1)
61746}
61747#[doc = "Store multiple 3-element structures from three registers"]
61748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
61749#[doc = "## Safety"]
61750#[doc = " * Neon instrinsic unsafe"]
61751#[inline]
61752#[cfg(target_arch = "arm")]
61753#[target_feature(enable = "neon,v7")]
61754#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61755#[cfg_attr(test, assert_instr(vst3))]
61756pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
61757 unsafe extern "unadjusted" {
61758 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i16")]
61759 fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32);
61760 }
61761 _vst3_s16(a as _, b.0, b.1, b.2, 2)
61762}
61763#[doc = "Store multiple 3-element structures from three registers"]
61764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
61765#[doc = "## Safety"]
61766#[doc = " * Neon instrinsic unsafe"]
61767#[inline]
61768#[cfg(target_arch = "arm")]
61769#[target_feature(enable = "neon,v7")]
61770#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61771#[cfg_attr(test, assert_instr(vst3))]
61772pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
61773 unsafe extern "unadjusted" {
61774 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i16")]
61775 fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32);
61776 }
61777 _vst3q_s16(a as _, b.0, b.1, b.2, 2)
61778}
61779#[doc = "Store multiple 3-element structures from three registers"]
61780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
61781#[doc = "## Safety"]
61782#[doc = " * Neon instrinsic unsafe"]
61783#[inline]
61784#[cfg(target_arch = "arm")]
61785#[target_feature(enable = "neon,v7")]
61786#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61787#[cfg_attr(test, assert_instr(vst3))]
61788pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
61789 unsafe extern "unadjusted" {
61790 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2i32")]
61791 fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32);
61792 }
61793 _vst3_s32(a as _, b.0, b.1, b.2, 4)
61794}
61795#[doc = "Store multiple 3-element structures from three registers"]
61796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
61797#[doc = "## Safety"]
61798#[doc = " * Neon instrinsic unsafe"]
61799#[inline]
61800#[cfg(target_arch = "arm")]
61801#[target_feature(enable = "neon,v7")]
61802#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61803#[cfg_attr(test, assert_instr(vst3))]
61804pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
61805 unsafe extern "unadjusted" {
61806 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i32")]
61807 fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32);
61808 }
61809 _vst3q_s32(a as _, b.0, b.1, b.2, 4)
61810}
61811#[doc = "Store multiple 3-element structures from three registers"]
61812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
61813#[doc = "## Safety"]
61814#[doc = " * Neon instrinsic unsafe"]
61815#[inline]
61816#[target_feature(enable = "neon")]
61817#[cfg(not(target_arch = "arm"))]
61818#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61819#[cfg_attr(test, assert_instr(st3))]
61820pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
61821 unsafe extern "unadjusted" {
61822 #[cfg_attr(
61823 any(target_arch = "aarch64", target_arch = "arm64ec"),
61824 link_name = "llvm.aarch64.neon.st3.v2f32.p0i8"
61825 )]
61826 fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8);
61827 }
61828 _vst3_f32(b.0, b.1, b.2, a as _)
61829}
61830#[doc = "Store multiple 3-element structures from three registers"]
61831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
61832#[doc = "## Safety"]
61833#[doc = " * Neon instrinsic unsafe"]
61834#[inline]
61835#[target_feature(enable = "neon")]
61836#[cfg(not(target_arch = "arm"))]
61837#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61838#[cfg_attr(test, assert_instr(st3))]
61839pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
61840 unsafe extern "unadjusted" {
61841 #[cfg_attr(
61842 any(target_arch = "aarch64", target_arch = "arm64ec"),
61843 link_name = "llvm.aarch64.neon.st3.v4f32.p0i8"
61844 )]
61845 fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8);
61846 }
61847 _vst3q_f32(b.0, b.1, b.2, a as _)
61848}
61849#[doc = "Store multiple 3-element structures from three registers"]
61850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
61851#[doc = "## Safety"]
61852#[doc = " * Neon instrinsic unsafe"]
61853#[inline]
61854#[target_feature(enable = "neon")]
61855#[cfg(not(target_arch = "arm"))]
61856#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61857#[cfg_attr(test, assert_instr(st3))]
61858pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
61859 unsafe extern "unadjusted" {
61860 #[cfg_attr(
61861 any(target_arch = "aarch64", target_arch = "arm64ec"),
61862 link_name = "llvm.aarch64.neon.st3.v8i8.p0i8"
61863 )]
61864 fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
61865 }
61866 _vst3_s8(b.0, b.1, b.2, a as _)
61867}
61868#[doc = "Store multiple 3-element structures from three registers"]
61869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
61870#[doc = "## Safety"]
61871#[doc = " * Neon instrinsic unsafe"]
61872#[inline]
61873#[target_feature(enable = "neon")]
61874#[cfg(not(target_arch = "arm"))]
61875#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61876#[cfg_attr(test, assert_instr(st3))]
61877pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
61878 unsafe extern "unadjusted" {
61879 #[cfg_attr(
61880 any(target_arch = "aarch64", target_arch = "arm64ec"),
61881 link_name = "llvm.aarch64.neon.st3.v16i8.p0i8"
61882 )]
61883 fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
61884 }
61885 _vst3q_s8(b.0, b.1, b.2, a as _)
61886}
61887#[doc = "Store multiple 3-element structures from three registers"]
61888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
61889#[doc = "## Safety"]
61890#[doc = " * Neon instrinsic unsafe"]
61891#[inline]
61892#[target_feature(enable = "neon")]
61893#[cfg(not(target_arch = "arm"))]
61894#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61895#[cfg_attr(test, assert_instr(st3))]
61896pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
61897 unsafe extern "unadjusted" {
61898 #[cfg_attr(
61899 any(target_arch = "aarch64", target_arch = "arm64ec"),
61900 link_name = "llvm.aarch64.neon.st3.v4i16.p0i8"
61901 )]
61902 fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8);
61903 }
61904 _vst3_s16(b.0, b.1, b.2, a as _)
61905}
61906#[doc = "Store multiple 3-element structures from three registers"]
61907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
61908#[doc = "## Safety"]
61909#[doc = " * Neon instrinsic unsafe"]
61910#[inline]
61911#[target_feature(enable = "neon")]
61912#[cfg(not(target_arch = "arm"))]
61913#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61914#[cfg_attr(test, assert_instr(st3))]
61915pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
61916 unsafe extern "unadjusted" {
61917 #[cfg_attr(
61918 any(target_arch = "aarch64", target_arch = "arm64ec"),
61919 link_name = "llvm.aarch64.neon.st3.v8i16.p0i8"
61920 )]
61921 fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8);
61922 }
61923 _vst3q_s16(b.0, b.1, b.2, a as _)
61924}
61925#[doc = "Store multiple 3-element structures from three registers"]
61926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
61927#[doc = "## Safety"]
61928#[doc = " * Neon instrinsic unsafe"]
61929#[inline]
61930#[target_feature(enable = "neon")]
61931#[cfg(not(target_arch = "arm"))]
61932#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61933#[cfg_attr(test, assert_instr(st3))]
61934pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
61935 unsafe extern "unadjusted" {
61936 #[cfg_attr(
61937 any(target_arch = "aarch64", target_arch = "arm64ec"),
61938 link_name = "llvm.aarch64.neon.st3.v2i32.p0i8"
61939 )]
61940 fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8);
61941 }
61942 _vst3_s32(b.0, b.1, b.2, a as _)
61943}
61944#[doc = "Store multiple 3-element structures from three registers"]
61945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
61946#[doc = "## Safety"]
61947#[doc = " * Neon instrinsic unsafe"]
61948#[inline]
61949#[target_feature(enable = "neon")]
61950#[cfg(not(target_arch = "arm"))]
61951#[stable(feature = "neon_intrinsics", since = "1.59.0")]
61952#[cfg_attr(test, assert_instr(st3))]
61953pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
61954 unsafe extern "unadjusted" {
61955 #[cfg_attr(
61956 any(target_arch = "aarch64", target_arch = "arm64ec"),
61957 link_name = "llvm.aarch64.neon.st3.v4i32.p0i8"
61958 )]
61959 fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8);
61960 }
61961 _vst3q_s32(b.0, b.1, b.2, a as _)
61962}
61963#[doc = "Store multiple 3-element structures from three registers"]
61964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
61965#[doc = "## Safety"]
61966#[doc = " * Neon instrinsic unsafe"]
61967#[inline]
61968#[cfg(target_arch = "arm")]
61969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61970#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
61971#[rustc_legacy_const_generics(2)]
61972#[target_feature(enable = "neon,fp16")]
61973#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
61974pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
61975 static_assert_uimm_bits!(LANE, 2);
61976 unsafe extern "unadjusted" {
61977 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f16")]
61978 fn _vst3_lane_f16(
61979 ptr: *mut i8,
61980 a: float16x4_t,
61981 b: float16x4_t,
61982 c: float16x4_t,
61983 n: i32,
61984 size: i32,
61985 );
61986 }
61987 _vst3_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
61988}
61989#[doc = "Store multiple 3-element structures from three registers"]
61990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
61991#[doc = "## Safety"]
61992#[doc = " * Neon instrinsic unsafe"]
61993#[inline]
61994#[cfg(target_arch = "arm")]
61995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61996#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
61997#[rustc_legacy_const_generics(2)]
61998#[target_feature(enable = "neon,fp16")]
61999#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62000pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
62001 static_assert_uimm_bits!(LANE, 3);
62002 unsafe extern "unadjusted" {
62003 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8f16")]
62004 fn _vst3q_lane_f16(
62005 ptr: *mut i8,
62006 a: float16x8_t,
62007 b: float16x8_t,
62008 c: float16x8_t,
62009 n: i32,
62010 size: i32,
62011 );
62012 }
62013 _vst3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
62014}
62015#[doc = "Store multiple 3-element structures from three registers"]
62016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
62017#[doc = "## Safety"]
62018#[doc = " * Neon instrinsic unsafe"]
62019#[inline]
62020#[cfg(not(target_arch = "arm"))]
62021#[rustc_legacy_const_generics(2)]
62022#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62023#[target_feature(enable = "neon,fp16")]
62024#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62025pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
62026 static_assert_uimm_bits!(LANE, 2);
62027 unsafe extern "unadjusted" {
62028 #[cfg_attr(
62029 any(target_arch = "aarch64", target_arch = "arm64ec"),
62030 link_name = "llvm.aarch64.neon.st3lane.v4f16.p0i8"
62031 )]
62032 fn _vst3_lane_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, n: i64, ptr: *mut i8);
62033 }
62034 _vst3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
62035}
62036#[doc = "Store multiple 3-element structures from three registers"]
62037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
62038#[doc = "## Safety"]
62039#[doc = " * Neon instrinsic unsafe"]
62040#[inline]
62041#[cfg(not(target_arch = "arm"))]
62042#[rustc_legacy_const_generics(2)]
62043#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62044#[target_feature(enable = "neon,fp16")]
62045#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62046pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
62047 static_assert_uimm_bits!(LANE, 3);
62048 unsafe extern "unadjusted" {
62049 #[cfg_attr(
62050 any(target_arch = "aarch64", target_arch = "arm64ec"),
62051 link_name = "llvm.aarch64.neon.st3lane.v8f16.p0i8"
62052 )]
62053 fn _vst3q_lane_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, n: i64, ptr: *mut i8);
62054 }
62055 _vst3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
62056}
62057#[doc = "Store multiple 3-element structures from three registers"]
62058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
62059#[doc = "## Safety"]
62060#[doc = " * Neon instrinsic unsafe"]
62061#[inline]
62062#[cfg(target_arch = "arm")]
62063#[target_feature(enable = "neon,v7")]
62064#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62065#[rustc_legacy_const_generics(2)]
62066#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62067pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
62068 static_assert_uimm_bits!(LANE, 1);
62069 unsafe extern "unadjusted" {
62070 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2f32")]
62071 fn _vst3_lane_f32(
62072 ptr: *mut i8,
62073 a: float32x2_t,
62074 b: float32x2_t,
62075 c: float32x2_t,
62076 n: i32,
62077 size: i32,
62078 );
62079 }
62080 _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
62081}
62082#[doc = "Store multiple 3-element structures from three registers"]
62083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
62084#[doc = "## Safety"]
62085#[doc = " * Neon instrinsic unsafe"]
62086#[inline]
62087#[cfg(target_arch = "arm")]
62088#[target_feature(enable = "neon,v7")]
62089#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62090#[rustc_legacy_const_generics(2)]
62091#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62092pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
62093 static_assert_uimm_bits!(LANE, 2);
62094 unsafe extern "unadjusted" {
62095 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f32")]
62096 fn _vst3q_lane_f32(
62097 ptr: *mut i8,
62098 a: float32x4_t,
62099 b: float32x4_t,
62100 c: float32x4_t,
62101 n: i32,
62102 size: i32,
62103 );
62104 }
62105 _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
62106}
62107#[doc = "Store multiple 3-element structures from three registers"]
62108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
62109#[doc = "## Safety"]
62110#[doc = " * Neon instrinsic unsafe"]
62111#[inline]
62112#[cfg(target_arch = "arm")]
62113#[target_feature(enable = "neon,v7")]
62114#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62115#[rustc_legacy_const_generics(2)]
62116#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62117pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
62118 static_assert_uimm_bits!(LANE, 3);
62119 unsafe extern "unadjusted" {
62120 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")]
62121 fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32);
62122 }
62123 _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
62124}
62125#[doc = "Store multiple 3-element structures from three registers"]
62126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
62127#[doc = "## Safety"]
62128#[doc = " * Neon instrinsic unsafe"]
62129#[inline]
62130#[cfg(target_arch = "arm")]
62131#[target_feature(enable = "neon,v7")]
62132#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62133#[rustc_legacy_const_generics(2)]
62134#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62135pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
62136 static_assert_uimm_bits!(LANE, 2);
62137 unsafe extern "unadjusted" {
62138 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i16")]
62139 fn _vst3_lane_s16(
62140 ptr: *mut i8,
62141 a: int16x4_t,
62142 b: int16x4_t,
62143 c: int16x4_t,
62144 n: i32,
62145 size: i32,
62146 );
62147 }
62148 _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
62149}
62150#[doc = "Store multiple 3-element structures from three registers"]
62151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
62152#[doc = "## Safety"]
62153#[doc = " * Neon instrinsic unsafe"]
62154#[inline]
62155#[cfg(target_arch = "arm")]
62156#[target_feature(enable = "neon,v7")]
62157#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62158#[rustc_legacy_const_generics(2)]
62159#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62160pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
62161 static_assert_uimm_bits!(LANE, 3);
62162 unsafe extern "unadjusted" {
62163 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i16")]
62164 fn _vst3q_lane_s16(
62165 ptr: *mut i8,
62166 a: int16x8_t,
62167 b: int16x8_t,
62168 c: int16x8_t,
62169 n: i32,
62170 size: i32,
62171 );
62172 }
62173 _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
62174}
62175#[doc = "Store multiple 3-element structures from three registers"]
62176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
62177#[doc = "## Safety"]
62178#[doc = " * Neon instrinsic unsafe"]
62179#[inline]
62180#[cfg(target_arch = "arm")]
62181#[target_feature(enable = "neon,v7")]
62182#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62183#[rustc_legacy_const_generics(2)]
62184#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62185pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
62186 static_assert_uimm_bits!(LANE, 1);
62187 unsafe extern "unadjusted" {
62188 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2i32")]
62189 fn _vst3_lane_s32(
62190 ptr: *mut i8,
62191 a: int32x2_t,
62192 b: int32x2_t,
62193 c: int32x2_t,
62194 n: i32,
62195 size: i32,
62196 );
62197 }
62198 _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
62199}
62200#[doc = "Store multiple 3-element structures from three registers"]
62201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
62202#[doc = "## Safety"]
62203#[doc = " * Neon instrinsic unsafe"]
62204#[inline]
62205#[cfg(target_arch = "arm")]
62206#[target_feature(enable = "neon,v7")]
62207#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
62208#[rustc_legacy_const_generics(2)]
62209#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62210pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
62211 static_assert_uimm_bits!(LANE, 2);
62212 unsafe extern "unadjusted" {
62213 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i32")]
62214 fn _vst3q_lane_s32(
62215 ptr: *mut i8,
62216 a: int32x4_t,
62217 b: int32x4_t,
62218 c: int32x4_t,
62219 n: i32,
62220 size: i32,
62221 );
62222 }
62223 _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
62224}
62225#[doc = "Store multiple 3-element structures from three registers"]
62226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
62227#[doc = "## Safety"]
62228#[doc = " * Neon instrinsic unsafe"]
62229#[inline]
62230#[target_feature(enable = "neon")]
62231#[cfg(not(target_arch = "arm"))]
62232#[rustc_legacy_const_generics(2)]
62233#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62234#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62235pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
62236 static_assert_uimm_bits!(LANE, 1);
62237 unsafe extern "unadjusted" {
62238 #[cfg_attr(
62239 any(target_arch = "aarch64", target_arch = "arm64ec"),
62240 link_name = "llvm.aarch64.neon.st3lane.v2f32.p0i8"
62241 )]
62242 fn _vst3_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8);
62243 }
62244 _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
62245}
62246#[doc = "Store multiple 3-element structures from three registers"]
62247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
62248#[doc = "## Safety"]
62249#[doc = " * Neon instrinsic unsafe"]
62250#[inline]
62251#[target_feature(enable = "neon")]
62252#[cfg(not(target_arch = "arm"))]
62253#[rustc_legacy_const_generics(2)]
62254#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62255#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62256pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
62257 static_assert_uimm_bits!(LANE, 2);
62258 unsafe extern "unadjusted" {
62259 #[cfg_attr(
62260 any(target_arch = "aarch64", target_arch = "arm64ec"),
62261 link_name = "llvm.aarch64.neon.st3lane.v4f32.p0i8"
62262 )]
62263 fn _vst3q_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8);
62264 }
62265 _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
62266}
62267#[doc = "Store multiple 3-element structures from three registers"]
62268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
62269#[doc = "## Safety"]
62270#[doc = " * Neon instrinsic unsafe"]
62271#[inline]
62272#[target_feature(enable = "neon")]
62273#[cfg(not(target_arch = "arm"))]
62274#[rustc_legacy_const_generics(2)]
62275#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62276#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62277pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
62278 static_assert_uimm_bits!(LANE, 3);
62279 unsafe extern "unadjusted" {
62280 #[cfg_attr(
62281 any(target_arch = "aarch64", target_arch = "arm64ec"),
62282 link_name = "llvm.aarch64.neon.st3lane.v8i8.p0i8"
62283 )]
62284 fn _vst3_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8);
62285 }
62286 _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
62287}
62288#[doc = "Store multiple 3-element structures from three registers"]
62289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
62290#[doc = "## Safety"]
62291#[doc = " * Neon instrinsic unsafe"]
62292#[inline]
62293#[target_feature(enable = "neon")]
62294#[cfg(not(target_arch = "arm"))]
62295#[rustc_legacy_const_generics(2)]
62296#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62297#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62298pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
62299 static_assert_uimm_bits!(LANE, 2);
62300 unsafe extern "unadjusted" {
62301 #[cfg_attr(
62302 any(target_arch = "aarch64", target_arch = "arm64ec"),
62303 link_name = "llvm.aarch64.neon.st3lane.v4i16.p0i8"
62304 )]
62305 fn _vst3_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8);
62306 }
62307 _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
62308}
62309#[doc = "Store multiple 3-element structures from three registers"]
62310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
62311#[doc = "## Safety"]
62312#[doc = " * Neon instrinsic unsafe"]
62313#[inline]
62314#[target_feature(enable = "neon")]
62315#[cfg(not(target_arch = "arm"))]
62316#[rustc_legacy_const_generics(2)]
62317#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62318#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62319pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
62320 static_assert_uimm_bits!(LANE, 3);
62321 unsafe extern "unadjusted" {
62322 #[cfg_attr(
62323 any(target_arch = "aarch64", target_arch = "arm64ec"),
62324 link_name = "llvm.aarch64.neon.st3lane.v8i16.p0i8"
62325 )]
62326 fn _vst3q_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8);
62327 }
62328 _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
62329}
62330#[doc = "Store multiple 3-element structures from three registers"]
62331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
62332#[doc = "## Safety"]
62333#[doc = " * Neon instrinsic unsafe"]
62334#[inline]
62335#[target_feature(enable = "neon")]
62336#[cfg(not(target_arch = "arm"))]
62337#[rustc_legacy_const_generics(2)]
62338#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62340pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
62341 static_assert_uimm_bits!(LANE, 1);
62342 unsafe extern "unadjusted" {
62343 #[cfg_attr(
62344 any(target_arch = "aarch64", target_arch = "arm64ec"),
62345 link_name = "llvm.aarch64.neon.st3lane.v2i32.p0i8"
62346 )]
62347 fn _vst3_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8);
62348 }
62349 _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
62350}
62351#[doc = "Store multiple 3-element structures from three registers"]
62352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
62353#[doc = "## Safety"]
62354#[doc = " * Neon instrinsic unsafe"]
62355#[inline]
62356#[target_feature(enable = "neon")]
62357#[cfg(not(target_arch = "arm"))]
62358#[rustc_legacy_const_generics(2)]
62359#[cfg_attr(test, assert_instr(st3, LANE = 0))]
62360#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62361pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
62362 static_assert_uimm_bits!(LANE, 2);
62363 unsafe extern "unadjusted" {
62364 #[cfg_attr(
62365 any(target_arch = "aarch64", target_arch = "arm64ec"),
62366 link_name = "llvm.aarch64.neon.st3lane.v4i32.p0i8"
62367 )]
62368 fn _vst3q_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8);
62369 }
62370 _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
62371}
62372#[doc = "Store multiple 3-element structures from three registers"]
62373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
62374#[doc = "## Safety"]
62375#[doc = " * Neon instrinsic unsafe"]
62376#[inline]
62377#[target_feature(enable = "neon")]
62378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62380#[cfg_attr(
62381 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62382 assert_instr(st3, LANE = 0)
62383)]
62384#[rustc_legacy_const_generics(2)]
62385#[cfg_attr(
62386 not(target_arch = "arm"),
62387 stable(feature = "neon_intrinsics", since = "1.59.0")
62388)]
62389#[cfg_attr(
62390 target_arch = "arm",
62391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62392)]
62393pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
62394 static_assert_uimm_bits!(LANE, 3);
62395 vst3_lane_s8::<LANE>(transmute(a), transmute(b))
62396}
62397#[doc = "Store multiple 3-element structures from three registers"]
62398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
62399#[doc = "## Safety"]
62400#[doc = " * Neon instrinsic unsafe"]
62401#[inline]
62402#[target_feature(enable = "neon")]
62403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62405#[cfg_attr(
62406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62407 assert_instr(st3, LANE = 0)
62408)]
62409#[rustc_legacy_const_generics(2)]
62410#[cfg_attr(
62411 not(target_arch = "arm"),
62412 stable(feature = "neon_intrinsics", since = "1.59.0")
62413)]
62414#[cfg_attr(
62415 target_arch = "arm",
62416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62417)]
62418pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
62419 static_assert_uimm_bits!(LANE, 2);
62420 vst3_lane_s16::<LANE>(transmute(a), transmute(b))
62421}
62422#[doc = "Store multiple 3-element structures from three registers"]
62423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
62424#[doc = "## Safety"]
62425#[doc = " * Neon instrinsic unsafe"]
62426#[inline]
62427#[target_feature(enable = "neon")]
62428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62430#[cfg_attr(
62431 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62432 assert_instr(st3, LANE = 0)
62433)]
62434#[rustc_legacy_const_generics(2)]
62435#[cfg_attr(
62436 not(target_arch = "arm"),
62437 stable(feature = "neon_intrinsics", since = "1.59.0")
62438)]
62439#[cfg_attr(
62440 target_arch = "arm",
62441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62442)]
62443pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
62444 static_assert_uimm_bits!(LANE, 3);
62445 vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
62446}
62447#[doc = "Store multiple 3-element structures from three registers"]
62448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
62449#[doc = "## Safety"]
62450#[doc = " * Neon instrinsic unsafe"]
62451#[inline]
62452#[target_feature(enable = "neon")]
62453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62454#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62455#[cfg_attr(
62456 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62457 assert_instr(st3, LANE = 0)
62458)]
62459#[rustc_legacy_const_generics(2)]
62460#[cfg_attr(
62461 not(target_arch = "arm"),
62462 stable(feature = "neon_intrinsics", since = "1.59.0")
62463)]
62464#[cfg_attr(
62465 target_arch = "arm",
62466 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62467)]
62468pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
62469 static_assert_uimm_bits!(LANE, 1);
62470 vst3_lane_s32::<LANE>(transmute(a), transmute(b))
62471}
62472#[doc = "Store multiple 3-element structures from three registers"]
62473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
62474#[doc = "## Safety"]
62475#[doc = " * Neon instrinsic unsafe"]
62476#[inline]
62477#[target_feature(enable = "neon")]
62478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62480#[cfg_attr(
62481 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62482 assert_instr(st3, LANE = 0)
62483)]
62484#[rustc_legacy_const_generics(2)]
62485#[cfg_attr(
62486 not(target_arch = "arm"),
62487 stable(feature = "neon_intrinsics", since = "1.59.0")
62488)]
62489#[cfg_attr(
62490 target_arch = "arm",
62491 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62492)]
62493pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
62494 static_assert_uimm_bits!(LANE, 2);
62495 vst3q_lane_s32::<LANE>(transmute(a), transmute(b))
62496}
62497#[doc = "Store multiple 3-element structures from three registers"]
62498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
62499#[doc = "## Safety"]
62500#[doc = " * Neon instrinsic unsafe"]
62501#[inline]
62502#[target_feature(enable = "neon")]
62503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62505#[cfg_attr(
62506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62507 assert_instr(st3, LANE = 0)
62508)]
62509#[rustc_legacy_const_generics(2)]
62510#[cfg_attr(
62511 not(target_arch = "arm"),
62512 stable(feature = "neon_intrinsics", since = "1.59.0")
62513)]
62514#[cfg_attr(
62515 target_arch = "arm",
62516 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62517)]
62518pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
62519 static_assert_uimm_bits!(LANE, 3);
62520 vst3_lane_s8::<LANE>(transmute(a), transmute(b))
62521}
62522#[doc = "Store multiple 3-element structures from three registers"]
62523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
62524#[doc = "## Safety"]
62525#[doc = " * Neon instrinsic unsafe"]
62526#[inline]
62527#[target_feature(enable = "neon")]
62528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62530#[cfg_attr(
62531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62532 assert_instr(st3, LANE = 0)
62533)]
62534#[rustc_legacy_const_generics(2)]
62535#[cfg_attr(
62536 not(target_arch = "arm"),
62537 stable(feature = "neon_intrinsics", since = "1.59.0")
62538)]
62539#[cfg_attr(
62540 target_arch = "arm",
62541 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62542)]
62543pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
62544 static_assert_uimm_bits!(LANE, 2);
62545 vst3_lane_s16::<LANE>(transmute(a), transmute(b))
62546}
62547#[doc = "Store multiple 3-element structures from three registers"]
62548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
62549#[doc = "## Safety"]
62550#[doc = " * Neon instrinsic unsafe"]
62551#[inline]
62552#[target_feature(enable = "neon")]
62553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
62555#[cfg_attr(
62556 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62557 assert_instr(st3, LANE = 0)
62558)]
62559#[rustc_legacy_const_generics(2)]
62560#[cfg_attr(
62561 not(target_arch = "arm"),
62562 stable(feature = "neon_intrinsics", since = "1.59.0")
62563)]
62564#[cfg_attr(
62565 target_arch = "arm",
62566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62567)]
62568pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
62569 static_assert_uimm_bits!(LANE, 3);
62570 vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
62571}
62572#[doc = "Store multiple 3-element structures from three registers"]
62573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
62574#[doc = "## Safety"]
62575#[doc = " * Neon instrinsic unsafe"]
62576#[inline]
62577#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
62578#[target_feature(enable = "neon,aes")]
62579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
62580#[cfg_attr(
62581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62582 assert_instr(nop)
62583)]
62584#[cfg_attr(
62585 not(target_arch = "arm"),
62586 stable(feature = "neon_intrinsics", since = "1.59.0")
62587)]
62588#[cfg_attr(
62589 target_arch = "arm",
62590 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62591)]
62592pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
62593 vst3_s64(transmute(a), transmute(b))
62594}
62595#[doc = "Store multiple 3-element structures from three registers"]
62596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
62597#[doc = "## Safety"]
62598#[doc = " * Neon instrinsic unsafe"]
62599#[inline]
62600#[target_feature(enable = "neon")]
62601#[cfg(not(target_arch = "arm"))]
62602#[stable(feature = "neon_intrinsics", since = "1.59.0")]
62603#[cfg_attr(test, assert_instr(nop))]
62604pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
62605 unsafe extern "unadjusted" {
62606 #[cfg_attr(
62607 any(target_arch = "aarch64", target_arch = "arm64ec"),
62608 link_name = "llvm.aarch64.neon.st3.v1i64.p0i8"
62609 )]
62610 fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8);
62611 }
62612 _vst3_s64(b.0, b.1, b.2, a as _)
62613}
62614#[doc = "Store multiple 3-element structures from three registers"]
62615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
62616#[doc = "## Safety"]
62617#[doc = " * Neon instrinsic unsafe"]
62618#[inline]
62619#[cfg(target_arch = "arm")]
62620#[target_feature(enable = "neon,v7")]
62621#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62622#[cfg_attr(test, assert_instr(nop))]
62623pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
62624 unsafe extern "unadjusted" {
62625 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v1i64")]
62626 fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32);
62627 }
62628 _vst3_s64(a as _, b.0, b.1, b.2, 8)
62629}
62630#[doc = "Store multiple 3-element structures from three registers"]
62631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
62632#[doc = "## Safety"]
62633#[doc = " * Neon instrinsic unsafe"]
62634#[inline]
62635#[target_feature(enable = "neon")]
62636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
62638#[cfg_attr(
62639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62640 assert_instr(nop)
62641)]
62642#[cfg_attr(
62643 not(target_arch = "arm"),
62644 stable(feature = "neon_intrinsics", since = "1.59.0")
62645)]
62646#[cfg_attr(
62647 target_arch = "arm",
62648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62649)]
62650pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
62651 vst3_s64(transmute(a), transmute(b))
62652}
62653#[doc = "Store multiple 3-element structures from three registers"]
62654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
62655#[doc = "## Safety"]
62656#[doc = " * Neon instrinsic unsafe"]
62657#[inline]
62658#[target_feature(enable = "neon")]
62659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62661#[cfg_attr(
62662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62663 assert_instr(st3)
62664)]
62665#[cfg_attr(
62666 not(target_arch = "arm"),
62667 stable(feature = "neon_intrinsics", since = "1.59.0")
62668)]
62669#[cfg_attr(
62670 target_arch = "arm",
62671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62672)]
62673pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
62674 vst3_s8(transmute(a), transmute(b))
62675}
62676#[doc = "Store multiple 3-element structures from three registers"]
62677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
62678#[doc = "## Safety"]
62679#[doc = " * Neon instrinsic unsafe"]
62680#[inline]
62681#[target_feature(enable = "neon")]
62682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62684#[cfg_attr(
62685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62686 assert_instr(st3)
62687)]
62688#[cfg_attr(
62689 not(target_arch = "arm"),
62690 stable(feature = "neon_intrinsics", since = "1.59.0")
62691)]
62692#[cfg_attr(
62693 target_arch = "arm",
62694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62695)]
62696pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
62697 vst3q_s8(transmute(a), transmute(b))
62698}
62699#[doc = "Store multiple 3-element structures from three registers"]
62700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
62701#[doc = "## Safety"]
62702#[doc = " * Neon instrinsic unsafe"]
62703#[inline]
62704#[target_feature(enable = "neon")]
62705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62707#[cfg_attr(
62708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62709 assert_instr(st3)
62710)]
62711#[cfg_attr(
62712 not(target_arch = "arm"),
62713 stable(feature = "neon_intrinsics", since = "1.59.0")
62714)]
62715#[cfg_attr(
62716 target_arch = "arm",
62717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62718)]
62719pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
62720 vst3_s16(transmute(a), transmute(b))
62721}
62722#[doc = "Store multiple 3-element structures from three registers"]
62723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
62724#[doc = "## Safety"]
62725#[doc = " * Neon instrinsic unsafe"]
62726#[inline]
62727#[target_feature(enable = "neon")]
62728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62730#[cfg_attr(
62731 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62732 assert_instr(st3)
62733)]
62734#[cfg_attr(
62735 not(target_arch = "arm"),
62736 stable(feature = "neon_intrinsics", since = "1.59.0")
62737)]
62738#[cfg_attr(
62739 target_arch = "arm",
62740 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62741)]
62742pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
62743 vst3q_s16(transmute(a), transmute(b))
62744}
62745#[doc = "Store multiple 3-element structures from three registers"]
62746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
62747#[doc = "## Safety"]
62748#[doc = " * Neon instrinsic unsafe"]
62749#[inline]
62750#[target_feature(enable = "neon")]
62751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62753#[cfg_attr(
62754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62755 assert_instr(st3)
62756)]
62757#[cfg_attr(
62758 not(target_arch = "arm"),
62759 stable(feature = "neon_intrinsics", since = "1.59.0")
62760)]
62761#[cfg_attr(
62762 target_arch = "arm",
62763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62764)]
62765pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
62766 vst3_s32(transmute(a), transmute(b))
62767}
62768#[doc = "Store multiple 3-element structures from three registers"]
62769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
62770#[doc = "## Safety"]
62771#[doc = " * Neon instrinsic unsafe"]
62772#[inline]
62773#[target_feature(enable = "neon")]
62774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62776#[cfg_attr(
62777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62778 assert_instr(st3)
62779)]
62780#[cfg_attr(
62781 not(target_arch = "arm"),
62782 stable(feature = "neon_intrinsics", since = "1.59.0")
62783)]
62784#[cfg_attr(
62785 target_arch = "arm",
62786 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62787)]
62788pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
62789 vst3q_s32(transmute(a), transmute(b))
62790}
62791#[doc = "Store multiple 3-element structures from three registers"]
62792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
62793#[doc = "## Safety"]
62794#[doc = " * Neon instrinsic unsafe"]
62795#[inline]
62796#[target_feature(enable = "neon")]
62797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62799#[cfg_attr(
62800 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62801 assert_instr(st3)
62802)]
62803#[cfg_attr(
62804 not(target_arch = "arm"),
62805 stable(feature = "neon_intrinsics", since = "1.59.0")
62806)]
62807#[cfg_attr(
62808 target_arch = "arm",
62809 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62810)]
62811pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
62812 vst3_s8(transmute(a), transmute(b))
62813}
62814#[doc = "Store multiple 3-element structures from three registers"]
62815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
62816#[doc = "## Safety"]
62817#[doc = " * Neon instrinsic unsafe"]
62818#[inline]
62819#[target_feature(enable = "neon")]
62820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62822#[cfg_attr(
62823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62824 assert_instr(st3)
62825)]
62826#[cfg_attr(
62827 not(target_arch = "arm"),
62828 stable(feature = "neon_intrinsics", since = "1.59.0")
62829)]
62830#[cfg_attr(
62831 target_arch = "arm",
62832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62833)]
62834pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
62835 vst3q_s8(transmute(a), transmute(b))
62836}
62837#[doc = "Store multiple 3-element structures from three registers"]
62838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
62839#[doc = "## Safety"]
62840#[doc = " * Neon instrinsic unsafe"]
62841#[inline]
62842#[target_feature(enable = "neon")]
62843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62845#[cfg_attr(
62846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62847 assert_instr(st3)
62848)]
62849#[cfg_attr(
62850 not(target_arch = "arm"),
62851 stable(feature = "neon_intrinsics", since = "1.59.0")
62852)]
62853#[cfg_attr(
62854 target_arch = "arm",
62855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62856)]
62857pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
62858 vst3_s16(transmute(a), transmute(b))
62859}
62860#[doc = "Store multiple 3-element structures from three registers"]
62861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
62862#[doc = "## Safety"]
62863#[doc = " * Neon instrinsic unsafe"]
62864#[inline]
62865#[target_feature(enable = "neon")]
62866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
62868#[cfg_attr(
62869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62870 assert_instr(st3)
62871)]
62872#[cfg_attr(
62873 not(target_arch = "arm"),
62874 stable(feature = "neon_intrinsics", since = "1.59.0")
62875)]
62876#[cfg_attr(
62877 target_arch = "arm",
62878 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62879)]
62880pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
62881 vst3q_s16(transmute(a), transmute(b))
62882}
62883#[doc = "Store multiple 4-element structures from four registers"]
62884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
62885#[doc = "## Safety"]
62886#[doc = " * Neon instrinsic unsafe"]
62887#[inline]
62888#[cfg(target_arch = "arm")]
62889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62890#[target_feature(enable = "neon,fp16")]
62891#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62892#[cfg_attr(test, assert_instr(vst4))]
62893pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
62894 unsafe extern "unadjusted" {
62895 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f16")]
62896 fn _vst4_f16(
62897 ptr: *mut i8,
62898 a: float16x4_t,
62899 b: float16x4_t,
62900 c: float16x4_t,
62901 d: float16x4_t,
62902 size: i32,
62903 );
62904 }
62905 _vst4_f16(a as _, b.0, b.1, b.2, b.3, 2)
62906}
62907#[doc = "Store multiple 4-element structures from four registers"]
62908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
62909#[doc = "## Safety"]
62910#[doc = " * Neon instrinsic unsafe"]
62911#[inline]
62912#[cfg(target_arch = "arm")]
62913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62914#[target_feature(enable = "neon,fp16")]
62915#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62916#[cfg_attr(test, assert_instr(vst4))]
62917pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
62918 unsafe extern "unadjusted" {
62919 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8f16")]
62920 fn _vst4q_f16(
62921 ptr: *mut i8,
62922 a: float16x8_t,
62923 b: float16x8_t,
62924 c: float16x8_t,
62925 d: float16x8_t,
62926 size: i32,
62927 );
62928 }
62929 _vst4q_f16(a as _, b.0, b.1, b.2, b.3, 2)
62930}
62931#[doc = "Store multiple 4-element structures from four registers"]
62932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
62933#[doc = "## Safety"]
62934#[doc = " * Neon instrinsic unsafe"]
62935#[inline]
62936#[cfg(not(target_arch = "arm"))]
62937#[target_feature(enable = "neon,fp16")]
62938#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62939#[cfg_attr(test, assert_instr(st4))]
62940pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
62941 unsafe extern "unadjusted" {
62942 #[cfg_attr(
62943 any(target_arch = "aarch64", target_arch = "arm64ec"),
62944 link_name = "llvm.aarch64.neon.st4.v4f16.p0i8"
62945 )]
62946 fn _vst4_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, d: float16x4_t, ptr: *mut i8);
62947 }
62948 _vst4_f16(b.0, b.1, b.2, b.3, a as _)
62949}
62950#[doc = "Store multiple 4-element structures from four registers"]
62951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
62952#[doc = "## Safety"]
62953#[doc = " * Neon instrinsic unsafe"]
62954#[inline]
62955#[cfg(not(target_arch = "arm"))]
62956#[target_feature(enable = "neon,fp16")]
62957#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
62958#[cfg_attr(test, assert_instr(st4))]
62959pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
62960 unsafe extern "unadjusted" {
62961 #[cfg_attr(
62962 any(target_arch = "aarch64", target_arch = "arm64ec"),
62963 link_name = "llvm.aarch64.neon.st4.v8f16.p0i8"
62964 )]
62965 fn _vst4q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, d: float16x8_t, ptr: *mut i8);
62966 }
62967 _vst4q_f16(b.0, b.1, b.2, b.3, a as _)
62968}
62969#[doc = "Store multiple 4-element structures from four registers"]
62970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
62971#[doc = "## Safety"]
62972#[doc = " * Neon instrinsic unsafe"]
62973#[inline]
62974#[cfg(target_arch = "arm")]
62975#[target_feature(enable = "neon,v7")]
62976#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62977#[cfg_attr(test, assert_instr(vst4))]
62978pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
62979 unsafe extern "unadjusted" {
62980 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2f32")]
62981 fn _vst4_f32(
62982 ptr: *mut i8,
62983 a: float32x2_t,
62984 b: float32x2_t,
62985 c: float32x2_t,
62986 d: float32x2_t,
62987 size: i32,
62988 );
62989 }
62990 _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4)
62991}
62992#[doc = "Store multiple 4-element structures from four registers"]
62993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
62994#[doc = "## Safety"]
62995#[doc = " * Neon instrinsic unsafe"]
62996#[inline]
62997#[cfg(target_arch = "arm")]
62998#[target_feature(enable = "neon,v7")]
62999#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63000#[cfg_attr(test, assert_instr(vst4))]
63001pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
63002 unsafe extern "unadjusted" {
63003 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f32")]
63004 fn _vst4q_f32(
63005 ptr: *mut i8,
63006 a: float32x4_t,
63007 b: float32x4_t,
63008 c: float32x4_t,
63009 d: float32x4_t,
63010 size: i32,
63011 );
63012 }
63013 _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4)
63014}
63015#[doc = "Store multiple 4-element structures from four registers"]
63016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
63017#[doc = "## Safety"]
63018#[doc = " * Neon instrinsic unsafe"]
63019#[inline]
63020#[cfg(target_arch = "arm")]
63021#[target_feature(enable = "neon,v7")]
63022#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63023#[cfg_attr(test, assert_instr(vst4))]
63024pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
63025 unsafe extern "unadjusted" {
63026 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i8")]
63027 fn _vst4_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32);
63028 }
63029 _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1)
63030}
63031#[doc = "Store multiple 4-element structures from four registers"]
63032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
63033#[doc = "## Safety"]
63034#[doc = " * Neon instrinsic unsafe"]
63035#[inline]
63036#[cfg(target_arch = "arm")]
63037#[target_feature(enable = "neon,v7")]
63038#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63039#[cfg_attr(test, assert_instr(vst4))]
63040pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
63041 unsafe extern "unadjusted" {
63042 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v16i8")]
63043 fn _vst4q_s8(
63044 ptr: *mut i8,
63045 a: int8x16_t,
63046 b: int8x16_t,
63047 c: int8x16_t,
63048 d: int8x16_t,
63049 size: i32,
63050 );
63051 }
63052 _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1)
63053}
63054#[doc = "Store multiple 4-element structures from four registers"]
63055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
63056#[doc = "## Safety"]
63057#[doc = " * Neon instrinsic unsafe"]
63058#[inline]
63059#[cfg(target_arch = "arm")]
63060#[target_feature(enable = "neon,v7")]
63061#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63062#[cfg_attr(test, assert_instr(vst4))]
63063pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
63064 unsafe extern "unadjusted" {
63065 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i16")]
63066 fn _vst4_s16(
63067 ptr: *mut i8,
63068 a: int16x4_t,
63069 b: int16x4_t,
63070 c: int16x4_t,
63071 d: int16x4_t,
63072 size: i32,
63073 );
63074 }
63075 _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2)
63076}
63077#[doc = "Store multiple 4-element structures from four registers"]
63078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
63079#[doc = "## Safety"]
63080#[doc = " * Neon instrinsic unsafe"]
63081#[inline]
63082#[cfg(target_arch = "arm")]
63083#[target_feature(enable = "neon,v7")]
63084#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63085#[cfg_attr(test, assert_instr(vst4))]
63086pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
63087 unsafe extern "unadjusted" {
63088 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i16")]
63089 fn _vst4q_s16(
63090 ptr: *mut i8,
63091 a: int16x8_t,
63092 b: int16x8_t,
63093 c: int16x8_t,
63094 d: int16x8_t,
63095 size: i32,
63096 );
63097 }
63098 _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2)
63099}
63100#[doc = "Store multiple 4-element structures from four registers"]
63101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
63102#[doc = "## Safety"]
63103#[doc = " * Neon instrinsic unsafe"]
63104#[inline]
63105#[cfg(target_arch = "arm")]
63106#[target_feature(enable = "neon,v7")]
63107#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63108#[cfg_attr(test, assert_instr(vst4))]
63109pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
63110 unsafe extern "unadjusted" {
63111 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2i32")]
63112 fn _vst4_s32(
63113 ptr: *mut i8,
63114 a: int32x2_t,
63115 b: int32x2_t,
63116 c: int32x2_t,
63117 d: int32x2_t,
63118 size: i32,
63119 );
63120 }
63121 _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4)
63122}
63123#[doc = "Store multiple 4-element structures from four registers"]
63124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
63125#[doc = "## Safety"]
63126#[doc = " * Neon instrinsic unsafe"]
63127#[inline]
63128#[cfg(target_arch = "arm")]
63129#[target_feature(enable = "neon,v7")]
63130#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63131#[cfg_attr(test, assert_instr(vst4))]
63132pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
63133 unsafe extern "unadjusted" {
63134 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i32")]
63135 fn _vst4q_s32(
63136 ptr: *mut i8,
63137 a: int32x4_t,
63138 b: int32x4_t,
63139 c: int32x4_t,
63140 d: int32x4_t,
63141 size: i32,
63142 );
63143 }
63144 _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4)
63145}
63146#[doc = "Store multiple 4-element structures from four registers"]
63147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
63148#[doc = "## Safety"]
63149#[doc = " * Neon instrinsic unsafe"]
63150#[inline]
63151#[target_feature(enable = "neon")]
63152#[cfg(not(target_arch = "arm"))]
63153#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63154#[cfg_attr(test, assert_instr(st4))]
63155pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
63156 unsafe extern "unadjusted" {
63157 #[cfg_attr(
63158 any(target_arch = "aarch64", target_arch = "arm64ec"),
63159 link_name = "llvm.aarch64.neon.st4.v2f32.p0i8"
63160 )]
63161 fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8);
63162 }
63163 _vst4_f32(b.0, b.1, b.2, b.3, a as _)
63164}
63165#[doc = "Store multiple 4-element structures from four registers"]
63166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
63167#[doc = "## Safety"]
63168#[doc = " * Neon instrinsic unsafe"]
63169#[inline]
63170#[target_feature(enable = "neon")]
63171#[cfg(not(target_arch = "arm"))]
63172#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63173#[cfg_attr(test, assert_instr(st4))]
63174pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
63175 unsafe extern "unadjusted" {
63176 #[cfg_attr(
63177 any(target_arch = "aarch64", target_arch = "arm64ec"),
63178 link_name = "llvm.aarch64.neon.st4.v4f32.p0i8"
63179 )]
63180 fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8);
63181 }
63182 _vst4q_f32(b.0, b.1, b.2, b.3, a as _)
63183}
63184#[doc = "Store multiple 4-element structures from four registers"]
63185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
63186#[doc = "## Safety"]
63187#[doc = " * Neon instrinsic unsafe"]
63188#[inline]
63189#[target_feature(enable = "neon")]
63190#[cfg(not(target_arch = "arm"))]
63191#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63192#[cfg_attr(test, assert_instr(st4))]
63193pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
63194 unsafe extern "unadjusted" {
63195 #[cfg_attr(
63196 any(target_arch = "aarch64", target_arch = "arm64ec"),
63197 link_name = "llvm.aarch64.neon.st4.v8i8.p0i8"
63198 )]
63199 fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
63200 }
63201 _vst4_s8(b.0, b.1, b.2, b.3, a as _)
63202}
63203#[doc = "Store multiple 4-element structures from four registers"]
63204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
63205#[doc = "## Safety"]
63206#[doc = " * Neon instrinsic unsafe"]
63207#[inline]
63208#[target_feature(enable = "neon")]
63209#[cfg(not(target_arch = "arm"))]
63210#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63211#[cfg_attr(test, assert_instr(st4))]
63212pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
63213 unsafe extern "unadjusted" {
63214 #[cfg_attr(
63215 any(target_arch = "aarch64", target_arch = "arm64ec"),
63216 link_name = "llvm.aarch64.neon.st4.v16i8.p0i8"
63217 )]
63218 fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
63219 }
63220 _vst4q_s8(b.0, b.1, b.2, b.3, a as _)
63221}
63222#[doc = "Store multiple 4-element structures from four registers"]
63223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
63224#[doc = "## Safety"]
63225#[doc = " * Neon instrinsic unsafe"]
63226#[inline]
63227#[target_feature(enable = "neon")]
63228#[cfg(not(target_arch = "arm"))]
63229#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63230#[cfg_attr(test, assert_instr(st4))]
63231pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
63232 unsafe extern "unadjusted" {
63233 #[cfg_attr(
63234 any(target_arch = "aarch64", target_arch = "arm64ec"),
63235 link_name = "llvm.aarch64.neon.st4.v4i16.p0i8"
63236 )]
63237 fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8);
63238 }
63239 _vst4_s16(b.0, b.1, b.2, b.3, a as _)
63240}
63241#[doc = "Store multiple 4-element structures from four registers"]
63242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
63243#[doc = "## Safety"]
63244#[doc = " * Neon instrinsic unsafe"]
63245#[inline]
63246#[target_feature(enable = "neon")]
63247#[cfg(not(target_arch = "arm"))]
63248#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63249#[cfg_attr(test, assert_instr(st4))]
63250pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
63251 unsafe extern "unadjusted" {
63252 #[cfg_attr(
63253 any(target_arch = "aarch64", target_arch = "arm64ec"),
63254 link_name = "llvm.aarch64.neon.st4.v8i16.p0i8"
63255 )]
63256 fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8);
63257 }
63258 _vst4q_s16(b.0, b.1, b.2, b.3, a as _)
63259}
63260#[doc = "Store multiple 4-element structures from four registers"]
63261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
63262#[doc = "## Safety"]
63263#[doc = " * Neon instrinsic unsafe"]
63264#[inline]
63265#[target_feature(enable = "neon")]
63266#[cfg(not(target_arch = "arm"))]
63267#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63268#[cfg_attr(test, assert_instr(st4))]
63269pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
63270 unsafe extern "unadjusted" {
63271 #[cfg_attr(
63272 any(target_arch = "aarch64", target_arch = "arm64ec"),
63273 link_name = "llvm.aarch64.neon.st4.v2i32.p0i8"
63274 )]
63275 fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8);
63276 }
63277 _vst4_s32(b.0, b.1, b.2, b.3, a as _)
63278}
63279#[doc = "Store multiple 4-element structures from four registers"]
63280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
63281#[doc = "## Safety"]
63282#[doc = " * Neon instrinsic unsafe"]
63283#[inline]
63284#[target_feature(enable = "neon")]
63285#[cfg(not(target_arch = "arm"))]
63286#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63287#[cfg_attr(test, assert_instr(st4))]
63288pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
63289 unsafe extern "unadjusted" {
63290 #[cfg_attr(
63291 any(target_arch = "aarch64", target_arch = "arm64ec"),
63292 link_name = "llvm.aarch64.neon.st4.v4i32.p0i8"
63293 )]
63294 fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8);
63295 }
63296 _vst4q_s32(b.0, b.1, b.2, b.3, a as _)
63297}
63298#[doc = "Store multiple 4-element structures from four registers"]
63299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
63300#[doc = "## Safety"]
63301#[doc = " * Neon instrinsic unsafe"]
63302#[inline]
63303#[cfg(target_arch = "arm")]
63304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63305#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63306#[rustc_legacy_const_generics(2)]
63307#[target_feature(enable = "neon,fp16")]
63308#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63309pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
63310 static_assert_uimm_bits!(LANE, 2);
63311 unsafe extern "unadjusted" {
63312 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f16")]
63313 fn _vst4_lane_f16(
63314 ptr: *mut i8,
63315 a: float16x4_t,
63316 b: float16x4_t,
63317 c: float16x4_t,
63318 d: float16x4_t,
63319 n: i32,
63320 size: i32,
63321 );
63322 }
63323 _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
63324}
63325#[doc = "Store multiple 4-element structures from four registers"]
63326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
63327#[doc = "## Safety"]
63328#[doc = " * Neon instrinsic unsafe"]
63329#[inline]
63330#[cfg(target_arch = "arm")]
63331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63332#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63333#[rustc_legacy_const_generics(2)]
63334#[target_feature(enable = "neon,fp16")]
63335#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63336pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
63337 static_assert_uimm_bits!(LANE, 3);
63338 unsafe extern "unadjusted" {
63339 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8f16")]
63340 fn _vst4q_lane_f16(
63341 ptr: *mut i8,
63342 a: float16x8_t,
63343 b: float16x8_t,
63344 c: float16x8_t,
63345 d: float16x8_t,
63346 n: i32,
63347 size: i32,
63348 );
63349 }
63350 _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
63351}
63352#[doc = "Store multiple 4-element structures from four registers"]
63353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
63354#[doc = "## Safety"]
63355#[doc = " * Neon instrinsic unsafe"]
63356#[inline]
63357#[cfg(not(target_arch = "arm"))]
63358#[rustc_legacy_const_generics(2)]
63359#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63360#[target_feature(enable = "neon,fp16")]
63361#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63362pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
63363 static_assert_uimm_bits!(LANE, 2);
63364 unsafe extern "unadjusted" {
63365 #[cfg_attr(
63366 any(target_arch = "aarch64", target_arch = "arm64ec"),
63367 link_name = "llvm.aarch64.neon.st4lane.v4f16.p0i8"
63368 )]
63369 fn _vst4_lane_f16(
63370 a: float16x4_t,
63371 b: float16x4_t,
63372 c: float16x4_t,
63373 d: float16x4_t,
63374 n: i64,
63375 ptr: *mut i8,
63376 );
63377 }
63378 _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63379}
63380#[doc = "Store multiple 4-element structures from four registers"]
63381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
63382#[doc = "## Safety"]
63383#[doc = " * Neon instrinsic unsafe"]
63384#[inline]
63385#[cfg(not(target_arch = "arm"))]
63386#[rustc_legacy_const_generics(2)]
63387#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63388#[target_feature(enable = "neon,fp16")]
63389#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63390pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
63391 static_assert_uimm_bits!(LANE, 3);
63392 unsafe extern "unadjusted" {
63393 #[cfg_attr(
63394 any(target_arch = "aarch64", target_arch = "arm64ec"),
63395 link_name = "llvm.aarch64.neon.st4lane.v8f16.p0i8"
63396 )]
63397 fn _vst4q_lane_f16(
63398 a: float16x8_t,
63399 b: float16x8_t,
63400 c: float16x8_t,
63401 d: float16x8_t,
63402 n: i64,
63403 ptr: *mut i8,
63404 );
63405 }
63406 _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63407}
63408#[doc = "Store multiple 4-element structures from four registers"]
63409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
63410#[doc = "## Safety"]
63411#[doc = " * Neon instrinsic unsafe"]
63412#[inline]
63413#[cfg(target_arch = "arm")]
63414#[target_feature(enable = "neon,v7")]
63415#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63416#[rustc_legacy_const_generics(2)]
63417#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63418pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
63419 static_assert_uimm_bits!(LANE, 1);
63420 unsafe extern "unadjusted" {
63421 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2f32")]
63422 fn _vst4_lane_f32(
63423 ptr: *mut i8,
63424 a: float32x2_t,
63425 b: float32x2_t,
63426 c: float32x2_t,
63427 d: float32x2_t,
63428 n: i32,
63429 size: i32,
63430 );
63431 }
63432 _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
63433}
63434#[doc = "Store multiple 4-element structures from four registers"]
63435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
63436#[doc = "## Safety"]
63437#[doc = " * Neon instrinsic unsafe"]
63438#[inline]
63439#[cfg(target_arch = "arm")]
63440#[target_feature(enable = "neon,v7")]
63441#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63442#[rustc_legacy_const_generics(2)]
63443#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63444pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
63445 static_assert_uimm_bits!(LANE, 2);
63446 unsafe extern "unadjusted" {
63447 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f32")]
63448 fn _vst4q_lane_f32(
63449 ptr: *mut i8,
63450 a: float32x4_t,
63451 b: float32x4_t,
63452 c: float32x4_t,
63453 d: float32x4_t,
63454 n: i32,
63455 size: i32,
63456 );
63457 }
63458 _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
63459}
63460#[doc = "Store multiple 4-element structures from four registers"]
63461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
63462#[doc = "## Safety"]
63463#[doc = " * Neon instrinsic unsafe"]
63464#[inline]
63465#[cfg(target_arch = "arm")]
63466#[target_feature(enable = "neon,v7")]
63467#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63468#[rustc_legacy_const_generics(2)]
63469#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63470pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
63471 static_assert_uimm_bits!(LANE, 3);
63472 unsafe extern "unadjusted" {
63473 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i8")]
63474 fn _vst4_lane_s8(
63475 ptr: *mut i8,
63476 a: int8x8_t,
63477 b: int8x8_t,
63478 c: int8x8_t,
63479 d: int8x8_t,
63480 n: i32,
63481 size: i32,
63482 );
63483 }
63484 _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
63485}
63486#[doc = "Store multiple 4-element structures from four registers"]
63487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
63488#[doc = "## Safety"]
63489#[doc = " * Neon instrinsic unsafe"]
63490#[inline]
63491#[cfg(target_arch = "arm")]
63492#[target_feature(enable = "neon,v7")]
63493#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63494#[rustc_legacy_const_generics(2)]
63495#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63496pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
63497 static_assert_uimm_bits!(LANE, 2);
63498 unsafe extern "unadjusted" {
63499 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i16")]
63500 fn _vst4_lane_s16(
63501 ptr: *mut i8,
63502 a: int16x4_t,
63503 b: int16x4_t,
63504 c: int16x4_t,
63505 d: int16x4_t,
63506 n: i32,
63507 size: i32,
63508 );
63509 }
63510 _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
63511}
63512#[doc = "Store multiple 4-element structures from four registers"]
63513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
63514#[doc = "## Safety"]
63515#[doc = " * Neon instrinsic unsafe"]
63516#[inline]
63517#[cfg(target_arch = "arm")]
63518#[target_feature(enable = "neon,v7")]
63519#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63520#[rustc_legacy_const_generics(2)]
63521#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63522pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
63523 static_assert_uimm_bits!(LANE, 3);
63524 unsafe extern "unadjusted" {
63525 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i16")]
63526 fn _vst4q_lane_s16(
63527 ptr: *mut i8,
63528 a: int16x8_t,
63529 b: int16x8_t,
63530 c: int16x8_t,
63531 d: int16x8_t,
63532 n: i32,
63533 size: i32,
63534 );
63535 }
63536 _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
63537}
63538#[doc = "Store multiple 4-element structures from four registers"]
63539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
63540#[doc = "## Safety"]
63541#[doc = " * Neon instrinsic unsafe"]
63542#[inline]
63543#[cfg(target_arch = "arm")]
63544#[target_feature(enable = "neon,v7")]
63545#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63546#[rustc_legacy_const_generics(2)]
63547#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63548pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
63549 static_assert_uimm_bits!(LANE, 1);
63550 unsafe extern "unadjusted" {
63551 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2i32")]
63552 fn _vst4_lane_s32(
63553 ptr: *mut i8,
63554 a: int32x2_t,
63555 b: int32x2_t,
63556 c: int32x2_t,
63557 d: int32x2_t,
63558 n: i32,
63559 size: i32,
63560 );
63561 }
63562 _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
63563}
63564#[doc = "Store multiple 4-element structures from four registers"]
63565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
63566#[doc = "## Safety"]
63567#[doc = " * Neon instrinsic unsafe"]
63568#[inline]
63569#[cfg(target_arch = "arm")]
63570#[target_feature(enable = "neon,v7")]
63571#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
63572#[rustc_legacy_const_generics(2)]
63573#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63574pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
63575 static_assert_uimm_bits!(LANE, 2);
63576 unsafe extern "unadjusted" {
63577 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i32")]
63578 fn _vst4q_lane_s32(
63579 ptr: *mut i8,
63580 a: int32x4_t,
63581 b: int32x4_t,
63582 c: int32x4_t,
63583 d: int32x4_t,
63584 n: i32,
63585 size: i32,
63586 );
63587 }
63588 _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
63589}
63590#[doc = "Store multiple 4-element structures from four registers"]
63591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
63592#[doc = "## Safety"]
63593#[doc = " * Neon instrinsic unsafe"]
63594#[inline]
63595#[target_feature(enable = "neon")]
63596#[cfg(not(target_arch = "arm"))]
63597#[rustc_legacy_const_generics(2)]
63598#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63599#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63600pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
63601 static_assert_uimm_bits!(LANE, 1);
63602 unsafe extern "unadjusted" {
63603 #[cfg_attr(
63604 any(target_arch = "aarch64", target_arch = "arm64ec"),
63605 link_name = "llvm.aarch64.neon.st4lane.v2f32.p0i8"
63606 )]
63607 fn _vst4_lane_f32(
63608 a: float32x2_t,
63609 b: float32x2_t,
63610 c: float32x2_t,
63611 d: float32x2_t,
63612 n: i64,
63613 ptr: *mut i8,
63614 );
63615 }
63616 _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63617}
63618#[doc = "Store multiple 4-element structures from four registers"]
63619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
63620#[doc = "## Safety"]
63621#[doc = " * Neon instrinsic unsafe"]
63622#[inline]
63623#[target_feature(enable = "neon")]
63624#[cfg(not(target_arch = "arm"))]
63625#[rustc_legacy_const_generics(2)]
63626#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63627#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63628pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
63629 static_assert_uimm_bits!(LANE, 2);
63630 unsafe extern "unadjusted" {
63631 #[cfg_attr(
63632 any(target_arch = "aarch64", target_arch = "arm64ec"),
63633 link_name = "llvm.aarch64.neon.st4lane.v4f32.p0i8"
63634 )]
63635 fn _vst4q_lane_f32(
63636 a: float32x4_t,
63637 b: float32x4_t,
63638 c: float32x4_t,
63639 d: float32x4_t,
63640 n: i64,
63641 ptr: *mut i8,
63642 );
63643 }
63644 _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63645}
63646#[doc = "Store multiple 4-element structures from four registers"]
63647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
63648#[doc = "## Safety"]
63649#[doc = " * Neon instrinsic unsafe"]
63650#[inline]
63651#[target_feature(enable = "neon")]
63652#[cfg(not(target_arch = "arm"))]
63653#[rustc_legacy_const_generics(2)]
63654#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63655#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63656pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
63657 static_assert_uimm_bits!(LANE, 3);
63658 unsafe extern "unadjusted" {
63659 #[cfg_attr(
63660 any(target_arch = "aarch64", target_arch = "arm64ec"),
63661 link_name = "llvm.aarch64.neon.st4lane.v8i8.p0i8"
63662 )]
63663 fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8);
63664 }
63665 _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63666}
63667#[doc = "Store multiple 4-element structures from four registers"]
63668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
63669#[doc = "## Safety"]
63670#[doc = " * Neon instrinsic unsafe"]
63671#[inline]
63672#[target_feature(enable = "neon")]
63673#[cfg(not(target_arch = "arm"))]
63674#[rustc_legacy_const_generics(2)]
63675#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63676#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63677pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
63678 static_assert_uimm_bits!(LANE, 2);
63679 unsafe extern "unadjusted" {
63680 #[cfg_attr(
63681 any(target_arch = "aarch64", target_arch = "arm64ec"),
63682 link_name = "llvm.aarch64.neon.st4lane.v4i16.p0i8"
63683 )]
63684 fn _vst4_lane_s16(
63685 a: int16x4_t,
63686 b: int16x4_t,
63687 c: int16x4_t,
63688 d: int16x4_t,
63689 n: i64,
63690 ptr: *mut i8,
63691 );
63692 }
63693 _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63694}
63695#[doc = "Store multiple 4-element structures from four registers"]
63696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
63697#[doc = "## Safety"]
63698#[doc = " * Neon instrinsic unsafe"]
63699#[inline]
63700#[target_feature(enable = "neon")]
63701#[cfg(not(target_arch = "arm"))]
63702#[rustc_legacy_const_generics(2)]
63703#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63704#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63705pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
63706 static_assert_uimm_bits!(LANE, 3);
63707 unsafe extern "unadjusted" {
63708 #[cfg_attr(
63709 any(target_arch = "aarch64", target_arch = "arm64ec"),
63710 link_name = "llvm.aarch64.neon.st4lane.v8i16.p0i8"
63711 )]
63712 fn _vst4q_lane_s16(
63713 a: int16x8_t,
63714 b: int16x8_t,
63715 c: int16x8_t,
63716 d: int16x8_t,
63717 n: i64,
63718 ptr: *mut i8,
63719 );
63720 }
63721 _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63722}
63723#[doc = "Store multiple 4-element structures from four registers"]
63724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
63725#[doc = "## Safety"]
63726#[doc = " * Neon instrinsic unsafe"]
63727#[inline]
63728#[target_feature(enable = "neon")]
63729#[cfg(not(target_arch = "arm"))]
63730#[rustc_legacy_const_generics(2)]
63731#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63732#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63733pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
63734 static_assert_uimm_bits!(LANE, 1);
63735 unsafe extern "unadjusted" {
63736 #[cfg_attr(
63737 any(target_arch = "aarch64", target_arch = "arm64ec"),
63738 link_name = "llvm.aarch64.neon.st4lane.v2i32.p0i8"
63739 )]
63740 fn _vst4_lane_s32(
63741 a: int32x2_t,
63742 b: int32x2_t,
63743 c: int32x2_t,
63744 d: int32x2_t,
63745 n: i64,
63746 ptr: *mut i8,
63747 );
63748 }
63749 _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63750}
63751#[doc = "Store multiple 4-element structures from four registers"]
63752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
63753#[doc = "## Safety"]
63754#[doc = " * Neon instrinsic unsafe"]
63755#[inline]
63756#[target_feature(enable = "neon")]
63757#[cfg(not(target_arch = "arm"))]
63758#[rustc_legacy_const_generics(2)]
63759#[cfg_attr(test, assert_instr(st4, LANE = 0))]
63760#[stable(feature = "neon_intrinsics", since = "1.59.0")]
63761pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
63762 static_assert_uimm_bits!(LANE, 2);
63763 unsafe extern "unadjusted" {
63764 #[cfg_attr(
63765 any(target_arch = "aarch64", target_arch = "arm64ec"),
63766 link_name = "llvm.aarch64.neon.st4lane.v4i32.p0i8"
63767 )]
63768 fn _vst4q_lane_s32(
63769 a: int32x4_t,
63770 b: int32x4_t,
63771 c: int32x4_t,
63772 d: int32x4_t,
63773 n: i64,
63774 ptr: *mut i8,
63775 );
63776 }
63777 _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
63778}
63779#[doc = "Store multiple 4-element structures from four registers"]
63780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
63781#[doc = "## Safety"]
63782#[doc = " * Neon instrinsic unsafe"]
63783#[inline]
63784#[target_feature(enable = "neon")]
63785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63787#[cfg_attr(
63788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63789 assert_instr(st4, LANE = 0)
63790)]
63791#[rustc_legacy_const_generics(2)]
63792#[cfg_attr(
63793 not(target_arch = "arm"),
63794 stable(feature = "neon_intrinsics", since = "1.59.0")
63795)]
63796#[cfg_attr(
63797 target_arch = "arm",
63798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63799)]
63800pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
63801 static_assert_uimm_bits!(LANE, 3);
63802 vst4_lane_s8::<LANE>(transmute(a), transmute(b))
63803}
63804#[doc = "Store multiple 4-element structures from four registers"]
63805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
63806#[doc = "## Safety"]
63807#[doc = " * Neon instrinsic unsafe"]
63808#[inline]
63809#[target_feature(enable = "neon")]
63810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63812#[cfg_attr(
63813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63814 assert_instr(st4, LANE = 0)
63815)]
63816#[rustc_legacy_const_generics(2)]
63817#[cfg_attr(
63818 not(target_arch = "arm"),
63819 stable(feature = "neon_intrinsics", since = "1.59.0")
63820)]
63821#[cfg_attr(
63822 target_arch = "arm",
63823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63824)]
63825pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
63826 static_assert_uimm_bits!(LANE, 2);
63827 vst4_lane_s16::<LANE>(transmute(a), transmute(b))
63828}
63829#[doc = "Store multiple 4-element structures from four registers"]
63830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
63831#[doc = "## Safety"]
63832#[doc = " * Neon instrinsic unsafe"]
63833#[inline]
63834#[target_feature(enable = "neon")]
63835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63837#[cfg_attr(
63838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63839 assert_instr(st4, LANE = 0)
63840)]
63841#[rustc_legacy_const_generics(2)]
63842#[cfg_attr(
63843 not(target_arch = "arm"),
63844 stable(feature = "neon_intrinsics", since = "1.59.0")
63845)]
63846#[cfg_attr(
63847 target_arch = "arm",
63848 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63849)]
63850pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
63851 static_assert_uimm_bits!(LANE, 3);
63852 vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
63853}
63854#[doc = "Store multiple 4-element structures from four registers"]
63855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
63856#[doc = "## Safety"]
63857#[doc = " * Neon instrinsic unsafe"]
63858#[inline]
63859#[target_feature(enable = "neon")]
63860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63862#[cfg_attr(
63863 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63864 assert_instr(st4, LANE = 0)
63865)]
63866#[rustc_legacy_const_generics(2)]
63867#[cfg_attr(
63868 not(target_arch = "arm"),
63869 stable(feature = "neon_intrinsics", since = "1.59.0")
63870)]
63871#[cfg_attr(
63872 target_arch = "arm",
63873 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63874)]
63875pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
63876 static_assert_uimm_bits!(LANE, 1);
63877 vst4_lane_s32::<LANE>(transmute(a), transmute(b))
63878}
63879#[doc = "Store multiple 4-element structures from four registers"]
63880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
63881#[doc = "## Safety"]
63882#[doc = " * Neon instrinsic unsafe"]
63883#[inline]
63884#[target_feature(enable = "neon")]
63885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63887#[cfg_attr(
63888 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63889 assert_instr(st4, LANE = 0)
63890)]
63891#[rustc_legacy_const_generics(2)]
63892#[cfg_attr(
63893 not(target_arch = "arm"),
63894 stable(feature = "neon_intrinsics", since = "1.59.0")
63895)]
63896#[cfg_attr(
63897 target_arch = "arm",
63898 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63899)]
63900pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
63901 static_assert_uimm_bits!(LANE, 2);
63902 vst4q_lane_s32::<LANE>(transmute(a), transmute(b))
63903}
63904#[doc = "Store multiple 4-element structures from four registers"]
63905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
63906#[doc = "## Safety"]
63907#[doc = " * Neon instrinsic unsafe"]
63908#[inline]
63909#[target_feature(enable = "neon")]
63910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63912#[cfg_attr(
63913 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63914 assert_instr(st4, LANE = 0)
63915)]
63916#[rustc_legacy_const_generics(2)]
63917#[cfg_attr(
63918 not(target_arch = "arm"),
63919 stable(feature = "neon_intrinsics", since = "1.59.0")
63920)]
63921#[cfg_attr(
63922 target_arch = "arm",
63923 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63924)]
63925pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
63926 static_assert_uimm_bits!(LANE, 3);
63927 vst4_lane_s8::<LANE>(transmute(a), transmute(b))
63928}
63929#[doc = "Store multiple 4-element structures from four registers"]
63930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
63931#[doc = "## Safety"]
63932#[doc = " * Neon instrinsic unsafe"]
63933#[inline]
63934#[target_feature(enable = "neon")]
63935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63937#[cfg_attr(
63938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63939 assert_instr(st4, LANE = 0)
63940)]
63941#[rustc_legacy_const_generics(2)]
63942#[cfg_attr(
63943 not(target_arch = "arm"),
63944 stable(feature = "neon_intrinsics", since = "1.59.0")
63945)]
63946#[cfg_attr(
63947 target_arch = "arm",
63948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63949)]
63950pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
63951 static_assert_uimm_bits!(LANE, 2);
63952 vst4_lane_s16::<LANE>(transmute(a), transmute(b))
63953}
63954#[doc = "Store multiple 4-element structures from four registers"]
63955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
63956#[doc = "## Safety"]
63957#[doc = " * Neon instrinsic unsafe"]
63958#[inline]
63959#[target_feature(enable = "neon")]
63960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
63962#[cfg_attr(
63963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63964 assert_instr(st4, LANE = 0)
63965)]
63966#[rustc_legacy_const_generics(2)]
63967#[cfg_attr(
63968 not(target_arch = "arm"),
63969 stable(feature = "neon_intrinsics", since = "1.59.0")
63970)]
63971#[cfg_attr(
63972 target_arch = "arm",
63973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63974)]
63975pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
63976 static_assert_uimm_bits!(LANE, 3);
63977 vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
63978}
63979#[doc = "Store multiple 4-element structures from four registers"]
63980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
63981#[doc = "## Safety"]
63982#[doc = " * Neon instrinsic unsafe"]
63983#[inline]
63984#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
63985#[target_feature(enable = "neon,aes")]
63986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
63987#[cfg_attr(
63988 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63989 assert_instr(nop)
63990)]
63991#[cfg_attr(
63992 not(target_arch = "arm"),
63993 stable(feature = "neon_intrinsics", since = "1.59.0")
63994)]
63995#[cfg_attr(
63996 target_arch = "arm",
63997 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63998)]
63999pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
64000 vst4_s64(transmute(a), transmute(b))
64001}
64002#[doc = "Store multiple 4-element structures from four registers"]
64003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
64004#[doc = "## Safety"]
64005#[doc = " * Neon instrinsic unsafe"]
64006#[inline]
64007#[cfg(target_arch = "arm")]
64008#[target_feature(enable = "neon,v7")]
64009#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64010#[cfg_attr(test, assert_instr(nop))]
64011pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
64012 unsafe extern "unadjusted" {
64013 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v1i64")]
64014 fn _vst4_s64(
64015 ptr: *mut i8,
64016 a: int64x1_t,
64017 b: int64x1_t,
64018 c: int64x1_t,
64019 d: int64x1_t,
64020 size: i32,
64021 );
64022 }
64023 _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8)
64024}
64025#[doc = "Store multiple 4-element structures from four registers"]
64026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
64027#[doc = "## Safety"]
64028#[doc = " * Neon instrinsic unsafe"]
64029#[inline]
64030#[target_feature(enable = "neon")]
64031#[cfg(not(target_arch = "arm"))]
64032#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64033#[cfg_attr(test, assert_instr(nop))]
64034pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
64035 unsafe extern "unadjusted" {
64036 #[cfg_attr(
64037 any(target_arch = "aarch64", target_arch = "arm64ec"),
64038 link_name = "llvm.aarch64.neon.st4.v1i64.p0i8"
64039 )]
64040 fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8);
64041 }
64042 _vst4_s64(b.0, b.1, b.2, b.3, a as _)
64043}
64044#[doc = "Store multiple 4-element structures from four registers"]
64045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
64046#[doc = "## Safety"]
64047#[doc = " * Neon instrinsic unsafe"]
64048#[inline]
64049#[target_feature(enable = "neon")]
64050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
64052#[cfg_attr(
64053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64054 assert_instr(nop)
64055)]
64056#[cfg_attr(
64057 not(target_arch = "arm"),
64058 stable(feature = "neon_intrinsics", since = "1.59.0")
64059)]
64060#[cfg_attr(
64061 target_arch = "arm",
64062 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64063)]
64064pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
64065 vst4_s64(transmute(a), transmute(b))
64066}
64067#[doc = "Store multiple 4-element structures from four registers"]
64068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
64069#[doc = "## Safety"]
64070#[doc = " * Neon instrinsic unsafe"]
64071#[inline]
64072#[target_feature(enable = "neon")]
64073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64075#[cfg_attr(
64076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64077 assert_instr(st4)
64078)]
64079#[cfg_attr(
64080 not(target_arch = "arm"),
64081 stable(feature = "neon_intrinsics", since = "1.59.0")
64082)]
64083#[cfg_attr(
64084 target_arch = "arm",
64085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64086)]
64087pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
64088 vst4_s8(transmute(a), transmute(b))
64089}
64090#[doc = "Store multiple 4-element structures from four registers"]
64091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
64092#[doc = "## Safety"]
64093#[doc = " * Neon instrinsic unsafe"]
64094#[inline]
64095#[target_feature(enable = "neon")]
64096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64098#[cfg_attr(
64099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64100 assert_instr(st4)
64101)]
64102#[cfg_attr(
64103 not(target_arch = "arm"),
64104 stable(feature = "neon_intrinsics", since = "1.59.0")
64105)]
64106#[cfg_attr(
64107 target_arch = "arm",
64108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64109)]
64110pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
64111 vst4q_s8(transmute(a), transmute(b))
64112}
64113#[doc = "Store multiple 4-element structures from four registers"]
64114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
64115#[doc = "## Safety"]
64116#[doc = " * Neon instrinsic unsafe"]
64117#[inline]
64118#[target_feature(enable = "neon")]
64119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64121#[cfg_attr(
64122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64123 assert_instr(st4)
64124)]
64125#[cfg_attr(
64126 not(target_arch = "arm"),
64127 stable(feature = "neon_intrinsics", since = "1.59.0")
64128)]
64129#[cfg_attr(
64130 target_arch = "arm",
64131 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64132)]
64133pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
64134 vst4_s16(transmute(a), transmute(b))
64135}
64136#[doc = "Store multiple 4-element structures from four registers"]
64137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
64138#[doc = "## Safety"]
64139#[doc = " * Neon instrinsic unsafe"]
64140#[inline]
64141#[target_feature(enable = "neon")]
64142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64144#[cfg_attr(
64145 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64146 assert_instr(st4)
64147)]
64148#[cfg_attr(
64149 not(target_arch = "arm"),
64150 stable(feature = "neon_intrinsics", since = "1.59.0")
64151)]
64152#[cfg_attr(
64153 target_arch = "arm",
64154 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64155)]
64156pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
64157 vst4q_s16(transmute(a), transmute(b))
64158}
64159#[doc = "Store multiple 4-element structures from four registers"]
64160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
64161#[doc = "## Safety"]
64162#[doc = " * Neon instrinsic unsafe"]
64163#[inline]
64164#[target_feature(enable = "neon")]
64165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64167#[cfg_attr(
64168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64169 assert_instr(st4)
64170)]
64171#[cfg_attr(
64172 not(target_arch = "arm"),
64173 stable(feature = "neon_intrinsics", since = "1.59.0")
64174)]
64175#[cfg_attr(
64176 target_arch = "arm",
64177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64178)]
64179pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
64180 vst4_s32(transmute(a), transmute(b))
64181}
64182#[doc = "Store multiple 4-element structures from four registers"]
64183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
64184#[doc = "## Safety"]
64185#[doc = " * Neon instrinsic unsafe"]
64186#[inline]
64187#[target_feature(enable = "neon")]
64188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64190#[cfg_attr(
64191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64192 assert_instr(st4)
64193)]
64194#[cfg_attr(
64195 not(target_arch = "arm"),
64196 stable(feature = "neon_intrinsics", since = "1.59.0")
64197)]
64198#[cfg_attr(
64199 target_arch = "arm",
64200 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64201)]
64202pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
64203 vst4q_s32(transmute(a), transmute(b))
64204}
64205#[doc = "Store multiple 4-element structures from four registers"]
64206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
64207#[doc = "## Safety"]
64208#[doc = " * Neon instrinsic unsafe"]
64209#[inline]
64210#[target_feature(enable = "neon")]
64211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64213#[cfg_attr(
64214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64215 assert_instr(st4)
64216)]
64217#[cfg_attr(
64218 not(target_arch = "arm"),
64219 stable(feature = "neon_intrinsics", since = "1.59.0")
64220)]
64221#[cfg_attr(
64222 target_arch = "arm",
64223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64224)]
64225pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
64226 vst4_s8(transmute(a), transmute(b))
64227}
64228#[doc = "Store multiple 4-element structures from four registers"]
64229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
64230#[doc = "## Safety"]
64231#[doc = " * Neon instrinsic unsafe"]
64232#[inline]
64233#[target_feature(enable = "neon")]
64234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64236#[cfg_attr(
64237 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64238 assert_instr(st4)
64239)]
64240#[cfg_attr(
64241 not(target_arch = "arm"),
64242 stable(feature = "neon_intrinsics", since = "1.59.0")
64243)]
64244#[cfg_attr(
64245 target_arch = "arm",
64246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64247)]
64248pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
64249 vst4q_s8(transmute(a), transmute(b))
64250}
64251#[doc = "Store multiple 4-element structures from four registers"]
64252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
64253#[doc = "## Safety"]
64254#[doc = " * Neon instrinsic unsafe"]
64255#[inline]
64256#[target_feature(enable = "neon")]
64257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64258#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64259#[cfg_attr(
64260 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64261 assert_instr(st4)
64262)]
64263#[cfg_attr(
64264 not(target_arch = "arm"),
64265 stable(feature = "neon_intrinsics", since = "1.59.0")
64266)]
64267#[cfg_attr(
64268 target_arch = "arm",
64269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64270)]
64271pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
64272 vst4_s16(transmute(a), transmute(b))
64273}
64274#[doc = "Store multiple 4-element structures from four registers"]
64275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
64276#[doc = "## Safety"]
64277#[doc = " * Neon instrinsic unsafe"]
64278#[inline]
64279#[target_feature(enable = "neon")]
64280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64281#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
64282#[cfg_attr(
64283 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64284 assert_instr(st4)
64285)]
64286#[cfg_attr(
64287 not(target_arch = "arm"),
64288 stable(feature = "neon_intrinsics", since = "1.59.0")
64289)]
64290#[cfg_attr(
64291 target_arch = "arm",
64292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64293)]
64294pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
64295 vst4q_s16(transmute(a), transmute(b))
64296}
64297#[doc = "Subtract"]
64298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
64299#[inline]
64300#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
64301#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
64302#[cfg_attr(
64303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64304 assert_instr(fsub)
64305)]
64306#[target_feature(enable = "neon,fp16")]
64307#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64308pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
64309 unsafe { simd_sub(a, b) }
64310}
64311#[doc = "Subtract"]
64312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
64313#[inline]
64314#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
64315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
64316#[cfg_attr(
64317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64318 assert_instr(fsub)
64319)]
64320#[target_feature(enable = "neon,fp16")]
64321#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64322pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
64323 unsafe { simd_sub(a, b) }
64324}
64325#[doc = "Subtract"]
64326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
64327#[inline]
64328#[target_feature(enable = "neon")]
64329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64330#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
64331#[cfg_attr(
64332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64333 assert_instr(fsub)
64334)]
64335#[cfg_attr(
64336 not(target_arch = "arm"),
64337 stable(feature = "neon_intrinsics", since = "1.59.0")
64338)]
64339#[cfg_attr(
64340 target_arch = "arm",
64341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64342)]
64343pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
64344 unsafe { simd_sub(a, b) }
64345}
64346#[doc = "Subtract"]
64347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
64348#[inline]
64349#[target_feature(enable = "neon")]
64350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64351#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
64352#[cfg_attr(
64353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64354 assert_instr(fsub)
64355)]
64356#[cfg_attr(
64357 not(target_arch = "arm"),
64358 stable(feature = "neon_intrinsics", since = "1.59.0")
64359)]
64360#[cfg_attr(
64361 target_arch = "arm",
64362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64363)]
64364pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
64365 unsafe { simd_sub(a, b) }
64366}
64367#[doc = "Subtract"]
64368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
64369#[inline]
64370#[target_feature(enable = "neon")]
64371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64372#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
64373#[cfg_attr(
64374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64375 assert_instr(sub)
64376)]
64377#[cfg_attr(
64378 not(target_arch = "arm"),
64379 stable(feature = "neon_intrinsics", since = "1.59.0")
64380)]
64381#[cfg_attr(
64382 target_arch = "arm",
64383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64384)]
64385pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
64386 unsafe { simd_sub(a, b) }
64387}
64388#[doc = "Subtract"]
64389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
64390#[inline]
64391#[target_feature(enable = "neon")]
64392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64393#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
64394#[cfg_attr(
64395 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64396 assert_instr(sub)
64397)]
64398#[cfg_attr(
64399 not(target_arch = "arm"),
64400 stable(feature = "neon_intrinsics", since = "1.59.0")
64401)]
64402#[cfg_attr(
64403 target_arch = "arm",
64404 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64405)]
64406pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
64407 unsafe { simd_sub(a, b) }
64408}
64409#[doc = "Subtract"]
64410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
64411#[inline]
64412#[target_feature(enable = "neon")]
64413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64414#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
64415#[cfg_attr(
64416 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64417 assert_instr(sub)
64418)]
64419#[cfg_attr(
64420 not(target_arch = "arm"),
64421 stable(feature = "neon_intrinsics", since = "1.59.0")
64422)]
64423#[cfg_attr(
64424 target_arch = "arm",
64425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64426)]
64427pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
64428 unsafe { simd_sub(a, b) }
64429}
64430#[doc = "Subtract"]
64431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
64432#[inline]
64433#[target_feature(enable = "neon")]
64434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64435#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
64436#[cfg_attr(
64437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64438 assert_instr(sub)
64439)]
64440#[cfg_attr(
64441 not(target_arch = "arm"),
64442 stable(feature = "neon_intrinsics", since = "1.59.0")
64443)]
64444#[cfg_attr(
64445 target_arch = "arm",
64446 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64447)]
64448pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
64449 unsafe { simd_sub(a, b) }
64450}
64451#[doc = "Subtract"]
64452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
64453#[inline]
64454#[target_feature(enable = "neon")]
64455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64456#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
64457#[cfg_attr(
64458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64459 assert_instr(sub)
64460)]
64461#[cfg_attr(
64462 not(target_arch = "arm"),
64463 stable(feature = "neon_intrinsics", since = "1.59.0")
64464)]
64465#[cfg_attr(
64466 target_arch = "arm",
64467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64468)]
64469pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
64470 unsafe { simd_sub(a, b) }
64471}
64472#[doc = "Subtract"]
64473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
64474#[inline]
64475#[target_feature(enable = "neon")]
64476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64477#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
64478#[cfg_attr(
64479 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64480 assert_instr(sub)
64481)]
64482#[cfg_attr(
64483 not(target_arch = "arm"),
64484 stable(feature = "neon_intrinsics", since = "1.59.0")
64485)]
64486#[cfg_attr(
64487 target_arch = "arm",
64488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64489)]
64490pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
64491 unsafe { simd_sub(a, b) }
64492}
64493#[doc = "Subtract"]
64494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
64495#[inline]
64496#[target_feature(enable = "neon")]
64497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64498#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
64499#[cfg_attr(
64500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64501 assert_instr(sub)
64502)]
64503#[cfg_attr(
64504 not(target_arch = "arm"),
64505 stable(feature = "neon_intrinsics", since = "1.59.0")
64506)]
64507#[cfg_attr(
64508 target_arch = "arm",
64509 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64510)]
64511pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
64512 unsafe { simd_sub(a, b) }
64513}
64514#[doc = "Subtract"]
64515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
64516#[inline]
64517#[target_feature(enable = "neon")]
64518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64519#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
64520#[cfg_attr(
64521 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64522 assert_instr(sub)
64523)]
64524#[cfg_attr(
64525 not(target_arch = "arm"),
64526 stable(feature = "neon_intrinsics", since = "1.59.0")
64527)]
64528#[cfg_attr(
64529 target_arch = "arm",
64530 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64531)]
64532pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
64533 unsafe { simd_sub(a, b) }
64534}
64535#[doc = "Subtract"]
64536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
64537#[inline]
64538#[target_feature(enable = "neon")]
64539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
64541#[cfg_attr(
64542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64543 assert_instr(sub)
64544)]
64545#[cfg_attr(
64546 not(target_arch = "arm"),
64547 stable(feature = "neon_intrinsics", since = "1.59.0")
64548)]
64549#[cfg_attr(
64550 target_arch = "arm",
64551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64552)]
64553pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
64554 unsafe { simd_sub(a, b) }
64555}
64556#[doc = "Subtract"]
64557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
64558#[inline]
64559#[target_feature(enable = "neon")]
64560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64561#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
64562#[cfg_attr(
64563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64564 assert_instr(sub)
64565)]
64566#[cfg_attr(
64567 not(target_arch = "arm"),
64568 stable(feature = "neon_intrinsics", since = "1.59.0")
64569)]
64570#[cfg_attr(
64571 target_arch = "arm",
64572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64573)]
64574pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
64575 unsafe { simd_sub(a, b) }
64576}
64577#[doc = "Subtract"]
64578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
64579#[inline]
64580#[target_feature(enable = "neon")]
64581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
64583#[cfg_attr(
64584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64585 assert_instr(sub)
64586)]
64587#[cfg_attr(
64588 not(target_arch = "arm"),
64589 stable(feature = "neon_intrinsics", since = "1.59.0")
64590)]
64591#[cfg_attr(
64592 target_arch = "arm",
64593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64594)]
64595pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
64596 unsafe { simd_sub(a, b) }
64597}
64598#[doc = "Subtract"]
64599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
64600#[inline]
64601#[target_feature(enable = "neon")]
64602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64603#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
64604#[cfg_attr(
64605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64606 assert_instr(sub)
64607)]
64608#[cfg_attr(
64609 not(target_arch = "arm"),
64610 stable(feature = "neon_intrinsics", since = "1.59.0")
64611)]
64612#[cfg_attr(
64613 target_arch = "arm",
64614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64615)]
64616pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
64617 unsafe { simd_sub(a, b) }
64618}
64619#[doc = "Subtract"]
64620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
64621#[inline]
64622#[target_feature(enable = "neon")]
64623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64624#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
64625#[cfg_attr(
64626 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64627 assert_instr(sub)
64628)]
64629#[cfg_attr(
64630 not(target_arch = "arm"),
64631 stable(feature = "neon_intrinsics", since = "1.59.0")
64632)]
64633#[cfg_attr(
64634 target_arch = "arm",
64635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64636)]
64637pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
64638 unsafe { simd_sub(a, b) }
64639}
64640#[doc = "Subtract"]
64641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
64642#[inline]
64643#[target_feature(enable = "neon")]
64644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64645#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
64646#[cfg_attr(
64647 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64648 assert_instr(sub)
64649)]
64650#[cfg_attr(
64651 not(target_arch = "arm"),
64652 stable(feature = "neon_intrinsics", since = "1.59.0")
64653)]
64654#[cfg_attr(
64655 target_arch = "arm",
64656 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64657)]
64658pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
64659 unsafe { simd_sub(a, b) }
64660}
64661#[doc = "Subtract"]
64662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
64663#[inline]
64664#[target_feature(enable = "neon")]
64665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64666#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
64667#[cfg_attr(
64668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64669 assert_instr(sub)
64670)]
64671#[cfg_attr(
64672 not(target_arch = "arm"),
64673 stable(feature = "neon_intrinsics", since = "1.59.0")
64674)]
64675#[cfg_attr(
64676 target_arch = "arm",
64677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64678)]
64679pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
64680 unsafe { simd_sub(a, b) }
64681}
64682#[doc = "Subtract"]
64683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
64684#[inline]
64685#[target_feature(enable = "neon")]
64686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64687#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
64688#[cfg_attr(
64689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64690 assert_instr(sub)
64691)]
64692#[cfg_attr(
64693 not(target_arch = "arm"),
64694 stable(feature = "neon_intrinsics", since = "1.59.0")
64695)]
64696#[cfg_attr(
64697 target_arch = "arm",
64698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64699)]
64700pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
64701 unsafe { simd_sub(a, b) }
64702}
64703#[doc = "Subtract returning high narrow"]
64704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
64705#[inline]
64706#[target_feature(enable = "neon")]
64707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64709#[cfg_attr(
64710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64711 assert_instr(subhn2)
64712)]
64713#[cfg_attr(
64714 not(target_arch = "arm"),
64715 stable(feature = "neon_intrinsics", since = "1.59.0")
64716)]
64717#[cfg_attr(
64718 target_arch = "arm",
64719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64720)]
64721pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
64722 let d: int8x8_t = vsubhn_s16(b, c);
64723 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
64724}
64725#[doc = "Subtract returning high narrow"]
64726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
64727#[inline]
64728#[target_feature(enable = "neon")]
64729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64731#[cfg_attr(
64732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64733 assert_instr(subhn2)
64734)]
64735#[cfg_attr(
64736 not(target_arch = "arm"),
64737 stable(feature = "neon_intrinsics", since = "1.59.0")
64738)]
64739#[cfg_attr(
64740 target_arch = "arm",
64741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64742)]
64743pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
64744 let d: int16x4_t = vsubhn_s32(b, c);
64745 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
64746}
64747#[doc = "Subtract returning high narrow"]
64748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
64749#[inline]
64750#[target_feature(enable = "neon")]
64751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64753#[cfg_attr(
64754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64755 assert_instr(subhn2)
64756)]
64757#[cfg_attr(
64758 not(target_arch = "arm"),
64759 stable(feature = "neon_intrinsics", since = "1.59.0")
64760)]
64761#[cfg_attr(
64762 target_arch = "arm",
64763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64764)]
64765pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
64766 let d: int32x2_t = vsubhn_s64(b, c);
64767 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
64768}
64769#[doc = "Subtract returning high narrow"]
64770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
64771#[inline]
64772#[target_feature(enable = "neon")]
64773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64775#[cfg_attr(
64776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64777 assert_instr(subhn2)
64778)]
64779#[cfg_attr(
64780 not(target_arch = "arm"),
64781 stable(feature = "neon_intrinsics", since = "1.59.0")
64782)]
64783#[cfg_attr(
64784 target_arch = "arm",
64785 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64786)]
64787pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
64788 let d: uint8x8_t = vsubhn_u16(b, c);
64789 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
64790}
64791#[doc = "Subtract returning high narrow"]
64792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
64793#[inline]
64794#[target_feature(enable = "neon")]
64795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64797#[cfg_attr(
64798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64799 assert_instr(subhn2)
64800)]
64801#[cfg_attr(
64802 not(target_arch = "arm"),
64803 stable(feature = "neon_intrinsics", since = "1.59.0")
64804)]
64805#[cfg_attr(
64806 target_arch = "arm",
64807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64808)]
64809pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
64810 let d: uint16x4_t = vsubhn_u32(b, c);
64811 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
64812}
64813#[doc = "Subtract returning high narrow"]
64814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
64815#[inline]
64816#[target_feature(enable = "neon")]
64817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64819#[cfg_attr(
64820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64821 assert_instr(subhn2)
64822)]
64823#[cfg_attr(
64824 not(target_arch = "arm"),
64825 stable(feature = "neon_intrinsics", since = "1.59.0")
64826)]
64827#[cfg_attr(
64828 target_arch = "arm",
64829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64830)]
64831pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
64832 let d: uint32x2_t = vsubhn_u64(b, c);
64833 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
64834}
64835#[doc = "Subtract returning high narrow"]
64836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
64837#[inline]
64838#[target_feature(enable = "neon")]
64839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64841#[cfg_attr(
64842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64843 assert_instr(subhn)
64844)]
64845#[cfg_attr(
64846 not(target_arch = "arm"),
64847 stable(feature = "neon_intrinsics", since = "1.59.0")
64848)]
64849#[cfg_attr(
64850 target_arch = "arm",
64851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64852)]
64853pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
64854 let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
64855 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
64856}
64857#[doc = "Subtract returning high narrow"]
64858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
64859#[inline]
64860#[target_feature(enable = "neon")]
64861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64862#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64863#[cfg_attr(
64864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64865 assert_instr(subhn)
64866)]
64867#[cfg_attr(
64868 not(target_arch = "arm"),
64869 stable(feature = "neon_intrinsics", since = "1.59.0")
64870)]
64871#[cfg_attr(
64872 target_arch = "arm",
64873 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64874)]
64875pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
64876 let c: i32x4 = i32x4::new(16, 16, 16, 16);
64877 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
64878}
64879#[doc = "Subtract returning high narrow"]
64880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
64881#[inline]
64882#[target_feature(enable = "neon")]
64883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64885#[cfg_attr(
64886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64887 assert_instr(subhn)
64888)]
64889#[cfg_attr(
64890 not(target_arch = "arm"),
64891 stable(feature = "neon_intrinsics", since = "1.59.0")
64892)]
64893#[cfg_attr(
64894 target_arch = "arm",
64895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64896)]
64897pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
64898 let c: i64x2 = i64x2::new(32, 32);
64899 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
64900}
64901#[doc = "Subtract returning high narrow"]
64902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
64903#[inline]
64904#[target_feature(enable = "neon")]
64905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64907#[cfg_attr(
64908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64909 assert_instr(subhn)
64910)]
64911#[cfg_attr(
64912 not(target_arch = "arm"),
64913 stable(feature = "neon_intrinsics", since = "1.59.0")
64914)]
64915#[cfg_attr(
64916 target_arch = "arm",
64917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64918)]
64919pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
64920 let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
64921 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
64922}
64923#[doc = "Subtract returning high narrow"]
64924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
64925#[inline]
64926#[target_feature(enable = "neon")]
64927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64929#[cfg_attr(
64930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64931 assert_instr(subhn)
64932)]
64933#[cfg_attr(
64934 not(target_arch = "arm"),
64935 stable(feature = "neon_intrinsics", since = "1.59.0")
64936)]
64937#[cfg_attr(
64938 target_arch = "arm",
64939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64940)]
64941pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
64942 let c: u32x4 = u32x4::new(16, 16, 16, 16);
64943 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
64944}
64945#[doc = "Subtract returning high narrow"]
64946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
64947#[inline]
64948#[target_feature(enable = "neon")]
64949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
64951#[cfg_attr(
64952 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64953 assert_instr(subhn)
64954)]
64955#[cfg_attr(
64956 not(target_arch = "arm"),
64957 stable(feature = "neon_intrinsics", since = "1.59.0")
64958)]
64959#[cfg_attr(
64960 target_arch = "arm",
64961 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64962)]
64963pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
64964 let c: u64x2 = u64x2::new(32, 32);
64965 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
64966}
64967#[doc = "Signed Subtract Long"]
64968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
64969#[inline]
64970#[target_feature(enable = "neon")]
64971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
64973#[cfg_attr(
64974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64975 assert_instr(ssubl)
64976)]
64977#[cfg_attr(
64978 not(target_arch = "arm"),
64979 stable(feature = "neon_intrinsics", since = "1.59.0")
64980)]
64981#[cfg_attr(
64982 target_arch = "arm",
64983 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64984)]
64985pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
64986 unsafe {
64987 let c: int16x8_t = simd_cast(a);
64988 let d: int16x8_t = simd_cast(b);
64989 simd_sub(c, d)
64990 }
64991}
64992#[doc = "Signed Subtract Long"]
64993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
64994#[inline]
64995#[target_feature(enable = "neon")]
64996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
64998#[cfg_attr(
64999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65000 assert_instr(ssubl)
65001)]
65002#[cfg_attr(
65003 not(target_arch = "arm"),
65004 stable(feature = "neon_intrinsics", since = "1.59.0")
65005)]
65006#[cfg_attr(
65007 target_arch = "arm",
65008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65009)]
65010pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
65011 unsafe {
65012 let c: int32x4_t = simd_cast(a);
65013 let d: int32x4_t = simd_cast(b);
65014 simd_sub(c, d)
65015 }
65016}
65017#[doc = "Signed Subtract Long"]
65018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
65019#[inline]
65020#[target_feature(enable = "neon")]
65021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
65023#[cfg_attr(
65024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65025 assert_instr(ssubl)
65026)]
65027#[cfg_attr(
65028 not(target_arch = "arm"),
65029 stable(feature = "neon_intrinsics", since = "1.59.0")
65030)]
65031#[cfg_attr(
65032 target_arch = "arm",
65033 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65034)]
65035pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
65036 unsafe {
65037 let c: int64x2_t = simd_cast(a);
65038 let d: int64x2_t = simd_cast(b);
65039 simd_sub(c, d)
65040 }
65041}
65042#[doc = "Unsigned Subtract Long"]
65043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
65044#[inline]
65045#[target_feature(enable = "neon")]
65046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
65048#[cfg_attr(
65049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65050 assert_instr(usubl)
65051)]
65052#[cfg_attr(
65053 not(target_arch = "arm"),
65054 stable(feature = "neon_intrinsics", since = "1.59.0")
65055)]
65056#[cfg_attr(
65057 target_arch = "arm",
65058 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65059)]
65060pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
65061 unsafe {
65062 let c: uint16x8_t = simd_cast(a);
65063 let d: uint16x8_t = simd_cast(b);
65064 simd_sub(c, d)
65065 }
65066}
65067#[doc = "Unsigned Subtract Long"]
65068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
65069#[inline]
65070#[target_feature(enable = "neon")]
65071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
65073#[cfg_attr(
65074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65075 assert_instr(usubl)
65076)]
65077#[cfg_attr(
65078 not(target_arch = "arm"),
65079 stable(feature = "neon_intrinsics", since = "1.59.0")
65080)]
65081#[cfg_attr(
65082 target_arch = "arm",
65083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65084)]
65085pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
65086 unsafe {
65087 let c: uint32x4_t = simd_cast(a);
65088 let d: uint32x4_t = simd_cast(b);
65089 simd_sub(c, d)
65090 }
65091}
65092#[doc = "Unsigned Subtract Long"]
65093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
65094#[inline]
65095#[target_feature(enable = "neon")]
65096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
65098#[cfg_attr(
65099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65100 assert_instr(usubl)
65101)]
65102#[cfg_attr(
65103 not(target_arch = "arm"),
65104 stable(feature = "neon_intrinsics", since = "1.59.0")
65105)]
65106#[cfg_attr(
65107 target_arch = "arm",
65108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65109)]
65110pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
65111 unsafe {
65112 let c: uint64x2_t = simd_cast(a);
65113 let d: uint64x2_t = simd_cast(b);
65114 simd_sub(c, d)
65115 }
65116}
65117#[doc = "Signed Subtract Wide"]
65118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
65119#[inline]
65120#[target_feature(enable = "neon")]
65121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
65123#[cfg_attr(
65124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65125 assert_instr(ssubw)
65126)]
65127#[cfg_attr(
65128 not(target_arch = "arm"),
65129 stable(feature = "neon_intrinsics", since = "1.59.0")
65130)]
65131#[cfg_attr(
65132 target_arch = "arm",
65133 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65134)]
65135pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
65136 unsafe { simd_sub(a, simd_cast(b)) }
65137}
65138#[doc = "Signed Subtract Wide"]
65139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
65140#[inline]
65141#[target_feature(enable = "neon")]
65142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
65144#[cfg_attr(
65145 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65146 assert_instr(ssubw)
65147)]
65148#[cfg_attr(
65149 not(target_arch = "arm"),
65150 stable(feature = "neon_intrinsics", since = "1.59.0")
65151)]
65152#[cfg_attr(
65153 target_arch = "arm",
65154 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65155)]
65156pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
65157 unsafe { simd_sub(a, simd_cast(b)) }
65158}
65159#[doc = "Signed Subtract Wide"]
65160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
65161#[inline]
65162#[target_feature(enable = "neon")]
65163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
65165#[cfg_attr(
65166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65167 assert_instr(ssubw)
65168)]
65169#[cfg_attr(
65170 not(target_arch = "arm"),
65171 stable(feature = "neon_intrinsics", since = "1.59.0")
65172)]
65173#[cfg_attr(
65174 target_arch = "arm",
65175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65176)]
65177pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
65178 unsafe { simd_sub(a, simd_cast(b)) }
65179}
65180#[doc = "Unsigned Subtract Wide"]
65181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
65182#[inline]
65183#[target_feature(enable = "neon")]
65184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65185#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
65186#[cfg_attr(
65187 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65188 assert_instr(usubw)
65189)]
65190#[cfg_attr(
65191 not(target_arch = "arm"),
65192 stable(feature = "neon_intrinsics", since = "1.59.0")
65193)]
65194#[cfg_attr(
65195 target_arch = "arm",
65196 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65197)]
65198pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
65199 unsafe { simd_sub(a, simd_cast(b)) }
65200}
65201#[doc = "Unsigned Subtract Wide"]
65202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
65203#[inline]
65204#[target_feature(enable = "neon")]
65205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
65207#[cfg_attr(
65208 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65209 assert_instr(usubw)
65210)]
65211#[cfg_attr(
65212 not(target_arch = "arm"),
65213 stable(feature = "neon_intrinsics", since = "1.59.0")
65214)]
65215#[cfg_attr(
65216 target_arch = "arm",
65217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65218)]
65219pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
65220 unsafe { simd_sub(a, simd_cast(b)) }
65221}
65222#[doc = "Unsigned Subtract Wide"]
65223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
65224#[inline]
65225#[target_feature(enable = "neon")]
65226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65227#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
65228#[cfg_attr(
65229 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65230 assert_instr(usubw)
65231)]
65232#[cfg_attr(
65233 not(target_arch = "arm"),
65234 stable(feature = "neon_intrinsics", since = "1.59.0")
65235)]
65236#[cfg_attr(
65237 target_arch = "arm",
65238 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65239)]
65240pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
65241 unsafe { simd_sub(a, simd_cast(b)) }
65242}
65243#[doc = "Dot product index form with signed and unsigned integers"]
65244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
65245#[inline]
65246#[target_feature(enable = "neon,i8mm")]
65247#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
65249#[cfg_attr(
65250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65251 assert_instr(sudot, LANE = 0)
65252)]
65253#[rustc_legacy_const_generics(3)]
65254#[cfg_attr(
65255 not(target_arch = "arm"),
65256 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
65257)]
65258#[cfg_attr(
65259 target_arch = "arm",
65260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65261)]
65262pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
65263 static_assert_uimm_bits!(LANE, 1);
65264 unsafe {
65265 let c: uint32x2_t = transmute(c);
65266 let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
65267 vusdot_s32(a, transmute(c), b)
65268 }
65269}
65270#[doc = "Dot product index form with signed and unsigned integers"]
65271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
65272#[inline]
65273#[target_feature(enable = "neon,i8mm")]
65274#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
65276#[cfg_attr(
65277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65278 assert_instr(sudot, LANE = 0)
65279)]
65280#[rustc_legacy_const_generics(3)]
65281#[cfg_attr(
65282 not(target_arch = "arm"),
65283 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
65284)]
65285#[cfg_attr(
65286 target_arch = "arm",
65287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65288)]
65289pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
65290 static_assert_uimm_bits!(LANE, 1);
65291 unsafe {
65292 let c: uint32x2_t = transmute(c);
65293 let c: uint32x4_t =
65294 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
65295 vusdotq_s32(a, transmute(c), b)
65296 }
65297}
65298#[doc = "Table look-up"]
65299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
65300#[inline]
65301#[target_feature(enable = "neon")]
65302#[cfg(target_arch = "arm")]
65303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65304#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65305#[cfg_attr(test, assert_instr(vtbl))]
65306fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
65307 unsafe extern "unadjusted" {
65308 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")]
65309 fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
65310 }
65311 unsafe { _vtbl1(a, b) }
65312}
65313#[doc = "Table look-up"]
65314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
65315#[inline]
65316#[target_feature(enable = "neon")]
65317#[cfg(target_arch = "arm")]
65318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65319#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65320#[cfg_attr(test, assert_instr(vtbl))]
65321pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
65322 vtbl1(a, b)
65323}
65324#[doc = "Table look-up"]
65325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
65326#[inline]
65327#[cfg(target_endian = "little")]
65328#[target_feature(enable = "neon")]
65329#[cfg(target_arch = "arm")]
65330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65331#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65332#[cfg_attr(test, assert_instr(vtbl))]
65333pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
65334 unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
65335}
65336#[doc = "Table look-up"]
65337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
65338#[inline]
65339#[cfg(target_endian = "big")]
65340#[target_feature(enable = "neon")]
65341#[cfg(target_arch = "arm")]
65342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65343#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65344#[cfg_attr(test, assert_instr(vtbl))]
65345pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
65346 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65347 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65348 unsafe {
65349 let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
65350 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65351 }
65352}
65353#[doc = "Table look-up"]
65354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
65355#[inline]
65356#[cfg(target_endian = "little")]
65357#[target_feature(enable = "neon")]
65358#[cfg(target_arch = "arm")]
65359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65360#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65361#[cfg_attr(test, assert_instr(vtbl))]
65362pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
65363 unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
65364}
65365#[doc = "Table look-up"]
65366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
65367#[inline]
65368#[cfg(target_endian = "big")]
65369#[target_feature(enable = "neon")]
65370#[cfg(target_arch = "arm")]
65371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65372#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65373#[cfg_attr(test, assert_instr(vtbl))]
65374pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
65375 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65376 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65377 unsafe {
65378 let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
65379 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65380 }
65381}
65382#[doc = "Table look-up"]
65383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
65384#[inline]
65385#[target_feature(enable = "neon")]
65386#[cfg(target_arch = "arm")]
65387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65388#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65389#[cfg_attr(test, assert_instr(vtbl))]
65390fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
65391 unsafe extern "unadjusted" {
65392 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")]
65393 fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
65394 }
65395 unsafe { _vtbl2(a, b, c) }
65396}
65397#[doc = "Table look-up"]
65398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
65399#[inline]
65400#[target_feature(enable = "neon")]
65401#[cfg(target_arch = "arm")]
65402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65403#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65404#[cfg_attr(test, assert_instr(vtbl))]
65405pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
65406 vtbl2(a.0, a.1, b)
65407}
65408#[doc = "Table look-up"]
65409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
65410#[inline]
65411#[cfg(target_endian = "little")]
65412#[target_feature(enable = "neon")]
65413#[cfg(target_arch = "arm")]
65414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65415#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65416#[cfg_attr(test, assert_instr(vtbl))]
65417pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
65418 unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
65419}
65420#[doc = "Table look-up"]
65421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
65422#[inline]
65423#[cfg(target_endian = "big")]
65424#[target_feature(enable = "neon")]
65425#[cfg(target_arch = "arm")]
65426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65427#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65428#[cfg_attr(test, assert_instr(vtbl))]
65429pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
65430 let mut a: uint8x8x2_t = a;
65431 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65432 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65433 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65434 unsafe {
65435 let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
65436 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65437 }
65438}
65439#[doc = "Table look-up"]
65440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
65441#[inline]
65442#[cfg(target_endian = "little")]
65443#[target_feature(enable = "neon")]
65444#[cfg(target_arch = "arm")]
65445#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65446#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65447#[cfg_attr(test, assert_instr(vtbl))]
65448pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
65449 unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
65450}
65451#[doc = "Table look-up"]
65452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
65453#[inline]
65454#[cfg(target_endian = "big")]
65455#[target_feature(enable = "neon")]
65456#[cfg(target_arch = "arm")]
65457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65458#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65459#[cfg_attr(test, assert_instr(vtbl))]
65460pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
65461 let mut a: poly8x8x2_t = a;
65462 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65463 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65464 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65465 unsafe {
65466 let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
65467 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65468 }
65469}
65470#[doc = "Table look-up"]
65471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
65472#[inline]
65473#[target_feature(enable = "neon")]
65474#[cfg(target_arch = "arm")]
65475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65476#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65477#[cfg_attr(test, assert_instr(vtbl))]
65478fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
65479 unsafe extern "unadjusted" {
65480 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")]
65481 fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
65482 }
65483 unsafe { _vtbl3(a, b, c, d) }
65484}
65485#[doc = "Table look-up"]
65486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
65487#[inline]
65488#[target_feature(enable = "neon")]
65489#[cfg(target_arch = "arm")]
65490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65491#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65492#[cfg_attr(test, assert_instr(vtbl))]
65493pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
65494 vtbl3(a.0, a.1, a.2, b)
65495}
65496#[doc = "Table look-up"]
65497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
65498#[inline]
65499#[cfg(target_endian = "little")]
65500#[target_feature(enable = "neon")]
65501#[cfg(target_arch = "arm")]
65502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65503#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65504#[cfg_attr(test, assert_instr(vtbl))]
65505pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
65506 unsafe {
65507 transmute(vtbl3(
65508 transmute(a.0),
65509 transmute(a.1),
65510 transmute(a.2),
65511 transmute(b),
65512 ))
65513 }
65514}
65515#[doc = "Table look-up"]
65516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
65517#[inline]
65518#[cfg(target_endian = "big")]
65519#[target_feature(enable = "neon")]
65520#[cfg(target_arch = "arm")]
65521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65522#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65523#[cfg_attr(test, assert_instr(vtbl))]
65524pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
65525 let mut a: uint8x8x3_t = a;
65526 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65527 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65528 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
65529 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65530 unsafe {
65531 let ret_val: uint8x8_t = transmute(vtbl3(
65532 transmute(a.0),
65533 transmute(a.1),
65534 transmute(a.2),
65535 transmute(b),
65536 ));
65537 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65538 }
65539}
65540#[doc = "Table look-up"]
65541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
65542#[inline]
65543#[cfg(target_endian = "little")]
65544#[target_feature(enable = "neon")]
65545#[cfg(target_arch = "arm")]
65546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65547#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65548#[cfg_attr(test, assert_instr(vtbl))]
65549pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
65550 unsafe {
65551 transmute(vtbl3(
65552 transmute(a.0),
65553 transmute(a.1),
65554 transmute(a.2),
65555 transmute(b),
65556 ))
65557 }
65558}
65559#[doc = "Table look-up"]
65560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
65561#[inline]
65562#[cfg(target_endian = "big")]
65563#[target_feature(enable = "neon")]
65564#[cfg(target_arch = "arm")]
65565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65566#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65567#[cfg_attr(test, assert_instr(vtbl))]
65568pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
65569 let mut a: poly8x8x3_t = a;
65570 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65571 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65572 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
65573 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65574 unsafe {
65575 let ret_val: poly8x8_t = transmute(vtbl3(
65576 transmute(a.0),
65577 transmute(a.1),
65578 transmute(a.2),
65579 transmute(b),
65580 ));
65581 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65582 }
65583}
65584#[doc = "Table look-up"]
65585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
65586#[inline]
65587#[target_feature(enable = "neon")]
65588#[cfg(target_arch = "arm")]
65589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65590#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65591#[cfg_attr(test, assert_instr(vtbl))]
65592fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
65593 unsafe extern "unadjusted" {
65594 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")]
65595 fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
65596 }
65597 unsafe { _vtbl4(a, b, c, d, e) }
65598}
65599#[doc = "Table look-up"]
65600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
65601#[inline]
65602#[target_feature(enable = "neon")]
65603#[cfg(target_arch = "arm")]
65604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65605#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65606#[cfg_attr(test, assert_instr(vtbl))]
65607pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
65608 vtbl4(a.0, a.1, a.2, a.3, b)
65609}
65610#[doc = "Table look-up"]
65611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
65612#[inline]
65613#[cfg(target_endian = "little")]
65614#[target_feature(enable = "neon")]
65615#[cfg(target_arch = "arm")]
65616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65617#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65618#[cfg_attr(test, assert_instr(vtbl))]
65619pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
65620 unsafe {
65621 transmute(vtbl4(
65622 transmute(a.0),
65623 transmute(a.1),
65624 transmute(a.2),
65625 transmute(a.3),
65626 transmute(b),
65627 ))
65628 }
65629}
65630#[doc = "Table look-up"]
65631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
65632#[inline]
65633#[cfg(target_endian = "big")]
65634#[target_feature(enable = "neon")]
65635#[cfg(target_arch = "arm")]
65636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65637#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65638#[cfg_attr(test, assert_instr(vtbl))]
65639pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
65640 let mut a: uint8x8x4_t = a;
65641 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65642 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65643 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
65644 a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
65645 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65646 unsafe {
65647 let ret_val: uint8x8_t = transmute(vtbl4(
65648 transmute(a.0),
65649 transmute(a.1),
65650 transmute(a.2),
65651 transmute(a.3),
65652 transmute(b),
65653 ));
65654 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65655 }
65656}
65657#[doc = "Table look-up"]
65658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
65659#[inline]
65660#[cfg(target_endian = "little")]
65661#[target_feature(enable = "neon")]
65662#[cfg(target_arch = "arm")]
65663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65664#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65665#[cfg_attr(test, assert_instr(vtbl))]
65666pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
65667 unsafe {
65668 transmute(vtbl4(
65669 transmute(a.0),
65670 transmute(a.1),
65671 transmute(a.2),
65672 transmute(a.3),
65673 transmute(b),
65674 ))
65675 }
65676}
65677#[doc = "Table look-up"]
65678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
65679#[inline]
65680#[cfg(target_endian = "big")]
65681#[target_feature(enable = "neon")]
65682#[cfg(target_arch = "arm")]
65683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65684#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65685#[cfg_attr(test, assert_instr(vtbl))]
65686pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
65687 let mut a: poly8x8x4_t = a;
65688 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65689 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65690 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
65691 a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
65692 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65693 unsafe {
65694 let ret_val: poly8x8_t = transmute(vtbl4(
65695 transmute(a.0),
65696 transmute(a.1),
65697 transmute(a.2),
65698 transmute(a.3),
65699 transmute(b),
65700 ));
65701 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65702 }
65703}
65704#[doc = "Extended table look-up"]
65705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
65706#[inline]
65707#[target_feature(enable = "neon,v7")]
65708#[cfg(target_arch = "arm")]
65709#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65710#[cfg_attr(test, assert_instr(vtbx))]
65711fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
65712 unsafe extern "unadjusted" {
65713 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")]
65714 fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
65715 }
65716 unsafe { _vtbx1(a, b, c) }
65717}
65718#[doc = "Extended table look-up"]
65719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
65720#[inline]
65721#[target_feature(enable = "neon,v7")]
65722#[cfg(target_arch = "arm")]
65723#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65724#[cfg_attr(test, assert_instr(vtbx))]
65725pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
65726 vtbx1(a, b, c)
65727}
65728#[doc = "Extended table look-up"]
65729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
65730#[inline]
65731#[cfg(target_endian = "little")]
65732#[target_feature(enable = "neon,v7")]
65733#[cfg(target_arch = "arm")]
65734#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65735#[cfg_attr(test, assert_instr(vtbx))]
65736pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
65737 unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
65738}
65739#[doc = "Extended table look-up"]
65740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
65741#[inline]
65742#[cfg(target_endian = "big")]
65743#[target_feature(enable = "neon,v7")]
65744#[cfg(target_arch = "arm")]
65745#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65746#[cfg_attr(test, assert_instr(vtbx))]
65747pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
65748 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65749 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65750 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
65751 unsafe {
65752 let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
65753 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65754 }
65755}
65756#[doc = "Extended table look-up"]
65757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
65758#[inline]
65759#[cfg(target_endian = "little")]
65760#[target_feature(enable = "neon,v7")]
65761#[cfg(target_arch = "arm")]
65762#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65763#[cfg_attr(test, assert_instr(vtbx))]
65764pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
65765 unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
65766}
65767#[doc = "Extended table look-up"]
65768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
65769#[inline]
65770#[cfg(target_endian = "big")]
65771#[target_feature(enable = "neon,v7")]
65772#[cfg(target_arch = "arm")]
65773#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65774#[cfg_attr(test, assert_instr(vtbx))]
65775pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
65776 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65777 let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
65778 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
65779 unsafe {
65780 let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
65781 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65782 }
65783}
65784#[doc = "Extended table look-up"]
65785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
65786#[inline]
65787#[target_feature(enable = "neon,v7")]
65788#[cfg(target_arch = "arm")]
65789#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65790#[cfg_attr(test, assert_instr(vtbx))]
65791fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
65792 unsafe extern "unadjusted" {
65793 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")]
65794 fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
65795 }
65796 unsafe { _vtbx2(a, b, c, d) }
65797}
65798#[doc = "Extended table look-up"]
65799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
65800#[inline]
65801#[target_feature(enable = "neon,v7")]
65802#[cfg(target_arch = "arm")]
65803#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65804#[cfg_attr(test, assert_instr(vtbx))]
65805pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
65806 vtbx2(a, b.0, b.1, c)
65807}
65808#[doc = "Extended table look-up"]
65809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
65810#[inline]
65811#[cfg(target_endian = "little")]
65812#[target_feature(enable = "neon,v7")]
65813#[cfg(target_arch = "arm")]
65814#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65815#[cfg_attr(test, assert_instr(vtbx))]
65816pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
65817 unsafe {
65818 transmute(vtbx2(
65819 transmute(a),
65820 transmute(b.0),
65821 transmute(b.1),
65822 transmute(c),
65823 ))
65824 }
65825}
65826#[doc = "Extended table look-up"]
65827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
65828#[inline]
65829#[cfg(target_endian = "big")]
65830#[target_feature(enable = "neon,v7")]
65831#[cfg(target_arch = "arm")]
65832#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65833#[cfg_attr(test, assert_instr(vtbx))]
65834pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
65835 let mut b: uint8x8x2_t = b;
65836 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65837 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65838 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65839 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
65840 unsafe {
65841 let ret_val: uint8x8_t = transmute(vtbx2(
65842 transmute(a),
65843 transmute(b.0),
65844 transmute(b.1),
65845 transmute(c),
65846 ));
65847 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65848 }
65849}
65850#[doc = "Extended table look-up"]
65851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
65852#[inline]
65853#[cfg(target_endian = "little")]
65854#[target_feature(enable = "neon,v7")]
65855#[cfg(target_arch = "arm")]
65856#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65857#[cfg_attr(test, assert_instr(vtbx))]
65858pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
65859 unsafe {
65860 transmute(vtbx2(
65861 transmute(a),
65862 transmute(b.0),
65863 transmute(b.1),
65864 transmute(c),
65865 ))
65866 }
65867}
65868#[doc = "Extended table look-up"]
65869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
65870#[inline]
65871#[cfg(target_endian = "big")]
65872#[target_feature(enable = "neon,v7")]
65873#[cfg(target_arch = "arm")]
65874#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65875#[cfg_attr(test, assert_instr(vtbx))]
65876pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
65877 let mut b: poly8x8x2_t = b;
65878 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65879 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65880 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65881 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
65882 unsafe {
65883 let ret_val: poly8x8_t = transmute(vtbx2(
65884 transmute(a),
65885 transmute(b.0),
65886 transmute(b.1),
65887 transmute(c),
65888 ));
65889 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65890 }
65891}
65892#[doc = "Extended table look-up"]
65893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
65894#[inline]
65895#[target_feature(enable = "neon,v7")]
65896#[cfg(target_arch = "arm")]
65897#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65898#[cfg_attr(test, assert_instr(vtbx))]
65899fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
65900 unsafe extern "unadjusted" {
65901 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")]
65902 fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
65903 }
65904 unsafe { _vtbx3(a, b, c, d, e) }
65905}
65906#[doc = "Extended table look-up"]
65907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
65908#[inline]
65909#[target_feature(enable = "neon,v7")]
65910#[cfg(target_arch = "arm")]
65911#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65912#[cfg_attr(test, assert_instr(vtbx))]
65913pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
65914 vtbx3(a, b.0, b.1, b.2, c)
65915}
65916#[doc = "Extended table look-up"]
65917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
65918#[inline]
65919#[cfg(target_endian = "little")]
65920#[target_feature(enable = "neon,v7")]
65921#[cfg(target_arch = "arm")]
65922#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65923#[cfg_attr(test, assert_instr(vtbx))]
65924pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
65925 unsafe {
65926 transmute(vtbx3(
65927 transmute(a),
65928 transmute(b.0),
65929 transmute(b.1),
65930 transmute(b.2),
65931 transmute(c),
65932 ))
65933 }
65934}
65935#[doc = "Extended table look-up"]
65936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
65937#[inline]
65938#[cfg(target_endian = "big")]
65939#[target_feature(enable = "neon,v7")]
65940#[cfg(target_arch = "arm")]
65941#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65942#[cfg_attr(test, assert_instr(vtbx))]
65943pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
65944 let mut b: uint8x8x3_t = b;
65945 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65946 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65947 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65948 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
65949 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
65950 unsafe {
65951 let ret_val: uint8x8_t = transmute(vtbx3(
65952 transmute(a),
65953 transmute(b.0),
65954 transmute(b.1),
65955 transmute(b.2),
65956 transmute(c),
65957 ));
65958 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
65959 }
65960}
65961#[doc = "Extended table look-up"]
65962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
65963#[inline]
65964#[cfg(target_endian = "little")]
65965#[target_feature(enable = "neon,v7")]
65966#[cfg(target_arch = "arm")]
65967#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65968#[cfg_attr(test, assert_instr(vtbx))]
65969pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
65970 unsafe {
65971 transmute(vtbx3(
65972 transmute(a),
65973 transmute(b.0),
65974 transmute(b.1),
65975 transmute(b.2),
65976 transmute(c),
65977 ))
65978 }
65979}
65980#[doc = "Extended table look-up"]
65981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
65982#[inline]
65983#[cfg(target_endian = "big")]
65984#[target_feature(enable = "neon,v7")]
65985#[cfg(target_arch = "arm")]
65986#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65987#[cfg_attr(test, assert_instr(vtbx))]
65988pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
65989 let mut b: poly8x8x3_t = b;
65990 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
65991 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
65992 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
65993 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
65994 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
65995 unsafe {
65996 let ret_val: poly8x8_t = transmute(vtbx3(
65997 transmute(a),
65998 transmute(b.0),
65999 transmute(b.1),
66000 transmute(b.2),
66001 transmute(c),
66002 ));
66003 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
66004 }
66005}
66006#[doc = "Extended table look-up"]
66007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
66008#[inline]
66009#[target_feature(enable = "neon,v7")]
66010#[cfg(target_arch = "arm")]
66011#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66012#[cfg_attr(test, assert_instr(vtbx))]
66013fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t {
66014 unsafe extern "unadjusted" {
66015 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")]
66016 fn _vtbx4(
66017 a: int8x8_t,
66018 b: int8x8_t,
66019 c: int8x8_t,
66020 d: int8x8_t,
66021 e: int8x8_t,
66022 f: int8x8_t,
66023 ) -> int8x8_t;
66024 }
66025 unsafe { _vtbx4(a, b, c, d, e, f) }
66026}
66027#[doc = "Extended table look-up"]
66028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
66029#[inline]
66030#[cfg(target_endian = "little")]
66031#[target_feature(enable = "neon,v7")]
66032#[cfg(target_arch = "arm")]
66033#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66034#[cfg_attr(test, assert_instr(vtbx))]
66035pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
66036 unsafe {
66037 vtbx4(
66038 a,
66039 transmute(b.0),
66040 transmute(b.1),
66041 transmute(b.2),
66042 transmute(b.3),
66043 c,
66044 )
66045 }
66046}
66047#[doc = "Extended table look-up"]
66048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
66049#[inline]
66050#[cfg(target_endian = "big")]
66051#[target_feature(enable = "neon,v7")]
66052#[cfg(target_arch = "arm")]
66053#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66054#[cfg_attr(test, assert_instr(vtbx))]
66055pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
66056 let mut b: int8x8x4_t = b;
66057 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
66058 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
66059 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
66060 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
66061 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
66062 let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
66063 unsafe {
66064 let ret_val: int8x8_t = vtbx4(
66065 a,
66066 transmute(b.0),
66067 transmute(b.1),
66068 transmute(b.2),
66069 transmute(b.3),
66070 c,
66071 );
66072 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
66073 }
66074}
66075#[doc = "Extended table look-up"]
66076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
66077#[inline]
66078#[cfg(target_endian = "little")]
66079#[target_feature(enable = "neon,v7")]
66080#[cfg(target_arch = "arm")]
66081#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66082#[cfg_attr(test, assert_instr(vtbx))]
66083pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
66084 unsafe {
66085 transmute(vtbx4(
66086 transmute(a),
66087 transmute(b.0),
66088 transmute(b.1),
66089 transmute(b.2),
66090 transmute(b.3),
66091 transmute(c),
66092 ))
66093 }
66094}
66095#[doc = "Extended table look-up"]
66096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
66097#[inline]
66098#[cfg(target_endian = "big")]
66099#[target_feature(enable = "neon,v7")]
66100#[cfg(target_arch = "arm")]
66101#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66102#[cfg_attr(test, assert_instr(vtbx))]
66103pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
66104 let mut b: uint8x8x4_t = b;
66105 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
66106 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
66107 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
66108 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
66109 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
66110 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
66111 unsafe {
66112 let ret_val: uint8x8_t = transmute(vtbx4(
66113 transmute(a),
66114 transmute(b.0),
66115 transmute(b.1),
66116 transmute(b.2),
66117 transmute(b.3),
66118 transmute(c),
66119 ));
66120 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
66121 }
66122}
66123#[doc = "Extended table look-up"]
66124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
66125#[inline]
66126#[cfg(target_endian = "little")]
66127#[target_feature(enable = "neon,v7")]
66128#[cfg(target_arch = "arm")]
66129#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66130#[cfg_attr(test, assert_instr(vtbx))]
66131pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
66132 unsafe {
66133 transmute(vtbx4(
66134 transmute(a),
66135 transmute(b.0),
66136 transmute(b.1),
66137 transmute(b.2),
66138 transmute(b.3),
66139 transmute(c),
66140 ))
66141 }
66142}
66143#[doc = "Extended table look-up"]
66144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
66145#[inline]
66146#[cfg(target_endian = "big")]
66147#[target_feature(enable = "neon,v7")]
66148#[cfg(target_arch = "arm")]
66149#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66150#[cfg_attr(test, assert_instr(vtbx))]
66151pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
66152 let mut b: poly8x8x4_t = b;
66153 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
66154 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
66155 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
66156 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
66157 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
66158 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
66159 unsafe {
66160 let ret_val: poly8x8_t = transmute(vtbx4(
66161 transmute(a),
66162 transmute(b.0),
66163 transmute(b.1),
66164 transmute(b.2),
66165 transmute(b.3),
66166 transmute(c),
66167 ));
66168 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
66169 }
66170}
66171#[doc = "Transpose elements"]
66172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
66173#[inline]
66174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66176#[cfg_attr(
66177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66178 assert_instr(trn)
66179)]
66180#[target_feature(enable = "neon,fp16")]
66181#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
66182pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
66183 unsafe {
66184 let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66185 let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66186 transmute((a1, b1))
66187 }
66188}
66189#[doc = "Transpose elements"]
66190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
66191#[inline]
66192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66194#[cfg_attr(
66195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66196 assert_instr(trn)
66197)]
66198#[target_feature(enable = "neon,fp16")]
66199#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
66200pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
66201 unsafe {
66202 let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66203 let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66204 transmute((a1, b1))
66205 }
66206}
66207#[doc = "Transpose elements"]
66208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
66209#[inline]
66210#[target_feature(enable = "neon")]
66211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66213#[cfg_attr(
66214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66215 assert_instr(zip)
66216)]
66217#[cfg_attr(
66218 not(target_arch = "arm"),
66219 stable(feature = "neon_intrinsics", since = "1.59.0")
66220)]
66221#[cfg_attr(
66222 target_arch = "arm",
66223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66224)]
66225pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
66226 unsafe {
66227 let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]);
66228 let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]);
66229 transmute((a1, b1))
66230 }
66231}
66232#[doc = "Transpose elements"]
66233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
66234#[inline]
66235#[target_feature(enable = "neon")]
66236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66238#[cfg_attr(
66239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66240 assert_instr(zip)
66241)]
66242#[cfg_attr(
66243 not(target_arch = "arm"),
66244 stable(feature = "neon_intrinsics", since = "1.59.0")
66245)]
66246#[cfg_attr(
66247 target_arch = "arm",
66248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66249)]
66250pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
66251 unsafe {
66252 let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]);
66253 let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]);
66254 transmute((a1, b1))
66255 }
66256}
66257#[doc = "Transpose elements"]
66258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
66259#[inline]
66260#[target_feature(enable = "neon")]
66261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66263#[cfg_attr(
66264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66265 assert_instr(zip)
66266)]
66267#[cfg_attr(
66268 not(target_arch = "arm"),
66269 stable(feature = "neon_intrinsics", since = "1.59.0")
66270)]
66271#[cfg_attr(
66272 target_arch = "arm",
66273 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66274)]
66275pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
66276 unsafe {
66277 let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
66278 let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
66279 transmute((a1, b1))
66280 }
66281}
66282#[doc = "Transpose elements"]
66283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
66284#[inline]
66285#[target_feature(enable = "neon")]
66286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66288#[cfg_attr(
66289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66290 assert_instr(trn)
66291)]
66292#[cfg_attr(
66293 not(target_arch = "arm"),
66294 stable(feature = "neon_intrinsics", since = "1.59.0")
66295)]
66296#[cfg_attr(
66297 target_arch = "arm",
66298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66299)]
66300pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
66301 unsafe {
66302 let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66303 let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66304 transmute((a1, b1))
66305 }
66306}
66307#[doc = "Transpose elements"]
66308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
66309#[inline]
66310#[target_feature(enable = "neon")]
66311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66313#[cfg_attr(
66314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66315 assert_instr(trn)
66316)]
66317#[cfg_attr(
66318 not(target_arch = "arm"),
66319 stable(feature = "neon_intrinsics", since = "1.59.0")
66320)]
66321#[cfg_attr(
66322 target_arch = "arm",
66323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66324)]
66325pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
66326 unsafe {
66327 let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66328 let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66329 transmute((a1, b1))
66330 }
66331}
66332#[doc = "Transpose elements"]
66333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
66334#[inline]
66335#[target_feature(enable = "neon")]
66336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66338#[cfg_attr(
66339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66340 assert_instr(trn)
66341)]
66342#[cfg_attr(
66343 not(target_arch = "arm"),
66344 stable(feature = "neon_intrinsics", since = "1.59.0")
66345)]
66346#[cfg_attr(
66347 target_arch = "arm",
66348 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66349)]
66350pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
66351 unsafe {
66352 let a1: int8x16_t = simd_shuffle!(
66353 a,
66354 b,
66355 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
66356 );
66357 let b1: int8x16_t = simd_shuffle!(
66358 a,
66359 b,
66360 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
66361 );
66362 transmute((a1, b1))
66363 }
66364}
66365#[doc = "Transpose elements"]
66366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
66367#[inline]
66368#[target_feature(enable = "neon")]
66369#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66370#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66371#[cfg_attr(
66372 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66373 assert_instr(trn)
66374)]
66375#[cfg_attr(
66376 not(target_arch = "arm"),
66377 stable(feature = "neon_intrinsics", since = "1.59.0")
66378)]
66379#[cfg_attr(
66380 target_arch = "arm",
66381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66382)]
66383pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
66384 unsafe {
66385 let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66386 let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66387 transmute((a1, b1))
66388 }
66389}
66390#[doc = "Transpose elements"]
66391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
66392#[inline]
66393#[target_feature(enable = "neon")]
66394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66396#[cfg_attr(
66397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66398 assert_instr(trn)
66399)]
66400#[cfg_attr(
66401 not(target_arch = "arm"),
66402 stable(feature = "neon_intrinsics", since = "1.59.0")
66403)]
66404#[cfg_attr(
66405 target_arch = "arm",
66406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66407)]
66408pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
66409 unsafe {
66410 let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66411 let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66412 transmute((a1, b1))
66413 }
66414}
66415#[doc = "Transpose elements"]
66416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
66417#[inline]
66418#[target_feature(enable = "neon")]
66419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66421#[cfg_attr(
66422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66423 assert_instr(trn)
66424)]
66425#[cfg_attr(
66426 not(target_arch = "arm"),
66427 stable(feature = "neon_intrinsics", since = "1.59.0")
66428)]
66429#[cfg_attr(
66430 target_arch = "arm",
66431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66432)]
66433pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
66434 unsafe {
66435 let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66436 let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66437 transmute((a1, b1))
66438 }
66439}
66440#[doc = "Transpose elements"]
66441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
66442#[inline]
66443#[target_feature(enable = "neon")]
66444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66446#[cfg_attr(
66447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66448 assert_instr(trn)
66449)]
66450#[cfg_attr(
66451 not(target_arch = "arm"),
66452 stable(feature = "neon_intrinsics", since = "1.59.0")
66453)]
66454#[cfg_attr(
66455 target_arch = "arm",
66456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66457)]
66458pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
66459 unsafe {
66460 let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66461 let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66462 transmute((a1, b1))
66463 }
66464}
66465#[doc = "Transpose elements"]
66466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
66467#[inline]
66468#[target_feature(enable = "neon")]
66469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66470#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66471#[cfg_attr(
66472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66473 assert_instr(trn)
66474)]
66475#[cfg_attr(
66476 not(target_arch = "arm"),
66477 stable(feature = "neon_intrinsics", since = "1.59.0")
66478)]
66479#[cfg_attr(
66480 target_arch = "arm",
66481 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66482)]
66483pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
66484 unsafe {
66485 let a1: uint8x16_t = simd_shuffle!(
66486 a,
66487 b,
66488 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
66489 );
66490 let b1: uint8x16_t = simd_shuffle!(
66491 a,
66492 b,
66493 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
66494 );
66495 transmute((a1, b1))
66496 }
66497}
66498#[doc = "Transpose elements"]
66499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
66500#[inline]
66501#[target_feature(enable = "neon")]
66502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66504#[cfg_attr(
66505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66506 assert_instr(trn)
66507)]
66508#[cfg_attr(
66509 not(target_arch = "arm"),
66510 stable(feature = "neon_intrinsics", since = "1.59.0")
66511)]
66512#[cfg_attr(
66513 target_arch = "arm",
66514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66515)]
66516pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
66517 unsafe {
66518 let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66519 let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66520 transmute((a1, b1))
66521 }
66522}
66523#[doc = "Transpose elements"]
66524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
66525#[inline]
66526#[target_feature(enable = "neon")]
66527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66529#[cfg_attr(
66530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66531 assert_instr(trn)
66532)]
66533#[cfg_attr(
66534 not(target_arch = "arm"),
66535 stable(feature = "neon_intrinsics", since = "1.59.0")
66536)]
66537#[cfg_attr(
66538 target_arch = "arm",
66539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66540)]
66541pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
66542 unsafe {
66543 let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66544 let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66545 transmute((a1, b1))
66546 }
66547}
66548#[doc = "Transpose elements"]
66549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
66550#[inline]
66551#[target_feature(enable = "neon")]
66552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66553#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66554#[cfg_attr(
66555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66556 assert_instr(trn)
66557)]
66558#[cfg_attr(
66559 not(target_arch = "arm"),
66560 stable(feature = "neon_intrinsics", since = "1.59.0")
66561)]
66562#[cfg_attr(
66563 target_arch = "arm",
66564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66565)]
66566pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
66567 unsafe {
66568 let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66569 let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66570 transmute((a1, b1))
66571 }
66572}
66573#[doc = "Transpose elements"]
66574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
66575#[inline]
66576#[target_feature(enable = "neon")]
66577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66579#[cfg_attr(
66580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66581 assert_instr(trn)
66582)]
66583#[cfg_attr(
66584 not(target_arch = "arm"),
66585 stable(feature = "neon_intrinsics", since = "1.59.0")
66586)]
66587#[cfg_attr(
66588 target_arch = "arm",
66589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66590)]
66591pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
66592 unsafe {
66593 let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66594 let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66595 transmute((a1, b1))
66596 }
66597}
66598#[doc = "Transpose elements"]
66599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
66600#[inline]
66601#[target_feature(enable = "neon")]
66602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66604#[cfg_attr(
66605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66606 assert_instr(trn)
66607)]
66608#[cfg_attr(
66609 not(target_arch = "arm"),
66610 stable(feature = "neon_intrinsics", since = "1.59.0")
66611)]
66612#[cfg_attr(
66613 target_arch = "arm",
66614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66615)]
66616pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
66617 unsafe {
66618 let a1: poly8x16_t = simd_shuffle!(
66619 a,
66620 b,
66621 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
66622 );
66623 let b1: poly8x16_t = simd_shuffle!(
66624 a,
66625 b,
66626 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
66627 );
66628 transmute((a1, b1))
66629 }
66630}
66631#[doc = "Transpose elements"]
66632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
66633#[inline]
66634#[target_feature(enable = "neon")]
66635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66637#[cfg_attr(
66638 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66639 assert_instr(trn)
66640)]
66641#[cfg_attr(
66642 not(target_arch = "arm"),
66643 stable(feature = "neon_intrinsics", since = "1.59.0")
66644)]
66645#[cfg_attr(
66646 target_arch = "arm",
66647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66648)]
66649pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
66650 unsafe {
66651 let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
66652 let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
66653 transmute((a1, b1))
66654 }
66655}
66656#[doc = "Transpose elements"]
66657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
66658#[inline]
66659#[target_feature(enable = "neon")]
66660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
66662#[cfg_attr(
66663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66664 assert_instr(trn)
66665)]
66666#[cfg_attr(
66667 not(target_arch = "arm"),
66668 stable(feature = "neon_intrinsics", since = "1.59.0")
66669)]
66670#[cfg_attr(
66671 target_arch = "arm",
66672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66673)]
66674pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
66675 unsafe {
66676 let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
66677 let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
66678 transmute((a1, b1))
66679 }
66680}
66681#[doc = "Signed compare bitwise Test bits nonzero"]
66682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
66683#[inline]
66684#[target_feature(enable = "neon")]
66685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66687#[cfg_attr(
66688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66689 assert_instr(cmtst)
66690)]
66691#[cfg_attr(
66692 not(target_arch = "arm"),
66693 stable(feature = "neon_intrinsics", since = "1.59.0")
66694)]
66695#[cfg_attr(
66696 target_arch = "arm",
66697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66698)]
66699pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
66700 unsafe {
66701 let c: int8x8_t = simd_and(a, b);
66702 let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
66703 simd_ne(c, transmute(d))
66704 }
66705}
66706#[doc = "Signed compare bitwise Test bits nonzero"]
66707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
66708#[inline]
66709#[target_feature(enable = "neon")]
66710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66712#[cfg_attr(
66713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66714 assert_instr(cmtst)
66715)]
66716#[cfg_attr(
66717 not(target_arch = "arm"),
66718 stable(feature = "neon_intrinsics", since = "1.59.0")
66719)]
66720#[cfg_attr(
66721 target_arch = "arm",
66722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66723)]
66724pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
66725 unsafe {
66726 let c: int8x16_t = simd_and(a, b);
66727 let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
66728 simd_ne(c, transmute(d))
66729 }
66730}
66731#[doc = "Signed compare bitwise Test bits nonzero"]
66732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
66733#[inline]
66734#[target_feature(enable = "neon")]
66735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66736#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66737#[cfg_attr(
66738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66739 assert_instr(cmtst)
66740)]
66741#[cfg_attr(
66742 not(target_arch = "arm"),
66743 stable(feature = "neon_intrinsics", since = "1.59.0")
66744)]
66745#[cfg_attr(
66746 target_arch = "arm",
66747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66748)]
66749pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
66750 unsafe {
66751 let c: int16x4_t = simd_and(a, b);
66752 let d: i16x4 = i16x4::new(0, 0, 0, 0);
66753 simd_ne(c, transmute(d))
66754 }
66755}
66756#[doc = "Signed compare bitwise Test bits nonzero"]
66757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
66758#[inline]
66759#[target_feature(enable = "neon")]
66760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66762#[cfg_attr(
66763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66764 assert_instr(cmtst)
66765)]
66766#[cfg_attr(
66767 not(target_arch = "arm"),
66768 stable(feature = "neon_intrinsics", since = "1.59.0")
66769)]
66770#[cfg_attr(
66771 target_arch = "arm",
66772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66773)]
66774pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
66775 unsafe {
66776 let c: int16x8_t = simd_and(a, b);
66777 let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
66778 simd_ne(c, transmute(d))
66779 }
66780}
66781#[doc = "Signed compare bitwise Test bits nonzero"]
66782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
66783#[inline]
66784#[target_feature(enable = "neon")]
66785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66787#[cfg_attr(
66788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66789 assert_instr(cmtst)
66790)]
66791#[cfg_attr(
66792 not(target_arch = "arm"),
66793 stable(feature = "neon_intrinsics", since = "1.59.0")
66794)]
66795#[cfg_attr(
66796 target_arch = "arm",
66797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66798)]
66799pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
66800 unsafe {
66801 let c: int32x2_t = simd_and(a, b);
66802 let d: i32x2 = i32x2::new(0, 0);
66803 simd_ne(c, transmute(d))
66804 }
66805}
66806#[doc = "Signed compare bitwise Test bits nonzero"]
66807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
66808#[inline]
66809#[target_feature(enable = "neon")]
66810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66812#[cfg_attr(
66813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66814 assert_instr(cmtst)
66815)]
66816#[cfg_attr(
66817 not(target_arch = "arm"),
66818 stable(feature = "neon_intrinsics", since = "1.59.0")
66819)]
66820#[cfg_attr(
66821 target_arch = "arm",
66822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66823)]
66824pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
66825 unsafe {
66826 let c: int32x4_t = simd_and(a, b);
66827 let d: i32x4 = i32x4::new(0, 0, 0, 0);
66828 simd_ne(c, transmute(d))
66829 }
66830}
66831#[doc = "Signed compare bitwise Test bits nonzero"]
66832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
66833#[inline]
66834#[target_feature(enable = "neon")]
66835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66837#[cfg_attr(
66838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66839 assert_instr(cmtst)
66840)]
66841#[cfg_attr(
66842 not(target_arch = "arm"),
66843 stable(feature = "neon_intrinsics", since = "1.59.0")
66844)]
66845#[cfg_attr(
66846 target_arch = "arm",
66847 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66848)]
66849pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
66850 unsafe {
66851 let c: poly8x8_t = simd_and(a, b);
66852 let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
66853 simd_ne(c, transmute(d))
66854 }
66855}
66856#[doc = "Signed compare bitwise Test bits nonzero"]
66857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
66858#[inline]
66859#[target_feature(enable = "neon")]
66860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66862#[cfg_attr(
66863 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66864 assert_instr(cmtst)
66865)]
66866#[cfg_attr(
66867 not(target_arch = "arm"),
66868 stable(feature = "neon_intrinsics", since = "1.59.0")
66869)]
66870#[cfg_attr(
66871 target_arch = "arm",
66872 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66873)]
66874pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
66875 unsafe {
66876 let c: poly8x16_t = simd_and(a, b);
66877 let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
66878 simd_ne(c, transmute(d))
66879 }
66880}
66881#[doc = "Signed compare bitwise Test bits nonzero"]
66882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
66883#[inline]
66884#[target_feature(enable = "neon")]
66885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66887#[cfg_attr(
66888 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66889 assert_instr(cmtst)
66890)]
66891#[cfg_attr(
66892 not(target_arch = "arm"),
66893 stable(feature = "neon_intrinsics", since = "1.59.0")
66894)]
66895#[cfg_attr(
66896 target_arch = "arm",
66897 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66898)]
66899pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
66900 unsafe {
66901 let c: poly16x4_t = simd_and(a, b);
66902 let d: i16x4 = i16x4::new(0, 0, 0, 0);
66903 simd_ne(c, transmute(d))
66904 }
66905}
66906#[doc = "Signed compare bitwise Test bits nonzero"]
66907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
66908#[inline]
66909#[target_feature(enable = "neon")]
66910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66912#[cfg_attr(
66913 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66914 assert_instr(cmtst)
66915)]
66916#[cfg_attr(
66917 not(target_arch = "arm"),
66918 stable(feature = "neon_intrinsics", since = "1.59.0")
66919)]
66920#[cfg_attr(
66921 target_arch = "arm",
66922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66923)]
66924pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
66925 unsafe {
66926 let c: poly16x8_t = simd_and(a, b);
66927 let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
66928 simd_ne(c, transmute(d))
66929 }
66930}
66931#[doc = "Unsigned compare bitwise Test bits nonzero"]
66932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
66933#[inline]
66934#[target_feature(enable = "neon")]
66935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66937#[cfg_attr(
66938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66939 assert_instr(cmtst)
66940)]
66941#[cfg_attr(
66942 not(target_arch = "arm"),
66943 stable(feature = "neon_intrinsics", since = "1.59.0")
66944)]
66945#[cfg_attr(
66946 target_arch = "arm",
66947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66948)]
66949pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
66950 unsafe {
66951 let c: uint8x8_t = simd_and(a, b);
66952 let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
66953 simd_ne(c, transmute(d))
66954 }
66955}
66956#[doc = "Unsigned compare bitwise Test bits nonzero"]
66957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
66958#[inline]
66959#[target_feature(enable = "neon")]
66960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66962#[cfg_attr(
66963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66964 assert_instr(cmtst)
66965)]
66966#[cfg_attr(
66967 not(target_arch = "arm"),
66968 stable(feature = "neon_intrinsics", since = "1.59.0")
66969)]
66970#[cfg_attr(
66971 target_arch = "arm",
66972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66973)]
66974pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
66975 unsafe {
66976 let c: uint8x16_t = simd_and(a, b);
66977 let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
66978 simd_ne(c, transmute(d))
66979 }
66980}
66981#[doc = "Unsigned compare bitwise Test bits nonzero"]
66982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
66983#[inline]
66984#[target_feature(enable = "neon")]
66985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
66987#[cfg_attr(
66988 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66989 assert_instr(cmtst)
66990)]
66991#[cfg_attr(
66992 not(target_arch = "arm"),
66993 stable(feature = "neon_intrinsics", since = "1.59.0")
66994)]
66995#[cfg_attr(
66996 target_arch = "arm",
66997 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66998)]
66999pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
67000 unsafe {
67001 let c: uint16x4_t = simd_and(a, b);
67002 let d: u16x4 = u16x4::new(0, 0, 0, 0);
67003 simd_ne(c, transmute(d))
67004 }
67005}
67006#[doc = "Unsigned compare bitwise Test bits nonzero"]
67007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
67008#[inline]
67009#[target_feature(enable = "neon")]
67010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
67012#[cfg_attr(
67013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67014 assert_instr(cmtst)
67015)]
67016#[cfg_attr(
67017 not(target_arch = "arm"),
67018 stable(feature = "neon_intrinsics", since = "1.59.0")
67019)]
67020#[cfg_attr(
67021 target_arch = "arm",
67022 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67023)]
67024pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
67025 unsafe {
67026 let c: uint16x8_t = simd_and(a, b);
67027 let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
67028 simd_ne(c, transmute(d))
67029 }
67030}
67031#[doc = "Unsigned compare bitwise Test bits nonzero"]
67032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
67033#[inline]
67034#[target_feature(enable = "neon")]
67035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
67037#[cfg_attr(
67038 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67039 assert_instr(cmtst)
67040)]
67041#[cfg_attr(
67042 not(target_arch = "arm"),
67043 stable(feature = "neon_intrinsics", since = "1.59.0")
67044)]
67045#[cfg_attr(
67046 target_arch = "arm",
67047 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67048)]
67049pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
67050 unsafe {
67051 let c: uint32x2_t = simd_and(a, b);
67052 let d: u32x2 = u32x2::new(0, 0);
67053 simd_ne(c, transmute(d))
67054 }
67055}
67056#[doc = "Unsigned compare bitwise Test bits nonzero"]
67057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
67058#[inline]
67059#[target_feature(enable = "neon")]
67060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
67062#[cfg_attr(
67063 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67064 assert_instr(cmtst)
67065)]
67066#[cfg_attr(
67067 not(target_arch = "arm"),
67068 stable(feature = "neon_intrinsics", since = "1.59.0")
67069)]
67070#[cfg_attr(
67071 target_arch = "arm",
67072 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67073)]
67074pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
67075 unsafe {
67076 let c: uint32x4_t = simd_and(a, b);
67077 let d: u32x4 = u32x4::new(0, 0, 0, 0);
67078 simd_ne(c, transmute(d))
67079 }
67080}
67081#[doc = "Dot product index form with unsigned and signed integers"]
67082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
67083#[inline]
67084#[target_feature(enable = "neon,i8mm")]
67085#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
67087#[cfg_attr(
67088 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67089 assert_instr(usdot, LANE = 0)
67090)]
67091#[rustc_legacy_const_generics(3)]
67092#[cfg_attr(
67093 not(target_arch = "arm"),
67094 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
67095)]
67096#[cfg_attr(
67097 target_arch = "arm",
67098 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67099)]
67100pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
67101 static_assert_uimm_bits!(LANE, 1);
67102 unsafe {
67103 let c: int32x2_t = transmute(c);
67104 let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
67105 vusdot_s32(a, b, transmute(c))
67106 }
67107}
67108#[doc = "Dot product index form with unsigned and signed integers"]
67109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
67110#[inline]
67111#[target_feature(enable = "neon,i8mm")]
67112#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
67114#[cfg_attr(
67115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67116 assert_instr(usdot, LANE = 0)
67117)]
67118#[rustc_legacy_const_generics(3)]
67119#[cfg_attr(
67120 not(target_arch = "arm"),
67121 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
67122)]
67123#[cfg_attr(
67124 target_arch = "arm",
67125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67126)]
67127pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
67128 static_assert_uimm_bits!(LANE, 1);
67129 unsafe {
67130 let c: int32x2_t = transmute(c);
67131 let c: int32x4_t =
67132 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
67133 vusdotq_s32(a, b, transmute(c))
67134 }
67135}
67136#[doc = "Dot product vector form with unsigned and signed integers"]
67137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
67138#[inline]
67139#[target_feature(enable = "neon,i8mm")]
67140#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
67142#[cfg_attr(
67143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67144 assert_instr(usdot)
67145)]
67146#[cfg_attr(
67147 not(target_arch = "arm"),
67148 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
67149)]
67150#[cfg_attr(
67151 target_arch = "arm",
67152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67153)]
67154pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
67155 unsafe extern "unadjusted" {
67156 #[cfg_attr(
67157 any(target_arch = "aarch64", target_arch = "arm64ec"),
67158 link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8"
67159 )]
67160 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")]
67161 fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t;
67162 }
67163 unsafe { _vusdot_s32(a, b, c) }
67164}
67165#[doc = "Dot product vector form with unsigned and signed integers"]
67166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
67167#[inline]
67168#[target_feature(enable = "neon,i8mm")]
67169#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
67171#[cfg_attr(
67172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67173 assert_instr(usdot)
67174)]
67175#[cfg_attr(
67176 not(target_arch = "arm"),
67177 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
67178)]
67179#[cfg_attr(
67180 target_arch = "arm",
67181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67182)]
67183pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
67184 unsafe extern "unadjusted" {
67185 #[cfg_attr(
67186 any(target_arch = "aarch64", target_arch = "arm64ec"),
67187 link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8"
67188 )]
67189 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")]
67190 fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
67191 }
67192 unsafe { _vusdotq_s32(a, b, c) }
67193}
67194#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
67195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
67196#[inline]
67197#[target_feature(enable = "neon,i8mm")]
67198#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
67200#[cfg_attr(
67201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67202 assert_instr(usmmla)
67203)]
67204#[cfg_attr(
67205 not(target_arch = "arm"),
67206 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
67207)]
67208#[cfg_attr(
67209 target_arch = "arm",
67210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67211)]
67212pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
67213 unsafe extern "unadjusted" {
67214 #[cfg_attr(
67215 any(target_arch = "aarch64", target_arch = "arm64ec"),
67216 link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8"
67217 )]
67218 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")]
67219 fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
67220 }
67221 unsafe { _vusmmlaq_s32(a, b, c) }
67222}
67223#[doc = "Unzip vectors"]
67224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
67225#[inline]
67226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67227#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67228#[cfg_attr(
67229 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67230 assert_instr(uzp)
67231)]
67232#[target_feature(enable = "neon,fp16")]
67233#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67234pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
67235 unsafe {
67236 let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67237 let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67238 transmute((a0, b0))
67239 }
67240}
67241#[doc = "Unzip vectors"]
67242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
67243#[inline]
67244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67246#[cfg_attr(
67247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67248 assert_instr(uzp)
67249)]
67250#[target_feature(enable = "neon,fp16")]
67251#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67252pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
67253 unsafe {
67254 let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67255 let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67256 transmute((a0, b0))
67257 }
67258}
67259#[doc = "Unzip vectors"]
67260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
67261#[inline]
67262#[target_feature(enable = "neon")]
67263#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67264#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
67265#[cfg_attr(
67266 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67267 assert_instr(zip)
67268)]
67269#[cfg_attr(
67270 not(target_arch = "arm"),
67271 stable(feature = "neon_intrinsics", since = "1.59.0")
67272)]
67273#[cfg_attr(
67274 target_arch = "arm",
67275 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67276)]
67277pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
67278 unsafe {
67279 let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
67280 let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
67281 transmute((a0, b0))
67282 }
67283}
67284#[doc = "Unzip vectors"]
67285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
67286#[inline]
67287#[target_feature(enable = "neon")]
67288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67289#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
67290#[cfg_attr(
67291 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67292 assert_instr(zip)
67293)]
67294#[cfg_attr(
67295 not(target_arch = "arm"),
67296 stable(feature = "neon_intrinsics", since = "1.59.0")
67297)]
67298#[cfg_attr(
67299 target_arch = "arm",
67300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67301)]
67302pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
67303 unsafe {
67304 let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
67305 let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
67306 transmute((a0, b0))
67307 }
67308}
67309#[doc = "Unzip vectors"]
67310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
67311#[inline]
67312#[target_feature(enable = "neon")]
67313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
67315#[cfg_attr(
67316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67317 assert_instr(zip)
67318)]
67319#[cfg_attr(
67320 not(target_arch = "arm"),
67321 stable(feature = "neon_intrinsics", since = "1.59.0")
67322)]
67323#[cfg_attr(
67324 target_arch = "arm",
67325 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67326)]
67327pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
67328 unsafe {
67329 let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
67330 let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
67331 transmute((a0, b0))
67332 }
67333}
67334#[doc = "Unzip vectors"]
67335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
67336#[inline]
67337#[target_feature(enable = "neon")]
67338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67340#[cfg_attr(
67341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67342 assert_instr(uzp)
67343)]
67344#[cfg_attr(
67345 not(target_arch = "arm"),
67346 stable(feature = "neon_intrinsics", since = "1.59.0")
67347)]
67348#[cfg_attr(
67349 target_arch = "arm",
67350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67351)]
67352pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
67353 unsafe {
67354 let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67355 let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67356 transmute((a0, b0))
67357 }
67358}
67359#[doc = "Unzip vectors"]
67360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
67361#[inline]
67362#[target_feature(enable = "neon")]
67363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67364#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67365#[cfg_attr(
67366 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67367 assert_instr(uzp)
67368)]
67369#[cfg_attr(
67370 not(target_arch = "arm"),
67371 stable(feature = "neon_intrinsics", since = "1.59.0")
67372)]
67373#[cfg_attr(
67374 target_arch = "arm",
67375 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67376)]
67377pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
67378 unsafe {
67379 let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67380 let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67381 transmute((a0, b0))
67382 }
67383}
67384#[doc = "Unzip vectors"]
67385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
67386#[inline]
67387#[target_feature(enable = "neon")]
67388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67390#[cfg_attr(
67391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67392 assert_instr(uzp)
67393)]
67394#[cfg_attr(
67395 not(target_arch = "arm"),
67396 stable(feature = "neon_intrinsics", since = "1.59.0")
67397)]
67398#[cfg_attr(
67399 target_arch = "arm",
67400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67401)]
67402pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
67403 unsafe {
67404 let a0: int8x16_t = simd_shuffle!(
67405 a,
67406 b,
67407 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
67408 );
67409 let b0: int8x16_t = simd_shuffle!(
67410 a,
67411 b,
67412 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
67413 );
67414 transmute((a0, b0))
67415 }
67416}
67417#[doc = "Unzip vectors"]
67418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
67419#[inline]
67420#[target_feature(enable = "neon")]
67421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67423#[cfg_attr(
67424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67425 assert_instr(uzp)
67426)]
67427#[cfg_attr(
67428 not(target_arch = "arm"),
67429 stable(feature = "neon_intrinsics", since = "1.59.0")
67430)]
67431#[cfg_attr(
67432 target_arch = "arm",
67433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67434)]
67435pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
67436 unsafe {
67437 let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67438 let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67439 transmute((a0, b0))
67440 }
67441}
67442#[doc = "Unzip vectors"]
67443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
67444#[inline]
67445#[target_feature(enable = "neon")]
67446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67448#[cfg_attr(
67449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67450 assert_instr(uzp)
67451)]
67452#[cfg_attr(
67453 not(target_arch = "arm"),
67454 stable(feature = "neon_intrinsics", since = "1.59.0")
67455)]
67456#[cfg_attr(
67457 target_arch = "arm",
67458 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67459)]
67460pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
67461 unsafe {
67462 let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67463 let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67464 transmute((a0, b0))
67465 }
67466}
67467#[doc = "Unzip vectors"]
67468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
67469#[inline]
67470#[target_feature(enable = "neon")]
67471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67473#[cfg_attr(
67474 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67475 assert_instr(uzp)
67476)]
67477#[cfg_attr(
67478 not(target_arch = "arm"),
67479 stable(feature = "neon_intrinsics", since = "1.59.0")
67480)]
67481#[cfg_attr(
67482 target_arch = "arm",
67483 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67484)]
67485pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
67486 unsafe {
67487 let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67488 let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67489 transmute((a0, b0))
67490 }
67491}
67492#[doc = "Unzip vectors"]
67493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
67494#[inline]
67495#[target_feature(enable = "neon")]
67496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67498#[cfg_attr(
67499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67500 assert_instr(uzp)
67501)]
67502#[cfg_attr(
67503 not(target_arch = "arm"),
67504 stable(feature = "neon_intrinsics", since = "1.59.0")
67505)]
67506#[cfg_attr(
67507 target_arch = "arm",
67508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67509)]
67510pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
67511 unsafe {
67512 let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67513 let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67514 transmute((a0, b0))
67515 }
67516}
67517#[doc = "Unzip vectors"]
67518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
67519#[inline]
67520#[target_feature(enable = "neon")]
67521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67522#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67523#[cfg_attr(
67524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67525 assert_instr(uzp)
67526)]
67527#[cfg_attr(
67528 not(target_arch = "arm"),
67529 stable(feature = "neon_intrinsics", since = "1.59.0")
67530)]
67531#[cfg_attr(
67532 target_arch = "arm",
67533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67534)]
67535pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
67536 unsafe {
67537 let a0: uint8x16_t = simd_shuffle!(
67538 a,
67539 b,
67540 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
67541 );
67542 let b0: uint8x16_t = simd_shuffle!(
67543 a,
67544 b,
67545 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
67546 );
67547 transmute((a0, b0))
67548 }
67549}
67550#[doc = "Unzip vectors"]
67551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
67552#[inline]
67553#[target_feature(enable = "neon")]
67554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67556#[cfg_attr(
67557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67558 assert_instr(uzp)
67559)]
67560#[cfg_attr(
67561 not(target_arch = "arm"),
67562 stable(feature = "neon_intrinsics", since = "1.59.0")
67563)]
67564#[cfg_attr(
67565 target_arch = "arm",
67566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67567)]
67568pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
67569 unsafe {
67570 let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67571 let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67572 transmute((a0, b0))
67573 }
67574}
67575#[doc = "Unzip vectors"]
67576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
67577#[inline]
67578#[target_feature(enable = "neon")]
67579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67580#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67581#[cfg_attr(
67582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67583 assert_instr(uzp)
67584)]
67585#[cfg_attr(
67586 not(target_arch = "arm"),
67587 stable(feature = "neon_intrinsics", since = "1.59.0")
67588)]
67589#[cfg_attr(
67590 target_arch = "arm",
67591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67592)]
67593pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
67594 unsafe {
67595 let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67596 let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67597 transmute((a0, b0))
67598 }
67599}
67600#[doc = "Unzip vectors"]
67601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
67602#[inline]
67603#[target_feature(enable = "neon")]
67604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67606#[cfg_attr(
67607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67608 assert_instr(uzp)
67609)]
67610#[cfg_attr(
67611 not(target_arch = "arm"),
67612 stable(feature = "neon_intrinsics", since = "1.59.0")
67613)]
67614#[cfg_attr(
67615 target_arch = "arm",
67616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67617)]
67618pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
67619 unsafe {
67620 let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67621 let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67622 transmute((a0, b0))
67623 }
67624}
67625#[doc = "Unzip vectors"]
67626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
67627#[inline]
67628#[target_feature(enable = "neon")]
67629#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67630#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67631#[cfg_attr(
67632 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67633 assert_instr(uzp)
67634)]
67635#[cfg_attr(
67636 not(target_arch = "arm"),
67637 stable(feature = "neon_intrinsics", since = "1.59.0")
67638)]
67639#[cfg_attr(
67640 target_arch = "arm",
67641 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67642)]
67643pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
67644 unsafe {
67645 let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67646 let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67647 transmute((a0, b0))
67648 }
67649}
67650#[doc = "Unzip vectors"]
67651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
67652#[inline]
67653#[target_feature(enable = "neon")]
67654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67656#[cfg_attr(
67657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67658 assert_instr(uzp)
67659)]
67660#[cfg_attr(
67661 not(target_arch = "arm"),
67662 stable(feature = "neon_intrinsics", since = "1.59.0")
67663)]
67664#[cfg_attr(
67665 target_arch = "arm",
67666 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67667)]
67668pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
67669 unsafe {
67670 let a0: poly8x16_t = simd_shuffle!(
67671 a,
67672 b,
67673 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
67674 );
67675 let b0: poly8x16_t = simd_shuffle!(
67676 a,
67677 b,
67678 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
67679 );
67680 transmute((a0, b0))
67681 }
67682}
67683#[doc = "Unzip vectors"]
67684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
67685#[inline]
67686#[target_feature(enable = "neon")]
67687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67689#[cfg_attr(
67690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67691 assert_instr(uzp)
67692)]
67693#[cfg_attr(
67694 not(target_arch = "arm"),
67695 stable(feature = "neon_intrinsics", since = "1.59.0")
67696)]
67697#[cfg_attr(
67698 target_arch = "arm",
67699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67700)]
67701pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
67702 unsafe {
67703 let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
67704 let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
67705 transmute((a0, b0))
67706 }
67707}
67708#[doc = "Unzip vectors"]
67709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
67710#[inline]
67711#[target_feature(enable = "neon")]
67712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
67714#[cfg_attr(
67715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67716 assert_instr(uzp)
67717)]
67718#[cfg_attr(
67719 not(target_arch = "arm"),
67720 stable(feature = "neon_intrinsics", since = "1.59.0")
67721)]
67722#[cfg_attr(
67723 target_arch = "arm",
67724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67725)]
67726pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
67727 unsafe {
67728 let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
67729 let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
67730 transmute((a0, b0))
67731 }
67732}
67733#[doc = "Zip vectors"]
67734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
67735#[inline]
67736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67737#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
67738#[cfg_attr(
67739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67740 assert_instr(zip)
67741)]
67742#[target_feature(enable = "neon,fp16")]
67743#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67744pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
67745 unsafe {
67746 let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
67747 let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
67748 transmute((a0, b0))
67749 }
67750}
67751#[doc = "Zip vectors"]
67752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
67753#[inline]
67754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67755#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
67756#[cfg_attr(
67757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67758 assert_instr(zip)
67759)]
67760#[target_feature(enable = "neon,fp16")]
67761#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67762pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
67763 unsafe {
67764 let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
67765 let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
67766 transmute((a0, b0))
67767 }
67768}
67769#[doc = "Zip vectors"]
67770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
67771#[inline]
67772#[target_feature(enable = "neon")]
67773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
67775#[cfg_attr(
67776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67777 assert_instr(zip)
67778)]
67779#[cfg_attr(
67780 not(target_arch = "arm"),
67781 stable(feature = "neon_intrinsics", since = "1.59.0")
67782)]
67783#[cfg_attr(
67784 target_arch = "arm",
67785 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67786)]
67787pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
67788 unsafe {
67789 let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
67790 let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
67791 transmute((a0, b0))
67792 }
67793}
67794#[doc = "Zip vectors"]
67795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
67796#[inline]
67797#[target_feature(enable = "neon")]
67798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
67800#[cfg_attr(
67801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67802 assert_instr(zip)
67803)]
67804#[cfg_attr(
67805 not(target_arch = "arm"),
67806 stable(feature = "neon_intrinsics", since = "1.59.0")
67807)]
67808#[cfg_attr(
67809 target_arch = "arm",
67810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67811)]
67812pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
67813 unsafe {
67814 let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
67815 let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
67816 transmute((a0, b0))
67817 }
67818}
67819#[doc = "Zip vectors"]
67820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
67821#[inline]
67822#[target_feature(enable = "neon")]
67823#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67824#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
67825#[cfg_attr(
67826 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67827 assert_instr(zip)
67828)]
67829#[cfg_attr(
67830 not(target_arch = "arm"),
67831 stable(feature = "neon_intrinsics", since = "1.59.0")
67832)]
67833#[cfg_attr(
67834 target_arch = "arm",
67835 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67836)]
67837pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
67838 unsafe {
67839 let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
67840 let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
67841 transmute((a0, b0))
67842 }
67843}
67844#[doc = "Zip vectors"]
67845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
67846#[inline]
67847#[target_feature(enable = "neon")]
67848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
67850#[cfg_attr(
67851 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67852 assert_instr(zip)
67853)]
67854#[cfg_attr(
67855 not(target_arch = "arm"),
67856 stable(feature = "neon_intrinsics", since = "1.59.0")
67857)]
67858#[cfg_attr(
67859 target_arch = "arm",
67860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67861)]
67862pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
67863 unsafe {
67864 let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
67865 let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
67866 transmute((a0, b0))
67867 }
67868}
67869#[doc = "Zip vectors"]
67870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
67871#[inline]
67872#[target_feature(enable = "neon")]
67873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
67875#[cfg_attr(
67876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67877 assert_instr(zip)
67878)]
67879#[cfg_attr(
67880 not(target_arch = "arm"),
67881 stable(feature = "neon_intrinsics", since = "1.59.0")
67882)]
67883#[cfg_attr(
67884 target_arch = "arm",
67885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67886)]
67887pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
67888 unsafe {
67889 let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
67890 let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
67891 transmute((a0, b0))
67892 }
67893}
67894#[doc = "Zip vectors"]
67895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
67896#[inline]
67897#[target_feature(enable = "neon")]
67898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
67900#[cfg_attr(
67901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67902 assert_instr(zip)
67903)]
67904#[cfg_attr(
67905 not(target_arch = "arm"),
67906 stable(feature = "neon_intrinsics", since = "1.59.0")
67907)]
67908#[cfg_attr(
67909 target_arch = "arm",
67910 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67911)]
67912pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
67913 unsafe {
67914 let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
67915 let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
67916 transmute((a0, b0))
67917 }
67918}
67919#[doc = "Zip vectors"]
67920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
67921#[inline]
67922#[target_feature(enable = "neon")]
67923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
67925#[cfg_attr(
67926 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67927 assert_instr(zip)
67928)]
67929#[cfg_attr(
67930 not(target_arch = "arm"),
67931 stable(feature = "neon_intrinsics", since = "1.59.0")
67932)]
67933#[cfg_attr(
67934 target_arch = "arm",
67935 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67936)]
67937pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
67938 unsafe {
67939 let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
67940 let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
67941 transmute((a0, b0))
67942 }
67943}
67944#[doc = "Zip vectors"]
67945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
67946#[inline]
67947#[target_feature(enable = "neon")]
67948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
67950#[cfg_attr(
67951 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67952 assert_instr(zip)
67953)]
67954#[cfg_attr(
67955 not(target_arch = "arm"),
67956 stable(feature = "neon_intrinsics", since = "1.59.0")
67957)]
67958#[cfg_attr(
67959 target_arch = "arm",
67960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67961)]
67962pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
67963 unsafe {
67964 let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
67965 let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
67966 transmute((a0, b0))
67967 }
67968}
67969#[doc = "Zip vectors"]
67970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
67971#[inline]
67972#[target_feature(enable = "neon")]
67973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
67975#[cfg_attr(
67976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67977 assert_instr(zip)
67978)]
67979#[cfg_attr(
67980 not(target_arch = "arm"),
67981 stable(feature = "neon_intrinsics", since = "1.59.0")
67982)]
67983#[cfg_attr(
67984 target_arch = "arm",
67985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67986)]
67987pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
67988 unsafe {
67989 let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
67990 let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
67991 transmute((a0, b0))
67992 }
67993}
67994#[doc = "Zip vectors"]
67995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
67996#[inline]
67997#[target_feature(enable = "neon")]
67998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68000#[cfg_attr(
68001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68002 assert_instr(zip)
68003)]
68004#[cfg_attr(
68005 not(target_arch = "arm"),
68006 stable(feature = "neon_intrinsics", since = "1.59.0")
68007)]
68008#[cfg_attr(
68009 target_arch = "arm",
68010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68011)]
68012pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
68013 unsafe {
68014 let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
68015 let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
68016 transmute((a0, b0))
68017 }
68018}
68019#[doc = "Zip vectors"]
68020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
68021#[inline]
68022#[target_feature(enable = "neon")]
68023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68025#[cfg_attr(
68026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68027 assert_instr(zip)
68028)]
68029#[cfg_attr(
68030 not(target_arch = "arm"),
68031 stable(feature = "neon_intrinsics", since = "1.59.0")
68032)]
68033#[cfg_attr(
68034 target_arch = "arm",
68035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68036)]
68037pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
68038 unsafe {
68039 let a0: int8x16_t = simd_shuffle!(
68040 a,
68041 b,
68042 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
68043 );
68044 let b0: int8x16_t = simd_shuffle!(
68045 a,
68046 b,
68047 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
68048 );
68049 transmute((a0, b0))
68050 }
68051}
68052#[doc = "Zip vectors"]
68053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
68054#[inline]
68055#[target_feature(enable = "neon")]
68056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68058#[cfg_attr(
68059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68060 assert_instr(zip)
68061)]
68062#[cfg_attr(
68063 not(target_arch = "arm"),
68064 stable(feature = "neon_intrinsics", since = "1.59.0")
68065)]
68066#[cfg_attr(
68067 target_arch = "arm",
68068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68069)]
68070pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
68071 unsafe {
68072 let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
68073 let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
68074 transmute((a0, b0))
68075 }
68076}
68077#[doc = "Zip vectors"]
68078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
68079#[inline]
68080#[target_feature(enable = "neon")]
68081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68083#[cfg_attr(
68084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68085 assert_instr(zip)
68086)]
68087#[cfg_attr(
68088 not(target_arch = "arm"),
68089 stable(feature = "neon_intrinsics", since = "1.59.0")
68090)]
68091#[cfg_attr(
68092 target_arch = "arm",
68093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68094)]
68095pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
68096 unsafe {
68097 let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
68098 let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
68099 transmute((a0, b0))
68100 }
68101}
68102#[doc = "Zip vectors"]
68103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
68104#[inline]
68105#[target_feature(enable = "neon")]
68106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68108#[cfg_attr(
68109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68110 assert_instr(zip)
68111)]
68112#[cfg_attr(
68113 not(target_arch = "arm"),
68114 stable(feature = "neon_intrinsics", since = "1.59.0")
68115)]
68116#[cfg_attr(
68117 target_arch = "arm",
68118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68119)]
68120pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
68121 unsafe {
68122 let a0: uint8x16_t = simd_shuffle!(
68123 a,
68124 b,
68125 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
68126 );
68127 let b0: uint8x16_t = simd_shuffle!(
68128 a,
68129 b,
68130 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
68131 );
68132 transmute((a0, b0))
68133 }
68134}
68135#[doc = "Zip vectors"]
68136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
68137#[inline]
68138#[target_feature(enable = "neon")]
68139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68141#[cfg_attr(
68142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68143 assert_instr(zip)
68144)]
68145#[cfg_attr(
68146 not(target_arch = "arm"),
68147 stable(feature = "neon_intrinsics", since = "1.59.0")
68148)]
68149#[cfg_attr(
68150 target_arch = "arm",
68151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68152)]
68153pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
68154 unsafe {
68155 let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
68156 let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
68157 transmute((a0, b0))
68158 }
68159}
68160#[doc = "Zip vectors"]
68161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
68162#[inline]
68163#[target_feature(enable = "neon")]
68164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68166#[cfg_attr(
68167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68168 assert_instr(zip)
68169)]
68170#[cfg_attr(
68171 not(target_arch = "arm"),
68172 stable(feature = "neon_intrinsics", since = "1.59.0")
68173)]
68174#[cfg_attr(
68175 target_arch = "arm",
68176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68177)]
68178pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
68179 unsafe {
68180 let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
68181 let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
68182 transmute((a0, b0))
68183 }
68184}
68185#[doc = "Zip vectors"]
68186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
68187#[inline]
68188#[target_feature(enable = "neon")]
68189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68191#[cfg_attr(
68192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68193 assert_instr(zip)
68194)]
68195#[cfg_attr(
68196 not(target_arch = "arm"),
68197 stable(feature = "neon_intrinsics", since = "1.59.0")
68198)]
68199#[cfg_attr(
68200 target_arch = "arm",
68201 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68202)]
68203pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
68204 unsafe {
68205 let a0: poly8x16_t = simd_shuffle!(
68206 a,
68207 b,
68208 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
68209 );
68210 let b0: poly8x16_t = simd_shuffle!(
68211 a,
68212 b,
68213 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
68214 );
68215 transmute((a0, b0))
68216 }
68217}
68218#[doc = "Zip vectors"]
68219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
68220#[inline]
68221#[target_feature(enable = "neon")]
68222#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68223#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
68224#[cfg_attr(
68225 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68226 assert_instr(zip)
68227)]
68228#[cfg_attr(
68229 not(target_arch = "arm"),
68230 stable(feature = "neon_intrinsics", since = "1.59.0")
68231)]
68232#[cfg_attr(
68233 target_arch = "arm",
68234 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68235)]
68236pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
68237 unsafe {
68238 let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
68239 let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
68240 transmute((a0, b0))
68241 }
68242}