libad9361 0.2 Device specific library for AD936X transceivers

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ad9361.h
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1/*
2 * Copyright (C) 2015 Analog Devices, Inc.
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2.1 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 */
14
18#ifndef __AD9361_H__
19#define __AD9361_H__
20
21#ifdef __cplusplus
22 extern "C" {
23#endif
24
25
34#define FIXUP_INTERFACE_TIMING 1
38#define CHECK_SAMPLE_RATES 2
39
42#ifdef _WIN32
43# ifdef LIBAD9361_EXPORTS
44# define __api __declspec(dllexport)
45# else
46# define __api __declspec(dllimport)
47# endif
48#elif __GNUC__ >= 4 && !defined(MATLAB_MEX_FILE) && !defined(MATLAB_LOADLIBRARY)
49# define __api __attribute__((visibility ("default")))
50#else
51# define __api
52#endif
53
54 struct iio_context;
55 struct iio_device;
56
64 struct filter_design_parameters {
65 double Rdata;
66 double Fpass;
67 double Fstop;
68 double caldiv;
69 double FIR;
70 double HB1;
71 double DAC_div;
72 const char *Type;
73 const char *RxTx;
74 double RFbw;
75 double converter_rate;
76 double PLL_rate;
77 double Fcenter;
78 double wnom;
79 double FIRdBmin;
80 double int_FIR;
81 double PLL_mult;
82 double Apass;
83 double Astop;
84 double phEQ;
85 double HB2;
86 double HB3;
87 double maxTaps;
88};
89
90/* ---------------------------------------------------------------------------*/
91/* ------------------------- Top-level functions -----------------------------*/
103__api int ad9361_multichip_sync(struct iio_device *master,
104 struct iio_device **slaves, unsigned int num_slaves,
105 unsigned int flags);
106
112__api int ad9361_fmcomms5_multichip_sync(
113 struct iio_context *ctx, unsigned int flags);
114
124__api int ad9361_set_bb_rate(struct iio_device *dev, unsigned long rate);
125
131__api int ad9361_set_trx_fir_enable(struct iio_device *dev, int enable);
132
138__api int ad9361_get_trx_fir_enable(struct iio_device *dev, int *enable);
139
147__api int ad9361_generate_fir_taps(struct filter_design_parameters *parameters,
148 short *taps, int *num_taps, int *gain);
149
157__api int ad9361_calculate_rf_clock_chain(unsigned long tx_sample_rate,
158 unsigned long rate_gov,
159 unsigned long *rx_path_clks,
160 unsigned long *tx_path_clks);
161
168__api int ad9361_calculate_rf_clock_chain_fdp(struct filter_design_parameters *fdpTX,
169 struct filter_design_parameters *fdpRX,
170 unsigned long sample_rate);
171
183__api int ad9361_set_bb_rate_custom_filter_auto(struct iio_device *dev,
184 unsigned long rate);
185
195__api int ad9361_set_bb_rate_custom_filter_manual(struct iio_device *dev,
196 unsigned long rate, unsigned long Fpass,
197 unsigned long Fstop, unsigned long wnom_tx,
198 unsigned long wnom_rx);
199
217__api int ad9361_fmcomms5_phase_sync(struct iio_context *ctx, long long lo);
218
221#ifdef __cplusplus
222}
223#endif
224
225#undef __api
226
227#endif /* __AD9361_H__ */
ad9361_multichip_sync
__api int ad9361_multichip_sync(struct iio_device *master, struct iio_device **slaves, unsigned int num_slaves, unsigned int flags)
Multi-chip synchronization (MCS) management.
Definition ad9361_multichip_sync.c:42
ad9361_calculate_rf_clock_chain_fdp
__api int ad9361_calculate_rf_clock_chain_fdp(struct filter_design_parameters *fdpTX, struct filter_design_parameters *fdpRX, unsigned long sample_rate)
Calculate the clock path rates and default filter settings for both transmit and receiver for a desir...
Definition ad9361_design_taps.c:305
ad9361_set_trx_fir_enable
__api int ad9361_set_trx_fir_enable(struct iio_device *dev, int enable)
Enable or disable transmit and receiver FIRs simultaneously.
Definition ad9361_baseband_auto_rate.c:54
ad9361_set_bb_rate
__api int ad9361_set_bb_rate(struct iio_device *dev, unsigned long rate)
Baseband rate configuration with generic filter support.
Definition ad9361_baseband_auto_rate.c:80
ad9361_generate_fir_taps
__api int ad9361_generate_fir_taps(struct filter_design_parameters *parameters, short *taps, int *num_taps, int *gain)
Design custom FIR filter from specific design criteria.
Definition ad9361_design_taps.c:37
ad9361_fmcomms5_multichip_sync
__api int ad9361_fmcomms5_multichip_sync(struct iio_context *ctx, unsigned int flags)
FMComms5 specific MCS management.
Definition ad9361_multichip_sync.c:118
ad9361_get_trx_fir_enable
__api int ad9361_get_trx_fir_enable(struct iio_device *dev, int *enable)
Get current enable value of transmit and receiver FIRs.
Definition ad9361_baseband_auto_rate.c:64
ad9361_set_bb_rate_custom_filter_auto
__api int ad9361_set_bb_rate_custom_filter_auto(struct iio_device *dev, unsigned long rate)
Baseband rate configuration with custom filter support based on desired baseband sample rate.
Definition ad9361_design_taps.c:326
ad9361_calculate_rf_clock_chain
__api int ad9361_calculate_rf_clock_chain(unsigned long tx_sample_rate, unsigned long rate_gov, unsigned long *rx_path_clks, unsigned long *tx_path_clks)
Calculate the clock path rates for both transmit and receiver paths.
Definition ad9361_calculate_rf_clock_chain.c:177
ad9361_fmcomms5_phase_sync
__api int ad9361_fmcomms5_phase_sync(struct iio_context *ctx, long long lo)
FMComms5 phase synchronize all TX and RX channels together.
Definition ad9361_fmcomms5_phase_sync.c:577
ad9361_set_bb_rate_custom_filter_manual
__api int ad9361_set_bb_rate_custom_filter_manual(struct iio_device *dev, unsigned long rate, unsigned long Fpass, unsigned long Fstop, unsigned long wnom_tx, unsigned long wnom_rx)
Baseband rate configuration with custom filter support based on desired baseband sample rate and simp...
Definition ad9361_design_taps.c:359
filter_design_parameters
Custom Filter Design Parameters.
Definition ad9361.h:64
filter_design_parameters::FIRdBmin
double FIRdBmin
Definition ad9361.h:79
filter_design_parameters::caldiv
double caldiv
Definition ad9361.h:68
filter_design_parameters::PLL_rate
double PLL_rate
Definition ad9361.h:76
filter_design_parameters::HB3
double HB3
Definition ad9361.h:86
filter_design_parameters::PLL_mult
double PLL_mult
Definition ad9361.h:81
filter_design_parameters::RxTx
const char * RxTx
Definition ad9361.h:73
filter_design_parameters::FIR
double FIR
Definition ad9361.h:69
filter_design_parameters::wnom
double wnom
Definition ad9361.h:78
filter_design_parameters::Astop
double Astop
Definition ad9361.h:83
filter_design_parameters::HB1
double HB1
Definition ad9361.h:70
filter_design_parameters::converter_rate
double converter_rate
Definition ad9361.h:75
filter_design_parameters::Rdata
double Rdata
Definition ad9361.h:65
filter_design_parameters::Apass
double Apass
Definition ad9361.h:82
filter_design_parameters::DAC_div
double DAC_div
Definition ad9361.h:71
filter_design_parameters::Fstop
double Fstop
Definition ad9361.h:67
filter_design_parameters::Fpass
double Fpass
Definition ad9361.h:66
filter_design_parameters::maxTaps
double maxTaps
Definition ad9361.h:87
filter_design_parameters::HB2
double HB2
Definition ad9361.h:85
filter_design_parameters::RFbw
double RFbw
Definition ad9361.h:74
filter_design_parameters::Type
const char * Type
Definition ad9361.h:72
filter_design_parameters::Fcenter
double Fcenter
Definition ad9361.h:77
filter_design_parameters::phEQ
double phEQ
Definition ad9361.h:84
filter_design_parameters::int_FIR
double int_FIR
Definition ad9361.h:80