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#
#Copyright (c) 2023 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
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#      http://www.apache.org/licenses/LICENSE-2.0
#
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#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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############################################################################
#This is an experiment with an encoder table. It does not set fields
#that are initialized to zero (REXR, REXB). It sets NOREX, NEEDREX to
#indicated encoding constraints.
############################################################################



xed_reg_enum_t GPR8_R()::

OUTREG=XED_REG_AL -> REXR4=0 REXR=0 REG=0x0
OUTREG=XED_REG_CL -> REXR4=0 REXR=0 REG=0x1
OUTREG=XED_REG_DL -> REXR4=0 REXR=0 REG=0x2
OUTREG=XED_REG_BL -> REXR4=0 REXR=0 REG=0x3

VV0 OUTREG=XED_REG_AH -> REXR4=0 REXR=0 REG=0x4  NOREX=1
VV0 OUTREG=XED_REG_CH -> REXR4=0 REXR=0 REG=0x5  NOREX=1
VV0 OUTREG=XED_REG_DH -> REXR4=0 REXR=0 REG=0x6  NOREX=1
VV0 OUTREG=XED_REG_BH -> REXR4=0 REXR=0 REG=0x7  NOREX=1

OUTREG=XED_REG_SPL ->  REXR4=0 REXR=0 REG=0x4  NEEDREX=1
OUTREG=XED_REG_BPL ->  REXR4=0 REXR=0 REG=0x5  NEEDREX=1
OUTREG=XED_REG_SIL ->  REXR4=0 REXR=0 REG=0x6  NEEDREX=1
OUTREG=XED_REG_DIL ->  REXR4=0 REXR=0 REG=0x7  NEEDREX=1

OUTREG=XED_REG_R8B  -> REXR4=0 REXR=1 REG=0x0
OUTREG=XED_REG_R9B  -> REXR4=0 REXR=1 REG=0x1
OUTREG=XED_REG_R10B -> REXR4=0 REXR=1 REG=0x2
OUTREG=XED_REG_R11B -> REXR4=0 REXR=1 REG=0x3
OUTREG=XED_REG_R12B -> REXR4=0 REXR=1 REG=0x4
OUTREG=XED_REG_R13B -> REXR4=0 REXR=1 REG=0x5
OUTREG=XED_REG_R14B -> REXR4=0 REXR=1 REG=0x6
OUTREG=XED_REG_R15B -> REXR4=0 REXR=1 REG=0x7

OUTREG=XED_REG_R16B -> REXR4=1 REXR=0 REG=0x0  
OUTREG=XED_REG_R17B -> REXR4=1 REXR=0 REG=0x1  
OUTREG=XED_REG_R18B -> REXR4=1 REXR=0 REG=0x2  
OUTREG=XED_REG_R19B -> REXR4=1 REXR=0 REG=0x3  
OUTREG=XED_REG_R20B -> REXR4=1 REXR=0 REG=0x4  
OUTREG=XED_REG_R21B -> REXR4=1 REXR=0 REG=0x5  
OUTREG=XED_REG_R22B -> REXR4=1 REXR=0 REG=0x6  
OUTREG=XED_REG_R23B -> REXR4=1 REXR=0 REG=0x7  

OUTREG=XED_REG_R24B -> REXR4=1 REXR=1 REG=0x0  
OUTREG=XED_REG_R25B -> REXR4=1 REXR=1 REG=0x1  
OUTREG=XED_REG_R26B -> REXR4=1 REXR=1 REG=0x2  
OUTREG=XED_REG_R27B -> REXR4=1 REXR=1 REG=0x3  
OUTREG=XED_REG_R28B -> REXR4=1 REXR=1 REG=0x4  
OUTREG=XED_REG_R29B -> REXR4=1 REXR=1 REG=0x5  
OUTREG=XED_REG_R30B -> REXR4=1 REXR=1 REG=0x6  
OUTREG=XED_REG_R31B -> REXR4=1 REXR=1 REG=0x7  


xed_reg_enum_t GPR8_B()::
OUTREG=XED_REG_AL -> REXB4=0 REXB=0 RM=0x0
OUTREG=XED_REG_CL -> REXB4=0 REXB=0 RM=0x1
OUTREG=XED_REG_DL -> REXB4=0 REXB=0 RM=0x2
OUTREG=XED_REG_BL -> REXB4=0 REXB=0 RM=0x3

VV0 OUTREG=XED_REG_AH -> REXB4=0 REXB=0 RM=0x4  NOREX=1
VV0 OUTREG=XED_REG_CH -> REXB4=0 REXB=0 RM=0x5  NOREX=1
VV0 OUTREG=XED_REG_DH -> REXB4=0 REXB=0 RM=0x6  NOREX=1
VV0 OUTREG=XED_REG_BH -> REXB4=0 REXB=0 RM=0x7  NOREX=1

OUTREG=XED_REG_SPL -> REXB4=0 REXB=0 RM=0x4  NEEDREX=1
OUTREG=XED_REG_BPL -> REXB4=0 REXB=0 RM=0x5  NEEDREX=1
OUTREG=XED_REG_SIL -> REXB4=0 REXB=0 RM=0x6  NEEDREX=1
OUTREG=XED_REG_DIL -> REXB4=0 REXB=0 RM=0x7  NEEDREX=1

OUTREG=XED_REG_R8B  -> REXB4=0 REXB=1 RM=0x0
OUTREG=XED_REG_R9B  -> REXB4=0 REXB=1 RM=0x1
OUTREG=XED_REG_R10B -> REXB4=0 REXB=1 RM=0x2
OUTREG=XED_REG_R11B -> REXB4=0 REXB=1 RM=0x3
OUTREG=XED_REG_R12B -> REXB4=0 REXB=1 RM=0x4
OUTREG=XED_REG_R13B -> REXB4=0 REXB=1 RM=0x5
OUTREG=XED_REG_R14B -> REXB4=0 REXB=1 RM=0x6
OUTREG=XED_REG_R15B -> REXB4=0 REXB=1 RM=0x7

OUTREG=XED_REG_R16B -> REXB4=1 REXB=0 RM=0x0  
OUTREG=XED_REG_R17B -> REXB4=1 REXB=0 RM=0x1  
OUTREG=XED_REG_R18B -> REXB4=1 REXB=0 RM=0x2  
OUTREG=XED_REG_R19B -> REXB4=1 REXB=0 RM=0x3  
OUTREG=XED_REG_R20B -> REXB4=1 REXB=0 RM=0x4  
OUTREG=XED_REG_R21B -> REXB4=1 REXB=0 RM=0x5  
OUTREG=XED_REG_R22B -> REXB4=1 REXB=0 RM=0x6  
OUTREG=XED_REG_R23B -> REXB4=1 REXB=0 RM=0x7  

OUTREG=XED_REG_R24B -> REXB4=1 REXB=1 RM=0x0  
OUTREG=XED_REG_R25B -> REXB4=1 REXB=1 RM=0x1  
OUTREG=XED_REG_R26B -> REXB4=1 REXB=1 RM=0x2  
OUTREG=XED_REG_R27B -> REXB4=1 REXB=1 RM=0x3  
OUTREG=XED_REG_R28B -> REXB4=1 REXB=1 RM=0x4  
OUTREG=XED_REG_R29B -> REXB4=1 REXB=1 RM=0x5  
OUTREG=XED_REG_R30B -> REXB4=1 REXB=1 RM=0x6  
OUTREG=XED_REG_R31B -> REXB4=1 REXB=1 RM=0x7  


xed_reg_enum_t GPR8_SB()::
OUTREG=XED_REG_AL -> REXB4=0 REXB=0 SRM=0x0
OUTREG=XED_REG_CL -> REXB4=0 REXB=0 SRM=0x1
OUTREG=XED_REG_DL -> REXB4=0 REXB=0 SRM=0x2
OUTREG=XED_REG_BL -> REXB4=0 REXB=0 SRM=0x3

VV0 OUTREG=XED_REG_AH -> REXB4=0 REXB=0 SRM=0x4  NOREX=1
VV0 OUTREG=XED_REG_CH -> REXB4=0 REXB=0 SRM=0x5  NOREX=1
VV0 OUTREG=XED_REG_DH -> REXB4=0 REXB=0 SRM=0x6  NOREX=1
VV0 OUTREG=XED_REG_BH -> REXB4=0 REXB=0 SRM=0x7  NOREX=1

OUTREG=XED_REG_SPL -> REXB4=0 REXB=0 SRM=0x4  NEEDREX=1
OUTREG=XED_REG_BPL -> REXB4=0 REXB=0 SRM=0x5  NEEDREX=1
OUTREG=XED_REG_SIL -> REXB4=0 REXB=0 SRM=0x6  NEEDREX=1
OUTREG=XED_REG_DIL -> REXB4=0 REXB=0 SRM=0x7  NEEDREX=1

OUTREG=XED_REG_R8B  -> REXB4=0 REXB=1 SRM=0x0
OUTREG=XED_REG_R9B  -> REXB4=0 REXB=1 SRM=0x1
OUTREG=XED_REG_R10B -> REXB4=0 REXB=1 SRM=0x2
OUTREG=XED_REG_R11B -> REXB4=0 REXB=1 SRM=0x3
OUTREG=XED_REG_R12B -> REXB4=0 REXB=1 SRM=0x4
OUTREG=XED_REG_R13B -> REXB4=0 REXB=1 SRM=0x5
OUTREG=XED_REG_R14B -> REXB4=0 REXB=1 SRM=0x6
OUTREG=XED_REG_R15B -> REXB4=0 REXB=1 SRM=0x7

OUTREG=XED_REG_R16B -> REXB4=1 REXB=0 SRM=0x0  
OUTREG=XED_REG_R17B -> REXB4=1 REXB=0 SRM=0x1  
OUTREG=XED_REG_R18B -> REXB4=1 REXB=0 SRM=0x2  
OUTREG=XED_REG_R19B -> REXB4=1 REXB=0 SRM=0x3  
OUTREG=XED_REG_R20B -> REXB4=1 REXB=0 SRM=0x4  
OUTREG=XED_REG_R21B -> REXB4=1 REXB=0 SRM=0x5  
OUTREG=XED_REG_R22B -> REXB4=1 REXB=0 SRM=0x6  
OUTREG=XED_REG_R23B -> REXB4=1 REXB=0 SRM=0x7  

OUTREG=XED_REG_R24B -> REXB4=1 REXB=1 SRM=0x0  
OUTREG=XED_REG_R25B -> REXB4=1 REXB=1 SRM=0x1  
OUTREG=XED_REG_R26B -> REXB4=1 REXB=1 SRM=0x2  
OUTREG=XED_REG_R27B -> REXB4=1 REXB=1 SRM=0x3  
OUTREG=XED_REG_R28B -> REXB4=1 REXB=1 SRM=0x4  
OUTREG=XED_REG_R29B -> REXB4=1 REXB=1 SRM=0x5  
OUTREG=XED_REG_R30B -> REXB4=1 REXB=1 SRM=0x6  
OUTREG=XED_REG_R31B -> REXB4=1 REXB=1 SRM=0x7  
