#BEGIN_LEGAL
#
#Copyright (c) 2024 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
#
#
#
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING VSM4KEY4 (VSM4KEY4-128-2)
{
ICLASS:      VSM4KEY4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_128
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
PATTERN:     EVV 0xDA VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32
IFORM:       VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512
}

{
ICLASS:      VSM4KEY4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_128
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:     EVV 0xDA VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:dq:u32
IFORM:       VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512
}


# EMITTING VSM4KEY4 (VSM4KEY4-256-2)
{
ICLASS:      VSM4KEY4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_256
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
PATTERN:     EVV 0xDA VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 ZEROING=0 MASK=0
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32
IFORM:       VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512
}

{
ICLASS:      VSM4KEY4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_256
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:     EVV 0xDA VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL256 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=YMM_N3():r:qq:u32 MEM0:r:qq:u32
IFORM:       VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512
}


# EMITTING VSM4KEY4 (VSM4KEY4-512-1)
{
ICLASS:      VSM4KEY4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_512
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
PATTERN:     EVV 0xDA VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32
IFORM:       VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VSM4KEY4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_512
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:     EVV 0xDA VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=ZMM_N3():r:zu32 MEM0:r:zd:u32
IFORM:       VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512
}


# EMITTING VSM4RNDS4 (VSM4RNDS4-128-2)
{
ICLASS:      VSM4RNDS4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_128
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
PATTERN:     EVV 0xDA VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32
IFORM:       VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512
}

{
ICLASS:      VSM4RNDS4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_128
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:     EVV 0xDA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:dq:u32
IFORM:       VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512
}


# EMITTING VSM4RNDS4 (VSM4RNDS4-256-2)
{
ICLASS:      VSM4RNDS4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_256
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
PATTERN:     EVV 0xDA VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 ZEROING=0 MASK=0
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32
IFORM:       VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512
}

{
ICLASS:      VSM4RNDS4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_256
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:     EVV 0xDA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL256 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=YMM_N3():r:qq:u32 MEM0:r:qq:u32
IFORM:       VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512
}


# EMITTING VSM4RNDS4 (VSM4RNDS4-512-1)
{
ICLASS:      VSM4RNDS4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_512
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
PATTERN:     EVV 0xDA VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32
IFORM:       VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VSM4RNDS4
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     SM4_512
EXCEPTIONS:  AVX512-E6
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM 
PATTERN:     EVV 0xDA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=ZMM_N3():r:zu32 MEM0:r:zd:u32
IFORM:       VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512
}


