޴8l( H4ti,omap5-uevmti,omap5&7TI OMAP5 uEVM boardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000 /connector1/ocp/usbhshost@4a064000/ehci@4a064c00/usbether@3cpuscpu@0cpuarm,cortex-a15B@,`cpu cpu@1cpuarm,cortex-a15thermal-zonescpu_thermal'=Ktripscpu_alert[gpassivecpu_crit[Hg criticalcooling-mapsmap0r wgpu_thermal'=Ktripsgpu_crit[Hg criticalcore_thermal'=Ktripscore_crit[Hg criticaltimerarm,armv7-timer0   &pmuarm,cortex-a15-pmuinterrupt-controller@48211000arm,cortex-a15-gic@H!H! H!@ H!` &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(&socti,omap-inframpu ti,omap4-mpumpuocpti,omap5-l3-nocsimple-busl3_main_1l3_main_2l3_main_30D D0E@  l4@4a000000ti,omap5-l4-cfgsimple-bus J"scm@2000ti,omap5-scm-coresimple-bus   scm_conf@0sysconscm@2800%ti,omap5-scm-padconf-coresimple-bus (pinmux@40 ti,omap5-padconfpinctrl-single@default% ~~pinmux_twl6040_pins/~ttpinmux_mcpdm_pins(/B\^`bpinmux_mcbsp1_pins /LN PR pinmux_mcbsp2_pins /TVXZpinmux_i2c1_pins/llpinmux_mcspi2_pins /zzpinmux_mcspi3_pins /xz|~{{pinmux_mmc3_pins0/dfhjlnpinmux_wlan_pins/|palmas_msecure_pins/@nnpinmux_usbhost_pins0/pn  pinmux_led_gpio_pins/  pinmux_uart1_pins /`bdf||pinmux_uart3_pins/}}pinmux_uart5_pins /prtvpinmux_dss_hdmi_pins/pinmux_tpd12s015_pins/pinmux_evm_keys_gpio_pins/vpinmux_i2c5_pins/yyomap5_padconf_global@5a0sysconsimple-bus   pbias_regulator@60ti,pbias-omap5ti,pbias-omap`C pbias_mmc_omap5Jpbias_mmc_omap5Yw@q-cm_core_aon@4000ti,omap5-cm-core-aon@ clockspad_clks_src_ck fixed-clock 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`dlhdpll_mpu_m2_ck@170ti,divider-clockpper_dpll_hs_clk_divfixed-factor-clock..usb_dpll_hs_clk_divfixed-factor-clock44l3_iclk_div@100ti,divider-clock!!gpu_l3_iclkfixed-factor-clock!l4_root_clk_div@100ti,divider-clock!slimbus1_slimbus_clk@560ti,gate-clock" `aess_fclk@528ti,divider-clock#(dmic_sync_mux_ck@538 ti,mux-clock $%&8''dmic_gfclk@538 ti,mux-clock '("8mcasp_sync_mux_ck@540 ti,mux-clock $%&@))mcasp_gfclk@540 ti,mux-clock )("@mcbsp1_sync_mux_ck@548 ti,mux-clock $%&H**mcbsp1_gfclk@548 ti,mux-clock *("Hmcbsp2_sync_mux_ck@550 ti,mux-clock $%&P++mcbsp2_gfclk@550 ti,mux-clock +("Pmcbsp3_sync_mux_ck@558 ti,mux-clock $%&X,,mcbsp3_gfclk@558 ti,mux-clock ,("Xtimer5_gfclk_mux@568 ti,mux-clock%-htimer6_gfclk_mux@570 ti,mux-clock%-ptimer7_gfclk_mux@578 ti,mux-clock%-xtimer8_gfclk_mux@580 ti,mux-clock%-dummy_ck fixed-clockclockdomainscm_core@8000ti,omap5-cm-core0clocksdpll_per_byp_mux@14c ti,mux-clock.L//dpll_per_ck@140ti,omap4-dpll-clock/@DLH00dpll_per_x2_ckti,omap4-dpll-x2-clock011dpll_per_h11x2_ck@158ti,divider-clock1?X77dpll_per_h12x2_ck@15cti,divider-clock1?\<<dpll_per_h14x2_ck@164ti,divider-clock1?dGGdpll_per_m2_ck@150ti,divider-clock0P99dpll_per_m2x2_ck@150ti,divider-clock1P88dpll_per_m3x2_ck@154ti,divider-clock1TUUdpll_unipro1_ck@200ti,omap4-dpll-clock 22dpll_unipro1_clkdcoldofixed-factor-clock2>>dpll_unipro1_m2_ck@210ti,divider-clock2??dpll_unipro2_ck@1c0ti,omap4-dpll-clock33dpll_unipro2_clkdcoldofixed-factor-clock3dpll_unipro2_m2_ck@1d0ti,divider-clock3dpll_usb_byp_mux@18c ti,mux-clock455dpll_usb_ck@180ti,omap4-dpll-j-type-clock566dpll_usb_clkdcoldofixed-factor-clock6EEdpll_usb_m2_ck@190ti,divider-clock6::func_128m_clkfixed-factor-clock7HHfunc_12m_fclkfixed-factor-clock8func_24m_clkfixed-factor-clock9&&func_48m_fclkfixed-factor-clock8;;func_96m_fclkfixed-factor-clock8==l3init_60m_fclk@104ti,divider-clock:@@dss_32khz_clk@1420ti,gate-clock-  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custefuse_sys_gfclk_divfixed-factor-clockdss_syc_gfclk_divfixed-factor-clock%%wkupaon_iclk_mux@108 ti,mux-clockRSSl3instr_ts_gclk_divfixed-factor-clockSgpio1_dbclk@1938ti,gate-clock-8timer1_gfclk_mux@1940 ti,mux-clock-@clockdomainsscrm@a000ti,omap5-scrm clocksauxclk0_src_gate_ck@310 ti,composite-no-wait-gate-clockTVVauxclk0_src_mux_ck@310ti,composite-mux-clock TUWWauxclk0_src_ckti,composite-clockVWXXauxclk0_ck@310ti,divider-clockXeeauxclk1_src_gate_ck@314 ti,composite-no-wait-gate-clockTYYauxclk1_src_mux_ck@314ti,composite-mux-clock TUZZauxclk1_src_ckti,composite-clockYZ[[auxclk1_ck@314ti,divider-clock[ffauxclk2_src_gate_ck@318 ti,composite-no-wait-gate-clockT\\auxclk2_src_mux_ck@318ti,composite-mux-clock TU]]auxclk2_src_ckti,composite-clock\]^^auxclk2_ck@318ti,divider-clock^ggauxclk3_src_gate_ck@31c ti,composite-no-wait-gate-clockT__auxclk3_src_mux_ck@31cti,composite-mux-clock TU``auxclk3_src_ckti,composite-clock_`aaauxclk3_ck@31cti,divider-clockahhauxclk4_src_gate_ck@320 ti,composite-no-wait-gate-clockT bbauxclk4_src_mux_ck@320ti,composite-mux-clock TU ccauxclk4_src_ckti,composite-clockbcddauxclk4_ck@320ti,divider-clockd iiauxclkreq0_ck@210 ti,mux-clockefghiauxclkreq1_ck@214 ti,mux-clockefghiauxclkreq2_ck@218 ti,mux-clockefghiauxclkreq3_ck@21c ti,mux-clockefghiclockdomainspinmux@c840 ti,omap5-padconfpinctrl-single@<default%jpinmux_palmas_sys_nirq_pins/(mmpinmux_usbhost_wkup_pins/jjpinmux_wlcore_irq_pin/ocmcram@40300000 mmio-sram@0dma-controller@4a056000ti,omap4430-sdmaJ`0  * 7kkgpio@4ae10000ti,omap4-gpioJ gpio1DVfgpio@48055000ti,omap4-gpioHP gpio2Vfgpio@48057000ti,omap4-gpioHp gpio3Vfgpio@48059000ti,omap4-gpioH  gpio4Vfgpio@4805b000ti,omap4-gpioH !gpio5Vfxxgpio@4805d000ti,omap4-gpioH "gpio6Vfgpio@48051000ti,omap4-gpioH #gpio7Vfgpio@48053000ti,omap4-gpioH0 ygpio8Vfp234r{ gpio8_234/msecuregpmc@50000000ti,omap4430-gpmcP krxtxgpmc!fckVfi2c@48070000 ti,omap4-i2cH 8i2c1default%lpalmas@48 ti,palmas Hdefault%mnppgpioti,palmas-gpioVfoopalmas_usbti,palmas-usb-vid' 1opalmas_clk32k@1ti,palmas-clk32kgaudiowwrtcti,palmas-rtc&p:Wgpadcti,palmas-gpadc} palmas_pmicti,palmas-pmic&p short-irqqq qq-q=qMqcqyqqrrqrqqsqqregulatorssmps123Jsmps123Y 'q`!5smps45Jsmps45Y 'q0!5smps6Jsmps6Ypqp!5smps7Jsmps7Yw@qw@!5uusmps8Jsmps8Y 'q0!5smps9Jsmps9Y q Gvvsmps10_out2 Jsmps10_out2YLK@qLK@!5smps10_out1 Jsmps10_out1YLK@qLK@ldo1Jldo1Yw@qw@ldo2Jldo2Y*q* Udisabledldo3Jldo3Y`q`5 Udisabledldo4Jldo4Yw@qw@ldo5Jldo5Yw@qw@!5ldo6Jldo6YOqO!5ldo7Jldo7Yq Udisabledldo8Jldo8Y-q-5 Udisabledldo9Jldo9Yw@q-5ldolnJldolnYw@qw@!5ldousbJldousbY1Pq1P!5regen3Jregen3!5palmas_power_buttonti,palmas-pwrbutton&p\twl@4b ti,twl6040Kdefault%t wjuuvwclk32k x eeprom@50 atmel,24c02Pi2c@48072000 ti,omap4-i2cH  9i2c2i2c@48060000 ti,omap4-i2cH =i2c3i2c@4807a000 ti,omap4-i2cH >i2c4i2c@4807c000 ti,omap4-i2cH <i2c5default%ygpio@22 ti,tca6424"Vfspinlock@4a0f6000ti,omap4-hwspinlockJ` spinlockspi@48098000ti,omap4-mcspiH  Amcspi1@k#k$k%k&k'k(k)k* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap4-mcspiH  Bmcspi2 k+k,k-k.tx0rx0tx1rx1default%zspi@480b8000ti,omap4-mcspiH  [mcspi3kktx0rx0default%{spi@480ba000ti,omap4-mcspiH  0mcspi4kFkGtx0rx0serial@4806a000ti,omap4-uartH Huart1ldefault%|serial@4806c000ti,omap4-uartH Iuart2lserial@48020000ti,omap4-uartH Juart3ldefault%}J~serial@4806e000ti,omap4-uartH Fuart4lserial@48066000ti,omap4-uartH` iuart5ldefault%serial@48068000ti,omap4-uartH juart6lmmc@4809c000ti,omap4-hsmmcH  Smmc1k=k>txrxmmc@480b4000ti,omap4-hsmmcH @ Vmmc2k/k0txrxsmmc@480ad000ti,omap4-hsmmcH  ^mmc3kMkNtxrx-8default%^~jwlcore@2 ti,wl1837default%&Kmmc@480d1000ti,omap4-hsmmcH  `mmc4k9k:txrx Udisabledmmc@480d5000ti,omap4-hsmmcH P ;mmc5k;k<txrx Udisabledmmu@4a066000ti,omap4-iommuJ` mmu_dsp_mmu@55082000ti,omap4-iommuU  dmmu_ipu_lkeypad@4ae1c000ti,omap4-keypadJkbdmcpdm@40132000ti,omap4-mcpdm@ I mpudma pmcpdmkAkBup_linkdn_linkUokaydefault%pdmclkdmic@4012e000ti,omap4-dmic@Impudma rdmickCup_link Udisabledmcbsp@40122000ti,omap4-mcbsp@ I mpudma commonmcbsp1k!k"txrxUokaydefault%mcbsp@40124000ti,omap4-mcbsp@@I@mpudma commonmcbsp2kktxrxUokaydefault%mcbsp@40126000ti,omap4-mcbsp@`I`mpudma commonmcbsp3kktxrx Udisabledmailbox@4a0f4000ti,omap4-mailboxJ@ mailboxmbox_ipu  mbox_dsp  timer@4ae18000ti,omap5430-timerJ %timer1timer@48032000ti,omap5430-timerH  &timer2timer@48034000ti,omap5430-timerH@ 'timer3timer@48036000ti,omap5430-timerH` (timer4timer@40138000ti,omap5430-timer@I )timer5timer@4013a000ti,omap5430-timer@I *timer6timer@4013c000ti,omap5430-timer@I +timer7timer@4013e000ti,omap5430-timer@I ,timer8timer@4803e000ti,omap5430-timerH -timer9timer@48086000ti,omap5430-timerH` .timer10timer@48088000ti,omap5430-timerH /timer11wdt@4ae14000ti,omap5-wdtti,omap3-wdtJ@ P wd_timer2dmm@4e000000 ti,omap5-dmmN qdmmemif@4c000000 ti,emif-4d5emif1 L n&=Remif@4d000000 ti,emif-4d5emif2 M o&=Romap_dwc3@4a020000ti,dwc3 usb_otg_ssJ ]eovdwc3@4a030000 snps,dwc3J$\\]peripheralhostotgusb2-phyusb3-phy peripheralocp2scp@4a080000ti,omap-ocp2scpJ  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J#, J#,J#< ~ti,omap5430-bandgapocp2scp@4a090000ti,omap-ocp2scpJ  ocp2scp3phy@4a096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrltsysclkrefclksata@4a141100snps,dwc-ahciJJ 6 sata-physatadss@58000000 ti,omap5-dssXUok dss_corefckdispc@58001000ti,omap5-dispcX  dss_dispcfckencoder@58002000ti,omap5-rfbiX  Udisabled dss_rfbi!fckickencoder@58004000 ti,omap5-dsiX@XB@XC@protophypll 5 Udisabled dss_dsi1 fcksys_clkencoder@58005000 ti,omap5-dsiXX@X@protophypll 7 Udisabled dss_dsi2 fcksys_clkencoder@58060000ti,omap5-hdmi XXXXwppllphycore eUok dss_hdmi fcksys_clkkL audio_txdefault%portendpointregulator-abb-mpu ti,abb-v2Jabb_mpu 2  J|J`J!J3base-addressint-addressefuse-addressldo-address 0 I a0 u,regulator-abb-mm ti,abb-v2Jabb_mm 2  J|J`J!J3base-addressint-addressefuse-addressldo-address 0 I a0 ufixedregulator-vmainregulator-fixedJvmainYLK@qLK@fixedregulator-vsys_cobraregulator-fixed Jvsys_cobra YLK@qLK@qqfixedregulator-vdds_1v8_mainregulator-fixedJvdds_1v8_main uYw@qw@rrfixedregulator-mmcsdregulator-fixed Jvmmcsd_fixedY-q-sssdhci0_pwrseqmmc-pwrseq-simplew ext_clockfixedregulator-mmcsdioregulator-fixedJvmmcsdio_fixedYw@qw@ x  pdefault%hsusb2_phyusb-nop-xceiv f main_clk$hsusb3_phyusb-nop-xceiv encoder ti,tpd12s015default%${portsport@0endpointport@1endpointconnectorhdmi-connector hdmibportendpointsoundti,abe-twl6040 omap5-uevm  $   Headset StereophoneHSOLHeadset StereophoneHSORLine OutAUXLLine OutAUXRHSMICHeadset MicHeadset MicHeadset Mic BiasAFMLLine InAFMRLine Inmemory@80000000memoryleds gpio-ledsled1 omap5:blue:usr1 {x heartbeat offevm_keys gpio-keysdefault%btn1 BTN1  {\ + 62evm_leds gpio-ledsled1 omap5:red:led { mmc0 offled2 omap5:green:led { mmc1 offled3 omap5:blue:led { mmc2 offled4 omap5:green:led1 { heartbeat offled5 omap5:green:led2 { default-on offled6 omap5:green:led3 { heartbeat offled7 omap5:green:led4 { default-on offled8 omap5:green:led5 { heartbeat off #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3serial4serial5display0ethernetdevice_typeregoperating-pointsclocksclock-namesclock-latencycooling-min-levelcooling-max-level#cooling-cellscpu0-supplylinux,phandlepolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceinterruptsinterrupt-controller#interrupt-cellsti,hwmodssramranges#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,index-power-of-twoti,dividersti,set-rate-parent#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpio-hoggpiosoutput-highline-namedmasdma-namesgpmc,num-csgpmc,num-waitpinsti,system-power-controllerti,mux-pad1ti,mux-pad2ti,enable-vbus-detectionti,enable-id-detectionti,wakeupid-gpiosti,backup-battery-chargeableti,backup-battery-charge-high-current#io-channel-cellsti,channel0-current-microampti,channel3-current-microampinterrupt-namesti,ldo6-vibratorsmps123-in-supplysmps45-in-supplysmps6-in-supplysmps7-in-supplysmps8-in-supplysmps9-in-supplysmps10_out2-in-supplysmps10_out1-in-supplyldo1-in-supplyldo2-in-supplyldo3-in-supplyldo4-in-supplyldo5-in-supplyldo6-in-supplyldo7-in-supplyldo8-in-supplyldo9-in-supplyldoln-in-supplyldousb-in-supplyregulator-always-onregulator-boot-onti,smps-rangestatuswakeup-sourcevio-supplyv2v1-supplyenable-active-highti,audpwron-gpio#hwlock-cellsti,spi-num-csinterrupts-extendedti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablemmc-pwrseqcap-power-off-cardref-clock-frequency#iommu-cellsti,iommu-bus-err-backreg-namesti,buffer-size#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmti,no-idle-on-initphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertutmi-modeextconvbus-supplyphysphy-namesdr_modesyscon-phy-power#phy-cellsport2-modeport3-mode#thermal-sensor-cellsports-implementedvdda-supplyremote-endpointti,settling-timeti,clock-cyclesti,tranxdone-status-maskti,ldovbb-override-maskti,ldovbb-vset-maskti,abb_infovin-supplystartup-delay-usreset-gpioslabelti,modelti,jack-detectionti,mclk-freqti,mcpdmti,twl6040ti,audio-routinglinux,default-triggerdefault-statelinux,codeautorepeatdebounce_interval