a8 ( AFcompulab,omap3-sbc-t3530compulab,omap3-cm-t3530ti,omap34xxti,omap3&!7CompuLab SBC-T3530 with CM-T3530chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/connector@0 m/connector@1memoryvmemorycpuscpu@0arm,cortex-a8vcpucpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-bush l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-bus  pinmux@30 ti,omap3-padconfpinctrl-single08$AdefaultOpinmux_uart3_pinsYnpmspinmux_mmc1_pins0Ymspinmux_green_led_pinsYm s pinmux_dss_dpi_pins_commonYmspinmux_dss_dpi_pins_cm_t35x0Ymspinmux_ads7846_pinsYmspinmux_mcspi1_pins Ymspinmux_i2c1_pinsYmspinmux_mcbsp2_pins Y mspinmux_smsc1_pinsYjmspinmux_hsusb0_pins`Yrtvxz|~mspinmux_twl4030_pinsYAmspinmux_mmc2_pinsPY(*,.02468:mspinmux_smsc2_pinsYmspinmux_tfp410_pinsYmspinmux_i2c3_pinsYmspinmux_sb_t35_audio_ampYmspinmux_sb_t35_usb_hub_pinsYmsscm_conf@270sysconp0msclocksmcbsp5_mux_fck{ti,composite-mux-clockhmsmcbsp5_fck{ti,composite-clockmcbsp1_mux_fck{ti,composite-mux-clockm s mcbsp1_fck{ti,composite-clock mcbsp2_mux_fck{ti,composite-mux-clock m s mcbsp2_fck{ti,composite-clock mcbsp3_mux_fck{ti,composite-mux-clock hmsmcbsp3_fck{ti,composite-clockmcbsp4_mux_fck{ti,composite-mux-clock hmsmcbsp4_fck{ti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \$pinmux_twl4030_vpins Ymsaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocksvirt_16_8m_ck{ fixed-clockYmsosc_sys_ck{ ti,mux-clock @mssys_ck{ti,divider-clockpmssys_clkout1{ti,gate-clock pdpll3_x2_ck{fixed-factor-clockdpll3_m2x2_ck{fixed-factor-clockmsdpll4_x2_ck{fixed-factor-clockcorex2_fck{fixed-factor-clockmswkup_l4_ick{fixed-factor-clockmNsNcorex2_d3_fck{fixed-factor-clockmscorex2_d5_fck{fixed-factor-clockmsclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclk{ fixed-clockomap_32k_fck{ fixed-clockm@s@virt_12m_ck{ fixed-clockmsvirt_13m_ck{ fixed-clock]@msvirt_19200000_ck{ fixed-clock$msvirt_26000000_ck{ fixed-clockmsvirt_38_4m_ck{ fixed-clockImsdpll4_ck{ti,omap3-dpll-per-clock D 0msdpll4_m2_ck{ti,divider-clock? Hm s dpll4_m2x2_mul_ck{fixed-factor-clock m!s!dpll4_m2x2_ck{ti,gate-clock! m"s"omap_96m_alwon_fck{fixed-factor-clock"m)s)dpll3_ck{ti,omap3-dpll-core-clock @ 0msdpll3_m3_ck{ti,divider-clock@m#s#dpll3_m3x2_mul_ck{fixed-factor-clock#m$s$dpll3_m3x2_ck{ti,gate-clock$  m%s%emu_core_alwon_ck{fixed-factor-clock%mbsbsys_altclk{ fixed-clockm.s.mcbsp_clks{ fixed-clockmsdpll3_m2_ck{ti,divider-clock @mscore_ck{fixed-factor-clockm&s&dpll1_fck{ti,divider-clock& @m's'dpll1_ck{ti,omap3-dpll-clock'  $ @ 4msdpll1_x2_ck{fixed-factor-clockm(s(dpll1_x2m2_ck{ti,divider-clock( Dm<s<cm_96m_fck{fixed-factor-clock)m*s*omap_96m_fck{ ti,mux-clock* @mEsEdpll4_m3_ck{ti,divider-clock @m+s+dpll4_m3x2_mul_ck{fixed-factor-clock+m,s,dpll4_m3x2_ck{ti,gate-clock, m-s-omap_54m_fck{ ti,mux-clock-. @m8s8cm_96m_d2_fck{fixed-factor-clock*m/s/omap_48m_fck{ ti,mux-clock/. @m0s0omap_12m_fck{fixed-factor-clock0mGsGdpll4_m4_ck{ti,divider-clock @m1s1dpll4_m4x2_mul_ck{ti,fixed-factor-clock1m2s2dpll4_m4x2_ck{ti,gate-clock2 msdpll4_m5_ck{ti,divider-clock?@m3s3dpll4_m5x2_mul_ck{ti,fixed-factor-clock3m4s4dpll4_m5x2_ck{ti,gate-clock4 mjsjdpll4_m6_ck{ti,divider-clock?@m5s5dpll4_m6x2_mul_ck{fixed-factor-clock5m6s6dpll4_m6x2_ck{ti,gate-clock6 m7s7emu_per_alwon_ck{fixed-factor-clock7mcscclkout2_src_gate_ck{ ti,composite-no-wait-gate-clock& pm9s9clkout2_src_mux_ck{ti,composite-mux-clock&*8 pm:s:clkout2_src_ck{ti,composite-clock9:m;s;sys_clkout2{ti,divider-clock;@ p/mpu_ck{fixed-factor-clock<m=s=arm_fck{ti,divider-clock= $emu_mpu_alwon_ck{fixed-factor-clock=mdsdl3_ick{ti,divider-clock& @m>s>l4_ick{ti,divider-clock> @m?s?rm_ick{ti,divider-clock? @gpt10_gate_fck{ti,composite-gate-clock  mAsAgpt10_mux_fck{ti,composite-mux-clock@ @mBsBgpt10_fck{ti,composite-clockABgpt11_gate_fck{ti,composite-gate-clock  mCsCgpt11_mux_fck{ti,composite-mux-clock@ @mDsDgpt11_fck{ti,composite-clockCDcore_96m_fck{fixed-factor-clockEmsmmchs2_fck{ti,wait-gate-clock msmmchs1_fck{ti,wait-gate-clock msi2c3_fck{ti,wait-gate-clock msi2c2_fck{ti,wait-gate-clock msi2c1_fck{ti,wait-gate-clock msmcbsp5_gate_fck{ti,composite-gate-clock  msmcbsp1_gate_fck{ti,composite-gate-clock  m s core_48m_fck{fixed-factor-clock0mFsFmcspi4_fck{ti,wait-gate-clockF msmcspi3_fck{ti,wait-gate-clockF msmcspi2_fck{ti,wait-gate-clockF msmcspi1_fck{ti,wait-gate-clockF msuart2_fck{ti,wait-gate-clockF msuart1_fck{ti,wait-gate-clockF  mscore_12m_fck{fixed-factor-clockGmHsHhdq_fck{ti,wait-gate-clockH mscore_l3_ick{fixed-factor-clock>mIsIsdrc_ick{ti,wait-gate-clockI msgpmc_fck{fixed-factor-clockIcore_l4_ick{fixed-factor-clock?mJsJmmchs2_ick{ti,omap3-interface-clockJ msmmchs1_ick{ti,omap3-interface-clockJ mshdq_ick{ti,omap3-interface-clockJ msmcspi4_ick{ti,omap3-interface-clockJ msmcspi3_ick{ti,omap3-interface-clockJ msmcspi2_ick{ti,omap3-interface-clockJ msmcspi1_ick{ti,omap3-interface-clockJ msi2c3_ick{ti,omap3-interface-clockJ msi2c2_ick{ti,omap3-interface-clockJ msi2c1_ick{ti,omap3-interface-clockJ msuart2_ick{ti,omap3-interface-clockJ msuart1_ick{ti,omap3-interface-clockJ  msgpt11_ick{ti,omap3-interface-clockJ  msgpt10_ick{ti,omap3-interface-clockJ  msmcbsp5_ick{ti,omap3-interface-clockJ  msmcbsp1_ick{ti,omap3-interface-clockJ  msomapctrl_ick{ti,omap3-interface-clockJ msdss_tv_fck{ti,gate-clock8msdss_96m_fck{ti,gate-clockEmsdss2_alwon_fck{ti,gate-clockmsdummy_ck{ fixed-clockgpt1_gate_fck{ti,composite-gate-clock mKsKgpt1_mux_fck{ti,composite-mux-clock@ @mLsLgpt1_fck{ti,composite-clockKLaes2_ick{ti,omap3-interface-clockJ mswkup_32k_fck{fixed-factor-clock@mMsMgpio1_dbck{ti,gate-clockM mssha12_ick{ti,omap3-interface-clockJ mswdt2_fck{ti,wait-gate-clockM mswdt2_ick{ti,omap3-interface-clockN mswdt1_ick{ti,omap3-interface-clockN msgpio1_ick{ti,omap3-interface-clockN msomap_32ksync_ick{ti,omap3-interface-clockN msgpt12_ick{ti,omap3-interface-clockN msgpt1_ick{ti,omap3-interface-clockN msper_96m_fck{fixed-factor-clock)m s per_48m_fck{fixed-factor-clock0mOsOuart3_fck{ti,wait-gate-clockO msgpt2_gate_fck{ti,composite-gate-clockmPsPgpt2_mux_fck{ti,composite-mux-clock@@mQsQgpt2_fck{ti,composite-clockPQgpt3_gate_fck{ti,composite-gate-clockmRsRgpt3_mux_fck{ti,composite-mux-clock@@mSsSgpt3_fck{ti,composite-clockRSgpt4_gate_fck{ti,composite-gate-clockmTsTgpt4_mux_fck{ti,composite-mux-clock@@mUsUgpt4_fck{ti,composite-clockTUgpt5_gate_fck{ti,composite-gate-clockmVsVgpt5_mux_fck{ti,composite-mux-clock@@mWsWgpt5_fck{ti,composite-clockVWgpt6_gate_fck{ti,composite-gate-clockmXsXgpt6_mux_fck{ti,composite-mux-clock@@mYsYgpt6_fck{ti,composite-clockXYgpt7_gate_fck{ti,composite-gate-clockmZsZgpt7_mux_fck{ti,composite-mux-clock@@m[s[gpt7_fck{ti,composite-clockZ[gpt8_gate_fck{ti,composite-gate-clock m\s\gpt8_mux_fck{ti,composite-mux-clock@@m]s]gpt8_fck{ti,composite-clock\]gpt9_gate_fck{ti,composite-gate-clock m^s^gpt9_mux_fck{ti,composite-mux-clock@@m_s_gpt9_fck{ti,composite-clock^_per_32k_alwon_fck{fixed-factor-clock@m`s`gpio6_dbck{ti,gate-clock`msgpio5_dbck{ti,gate-clock`msgpio4_dbck{ti,gate-clock`msgpio3_dbck{ti,gate-clock`msgpio2_dbck{ti,gate-clock` mswdt3_fck{ti,wait-gate-clock` msper_l4_ick{fixed-factor-clock?masagpio6_ick{ti,omap3-interface-clockamsgpio5_ick{ti,omap3-interface-clockamsgpio4_ick{ti,omap3-interface-clockamsgpio3_ick{ti,omap3-interface-clockamsgpio2_ick{ti,omap3-interface-clocka mswdt3_ick{ti,omap3-interface-clocka msuart3_ick{ti,omap3-interface-clocka msuart4_ick{ti,omap3-interface-clockamsgpt9_ick{ti,omap3-interface-clocka msgpt8_ick{ti,omap3-interface-clocka msgpt7_ick{ti,omap3-interface-clockamsgpt6_ick{ti,omap3-interface-clockamsgpt5_ick{ti,omap3-interface-clockamsgpt4_ick{ti,omap3-interface-clockamsgpt3_ick{ti,omap3-interface-clockamsgpt2_ick{ti,omap3-interface-clockamsmcbsp2_ick{ti,omap3-interface-clockamsmcbsp3_ick{ti,omap3-interface-clockamsmcbsp4_ick{ti,omap3-interface-clockamsmcbsp2_gate_fck{ti,composite-gate-clockm s mcbsp3_gate_fck{ti,composite-gate-clockmsmcbsp4_gate_fck{ti,composite-gate-clockmsemu_src_mux_ck{ ti,mux-clockbcd@meseemu_src_ck{ti,clkdm-gate-clockemfsfpclk_fck{ti,divider-clockf@pclkx2_fck{ti,divider-clockf@atclk_fck{ti,divider-clockf@traceclk_src_fck{ ti,mux-clockbcd@mgsgtraceclk_fck{ti,divider-clockg @secure_32k_fck{ fixed-clockmhshgpt12_fck{fixed-factor-clockhwdt1_fck{fixed-factor-clockhsecurity_l4_ick2{fixed-factor-clock?misiaes1_ick{ti,omap3-interface-clocki rng_ick{ti,omap3-interface-clocki sha11_ick{ti,omap3-interface-clocki des1_ick{ti,omap3-interface-clocki cam_mclk{ti,gate-clockjcam_ick{!ti,omap3-no-wait-interface-clock?mscsi2_96m_fck{ti,gate-clockmssecurity_l3_ick{fixed-factor-clock>mkskpka_ick{ti,omap3-interface-clockk icr_ick{ti,omap3-interface-clockJ des2_ick{ti,omap3-interface-clockJ mspro_ick{ti,omap3-interface-clockJ mailboxes_ick{ti,omap3-interface-clockJ ssi_l4_ick{fixed-factor-clock?mrsrsr1_fck{ti,wait-gate-clock sr2_fck{ti,wait-gate-clock sr_l4_ick{fixed-factor-clock?dpll2_fck{ti,divider-clock&@mlsldpll2_ck{ti,omap3-dpll-clockl$@4EW_mmsmdpll2_m2_ck{ti,divider-clockmDmnsniva2_ck{ti,wait-gate-clocknmsmodem_fck{ti,omap3-interface-clock mssad2d_ick{ti,omap3-interface-clock> msmad2d_ick{ti,omap3-interface-clock> msmspro_fck{ti,wait-gate-clock ssi_ssr_gate_fck_3430es2{ ti,composite-no-wait-gate-clock mosossi_ssr_div_fck_3430es2{ti,composite-divider-clock @$smpspssi_ssr_fck_3430es2{ti,composite-clockopmqsqssi_sst_fck_3430es2{fixed-factor-clockqmshsotgusb_ick_3430es2{"ti,omap3-hsotgusb-interface-clockI msssi_ick_3430es2{ti,omap3-ssi-interface-clockr msusim_gate_fck{ti,composite-gate-clockE  m}s}sys_d2_ck{fixed-factor-clockmtstomap_96m_d2_fck{fixed-factor-clockEmusuomap_96m_d4_fck{fixed-factor-clockEmvsvomap_96m_d8_fck{fixed-factor-clockEmwswomap_96m_d10_fck{fixed-factor-clockE mxsxdpll5_m2_d4_ck{fixed-factor-clocksmysydpll5_m2_d8_ck{fixed-factor-clocksmzszdpll5_m2_d16_ck{fixed-factor-clocksm{s{dpll5_m2_d20_ck{fixed-factor-clocksm|s|usim_mux_fck{ti,composite-mux-clock(tuvwxyz{| @m~s~usim_fck{ti,composite-clock}~usim_ick{ti,omap3-interface-clockN  msdpll5_ck{ti,omap3-dpll-clock  $ L 4EWmsdpll5_m2_ck{ti,divider-clock Pmssssgx_gate_fck{ti,composite-gate-clock& mscore_d3_ck{fixed-factor-clock&mscore_d4_ck{fixed-factor-clock&mscore_d6_ck{fixed-factor-clock&msomap_192m_alwon_fck{fixed-factor-clock"mscore_d2_ck{fixed-factor-clock&mssgx_mux_fck{ti,composite-mux-clock * @mssgx_fck{ti,composite-clocksgx_ick{ti,wait-gate-clock> mscpefuse_fck{ti,gate-clock msts_fck{ti,gate-clock@ msusbtll_fck{ti,wait-gate-clocks msusbtll_ick{ti,omap3-interface-clockJ msmmchs3_ick{ti,omap3-interface-clockJ msmmchs3_fck{ti,wait-gate-clock msdss1_alwon_fck_3430es2{ti,dss-gate-clockmsdss_ick_3430es2{ti,omap3-dss-interface-clock?msusbhost_120m_fck{ti,gate-clocksmsusbhost_48m_fck{ti,dss-gate-clock0msusbhost_ick{ti,omap3-dss-interface-clock?msclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainfdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainmd2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH msdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `mspbias_regulatorti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-msgpio@48310000ti,omap3-gpioH1gpio1 gpio@49050000ti,omap3-gpioIgpio2 msgpio@49052000ti,omap3-gpioI gpio3 msgpio@49054000ti,omap3-gpioI@ gpio4 gpio@49056000ti,omap3-gpioI`!gpio5 gpio@49058000ti,omap3-gpioI"gpio6 msserial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3lAdefaultOi2c@48070000 ti,omap3-i2cH8txrxi2c1AdefaultOat24@50 at24,24c02,Ptwl@48H& ti,twl4030AdefaultOaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci 5watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' msregulator-vdacti,twl4030-vdacw@w@msregulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0msregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5msregulator-vusb1v8ti,twl4030-vusb1v8msregulator-vusb3v1ti,twl4030-vusb3v1msregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio COmstwl4030-usbti,twl4030-usb Zhvmspwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad$0iglj. madcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9txrxi2c2i2c@48060000 ti,omap3-i2cH=txrxi2c3AdefaultOat24@50 at24,24c02,Pmailbox@48094000ti,omap3-mailboxmailboxH @dsp   spi@48098000ti,omap2-mcspiH Amcspi1+@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3AdefaultOads7846@0AdefaultO ti,ads78469D`& Vclu~ spi@4809a000ti,omap2-mcspiH Bmcspi2+ +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi3+ tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4+FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxAdefaultO mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxAdefaultO+mmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx >disabledmmu@480bd400Eti,omap2-iommuH mmu_ispRmsmmu@5d000000Eti,omap2-iommu]mmu_iva >disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@bmpu ;< lcommontxrx|mcbsp1 txrx >disabledmcbsp@49022000ti,omap3-mcbspI I bmpusidetone>?lcommontxrxsidetone|mcbsp2mcbsp2_sidetone!"txrx>okAdefaultOm s mcbsp@49024000ti,omap3-mcbspI@I bmpusidetoneYZlcommontxrxsidetone|mcbsp3mcbsp3_sidetonetxrx >disabledmcbsp@49026000ti,omap3-mcbspI`bmpu 67 lcommontxrx|mcbsp4txrx >disabledmcbsp@48096000ti,omap3-mcbspH `bmpu QR lcommontxrx|mcbsp5txrx >disabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs ehci-phy ehci-phyohci@48064400ti,ohci-omap3HD&Lehci@48064800 ti,ehci-omapHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcn0,-nand@0,0  sw.<xNx`oxxZZH<x#x4FZpartition@0^xloaderpartition@0x80000^ubootpartition@0x260000^uboot environment&partition@0x2a0000^linux*@partition@0x6a0000^rootfsjethernet@gpmcsmsc,lan9221smsc,lan9115d o.<N`o(--#xKKF4AdefaultO& ethernet@4,0smsc,lan9221smsc,lan9115AdefaultO& d o.<N`o(--#xKKF4usb_otg_hs@480ab000ti,omap3-musbH \]lmcdma usb_otg_hs*5= AdefaultOFU ]usb2-phyg2dss@48050000 ti,omap3-dssH>ok dss_corefckAdefaultOdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H bprotophypll >disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH >disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH >ok dss_vencfckmportendpointym s portendpointymsssi-controller@48058000 ti,omap3-ssissi>okHHbsysgddGlgdd_mpu q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHbtxrx&CDssi-port@4805b000ti,omap3-ssi-portHHbtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$$isp@480bc000 ti,omap3-ispH H |{portsleds gpio-ledsAdefaultO ledb ^cm-t3x:green  heartbeathsusb1_power_regregulator-fixed hsusb1_vbus2Z2Zpm s hsusb2_power_regregulator-fixed hsusb2_vbus2Z2Zpm s hsusb1_phyusb-nop-xceiv9  mshsusb2_phyusb-nop-xceiv9  msads7846-regregulator-fixed ads7846-reg2Z2Zmsconnector@1svideo-connector^tvportendpointy mssoundti,omap-twl4030cm-t35 regulator-vddvarioregulator-fixed vddvariomsregulator-vdd33aregulator-fixedvdd33amsregulator-mmc2-sdio-resetregulator-fixedregulator-mmc2-sdio-reset2Z2Z ^ msencoder@0 ti,tfp410 AdefaultOportsport@0endpoint@0ymsport@1endpoint@0ymsconnector@0dvi-connector^dviportendpointymsaudio_ampregulator-fixed audio_ampAdefaultO ^ / #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0display1device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesizebci3v1-supplyti,use-ledsti,pullupsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-replinux,wakeupti,dual-voltpbias-supplybus-widthvmmc-supplycd-gpiosnon-removablecap-power-off-cardstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-typelinux,default-triggerstartup-delay-usreset-gpiosti,modelti,mcbspregulator-always-onenable-active-highpowerdown-gpiosenable-active-low