j8p(8Qincostartec,omap3-lilly-dbb056incostartec,omap3-lilly-a83xti,omap36xxti,omap3&"7INCOstartec LILLY-DBB056 (DM3730)chosenA=console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0aliasesF/ocp/i2c@48070000K/ocp/i2c@48072000P/ocp/i2c@48060000U/ocp/serial@4806a000]/ocp/serial@4806c000e/ocp/serial@49020000m/ocp/serial@49042000memoryumemorycpuscpu@0arm,cortex-a8ucpucpus 'O 57pmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-bush l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-bus  pinmux@30 ti,omap3-padconfpinctrl-single084defaultBpinmux_uart1_pins LLNPR`fpinmux_uart2_pinsL@B`fpinmux_uart3_pinsLnp`fpinmux_i2c1_pinsL`fpinmux_i2c2_pinsL`fpinmux_i2c3_pinsL`fpinmux_hsusb1_pinsL`fpinmux_hsusb_otg_pins`Lrtvxz|~`fpinmux_mmc1_pins0L`fpinmux_spi2_pins L`fpinmux_twl4030_pinsLA`fpinmux_lan9117_pinsL`fpinmux_gpio4_pinsL`fpinmux_gpio5_pinsL\`fpinmux_lcd_pinsL`fpinmux_mmc2_pins`L(*,.02468:jl`fpinmux_spi1_pins L`fscm_conf@270sysconp0`fclocksmcbsp5_mux_fcknti,composite-mux-clock{h`fmcbsp5_fcknti,composite-clockmcbsp1_mux_fcknti,composite-mux-clock{` f mcbsp1_fcknti,composite-clock mcbsp2_mux_fcknti,composite-mux-clock {` f mcbsp2_fcknti,composite-clock mcbsp3_mux_fcknti,composite-mux-clock h`fmcbsp3_fcknti,composite-clock mcbsp4_mux_fcknti,composite-mux-clock {h`fmcbsp4_fcknti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \4defaultpinmux_lan9221_pinsLZ`fpinmux_tsc2048_pinsL`fpinmux_mmc1cd_pinsLV`fpinmux_twl4030_vpins L`faes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocksvirt_16_8m_ckn fixed-clockY`fosc_sys_ckn ti,mux-clock @`fsys_cknti,divider-clock{p`fsys_clkout1nti,gate-clock p{dpll3_x2_cknfixed-factor-clockdpll3_m2x2_cknfixed-factor-clock`fdpll4_x2_cknfixed-factor-clockcorex2_fcknfixed-factor-clock`fwkup_l4_icknfixed-factor-clock`MfMcorex2_d3_fcknfixed-factor-clock`fcorex2_d5_fcknfixed-factor-clock`fclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclkn fixed-clockomap_32k_fckn fixed-clock`?f?virt_12m_ckn fixed-clock`fvirt_13m_ckn fixed-clock]@`fvirt_19200000_ckn fixed-clock$`fvirt_26000000_ckn fixed-clock`fvirt_38_4m_ckn fixed-clockI`fdpll4_cknti,omap3-dpll-per-j-type-clock D 0`fdpll4_m2_cknti,divider-clock? H`fdpll4_m2x2_mul_cknfixed-factor-clock` f dpll4_m2x2_cknti,hsdiv-gate-clock { `!f!omap_96m_alwon_fcknfixed-factor-clock!`(f(dpll3_cknti,omap3-dpll-core-clock @ 0`fdpll3_m3_cknti,divider-clock{@`"f"dpll3_m3x2_mul_cknfixed-factor-clock"`#f#dpll3_m3x2_cknti,hsdiv-gate-clock#{  `$f$emu_core_alwon_cknfixed-factor-clock$`afasys_altclkn fixed-clock`-f-mcbsp_clksn fixed-clock`fdpll3_m2_cknti,divider-clock{ @`fcore_cknfixed-factor-clock`%f%dpll1_fcknti,divider-clock%{ @`&f&dpll1_cknti,omap3-dpll-clock&  $ @ 4`fdpll1_x2_cknfixed-factor-clock`'f'dpll1_x2m2_cknti,divider-clock' D`;f;cm_96m_fcknfixed-factor-clock(`)f)omap_96m_fckn ti,mux-clock){ @`DfDdpll4_m3_cknti,divider-clock{ @`*f*dpll4_m3x2_mul_cknfixed-factor-clock*`+f+dpll4_m3x2_cknti,hsdiv-gate-clock+{ `,f,omap_54m_fckn ti,mux-clock,-{ @`7f7cm_96m_d2_fcknfixed-factor-clock)`.f.omap_48m_fckn ti,mux-clock.-{ @`/f/omap_12m_fcknfixed-factor-clock/`FfFdpll4_m4_cknti,divider-clock @`0f0dpll4_m4x2_mul_cknti,fixed-factor-clock0`1f1dpll4_m4x2_cknti,gate-clock1{ `fdpll4_m5_cknti,divider-clock?@`2f2dpll4_m5x2_mul_cknti,fixed-factor-clock2`3f3dpll4_m5x2_cknti,hsdiv-gate-clock3{ `ifidpll4_m6_cknti,divider-clock{?@`4f4dpll4_m6x2_mul_cknfixed-factor-clock4`5f5dpll4_m6x2_cknti,hsdiv-gate-clock5{ `6f6emu_per_alwon_cknfixed-factor-clock6`bfbclkout2_src_gate_ckn ti,composite-no-wait-gate-clock%{ p`8f8clkout2_src_mux_cknti,composite-mux-clock%)7 p`9f9clkout2_src_cknti,composite-clock89`:f:sys_clkout2nti,divider-clock:{@ p"mpu_cknfixed-factor-clock;`<f<arm_fcknti,divider-clock< $emu_mpu_alwon_cknfixed-factor-clock<`cfcl3_icknti,divider-clock% @`=f=l4_icknti,divider-clock={ @`>f>rm_icknti,divider-clock>{ @gpt10_gate_fcknti,composite-gate-clock{  `@f@gpt10_mux_fcknti,composite-mux-clock?{ @`AfAgpt10_fcknti,composite-clock@Agpt11_gate_fcknti,composite-gate-clock{  `BfBgpt11_mux_fcknti,composite-mux-clock?{ @`CfCgpt11_fcknti,composite-clockBCcore_96m_fcknfixed-factor-clockD`fmmchs2_fcknti,wait-gate-clock {`fmmchs1_fcknti,wait-gate-clock {`fi2c3_fcknti,wait-gate-clock {`fi2c2_fcknti,wait-gate-clock {`fi2c1_fcknti,wait-gate-clock {`fmcbsp5_gate_fcknti,composite-gate-clock{  `fmcbsp1_gate_fcknti,composite-gate-clock{  `fcore_48m_fcknfixed-factor-clock/`EfEmcspi4_fcknti,wait-gate-clockE {`fmcspi3_fcknti,wait-gate-clockE {`fmcspi2_fcknti,wait-gate-clockE {`fmcspi1_fcknti,wait-gate-clockE {`fuart2_fcknti,wait-gate-clockE {`fuart1_fcknti,wait-gate-clockE { `fcore_12m_fcknfixed-factor-clockF`GfGhdq_fcknti,wait-gate-clockG {`fcore_l3_icknfixed-factor-clock=`HfHsdrc_icknti,wait-gate-clockH {`fgpmc_fcknfixed-factor-clockHcore_l4_icknfixed-factor-clock>`IfImmchs2_icknti,omap3-interface-clockI {`fmmchs1_icknti,omap3-interface-clockI {`fhdq_icknti,omap3-interface-clockI {`fmcspi4_icknti,omap3-interface-clockI {`fmcspi3_icknti,omap3-interface-clockI {`fmcspi2_icknti,omap3-interface-clockI {`fmcspi1_icknti,omap3-interface-clockI {`fi2c3_icknti,omap3-interface-clockI {`fi2c2_icknti,omap3-interface-clockI {`fi2c1_icknti,omap3-interface-clockI {`fuart2_icknti,omap3-interface-clockI {`fuart1_icknti,omap3-interface-clockI { `fgpt11_icknti,omap3-interface-clockI { `fgpt10_icknti,omap3-interface-clockI { `fmcbsp5_icknti,omap3-interface-clockI { `fmcbsp1_icknti,omap3-interface-clockI { `fomapctrl_icknti,omap3-interface-clockI {`fdss_tv_fcknti,gate-clock7{`fdss_96m_fcknti,gate-clockD{`fdss2_alwon_fcknti,gate-clock{`fdummy_ckn fixed-clockgpt1_gate_fcknti,composite-gate-clock{ `JfJgpt1_mux_fcknti,composite-mux-clock? @`KfKgpt1_fcknti,composite-clockJKaes2_icknti,omap3-interface-clockI{ `fwkup_32k_fcknfixed-factor-clock?`LfLgpio1_dbcknti,gate-clockL {`fsha12_icknti,omap3-interface-clockI {`fwdt2_fcknti,wait-gate-clockL {`fwdt2_icknti,omap3-interface-clockM {`fwdt1_icknti,omap3-interface-clockM {`fgpio1_icknti,omap3-interface-clockM {`fomap_32ksync_icknti,omap3-interface-clockM {`fgpt12_icknti,omap3-interface-clockM {`fgpt1_icknti,omap3-interface-clockM {`fper_96m_fcknfixed-factor-clock(` f per_48m_fcknfixed-factor-clock/`NfNuart3_fcknti,wait-gate-clockN{ `fgpt2_gate_fcknti,composite-gate-clock{`OfOgpt2_mux_fcknti,composite-mux-clock?@`PfPgpt2_fcknti,composite-clockOPgpt3_gate_fcknti,composite-gate-clock{`QfQgpt3_mux_fcknti,composite-mux-clock?{@`RfRgpt3_fcknti,composite-clockQRgpt4_gate_fcknti,composite-gate-clock{`SfSgpt4_mux_fcknti,composite-mux-clock?{@`TfTgpt4_fcknti,composite-clockSTgpt5_gate_fcknti,composite-gate-clock{`UfUgpt5_mux_fcknti,composite-mux-clock?{@`VfVgpt5_fcknti,composite-clockUVgpt6_gate_fcknti,composite-gate-clock{`WfWgpt6_mux_fcknti,composite-mux-clock?{@`XfXgpt6_fcknti,composite-clockWXgpt7_gate_fcknti,composite-gate-clock{`YfYgpt7_mux_fcknti,composite-mux-clock?{@`ZfZgpt7_fcknti,composite-clockYZgpt8_gate_fcknti,composite-gate-clock{ `[f[gpt8_mux_fcknti,composite-mux-clock?{@`\f\gpt8_fcknti,composite-clock[\gpt9_gate_fcknti,composite-gate-clock{ `]f]gpt9_mux_fcknti,composite-mux-clock?{@`^f^gpt9_fcknti,composite-clock]^per_32k_alwon_fcknfixed-factor-clock?`_f_gpio6_dbcknti,gate-clock_{`fgpio5_dbcknti,gate-clock_{`fgpio4_dbcknti,gate-clock_{`fgpio3_dbcknti,gate-clock_{`fgpio2_dbcknti,gate-clock_{ `fwdt3_fcknti,wait-gate-clock_{ `fper_l4_icknfixed-factor-clock>``f`gpio6_icknti,omap3-interface-clock`{`fgpio5_icknti,omap3-interface-clock`{`fgpio4_icknti,omap3-interface-clock`{`fgpio3_icknti,omap3-interface-clock`{`fgpio2_icknti,omap3-interface-clock`{ `fwdt3_icknti,omap3-interface-clock`{ `fuart3_icknti,omap3-interface-clock`{ `fuart4_icknti,omap3-interface-clock`{`fgpt9_icknti,omap3-interface-clock`{ `fgpt8_icknti,omap3-interface-clock`{ `fgpt7_icknti,omap3-interface-clock`{`fgpt6_icknti,omap3-interface-clock`{`fgpt5_icknti,omap3-interface-clock`{`fgpt4_icknti,omap3-interface-clock`{`fgpt3_icknti,omap3-interface-clock`{`fgpt2_icknti,omap3-interface-clock`{`fmcbsp2_icknti,omap3-interface-clock`{`fmcbsp3_icknti,omap3-interface-clock`{`fmcbsp4_icknti,omap3-interface-clock`{`fmcbsp2_gate_fcknti,composite-gate-clock{` f mcbsp3_gate_fcknti,composite-gate-clock{` f mcbsp4_gate_fcknti,composite-gate-clock{`femu_src_mux_ckn ti,mux-clockabc@`dfdemu_src_cknti,clkdm-gate-clockd`efepclk_fcknti,divider-clocke{@pclkx2_fcknti,divider-clocke{@atclk_fcknti,divider-clocke{@traceclk_src_fckn ti,mux-clockabc{@`ffftraceclk_fcknti,divider-clockf{ @secure_32k_fckn fixed-clock`gfggpt12_fcknfixed-factor-clockgwdt1_fcknfixed-factor-clockgsecurity_l4_ick2nfixed-factor-clock>`hfhaes1_icknti,omap3-interface-clockh{ rng_icknti,omap3-interface-clockh {sha11_icknti,omap3-interface-clockh {des1_icknti,omap3-interface-clockh {cam_mclknti,gate-clocki{cam_ickn!ti,omap3-no-wait-interface-clock>{`fcsi2_96m_fcknti,gate-clock{`fsecurity_l3_icknfixed-factor-clock=`jfjpka_icknti,omap3-interface-clockj {icr_icknti,omap3-interface-clockI {des2_icknti,omap3-interface-clockI {mspro_icknti,omap3-interface-clockI {mailboxes_icknti,omap3-interface-clockI {ssi_l4_icknfixed-factor-clock>`qfqsr1_fcknti,wait-gate-clock {sr2_fcknti,wait-gate-clock {sr_l4_icknfixed-factor-clock>dpll2_fcknti,divider-clock%{@`kfkdpll2_cknti,omap3-dpll-clockk$@48JR`lfldpll2_m2_cknti,divider-clocklD`mfmiva2_cknti,wait-gate-clockm{`fmodem_fcknti,omap3-interface-clock {`fsad2d_icknti,omap3-interface-clock= {`fmad2d_icknti,omap3-interface-clock= {`fmspro_fcknti,wait-gate-clock {ssi_ssr_gate_fck_3430es2n ti,composite-no-wait-gate-clock{ `nfnssi_ssr_div_fck_3430es2nti,composite-divider-clock{ @$f`ofossi_ssr_fck_3430es2nti,composite-clockno`pfpssi_sst_fck_3430es2nfixed-factor-clockp`fhsotgusb_ick_3430es2n"ti,omap3-hsotgusb-interface-clockH {`fssi_ick_3430es2nti,omap3-ssi-interface-clockq {`fusim_gate_fcknti,composite-gate-clockD{  `|f|sys_d2_cknfixed-factor-clock`sfsomap_96m_d2_fcknfixed-factor-clockD`tftomap_96m_d4_fcknfixed-factor-clockD`ufuomap_96m_d8_fcknfixed-factor-clockD`vfvomap_96m_d10_fcknfixed-factor-clockD `wfwdpll5_m2_d4_cknfixed-factor-clockr`xfxdpll5_m2_d8_cknfixed-factor-clockr`yfydpll5_m2_d16_cknfixed-factor-clockr`zfzdpll5_m2_d20_cknfixed-factor-clockr`{f{usim_mux_fcknti,composite-mux-clock(stuvwxyz{{ @`}f}usim_fcknti,composite-clock|}usim_icknti,omap3-interface-clockM { `fdpll5_cknti,omap3-dpll-clock  $ L 48J`~f~dpll5_m2_cknti,divider-clock~ P`rfrsgx_gate_fcknti,composite-gate-clock%{ `fcore_d3_cknfixed-factor-clock%`fcore_d4_cknfixed-factor-clock%`fcore_d6_cknfixed-factor-clock%`fomap_192m_alwon_fcknfixed-factor-clock!`fcore_d2_cknfixed-factor-clock%`fsgx_mux_fcknti,composite-mux-clock ) @`fsgx_fcknti,composite-clocksgx_icknti,wait-gate-clock= {`fcpefuse_fcknti,gate-clock {`fts_fcknti,gate-clock? {`fusbtll_fcknti,wait-gate-clockr {`fusbtll_icknti,omap3-interface-clockI {`fmmchs3_icknti,omap3-interface-clockI {`fmmchs3_fcknti,wait-gate-clock {`fdss1_alwon_fck_3430es2nti,dss-gate-clock{`fdss_ick_3430es2nti,omap3-dss-interface-clock>{`fusbhost_120m_fcknti,gate-clockr{`fusbhost_48m_fcknti,dss-gate-clock/{`fusbhost_icknti,omap3-dss-interface-clock>{`fuart4_fcknti,wait-gate-clockN{`fclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainedpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainld2d_clkdmti,clockdomain dpll5_clkdmti,clockdomain~sgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH `fdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH` r} ``fpbias_regulatorti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-`fgpio@48310000ti,omap3-gpioH1gpio14defaultB`fgpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio44defaultB`fgpio@49056000ti,omap3-gpioI`!gpio54defaultB`fgpio@49058000ti,omap3-gpioI"gpio64defaultB`fserial@4806a000ti,omap3-uartH  H12txrxuart1l4defaultBserial@4806c000ti,omap3-uartH I34txrxuart2l4defaultBserial@49020000ti,omap3-uartI J56txrxuart3l4defaultBi2c@48070000 ti,omap3-i2cH8txrxi2c1'@4defaultBtwl@48H& ti,twl40304defaultBaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2**-regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' -regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0-`fregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5`fregulator-vusb1v8ti,twl4030-vusb1v8`fregulator-vusb3v1ti,twl4030-vusb3v1`fregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpiotwl4030-usbti,twl4030-usb AO]kt`fpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcregulator-vdd2-i2c@48072000 ti,omap3-i2cH 9txrxi2c2'@4defaultBi2c@48060000 ti,omap3-i2cH=txrxi2c3'@4defaultBgpio@20 mcp,mcp23017 mailbox@48094000ti,omap3-mailboxmailboxH @dsp  spi@48098000ti,omap2-mcspiH Amcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3okay4defaultBspi@4809a000ti,omap2-mcspiH Bmcspi2 +,-.tx0rx0tx1rx1okay4defaultBtsc2046@0 ti,tsc2046&B@ ,94defaultBD,M VX_hPxspi@480b8000ti,omap2-mcspiH [mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx 4defaultBmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxokay  4defaultBmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp+`fmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@;mpu ;< EcommontxrxUmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspI I ;mpusidetone>?EcommontxrxsidetoneUmcbsp2mcbsp2_sidetone!"txrxokay` f mcbsp@49024000ti,omap3-mcbspI@I ;mpusidetoneYZEcommontxrxsidetoneUmcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbspI`;mpu 67 EcommontxrxUmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspH `;mpu QR EcommontxrxUmcbsp5txrx disabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1dtimer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5stimer@4903a000ti,omap3430-timerI*timer6stimer@4903c000ti,omap3430-timerI+timer7stimer@4903e000ti,omap3430-timerI,timer8stimer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12dusbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs4defaultB ehci-phyohci@48064400ti,ohci-omap3HD&Lehci@48064800 ti,ehci-omapHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcn00 nand@0,0 bch8&>P^dpdddKKdd<"<Sm2Kpartition@0MLOpartition@0x80000u-bootpartition@0x260000u-boot-environment&partition@0x280000kernel(Ppartition@0x780000 filesystemxethernet@7,0smsc,lan9221smsc,lan9115P ^<p<   < <dd2"<mKKS& 4defaultBmiiethernet@4,0smsc,lan9117smsc,lan9115P ^ApA   A Add<"<mKKS& 4defaultBmiiusb_otg_hs@480ab000ti,omap3-musbH \]Emcdma usb_otg_hs(3; 4defaultBDS [usb2-phyoe2dss@48050000 ti,omap3-dssH disabled dss_corefckdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H ;protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  disabled dss_vencfcktv_dac_clkssi-controller@48058000 ti,omap3-ssissiokHH;sysgddGEgdd_mpu p ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHH;txrx&CDssi-port@4805b000ti,omap3-ssi-portHH;txrx&EFserial@49042000ti,omap3-uartI PQRtxrxuart4l disabledregulator-abb-mpu ti,abb-v1 abb_mpu_ivakH0rH0h;base-addressint-addressy`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\4defaultpinmux_hsusb1_2_pins`L8:<>@BDFHJLN`fpinmux_gpio1_pinsLZ `fisp@480bc000 ti,omap3-ispH H nportsleds gpio-ledsled1lilly-a83x::led1  default-onsoundti,omap-twl4030 lilly-a83x vcc3regulator-fixedVCC32Z2Z-`fhsusb1_phyusb-nop-xceiv9`f #address-cells#size-cellscompatibleinterrupt-parentmodelbootargsi2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csstatusspi-max-frequencypendown-gpiovcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeupti,dual-voltpbias-supplycd-gpioscd-invertedvmmc-supplybus-widthcap-sdio-irqcap-sd-highspeedcap-mmc-highspeedwp-gpios#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securenum-portsport1-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthti,nand-ecc-optgpmc,mux-add-datagpmc,device-widthgpmc,wait-pingpmc,wait-monitoring-nsgpmc,burst-lengthgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nslabelbank-widthgpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthphy-modesmsc,force-internal-phymultipointnum-epsram-bitsinterface-typeusb-phyphy-namespower#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typelinux,default-triggerti,modelti,mcbsp