k8x(@Iheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap34xxti,omap3&77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/display@0memorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busyh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busy  pinmux@30 ti,omap3-padconfpinctrl-singley088default F pinmux_hsusbb2_pins`P          djpinmux_mmc1_pinsPP "$&djpinmux_mmc2_pins0P(*,.02djpinmux_wlan_gpioP^pinmux_uart3_pinsPnApdjpinmux_i2c3_pinsPdjpinmux_mcspi1_pins Pdjpinmux_mcspi3_pins Pdjpinmux_mcbsp3_pins P<>@Bdjpinmux_twl4030_pinsPAdjpinmux_sound2_pinsPnpinmux_led_blue_pinsPdjpinmux_led_green_pinsPd j pinmux_led_red_pinsPd j pinmux_poweroff_pinsPdjpinmux_powerdown_input_pinsPdjfpga_boot0_pins Pdjfpga_boot1_pins Prtvxdjpinmux_touchscreen_irq_pinsP4pinmux_touchscreen_wake_pinsPd j pinmux_dss_dpi_pinsPdjpinmux_lte430_pinsP8djpinmux_backlight_pinsP:d j scm_conf@270sysconyp0djclocksmcbsp5_mux_fckrti,composite-mux-clock} yhdjmcbsp5_fckrti,composite-clock}mcbsp1_mux_fckrti,composite-mux-clock} ydjmcbsp1_fckrti,composite-clock}mcbsp2_mux_fckrti,composite-mux-clock} ydjmcbsp2_fckrti,composite-clock}mcbsp3_mux_fckrti,composite-mux-clock} yhdjmcbsp3_fckrti,composite-clock}mcbsp4_mux_fckrti,composite-mux-clock} yhdjmcbsp4_fckrti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \pinmux_twl4030_vpins Pdjaes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocksvirt_16_8m_ckr fixed-clockYdjosc_sys_ckr ti,mux-clock}y @d j sys_ckrti,divider-clock} ypd%j%sys_clkout1rti,gate-clock} y pdpll3_x2_ckrfixed-factor-clock}!dpll3_m2x2_ckrfixed-factor-clock}"d$j$dpll4_x2_ckrfixed-factor-clock}#corex2_fckrfixed-factor-clock}$d&j&wkup_l4_ickrfixed-factor-clock}%dUjUcorex2_d3_fckrfixed-factor-clock}&djcorex2_d5_fckrfixed-factor-clock}&djclockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclkr fixed-clockomap_32k_fckr fixed-clockdGjGvirt_12m_ckr fixed-clockdjvirt_13m_ckr fixed-clock]@djvirt_19200000_ckr fixed-clock$djvirt_26000000_ckr fixed-clockdjvirt_38_4m_ckr fixed-clockIdjdpll4_ckrti,omap3-dpll-per-clock}%%y D 0d#j#dpll4_m2_ckrti,divider-clock}#?y Hd'j'dpll4_m2x2_mul_ckrfixed-factor-clock}'d(j(dpll4_m2x2_ckrti,gate-clock}(y d)j)omap_96m_alwon_fckrfixed-factor-clock})d0j0dpll3_ckrti,omap3-dpll-core-clock}%%y @ 0d!j!dpll3_m3_ckrti,divider-clock}!y@d*j*dpll3_m3x2_mul_ckrfixed-factor-clock}*d+j+dpll3_m3x2_ckrti,gate-clock}+ y d,j,emu_core_alwon_ckrfixed-factor-clock},dijisys_altclkr fixed-clockd5j5mcbsp_clksr fixed-clockd j dpll3_m2_ckrti,divider-clock}!y @d"j"core_ckrfixed-factor-clock}"d-j-dpll1_fckrti,divider-clock}-y @d.j.dpll1_ckrti,omap3-dpll-clock}%.y  $ @ 4djdpll1_x2_ckrfixed-factor-clock}d/j/dpll1_x2m2_ckrti,divider-clock}/y DdCjCcm_96m_fckrfixed-factor-clock}0d1j1omap_96m_fckr ti,mux-clock}1%y @dLjLdpll4_m3_ckrti,divider-clock}# y@d2j2dpll4_m3x2_mul_ckrfixed-factor-clock}2d3j3dpll4_m3x2_ckrti,gate-clock}3y d4j4omap_54m_fckr ti,mux-clock}45y @d?j?cm_96m_d2_fckrfixed-factor-clock}1d6j6omap_48m_fckr ti,mux-clock}65y @d7j7omap_12m_fckrfixed-factor-clock}7dNjNdpll4_m4_ckrti,divider-clock}# y@d8j8dpll4_m4x2_mul_ckrti,fixed-factor-clock}8 d9j9dpll4_m4x2_ckrti,gate-clock}9y djdpll4_m5_ckrti,divider-clock}#?y@d:j:dpll4_m5x2_mul_ckrti,fixed-factor-clock}: d;j;dpll4_m5x2_ckrti,gate-clock};y dqjqdpll4_m6_ckrti,divider-clock}#?y@d<j<dpll4_m6x2_mul_ckrfixed-factor-clock}<d=j=dpll4_m6x2_ckrti,gate-clock}=y d>j>emu_per_alwon_ckrfixed-factor-clock}>djjjclkout2_src_gate_ckr ti,composite-no-wait-gate-clock}-y pd@j@clkout2_src_mux_ckrti,composite-mux-clock}-%1?y pdAjAclkout2_src_ckrti,composite-clock}@AdBjBsys_clkout2rti,divider-clock}B@y p-mpu_ckrfixed-factor-clock}CdDjDarm_fckrti,divider-clock}Dy $emu_mpu_alwon_ckrfixed-factor-clock}Ddkjkl3_ickrti,divider-clock}-y @dEjEl4_ickrti,divider-clock}Ey @dFjFrm_ickrti,divider-clock}Fy @gpt10_gate_fckrti,composite-gate-clock}% y dHjHgpt10_mux_fckrti,composite-mux-clock}G%y @dIjIgpt10_fckrti,composite-clock}HIgpt11_gate_fckrti,composite-gate-clock}% y dJjJgpt11_mux_fckrti,composite-mux-clock}G%y @dKjKgpt11_fckrti,composite-clock}JKcore_96m_fckrfixed-factor-clock}Ld j mmchs2_fckrti,wait-gate-clock} y djmmchs1_fckrti,wait-gate-clock} y dji2c3_fckrti,wait-gate-clock} y dji2c2_fckrti,wait-gate-clock} y dji2c1_fckrti,wait-gate-clock} y djmcbsp5_gate_fckrti,composite-gate-clock}  y djmcbsp1_gate_fckrti,composite-gate-clock}  y djcore_48m_fckrfixed-factor-clock}7dMjMmcspi4_fckrti,wait-gate-clock}My djmcspi3_fckrti,wait-gate-clock}My djmcspi2_fckrti,wait-gate-clock}My djmcspi1_fckrti,wait-gate-clock}My djuart2_fckrti,wait-gate-clock}My djuart1_fckrti,wait-gate-clock}My  djcore_12m_fckrfixed-factor-clock}NdOjOhdq_fckrti,wait-gate-clock}Oy djcore_l3_ickrfixed-factor-clock}EdPjPsdrc_ickrti,wait-gate-clock}Py djgpmc_fckrfixed-factor-clock}Pcore_l4_ickrfixed-factor-clock}FdQjQmmchs2_ickrti,omap3-interface-clock}Qy djmmchs1_ickrti,omap3-interface-clock}Qy djhdq_ickrti,omap3-interface-clock}Qy djmcspi4_ickrti,omap3-interface-clock}Qy djmcspi3_ickrti,omap3-interface-clock}Qy djmcspi2_ickrti,omap3-interface-clock}Qy djmcspi1_ickrti,omap3-interface-clock}Qy dji2c3_ickrti,omap3-interface-clock}Qy dji2c2_ickrti,omap3-interface-clock}Qy dji2c1_ickrti,omap3-interface-clock}Qy djuart2_ickrti,omap3-interface-clock}Qy djuart1_ickrti,omap3-interface-clock}Qy  djgpt11_ickrti,omap3-interface-clock}Qy  djgpt10_ickrti,omap3-interface-clock}Qy  djmcbsp5_ickrti,omap3-interface-clock}Qy  djmcbsp1_ickrti,omap3-interface-clock}Qy  djomapctrl_ickrti,omap3-interface-clock}Qy djdss_tv_fckrti,gate-clock}?ydjdss_96m_fckrti,gate-clock}Lydjdss2_alwon_fckrti,gate-clock}%ydjdummy_ckr fixed-clockgpt1_gate_fckrti,composite-gate-clock}%y dRjRgpt1_mux_fckrti,composite-mux-clock}G%y @dSjSgpt1_fckrti,composite-clock}RSaes2_ickrti,omap3-interface-clock}Qy djwkup_32k_fckrfixed-factor-clock}GdTjTgpio1_dbckrti,gate-clock}Ty djsha12_ickrti,omap3-interface-clock}Qy djwdt2_fckrti,wait-gate-clock}Ty djwdt2_ickrti,omap3-interface-clock}Uy djwdt1_ickrti,omap3-interface-clock}Uy djgpio1_ickrti,omap3-interface-clock}Uy djomap_32ksync_ickrti,omap3-interface-clock}Uy djgpt12_ickrti,omap3-interface-clock}Uy djgpt1_ickrti,omap3-interface-clock}Uy djper_96m_fckrfixed-factor-clock}0djper_48m_fckrfixed-factor-clock}7dVjVuart3_fckrti,wait-gate-clock}Vy djgpt2_gate_fckrti,composite-gate-clock}%ydWjWgpt2_mux_fckrti,composite-mux-clock}G%y@dXjXgpt2_fckrti,composite-clock}WXgpt3_gate_fckrti,composite-gate-clock}%ydYjYgpt3_mux_fckrti,composite-mux-clock}G%y@dZjZgpt3_fckrti,composite-clock}YZgpt4_gate_fckrti,composite-gate-clock}%yd[j[gpt4_mux_fckrti,composite-mux-clock}G%y@d\j\gpt4_fckrti,composite-clock}[\gpt5_gate_fckrti,composite-gate-clock}%yd]j]gpt5_mux_fckrti,composite-mux-clock}G%y@d^j^gpt5_fckrti,composite-clock}]^gpt6_gate_fckrti,composite-gate-clock}%yd_j_gpt6_mux_fckrti,composite-mux-clock}G%y@d`j`gpt6_fckrti,composite-clock}_`gpt7_gate_fckrti,composite-gate-clock}%ydajagpt7_mux_fckrti,composite-mux-clock}G%y@dbjbgpt7_fckrti,composite-clock}abgpt8_gate_fckrti,composite-gate-clock}% ydcjcgpt8_mux_fckrti,composite-mux-clock}G%y@ddjdgpt8_fckrti,composite-clock}cdgpt9_gate_fckrti,composite-gate-clock}% ydejegpt9_mux_fckrti,composite-mux-clock}G%y@dfjfgpt9_fckrti,composite-clock}efper_32k_alwon_fckrfixed-factor-clock}Gdgjggpio6_dbckrti,gate-clock}gydjgpio5_dbckrti,gate-clock}gydjgpio4_dbckrti,gate-clock}gydjgpio3_dbckrti,gate-clock}gydjgpio2_dbckrti,gate-clock}gy djwdt3_fckrti,wait-gate-clock}gy djper_l4_ickrfixed-factor-clock}Fdhjhgpio6_ickrti,omap3-interface-clock}hydjgpio5_ickrti,omap3-interface-clock}hydjgpio4_ickrti,omap3-interface-clock}hydjgpio3_ickrti,omap3-interface-clock}hydjgpio2_ickrti,omap3-interface-clock}hy djwdt3_ickrti,omap3-interface-clock}hy djuart3_ickrti,omap3-interface-clock}hy djuart4_ickrti,omap3-interface-clock}hydjgpt9_ickrti,omap3-interface-clock}hy djgpt8_ickrti,omap3-interface-clock}hy djgpt7_ickrti,omap3-interface-clock}hydjgpt6_ickrti,omap3-interface-clock}hydjgpt5_ickrti,omap3-interface-clock}hydjgpt4_ickrti,omap3-interface-clock}hydjgpt3_ickrti,omap3-interface-clock}hydjgpt2_ickrti,omap3-interface-clock}hydjmcbsp2_ickrti,omap3-interface-clock}hydjmcbsp3_ickrti,omap3-interface-clock}hydjmcbsp4_ickrti,omap3-interface-clock}hydjmcbsp2_gate_fckrti,composite-gate-clock} ydjmcbsp3_gate_fckrti,composite-gate-clock} ydjmcbsp4_gate_fckrti,composite-gate-clock} ydjemu_src_mux_ckr ti,mux-clock}%ijky@dljlemu_src_ckrti,clkdm-gate-clock}ldmjmpclk_fckrti,divider-clock}my@pclkx2_fckrti,divider-clock}my@atclk_fckrti,divider-clock}my@traceclk_src_fckr ti,mux-clock}%ijky@dnjntraceclk_fckrti,divider-clock}n y@secure_32k_fckr fixed-clockdojogpt12_fckrfixed-factor-clock}owdt1_fckrfixed-factor-clock}osecurity_l4_ick2rfixed-factor-clock}Fdpjpaes1_ickrti,omap3-interface-clock}py rng_ickrti,omap3-interface-clock}py sha11_ickrti,omap3-interface-clock}py des1_ickrti,omap3-interface-clock}py cam_mclkrti,gate-clock}qycam_ickr!ti,omap3-no-wait-interface-clock}Fydjcsi2_96m_fckrti,gate-clock} ydjsecurity_l3_ickrfixed-factor-clock}Edrjrpka_ickrti,omap3-interface-clock}ry icr_ickrti,omap3-interface-clock}Qy des2_ickrti,omap3-interface-clock}Qy mspro_ickrti,omap3-interface-clock}Qy mailboxes_ickrti,omap3-interface-clock}Qy ssi_l4_ickrfixed-factor-clock}Fdyjysr1_fckrti,wait-gate-clock}%y sr2_fckrti,wait-gate-clock}%y sr_l4_ickrfixed-factor-clock}Fdpll2_fckrti,divider-clock}-y@dsjsdpll2_ckrti,omap3-dpll-clock}%sy$@4CU]dtjtdpll2_m2_ckrti,divider-clock}tyDdujuiva2_ckrti,wait-gate-clock}uydjmodem_fckrti,omap3-interface-clock}%y djsad2d_ickrti,omap3-interface-clock}Ey djmad2d_ickrti,omap3-interface-clock}Ey djmspro_fckrti,wait-gate-clock} y ssi_ssr_gate_fck_3430es2r ti,composite-no-wait-gate-clock}&y dvjvssi_ssr_div_fck_3430es2rti,composite-divider-clock}&y @$qdwjwssi_ssr_fck_3430es2rti,composite-clock}vwdxjxssi_sst_fck_3430es2rfixed-factor-clock}xdjhsotgusb_ick_3430es2r"ti,omap3-hsotgusb-interface-clock}Py djssi_ick_3430es2rti,omap3-ssi-interface-clock}yy djusim_gate_fckrti,composite-gate-clock}L y djsys_d2_ckrfixed-factor-clock}%d{j{omap_96m_d2_fckrfixed-factor-clock}Ld|j|omap_96m_d4_fckrfixed-factor-clock}Ld}j}omap_96m_d8_fckrfixed-factor-clock}Ld~j~omap_96m_d10_fckrfixed-factor-clock}L djdpll5_m2_d4_ckrfixed-factor-clock}zdjdpll5_m2_d8_ckrfixed-factor-clock}zdjdpll5_m2_d16_ckrfixed-factor-clock}zdjdpll5_m2_d20_ckrfixed-factor-clock}zdjusim_mux_fckrti,composite-mux-clock(}%{|}~y @djusim_fckrti,composite-clock}usim_ickrti,omap3-interface-clock}Uy  djdpll5_ckrti,omap3-dpll-clock}%%y  $ L 4CUdjdpll5_m2_ckrti,divider-clock}y Pdzjzsgx_gate_fckrti,composite-gate-clock}-y djcore_d3_ckrfixed-factor-clock}-djcore_d4_ckrfixed-factor-clock}-djcore_d6_ckrfixed-factor-clock}-djomap_192m_alwon_fckrfixed-factor-clock})djcore_d2_ckrfixed-factor-clock}-djsgx_mux_fckrti,composite-mux-clock }1y @djsgx_fckrti,composite-clock}sgx_ickrti,wait-gate-clock}Ey djcpefuse_fckrti,gate-clock}%y djts_fckrti,gate-clock}Gy djusbtll_fckrti,wait-gate-clock}zy djusbtll_ickrti,omap3-interface-clock}Qy djmmchs3_ickrti,omap3-interface-clock}Qy djmmchs3_fckrti,wait-gate-clock} y djdss1_alwon_fck_3430es2rti,dss-gate-clock}ydjdss_ick_3430es2rti,omap3-dss-interface-clock}Fydjusbhost_120m_fckrti,gate-clock}zydjusbhost_48m_fckrti,dss-gate-clock}7ydjusbhost_ickrti,omap3-dss-interface-clock}Fydjclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}!dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}mdpll4_clkdmti,clockdomain}#wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}td2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH djdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH` } `djpbias_regulatorti,pbias-omapypbias_mmc_omap2430pbias_mmc_omap2430w@-djgpio@48310000ti,omap3-gpioyH1gpio1 gpio@49050000ti,omap3-gpioyIgpio2 gpio@49052000ti,omap3-gpioyI gpio3 gpio@49054000ti,omap3-gpioyI@ gpio4 gpio@49056000ti,omap3-gpioyI`!gpio5 djgpio@49058000ti,omap3-gpioyI"gpio6 djserial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3l8defaultFi2c@48070000 ti,omap3-i2cyH8txrxi2c1'@twl@48yH& ti,twl40308defaultFaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci *watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 vdd_ehciw@w@8regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' djregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0djregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5djregulator-vusb1v8ti,twl4030-vusb1v8djregulator-vusb3v1ti,twl4030-vusb3v1djregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@8regulator-vsimti,twl4030-vsimw@-djgpioti,twl4030-gpio LXcdjtwl4030-usbti,twl4030-usb p~djpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrxi2c2 disabledi2c@48060000 ti,omap3-i2cyH=txrxi2c38defaultFmailbox@48094000ti,omap3-mailboxmailboxyH @ dsp  )spi@48098000ti,omap2-mcspiyH Amcspi14@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx38defaultFspidev@0spidevBlyTspi@4809a000ti,omap2-mcspiyH Bmcspi24 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [mcspi34 tx0rx0tx1rx18defaultFspidev@0spidevBlyTspi@480ba000ti,omap2-mcspiyH 0mcspi44FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1]=>txrxj8defaultFw mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx8defaultFwmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispdjmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxokaydjmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxokay8defaultFmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5txrx disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1 timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8)timer@49040000ti,omap3430-timeryI-timer9)timer@48086000ti,omap3430-timeryH`.timer10)timer@48088000ti,omap3430-timeryH/timer11)timer@48304000ti,omap3430-timeryH0@_timer12 6usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs Fehci-phyohci@48064400ti,ohci-omap3yHD&Lehci@48064800 ti,ehci-omapyHH&MQgpmc@6e000000ti,omap3430-gpmcgpmcynVbnand@0,0 ytsw$$$ 0)7FHWHh6wx-loader@0 X-Loaderybootloaders@80000U-Bootybootloaders_env@260000 U-Boot Envy&kernel@280000Kernely(@filesystem@680000 File Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs Q usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck8defaultFdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpointd j ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu }x ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$isp@480bc000 ti,omap3-ispyH H |rportshsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z pdjhsusb2_phyusb-nop-xceiv "djsoundti,omap-twl4030 -omap3beagle6regulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 ?'djgpio_poweroff8defaultFgpio-poweroff display@0 panel-dpilcd8defaultF Q portendpoint djpanel-timingP^ fn({V backlightgpio-backlight8defaultF    #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-typegpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-active-lowenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on