8Ș(r`(ti,am3517-craneboardti,am3517ti,omap3&#7TI AM3517 CraneBoard (TMDSEVM3517)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@4809e000memorylmemoryxcpuscpu@0arm,cortex-a8lcpux|cpupmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busx  pinmux@30 ti,omap3-padconfpinctrl-singlex08pinmux_tps_pins!5;scm_conf@270sysconxp05;clocksmcbsp5_mux_fckCti,composite-mux-clock|Pxh5;mcbsp5_fckCti,composite-clock|mcbsp1_mux_fckCti,composite-mux-clock|Px5;mcbsp1_fckCti,composite-clock|mcbsp2_mux_fckCti,composite-mux-clock| Px5 ; mcbsp2_fckCti,composite-clock| mcbsp3_mux_fckCti,composite-mux-clock| xh5 ; mcbsp3_fckCti,composite-clock| mcbsp4_mux_fckCti,composite-mux-clock| Pxh5;mcbsp4_fckCti,composite-clock|emac_ickCti,am35xx-gate-clock|x,P5w;wemac_fckCti,gate-clock|x,P vpfe_ickCti,am35xx-gate-clock|x,P5x;xvpfe_fckCti,gate-clock|x,P hsotgusb_ick_am35xxCti,am35xx-gate-clock|x,P5y;yhsotgusb_fck_am35xxCti,gate-clock|x,P5z;zhecc_ckCti,am35xx-gate-clock|x,P5{;{clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \aes@480c5000 ti,omap3-aesaesxH PP]ABbtxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_ckC fixed-clocklY5;osc_sys_ckC ti,mux-clock|x @5;sys_ckCti,divider-clock|P|xp5;sys_clkout1Cti,gate-clock|x pPdpll3_x2_ckCfixed-factor-clock|dpll3_m2x2_ckCfixed-factor-clock|5;dpll4_x2_ckCfixed-factor-clock|corex2_fckCfixed-factor-clock|5 ; wkup_l4_ickCfixed-factor-clock|5O;Ocorex2_d3_fckCfixed-factor-clock| 5p;pcorex2_d5_fckCfixed-factor-clock| 5q;qclockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclkC fixed-clocklomap_32k_fckC fixed-clockl5A;Avirt_12m_ckC fixed-clockl5;virt_13m_ckC fixed-clockl]@5;virt_19200000_ckC fixed-clockl$5;virt_26000000_ckC fixed-clockl5;virt_38_4m_ckC fixed-clocklI5;dpll4_ckCti,omap3-dpll-per-clock|x D 05;dpll4_m2_ckCti,divider-clock||?x H5!;!dpll4_m2x2_mul_ckCfixed-factor-clock|!5";"dpll4_m2x2_ckCti,gate-clock|"Px 5#;#omap_96m_alwon_fckCfixed-factor-clock|#5*;*dpll3_ckCti,omap3-dpll-core-clock|x @ 05;dpll3_m3_ckCti,divider-clock|P|x@5$;$dpll3_m3x2_mul_ckCfixed-factor-clock|$5%;%dpll3_m3x2_ckCti,gate-clock|%P x 5&;&emu_core_alwon_ckCfixed-factor-clock|&5c;csys_altclkC fixed-clockl5/;/mcbsp_clksC fixed-clockl5;dpll3_m2_ckCti,divider-clock|P|x @5;core_ckCfixed-factor-clock|5';'dpll1_fckCti,divider-clock|'P|x @5(;(dpll1_ckCti,omap3-dpll-clock|(x  $ @ 45;dpll1_x2_ckCfixed-factor-clock|5);)dpll1_x2m2_ckCti,divider-clock|)|x D5=;=cm_96m_fckCfixed-factor-clock|*5+;+omap_96m_fckC ti,mux-clock|+Px @5F;Fdpll4_m3_ckCti,divider-clock|P| x@5,;,dpll4_m3x2_mul_ckCfixed-factor-clock|,5-;-dpll4_m3x2_ckCti,gate-clock|-Px 5.;.omap_54m_fckC ti,mux-clock|./Px @59;9cm_96m_d2_fckCfixed-factor-clock|+50;0omap_48m_fckC ti,mux-clock|0/Px @51;1omap_12m_fckCfixed-factor-clock|15H;Hdpll4_m4_ckCti,divider-clock|| x@52;2dpll4_m4x2_mul_ckCti,fixed-factor-clock|253;3dpll4_m4x2_ckCti,gate-clock|3Px 5u;udpll4_m5_ckCti,divider-clock||?x@54;4dpll4_m5x2_mul_ckCti,fixed-factor-clock|455;5dpll4_m5x2_ckCti,gate-clock|5Px dpll4_m6_ckCti,divider-clock|P|?x@56;6dpll4_m6x2_mul_ckCfixed-factor-clock|657;7dpll4_m6x2_ckCti,gate-clock|7Px 58;8emu_per_alwon_ckCfixed-factor-clock|85d;dclkout2_src_gate_ckC ti,composite-no-wait-gate-clock|'Px p5:;:clkout2_src_mux_ckCti,composite-mux-clock|'+9x p5;;;clkout2_src_ckCti,composite-clock|:;5<;<sys_clkout2Cti,divider-clock|<P|@x pmpu_ckCfixed-factor-clock|=5>;>arm_fckCti,divider-clock|>x $|emu_mpu_alwon_ckCfixed-factor-clock|>5e;el3_ickCti,divider-clock|'|x @5?;?l4_ickCti,divider-clock|?P|x @5@;@rm_ickCti,divider-clock|@P|x @gpt10_gate_fckCti,composite-gate-clock|P x 5B;Bgpt10_mux_fckCti,composite-mux-clock|APx @5C;Cgpt10_fckCti,composite-clock|BCgpt11_gate_fckCti,composite-gate-clock|P x 5D;Dgpt11_mux_fckCti,composite-mux-clock|APx @5E;Egpt11_fckCti,composite-clock|DEcore_96m_fckCfixed-factor-clock|F5;mmchs2_fckCti,wait-gate-clock|x P5;mmchs1_fckCti,wait-gate-clock|x P5;i2c3_fckCti,wait-gate-clock|x P5;i2c2_fckCti,wait-gate-clock|x P5;i2c1_fckCti,wait-gate-clock|x P5;mcbsp5_gate_fckCti,composite-gate-clock|P x 5;mcbsp1_gate_fckCti,composite-gate-clock|P x 5;core_48m_fckCfixed-factor-clock|15G;Gmcspi4_fckCti,wait-gate-clock|Gx P5;mcspi3_fckCti,wait-gate-clock|Gx P5;mcspi2_fckCti,wait-gate-clock|Gx P5;mcspi1_fckCti,wait-gate-clock|Gx P5;uart2_fckCti,wait-gate-clock|Gx P5;uart1_fckCti,wait-gate-clock|Gx P 5;core_12m_fckCfixed-factor-clock|H5I;Ihdq_fckCti,wait-gate-clock|Ix P5;core_l3_ickCfixed-factor-clock|?5J;Jsdrc_ickCti,wait-gate-clock|Jx P5v;vgpmc_fckCfixed-factor-clock|Jcore_l4_ickCfixed-factor-clock|@5K;Kmmchs2_ickCti,omap3-interface-clock|Kx P5;mmchs1_ickCti,omap3-interface-clock|Kx P5;hdq_ickCti,omap3-interface-clock|Kx P5;mcspi4_ickCti,omap3-interface-clock|Kx P5;mcspi3_ickCti,omap3-interface-clock|Kx P5;mcspi2_ickCti,omap3-interface-clock|Kx P5;mcspi1_ickCti,omap3-interface-clock|Kx P5;i2c3_ickCti,omap3-interface-clock|Kx P5;i2c2_ickCti,omap3-interface-clock|Kx P5;i2c1_ickCti,omap3-interface-clock|Kx P5;uart2_ickCti,omap3-interface-clock|Kx P5;uart1_ickCti,omap3-interface-clock|Kx P 5;gpt11_ickCti,omap3-interface-clock|Kx P 5;gpt10_ickCti,omap3-interface-clock|Kx P 5;mcbsp5_ickCti,omap3-interface-clock|Kx P 5;mcbsp1_ickCti,omap3-interface-clock|Kx P 5;omapctrl_ickCti,omap3-interface-clock|Kx P5;dss_tv_fckCti,gate-clock|9xP5;dss_96m_fckCti,gate-clock|FxP5;dss2_alwon_fckCti,gate-clock|xP5;dummy_ckC fixed-clocklgpt1_gate_fckCti,composite-gate-clock|Px 5L;Lgpt1_mux_fckCti,composite-mux-clock|Ax @5M;Mgpt1_fckCti,composite-clock|LMaes2_ickCti,omap3-interface-clock|KPx 5;wkup_32k_fckCfixed-factor-clock|A5N;Ngpio1_dbckCti,gate-clock|Nx P5;sha12_ickCti,omap3-interface-clock|Kx P5;wdt2_fckCti,wait-gate-clock|Nx P5;wdt2_ickCti,omap3-interface-clock|Ox P5;wdt1_ickCti,omap3-interface-clock|Ox P5;gpio1_ickCti,omap3-interface-clock|Ox P5;omap_32ksync_ickCti,omap3-interface-clock|Ox P5;gpt12_ickCti,omap3-interface-clock|Ox P5;gpt1_ickCti,omap3-interface-clock|Ox P5;per_96m_fckCfixed-factor-clock|*5 ; per_48m_fckCfixed-factor-clock|15P;Puart3_fckCti,wait-gate-clock|PxP 5|;|gpt2_gate_fckCti,composite-gate-clock|Px5Q;Qgpt2_mux_fckCti,composite-mux-clock|Ax@5R;Rgpt2_fckCti,composite-clock|QRgpt3_gate_fckCti,composite-gate-clock|Px5S;Sgpt3_mux_fckCti,composite-mux-clock|APx@5T;Tgpt3_fckCti,composite-clock|STgpt4_gate_fckCti,composite-gate-clock|Px5U;Ugpt4_mux_fckCti,composite-mux-clock|APx@5V;Vgpt4_fckCti,composite-clock|UVgpt5_gate_fckCti,composite-gate-clock|Px5W;Wgpt5_mux_fckCti,composite-mux-clock|APx@5X;Xgpt5_fckCti,composite-clock|WXgpt6_gate_fckCti,composite-gate-clock|Px5Y;Ygpt6_mux_fckCti,composite-mux-clock|APx@5Z;Zgpt6_fckCti,composite-clock|YZgpt7_gate_fckCti,composite-gate-clock|Px5[;[gpt7_mux_fckCti,composite-mux-clock|APx@5\;\gpt7_fckCti,composite-clock|[\gpt8_gate_fckCti,composite-gate-clock|P x5];]gpt8_mux_fckCti,composite-mux-clock|APx@5^;^gpt8_fckCti,composite-clock|]^gpt9_gate_fckCti,composite-gate-clock|P x5_;_gpt9_mux_fckCti,composite-mux-clock|APx@5`;`gpt9_fckCti,composite-clock|_`per_32k_alwon_fckCfixed-factor-clock|A5a;agpio6_dbckCti,gate-clock|axP5};}gpio5_dbckCti,gate-clock|axP5~;~gpio4_dbckCti,gate-clock|axP5;gpio3_dbckCti,gate-clock|axP5;gpio2_dbckCti,gate-clock|axP 5;wdt3_fckCti,wait-gate-clock|axP 5;per_l4_ickCfixed-factor-clock|@5b;bgpio6_ickCti,omap3-interface-clock|bxP5;gpio5_ickCti,omap3-interface-clock|bxP5;gpio4_ickCti,omap3-interface-clock|bxP5;gpio3_ickCti,omap3-interface-clock|bxP5;gpio2_ickCti,omap3-interface-clock|bxP 5;wdt3_ickCti,omap3-interface-clock|bxP 5;uart3_ickCti,omap3-interface-clock|bxP 5;uart4_ickCti,omap3-interface-clock|bxP5;gpt9_ickCti,omap3-interface-clock|bxP 5;gpt8_ickCti,omap3-interface-clock|bxP 5;gpt7_ickCti,omap3-interface-clock|bxP5;gpt6_ickCti,omap3-interface-clock|bxP5;gpt5_ickCti,omap3-interface-clock|bxP5;gpt4_ickCti,omap3-interface-clock|bxP5;gpt3_ickCti,omap3-interface-clock|bxP5;gpt2_ickCti,omap3-interface-clock|bxP5;mcbsp2_ickCti,omap3-interface-clock|bxP5;mcbsp3_ickCti,omap3-interface-clock|bxP5;mcbsp4_ickCti,omap3-interface-clock|bxP5;mcbsp2_gate_fckCti,composite-gate-clock|Px5 ; mcbsp3_gate_fckCti,composite-gate-clock|Px5 ; mcbsp4_gate_fckCti,composite-gate-clock|Px5;emu_src_mux_ckC ti,mux-clock|cdex@5f;femu_src_ckCti,clkdm-gate-clock|f5g;gpclk_fckCti,divider-clock|gP|x@pclkx2_fckCti,divider-clock|gP|x@atclk_fckCti,divider-clock|gP|x@traceclk_src_fckC ti,mux-clock|cdePx@5h;htraceclk_fckCti,divider-clock|hP |x@secure_32k_fckC fixed-clockl5i;igpt12_fckCfixed-factor-clock|iwdt1_fckCfixed-factor-clock|iipss_ickCti,am35xx-interface-clock|Jx P5;rmii_ckC fixed-clockl5;pclk_ckC fixed-clockl5;uart4_ick_am35xxCti,omap3-interface-clock|Kx Puart4_fck_am35xxCti,wait-gate-clock|Gx Pdpll5_ckCti,omap3-dpll-clock|x  $ L 4 5j;jdpll5_m2_ckCti,divider-clock|j|x P5t;tsgx_gate_fckCti,composite-gate-clock|'Px 5r;rcore_d3_ckCfixed-factor-clock|'5k;kcore_d4_ckCfixed-factor-clock|'5l;lcore_d6_ckCfixed-factor-clock|'5m;momap_192m_alwon_fckCfixed-factor-clock|#5n;ncore_d2_ckCfixed-factor-clock|'5o;osgx_mux_fckCti,composite-mux-clock |klm+nopqx @5s;ssgx_fckCti,composite-clock|rssgx_ickCti,wait-gate-clock|?x P5;cpefuse_fckCti,gate-clock|x P5;ts_fckCti,gate-clock|Ax P5;usbtll_fckCti,wait-gate-clock|tx P5;usbtll_ickCti,omap3-interface-clock|Kx P5;mmchs3_ickCti,omap3-interface-clock|Kx P5;mmchs3_fckCti,wait-gate-clock|x P5;dss1_alwon_fck_3430es2Cti,dss-gate-clock|uPx5;dss_ick_3430es2Cti,omap3-dss-interface-clock|@xP5;usbhost_120m_fckCti,gate-clock|txP5;usbhost_48m_fckCti,dss-gate-clock|1xP5;usbhost_ickCti,omap3-dss-interface-clock|@xP5;clockdomainscore_l3_clkdmti,clockdomain|vwxyz{dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainh||}~emu_clkdmti,clockdomain|gdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain |dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|dpll5_clkdmti,clockdomain|jsgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH 5;dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH` '2 ?`5;pbias_regulatorti,pbias-omapxLpbias_mmc_omap2430Spbias_mmc_omap2430bw@z-5;gpio@48310000ti,omap3-gpioxH1gpio1gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5gpio@49058000ti,omap3-gpioxI"gpio6serial@4806a000ti,omap3-uartxH H]12btxrxuart1llserial@4806c000ti,omap3-uartxHI]34btxrxuart2llserial@49020000ti,omap3-uartxIJ]56btxrxuart3lli2c@48070000 ti,omap3-i2cxH8]btxrxi2c1l'@tps@2dx- ti,tps65910default& !-9EQregulatorsregulator@0x^vrtcsregulator@1x^viosregulator@2x^vdd1 Svdd_corebOzOsregulator@3x^vdd2Svdd_shvb2Zz2Zs5;regulator@4x^vdd3regulator@5x^vdig1regulator@6x^vdig2regulator@7x^vpllbw@zw@sregulator@8x^vdacbw@zw@sregulator@9x ^vaux1bw@zw@sregulator@10x ^vaux2bw@zw@sregulator@11x ^vaux33regulator@12x ^vmmcb2Zz2Zsregulator@13x ^vbbi2c@48072000 ti,omap3-i2cxH 9]btxrxi2c2l disabledi2c@48060000 ti,omap3-i2cxH=]btxrxi2c3l disabledmailbox@48094000ti,omap3-mailboxmailboxxH @ disableddsp  spi@48098000ti,omap2-mcspixH Amcspi1@]#$%&'()* btx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH Bmcspi2 ]+,-.btx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3 ]btx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4]FGbtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1]=>btxrxmmc@480b4000ti,omap3-hsmmcxH @Vmmc2]/0btxrx disabledmmc@480ad000ti,omap3-hsmmcxH ^mmc3]MNbtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_isp* disabledmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@:mpu ;< DcommontxrxTmcbsp1] btxrx disabledmcbsp@49022000ti,omap3-mcbspxI I :mpusidetone>?DcommontxrxsidetoneTmcbsp2mcbsp2_sidetone]!"btxrx disabledmcbsp@49024000ti,omap3-mcbspxI@I :mpusidetoneYZDcommontxrxsidetoneTmcbsp3mcbsp3_sidetone]btxrx disabledmcbsp@49026000ti,omap3-mcbspxI`:mpu 67 DcommontxrxTmcbsp4]btxrx disabledmcbsp@48096000ti,omap3-mcbspxH `:mpu QR DcommontxrxTmcbsp5]btxrx disabledsham@480c3000ti,omap3-shamshamxH 0d1]Ebrxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH  disabledtimer@48318000ti,omap3430-timerxH1%timer1ctimer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5rtimer@4903a000ti,omap3430-timerxI*timer6rtimer@4903c000ti,omap3430-timerxI+timer7rtimer@4903e000ti,omap3430-timerxI,timer8rtimer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11timer@48304000ti,omap3430-timerxH0@_timer12cusbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hsohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxnusb_otg_hs@480ab000ti,omap3-musbxH \]Dmcdma usb_otg_hs dss@48050000 ti,omap3-dssxH disabled dss_core|fckdispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H :protophypll disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  disabled dss_venc|fckssi-controller@48058000 ti,omap3-ssissi disabledxHH:sysgddGDgdd_mpussi-port@4805a000ti,omap3-ssi-portxHH:txrx&CDssi-port@4805b000ti,omap3-ssi-portxHH:txrx&EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabledx\GDmcethernet@0x5c000000ti,am3517-emac davinci_emacokayx\CDEFL+ DWethernet@0x5c030000ti,davinci_mdio davinci_mdiookayx\iB@serial@4809e000ti,omap3-uartuart4 disabledxH T]76btxrxllpinmux@480025d8 ti,omap3-padconfpinctrl-singlexH%$fixedregulator@0regulator-fixedSvbatbLK@zLK@5; #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,en-ck32k-xtalvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-always-onregulator-boot-on#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-width#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freq