{8u,(ttcl,am335x-sl50ti,am33xx&7Toby Churchill SL50 Serieschosenaliases=/ocp/i2c@44e0b000B/ocp/i2c@4802a000G/ocp/i2c@4819c000L/ocp/serial@44e09000T/ocp/serial@48022000\/ocp/serial@48024000d/ocp/serial@481a6000l/ocp/serial@481a8000t/ocp/serial@481aa000|/ocp/can@481cc000/ocp/can@481d0000/ocp/usb@47400000/usb@47401000/ocp/usb@47400000/usb@47401800#/ocp/usb@47400000/usb-phy@47401300#/ocp/usb@47400000/usb-phy@47401b00&/ocp/ethernet@4a100000/slave@4a100200&/ocp/ethernet@4a100000/slave@4a100300memorymemorycpuscpu@0arm,cortex-a8cpu  '( *28*cpupmuarm,cortex-a8-pmusocti,omap-inframpu ti,omap3-mpumpuocp simple-bus'l3_mainl4_wkup@44c00000ti,am3-l4-wkupsimple-bus 'D(prcm@200000 ti,am3-prcm @clocksclk_32768_ck. fixed-clock;KQclk_rc32k_ck. fixed-clock;}KQvirt_19200000_ck. fixed-clock;$K!Q!virt_24000000_ck. fixed-clock;n6K"Q"virt_25000000_ck. fixed-clock;}x@K#Q#virt_26000000_ck. fixed-clock;K$Q$tclkin_ck. fixed-clock;KQdpll_core_ck.ti,am3-dpll-core-clock \hKQdpll_core_x2_ck.ti,am3-dpll-x2-clockKQdpll_core_m4_ck.ti,divider-clockYdKQdpll_core_m5_ck.ti,divider-clockYdKQdpll_core_m6_ck.ti,divider-clockYddpll_mpu_ck.ti,am3-dpll-clock  ,KQdpll_mpu_m2_ck.ti,divider-clockYddpll_ddr_ck.ti,am3-dpll-no-gate-clock 4@KQdpll_ddr_m2_ck.ti,divider-clockYdKQdpll_ddr_m2_div2_ck.fixed-factor-clock{dpll_disp_ck.ti,am3-dpll-no-gate-clock HTK Q dpll_disp_m2_ck.ti,divider-clock YdKQdpll_per_ck.!ti,am3-dpll-no-gate-j-type-clock pK Q dpll_per_m2_ck.ti,divider-clock YdK Q dpll_per_m2_div4_wkupdm_ck.fixed-factor-clock {dpll_per_m2_div4_ck.fixed-factor-clock {cefuse_fck.ti,gate-clock clk_24mhz.fixed-factor-clock {K Q clkdiv32k_ck.fixed-factor-clock {K Q clkdiv32k_ick.ti,gate-clock LKQl3_gclk.fixed-factor-clock{KQpruss_ocp_gclk. ti,mux-clock0mmu_fck.ti,gate-clock timer1_fck. ti,mux-clock(timer2_fck. ti,mux-clock timer3_fck. ti,mux-clock  timer4_fck. ti,mux-clock timer5_fck. ti,mux-clock timer6_fck. ti,mux-clock timer7_fck. ti,mux-clock usbotg_fck.ti,gate-clock |dpll_core_m4_div2_ck.fixed-factor-clock{KQieee5000_fck.ti,gate-clockwdt1_fck. ti,mux-clock8l4_rtc_gclk.fixed-factor-clock{l4hs_gclk.fixed-factor-clock{l3s_gclk.fixed-factor-clock{l4fw_gclk.fixed-factor-clock{l4ls_gclk.fixed-factor-clock{K%Q%sysclk_div_ck.fixed-factor-clock{cpsw_125mhz_gclk.fixed-factor-clock{K;Q;cpsw_cpts_rft_clk. ti,mux-clock K<Q<gpio0_dbclk_mux_ck. ti,mux-clock <KQgpio0_dbclk.ti,gate-clockgpio1_dbclk.ti,gate-clockgpio2_dbclk.ti,gate-clockgpio3_dbclk.ti,gate-clocklcd_gclk. ti,mux-clock  4KQmmc_clk.fixed-factor-clock {gfx_fclk_clksel_ck. ti,mux-clock ,KQgfx_fck_div_ck.ti,divider-clock,Ysysclkout_pre_ck. ti,mux-clock KQclkout2_div_ck.ti,divider-clockYKQdbg_sysclk_ck.ti,gate-clockKQdbg_clka_ck.ti,gate-clockKQstm_pmd_clock_mux_ck. ti,mux-clockKQtrace_pmd_clk_mux_ck. ti,mux-clockKQstm_clk_div_ck.ti,divider-clockY@trace_clk_div_ck.ti,divider-clockY@clkout2_ck.ti,gate-clockclockdomainsclk_24mhz_clkdmti,clockdomainscm@210000ti,am3-scmsimple-bus!  '! pinmux@800pinctrl-single8 default pinmux_led_pins TX\`KCQCpinmux_uart0_pinsp0tK'Q'pinmux_uart4_pinsp6tK(Q(pinmux_i2c0_pins00K)Q)pinmux_i2c1_pins33K*Q*pinmux_i2c2_pinsx3|3K+Q+cpsw_defaulth00 $(,0004080<0@0K=Q=cpsw_sleeph'''' '$'(','0'4'8'<'@'K>Q>davinci_mdio_defaultH0LK?Q?davinci_mdio_sleepH'L'K@Q@pinmux_mmc1_pins`/K.Q.pinmux_emmc_pwrseq_pinsPKHQHpinmux_emmc_pinsP22111 11111K1Q1pinmux_audio_pins(    "KBQBpinmux_ehrpwm1a_pinsHLK:Q:pinmux_lwb_pinsX(074787D7T7X7P7@7<7K Q scm_conf@0sysconK4Q4clockssys_clkin_ck. ti,mux-clock!"#$@KQadc_tsc_fck.fixed-factor-clock{dcan0_fck.fixed-factor-clock{K3Q3dcan1_fck.fixed-factor-clock{K5Q5mcasp0_fck.fixed-factor-clock{mcasp1_fck.fixed-factor-clock{smartreflex0_fck.fixed-factor-clock{smartreflex1_fck.fixed-factor-clock{sha0_fck.fixed-factor-clock{aes0_fck.fixed-factor-clock{rng_fck.fixed-factor-clock{ehrpwm0_tbclk@44e10664.ti,gate-clock%dehrpwm1_tbclk@44e10664.ti,gate-clock%dehrpwm2_tbclk@44e10664.ti,gate-clock%dclockdomainsinterrupt-controller@48200000ti,am33xx-intc-BH KQedma@49000000 ti,edma3tpcctptc0tptc1tptc2ID@  SK&Q&gpio@44e07000ti,omap4-gpiogpio1^n-BDp`K/Q/gpio@4804c000ti,omap4-gpiogpio2^n-BHbKDQDgpio@481ac000ti,omap4-gpiogpio3^n-BH gpio@481ae000ti,omap4-gpiogpio4^n-BH>serial@44e09000ti,omap3-uartuart1;lD Hzokay&&txrxdefault'serial@48022000ti,omap3-uartuart2;lH I zdisabled&&txrxserial@48024000ti,omap3-uartuart3;lH@ J zdisabled&&txrxserial@481a6000ti,omap3-uartuart4;lH` , zdisabledserial@481a8000ti,omap3-uartuart5;lH -zokaydefault(serial@481aa000ti,omap3-uartuart6;lH . zdisabledi2c@44e0b000 ti,omap4-i2ci2c1DFzokaydefault);tps@24$ ti,tps65217&regulatorsregulator@0dcdc1``regulator@1dcdc2vdd_mpuH7KQregulator@2dcdc3 vdd_coreH0regulator@3ldo1w@w@regulator@4ldo22Z2Zregulator@5ldo3w@w@K-Q-regulator@6ldo42Z2ZK,Q,eeprom@50 at,24c256Pi2c@4802a000 ti,omap4-i2ci2c2HGzokaydefault*i2c@4819c000 ti,omap4-i2ci2c3Hzokaydefault+;tlv320aic3106@1bzokayti,tlv320aic3106&,2,?,L-KFQFmmc@48060000ti,omap4-hsmmcmmc1Xe|&&txrx@&Hzokaydefault. /0mmc@481d8000ti,omap4-hsmmcmmc2e&&txrx&Hzokaydefault102mmc@47810000ti,omap4-hsmmcmmc3e&G zdisabledspinlock@480ca000ti,omap4-hwspinlockH  spinlockwdt@44e35000 ti,omap3-wdt wd_timer2DP[can@481cc000ti,am3352-d_cand_can0H 3fck 4D4 zdisabledcan@481d0000ti,am3352-d_cand_can1H 5fck 4D7 zdisabledmailbox@480C8000ti,omap4-mailboxH Mmailboxwkup_m3  timer@44e31000ti,am335x-timer-1msDCtimer1&timer@48040000ti,am335x-timerHDtimer2timer@48042000ti,am335x-timerH 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G@0G@@@#PgluecontrollerschedulerqueuemgrfglueSzokayK8Q8epwmss@48300000ti,am33xx-pwmssH0epwmss0 zdisabled$'H0H0H0H0H0H0ecap@48300100ti,am33xx-ecapH0fecap0ecap0 zdisabledehrpwm@48300200ti,am33xx-ehrpwmH0ehrpwm0 zdisabledepwmss@48302000ti,am33xx-pwmssH0 epwmss1zokay$'H0!H0!H0!H0!H0"H0"ecap@48302100ti,am33xx-ecapH0!/fecap1ecap1 zdisabledehrpwm@48302200ti,am33xx-ehrpwmH0"ehrpwm1zokaydefault:KEQEepwmss@48304000ti,am33xx-pwmssH0@epwmss2 zdisabled$'H0AH0AH0AH0AH0BH0Becap@48304100ti,am33xx-ecapH0A=fecap2ecap2 zdisabledehrpwm@48304200ti,am33xx-ehrpwmH0Behrpwm2 zdisabledethernet@4a100000ti,cpswcpgmac0;< fckcpts @" .5BRJJ&()*+'c4zokaydefaultsleep=j>mdio@4a101000ti,davinci_mdio davinci_mdiotB@Jzokaydefaultsleep?j@KAQAslave@4a100200}Amiislave@4a100300}Amiicpsw-phy-sel@44e10650ti,am3352-cpsw-phy-selDP Pgmii-selocmcram@40300000 mmio-sram@0wkup_m3@44d00000ti,am3353-wkup-m3D@D wkup_m3elm@48080000ti,am3352-elmH elm zdisabledlcdc@4830e000ti,am33xx-tilcdcH0&$lcdc zdisabledtscadc@44e0d000ti,am3359-tscadcD&adc_tsc zdisabledtscti,am3359-tscadcti,am3359-adcgpmc@50000000ti,am3352-gpmcgpmcP d zdisabledsham@53100000ti,omap4-shamshamSm&$rxzokayaes@53500000 ti,omap4-aesaesSPg&&txrxzokaymcasp@48038000ti,am33xx-mcasp-audiomcasp0H F@PmpudatPQftxrxzokay&& txrxdefaultB@ KGQGmcasp@4803C000ti,am33xx-mcasp-audiomcasp1H F@@PmpudatRSftxrx zdisabled& & txrxrng@48310000 ti,omap4-rngrngH1 oleds gpio-ledsdefaultCled@0#sl50:green:usr0 D)offled@1#sl50:red:usr1 D)offled@2#sl50:green:usr2 D)offled@3#sl50:red:usr3 D)offdisp0pwm-backlight7E ,< (2<FPZcNdisp1pwm-backlight7E ,< (2<FPZcNsoundti,da830-evm-audio gAM335x-SL50pFGJHeadphone JackHPLOUTHeadphone JackHPROUTLINE1RLine InLINE1LLine Inpwrseq@0mmc-pwrseq-emmcdefaultH DK2Q2fixedregulator@0regulator-fixed vmmcsd_fixed2Z2ZK0Q0 #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1device_typeregoperating-pointsvoltage-toleranceclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shiftti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsinterrupt-controller#interrupt-cells#dma-cellsgpio-controller#gpio-cellsstatusdmasdma-namesti,pmic-shutdown-controllerregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-nameregulator-boot-onAVDD-supplyIOVDD-supplyDRVDD-supplyDVDD-supplyti,dual-voltti,needs-special-resetti,needs-special-hs-handlingbus-widthcd-gpiosvmmc-supplymmc-pwrseq#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csreg-namesti,ctrl_modinterrupt-namesdr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsysconpinctrl-1bus_freqmac-addressphy_idphy-modeti,no-reset-on-init#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsop-modetdm-slotsserial-dirtx-num-evtrx-num-evtlabeldefault-statepwmsbrightness-levelsdefault-brightness-levelti,modelti,audio-codecti,mcasp-controllerti,codec-clock-rateti,audio-routingreset-gpios