yV8q(qd ti,am33xx&7Newflow AM335x NanoBonechosenaliases=/ocp/i2c@44e0b000B/ocp/i2c@4802a000G/ocp/i2c@4819c000L/ocp/serial@44e09000T/ocp/serial@48022000\/ocp/serial@48024000d/ocp/serial@481a6000l/ocp/serial@481a8000t/ocp/serial@481aa000|/ocp/can@481cc000/ocp/can@481d0000/ocp/usb@47400000/usb@47401000/ocp/usb@47400000/usb@47401800#/ocp/usb@47400000/usb-phy@47401300#/ocp/usb@47400000/usb-phy@47401b00&/ocp/ethernet@4a100000/slave@4a100200&/ocp/ethernet@4a100000/slave@4a100300memorymemorycpuscpu@0arm,cortex-a8cpu  '( *28*cpupmuarm,cortex-a8-pmusocti,omap-inframpu ti,omap3-mpumpuocp simple-bus'l3_mainl4_wkup@44c00000ti,am3-l4-wkupsimple-bus 'D(prcm@200000 ti,am3-prcm @clocksclk_32768_ck. fixed-clock;KQclk_rc32k_ck. fixed-clock;}KQvirt_19200000_ck. fixed-clock;$K!Q!virt_24000000_ck. fixed-clock;n6K"Q"virt_25000000_ck. fixed-clock;}x@K#Q#virt_26000000_ck. fixed-clock;K$Q$tclkin_ck. fixed-clock;KQdpll_core_ck.ti,am3-dpll-core-clock \hKQdpll_core_x2_ck.ti,am3-dpll-x2-clockKQdpll_core_m4_ck.ti,divider-clockYdKQdpll_core_m5_ck.ti,divider-clockYdKQdpll_core_m6_ck.ti,divider-clockYddpll_mpu_ck.ti,am3-dpll-clock  ,KQdpll_mpu_m2_ck.ti,divider-clockYddpll_ddr_ck.ti,am3-dpll-no-gate-clock 4@KQdpll_ddr_m2_ck.ti,divider-clockYdKQdpll_ddr_m2_div2_ck.fixed-factor-clock{dpll_disp_ck.ti,am3-dpll-no-gate-clock HTK Q dpll_disp_m2_ck.ti,divider-clock YdKQdpll_per_ck.!ti,am3-dpll-no-gate-j-type-clock pK Q dpll_per_m2_ck.ti,divider-clock YdK Q dpll_per_m2_div4_wkupdm_ck.fixed-factor-clock {dpll_per_m2_div4_ck.fixed-factor-clock {cefuse_fck.ti,gate-clock clk_24mhz.fixed-factor-clock {K Q clkdiv32k_ck.fixed-factor-clock {K Q clkdiv32k_ick.ti,gate-clock LKQl3_gclk.fixed-factor-clock{KQpruss_ocp_gclk. ti,mux-clock0mmu_fck.ti,gate-clock timer1_fck. ti,mux-clock(timer2_fck. ti,mux-clock timer3_fck. ti,mux-clock  timer4_fck. ti,mux-clock timer5_fck. ti,mux-clock timer6_fck. ti,mux-clock timer7_fck. ti,mux-clock usbotg_fck.ti,gate-clock |dpll_core_m4_div2_ck.fixed-factor-clock{KQieee5000_fck.ti,gate-clockwdt1_fck. ti,mux-clock8l4_rtc_gclk.fixed-factor-clock{l4hs_gclk.fixed-factor-clock{l3s_gclk.fixed-factor-clock{l4fw_gclk.fixed-factor-clock{l4ls_gclk.fixed-factor-clock{K%Q%sysclk_div_ck.fixed-factor-clock{cpsw_125mhz_gclk.fixed-factor-clock{K:Q:cpsw_cpts_rft_clk. ti,mux-clock K;Q;gpio0_dbclk_mux_ck. ti,mux-clock <KQgpio0_dbclk.ti,gate-clockgpio1_dbclk.ti,gate-clockgpio2_dbclk.ti,gate-clockgpio3_dbclk.ti,gate-clocklcd_gclk. ti,mux-clock  4KQmmc_clk.fixed-factor-clock {gfx_fclk_clksel_ck. ti,mux-clock ,KQgfx_fck_div_ck.ti,divider-clock,Ysysclkout_pre_ck. ti,mux-clock KQclkout2_div_ck.ti,divider-clockYKQdbg_sysclk_ck.ti,gate-clockKQdbg_clka_ck.ti,gate-clockKQstm_pmd_clock_mux_ck. ti,mux-clockKQtrace_pmd_clk_mux_ck. ti,mux-clockKQstm_clk_div_ck.ti,divider-clockY@trace_clk_div_ck.ti,divider-clockY@clkout2_ck.ti,gate-clockclockdomainsclk_24mhz_clkdmti,clockdomainscm@210000ti,am3-scmsimple-bus!  '! pinmux@800pinctrl-single8 default misc_pins\K Q gpmc_pins000 00000 0$0(0,0004080<0p0| K=Q=i2c0_pins  K/Q/uart0_pinsp0tK'Q'uart1_pins x|0K(Q(uart2_pins 7P)T K*Q*uart3_pins 6`)d K,Q,uart4_pins 6h)l K-Q-uart5_pins,D K.Q.mmc1_pins@00000077K1Q1scm_conf@0sysconK4Q4clockssys_clkin_ck. ti,mux-clock!"#$@KQadc_tsc_fck.fixed-factor-clock{dcan0_fck.fixed-factor-clock{K3Q3dcan1_fck.fixed-factor-clock{K5Q5mcasp0_fck.fixed-factor-clock{mcasp1_fck.fixed-factor-clock{smartreflex0_fck.fixed-factor-clock{smartreflex1_fck.fixed-factor-clock{sha0_fck.fixed-factor-clock{aes0_fck.fixed-factor-clock{rng_fck.fixed-factor-clock{ehrpwm0_tbclk@44e10664.ti,gate-clock%dehrpwm1_tbclk@44e10664.ti,gate-clock%dehrpwm2_tbclk@44e10664.ti,gate-clock%dclockdomainsinterrupt-controller@48200000ti,am33xx-intc-BH KQedma@49000000 ti,edma3tpcctptc0tptc1tptc2ID@  SK&Q&gpio@44e07000ti,omap4-gpiogpio1^n-BDp`K)Q)gpio@4804c000ti,omap4-gpiogpio2^n-BHbK>Q>gpio@481ac000ti,omap4-gpiogpio3^n-BH K+Q+gpio@481ae000ti,omap4-gpiogpio4^n-BH>K2Q2serial@44e09000ti,omap3-uartuart1;lD Hzokay&&txrxdefault'serial@48022000ti,omap3-uartuart2;lH Izokay&&txrxdefault( ) serial@48024000ti,omap3-uartuart3;lH@ Jzokay&&txrxdefault* +serial@481a6000ti,omap3-uartuart4;lH` ,zokaydefault,serial@481a8000ti,omap3-uartuart5;lH -zokaydefault-serial@481aa000ti,omap3-uartuart6;lH .zokaydefault.i2c@44e0b000 ti,omap4-i2ci2c1DFzokaydefault;/gpio@20microchip,mcp23017^n tps@24$ ti,tps65217regulatorsregulator@0dcdc1  8Jregulator@1dcdc2^vdd_mpu 8 e 8JKQregulator@2dcdc3 ^vdd_core 8 e 8Jregulator@3ldo1 8Jregulator@4ldo20rX 4Vp8Jregulator@5ldo3 8Jregulator@6ldo40rX 4Vp8JK0Q0eeprom@53microchip,24c02Smrtc@68dallas,ds1307hi2c@4802a000 ti,omap4-i2ci2c2HG zdisabledi2c@4819c000 ti,omap4-i2ci2c3H zdisabledmmc@48060000ti,omap4-hsmmcmmc1v&&txrx@&Hzokay0default1 2 2mmc@481d8000ti,omap4-hsmmcmmc2&&txrx&H zdisabledmmc@47810000ti,omap4-hsmmcmmc3&G zdisabledspinlock@480ca000ti,omap4-hwspinlockH  spinlockwdt@44e35000 ti,omap3-wdt wd_timer2DP[can@481cc000ti,am3352-d_cand_can0H 3fck 4D4 zdisabledcan@481d0000ti,am3352-d_cand_can1H 5fck 4D7 zdisabledmailbox@480C8000ti,omap4-mailboxH Mmailboxwkup_m3 , 7timer@44e31000ti,am335x-timer-1msDCtimer1Btimer@48040000ti,am335x-timerHDtimer2timer@48042000ti,am335x-timerH Etimer3timer@48044000ti,am335x-timerH@\timer4Qtimer@48046000ti,am335x-timerH`]timer5Qtimer@48048000ti,am335x-timerH^timer6Qtimer@4804a000ti,am335x-timerH_timer7Qrtc@44e3e000ti,am3352-rtcti,da830-rtcDKLrtcspi@48030000ti,omap4-mcspiHA^spi0 &&&&tx0rx0tx1rx1 zdisabledspi@481a0000ti,omap4-mcspiH}^spi1 &*&+&,&-tx0rx0tx1rx1 zdisabledusb@47400000ti,am33xx-usbG@' usb_otg_hs zdisabledcontrol@44e10620ti,am335x-usb-ctrl-moduleD DHlphy_ctrlwakeup zdisabledK6Q6usb-phy@47401300ti,am335x-usb-phyG@lphy zdisabledv6K7Q7usb@47401000ti,musb-am33xx zdisabledG@G@ lmccontrolmcotg 7h8888888888 8 8 8 8 88888888888 8 8 8 8 8rx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15usb-phy@47401b00ti,am335x-usb-phyG@lphy zdisabledv6K9Q9usb@47401800ti,musb-am33xx zdisabledG@G@ lmccontrolmcotg 9h888888888888888888888888888888rx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15dma-controller@47402000ti,am3359-cppi41 G@G@ G@0G@@@#lgluecontrollerschedulerqueuemgrglueS zdisabledK8Q8epwmss@48300000ti,am33xx-pwmssH0epwmss0 zdisabled$'H0H0H0H0H0H0ecap@48300100ti,am33xx-ecapH0ecap0ecap0 zdisabledehrpwm@48300200ti,am33xx-ehrpwmH0ehrpwm0 zdisabledepwmss@48302000ti,am33xx-pwmssH0 epwmss1 zdisabled$'H0!H0!H0!H0!H0"H0"ecap@48302100ti,am33xx-ecapH0!/ecap1ecap1 zdisabledehrpwm@48302200ti,am33xx-ehrpwmH0"ehrpwm1 zdisabledepwmss@48304000ti,am33xx-pwmssH0@epwmss2 zdisabled$'H0AH0AH0AH0AH0BH0Becap@48304100ti,am33xx-ecapH0A=ecap2ecap2 zdisabledehrpwm@48304200ti,am33xx-ehrpwmH0Behrpwm2 zdisabledethernet@4a100000ti,cpswcpgmac0:; fckcpts +5@> JQ^nJJ&()*+'4zokaymdio@4a101000ti,davinci_mdio davinci_mdioB@JzokayK<Q<slave@4a100200<miislave@4a100300<miicpsw-phy-sel@44e10650ti,am3352-cpsw-phy-selDP lgmii-selocmcram@40300000 mmio-sram@0wkup_m3@44d00000ti,am3353-wkup-m3D@D wkup_m3elm@48080000ti,am3352-elmH elmzokaylcdc@4830e000ti,am33xx-tilcdcH0&$lcdc zdisabledtscadc@44e0d000ti,am3359-tscadcD&adc_tsc zdisabledtscti,am3359-tscadcti,am3359-adcgpmc@50000000ti,am3352-gpmcgpmcP d zokaydefault='nor@0,0  cfi-flashspansion,s29gl010p11t.9K\j| ((. Hb|FPpartition@0boot partition@1env1 partition@2env2partition@3kernel@partition@4rootfsPpartition@5userpartition@6datasham@53100000ti,omap4-shamshamSm&$rxaes@53500000 ti,omap4-aesaesSPg&&txrxmcasp@48038000ti,am33xx-mcasp-audiomcasp0H F@lmpudatPQtxrx zdisabled&& txrxmcasp@4803C000ti,am33xx-mcasp-audiomcasp1H F@@lmpudatRStxrx zdisabled& & txrxrng@48310000 ti,omap4-rngrngH1 oleds gpio-ledsled@0nanobone:green:usr1 >off #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1device_typeregoperating-pointsvoltage-toleranceclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shiftti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsinterrupt-controller#interrupt-cells#dma-cellsgpio-controller#gpio-cellsstatusdmasdma-namesrts-gpiors485-rts-active-highrs485-rx-during-txrs485-rts-delaylinux,rs485-enabled-at-boot-timeregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onregulator-namepagesizeti,dual-voltti,needs-special-resetti,needs-special-hs-handlingvmmc-supplybus-widthcd-gpioswp-gpios#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csreg-namesti,ctrl_modinterrupt-namesdr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsyscondual_emacbus_freqmac-addressphy_idphy-modedual_emac_res_vlanti,no-reset-on-init#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpinslinux,mtd-namebank-widthgpmc,mux-add-datagpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nslabeldefault-state