v8o(,onovatech,am335x-lxmti,am33xx&7NovaTech OrionLXmchosenaliases=/ocp/i2c@44e0b000B/ocp/i2c@4802a000G/ocp/i2c@4819c000L/ocp/serial@44e09000T/ocp/serial@48022000\/ocp/serial@48024000d/ocp/serial@481a6000l/ocp/serial@481a8000t/ocp/serial@481aa000|/ocp/can@481cc000/ocp/can@481d0000/ocp/usb@47400000/usb@47401000/ocp/usb@47400000/usb@47401800#/ocp/usb@47400000/usb-phy@47401300#/ocp/usb@47400000/usb-phy@47401b00&/ocp/ethernet@4a100000/slave@4a100200&/ocp/ethernet@4a100000/slave@4a100300memorymemory cpuscpu@0arm,cortex-a8cpu  '( *28*cpupmuarm,cortex-a8-pmusocti,omap-inframpu ti,omap3-mpumpuocp simple-bus'l3_mainl4_wkup@44c00000ti,am3-l4-wkupsimple-bus 'D(prcm@200000 ti,am3-prcm @clocksclk_32768_ck. fixed-clock;KQclk_rc32k_ck. fixed-clock;}KQvirt_19200000_ck. fixed-clock;$K Q virt_24000000_ck. fixed-clock;n6K!Q!virt_25000000_ck. fixed-clock;}x@K"Q"virt_26000000_ck. fixed-clock;K#Q#tclkin_ck. fixed-clock;KQdpll_core_ck.ti,am3-dpll-core-clock \hKQdpll_core_x2_ck.ti,am3-dpll-x2-clockKQdpll_core_m4_ck.ti,divider-clockYdKQdpll_core_m5_ck.ti,divider-clockYdKQdpll_core_m6_ck.ti,divider-clockYddpll_mpu_ck.ti,am3-dpll-clock  ,KQdpll_mpu_m2_ck.ti,divider-clockYddpll_ddr_ck.ti,am3-dpll-no-gate-clock 4@KQdpll_ddr_m2_ck.ti,divider-clockYdKQdpll_ddr_m2_div2_ck.fixed-factor-clock{dpll_disp_ck.ti,am3-dpll-no-gate-clock HTK Q dpll_disp_m2_ck.ti,divider-clock YdKQdpll_per_ck.!ti,am3-dpll-no-gate-j-type-clock pK Q dpll_per_m2_ck.ti,divider-clock YdK Q dpll_per_m2_div4_wkupdm_ck.fixed-factor-clock {dpll_per_m2_div4_ck.fixed-factor-clock {cefuse_fck.ti,gate-clock clk_24mhz.fixed-factor-clock {K Q clkdiv32k_ck.fixed-factor-clock {K Q clkdiv32k_ick.ti,gate-clock LKQl3_gclk.fixed-factor-clock{KQpruss_ocp_gclk. ti,mux-clock0mmu_fck.ti,gate-clock timer1_fck. ti,mux-clock(timer2_fck. ti,mux-clock timer3_fck. ti,mux-clock  timer4_fck. ti,mux-clock timer5_fck. ti,mux-clock timer6_fck. ti,mux-clock timer7_fck. ti,mux-clock usbotg_fck.ti,gate-clock |dpll_core_m4_div2_ck.fixed-factor-clock{KQieee5000_fck.ti,gate-clockwdt1_fck. ti,mux-clock8l4_rtc_gclk.fixed-factor-clock{l4hs_gclk.fixed-factor-clock{l3s_gclk.fixed-factor-clock{l4fw_gclk.fixed-factor-clock{l4ls_gclk.fixed-factor-clock{K$Q$sysclk_div_ck.fixed-factor-clock{cpsw_125mhz_gclk.fixed-factor-clock{K3Q3cpsw_cpts_rft_clk. ti,mux-clock K4Q4gpio0_dbclk_mux_ck. ti,mux-clock <KQgpio0_dbclk.ti,gate-clockgpio1_dbclk.ti,gate-clockgpio2_dbclk.ti,gate-clockgpio3_dbclk.ti,gate-clocklcd_gclk. ti,mux-clock  4KQmmc_clk.fixed-factor-clock {gfx_fclk_clksel_ck. ti,mux-clock ,KQgfx_fck_div_ck.ti,divider-clock,Ysysclkout_pre_ck. ti,mux-clock KQclkout2_div_ck.ti,divider-clockYKQdbg_sysclk_ck.ti,gate-clockKQdbg_clka_ck.ti,gate-clockKQstm_pmd_clock_mux_ck. ti,mux-clockKQtrace_pmd_clk_mux_ck. ti,mux-clockKQstm_clk_div_ck.ti,divider-clockY@trace_clk_div_ck.ti,divider-clockY@clkout2_ck.ti,gate-clockclockdomainsclk_24mhz_clkdmti,clockdomainscm@210000ti,am3-scmsimple-bus!  '! pinmux@800pinctrl-single8 pinmux_mmc1_pins0000000K)Q)pinmux_i2c0_pins((K'Q'cpsw_defaultd' !!$(<!@!D @PTh#l#p#t#x'!K5Q5cpsw_sleepd' '''$'('<'@'D'@'P'T'h'l'p't'x''K6Q6davinci_mdio_defaultH0LK7Q7davinci_mdio_sleepH'L'K8Q8pinmux_emmc_pinsP22111 11111K+Q+pinmux_uart0_pinsp0tK&Q&scm_conf@0sysconK-Q-clockssys_clkin_ck. ti,mux-clock !"#@KQadc_tsc_fck.fixed-factor-clock{dcan0_fck.fixed-factor-clock{K,Q,dcan1_fck.fixed-factor-clock{K.Q.mcasp0_fck.fixed-factor-clock{mcasp1_fck.fixed-factor-clock{smartreflex0_fck.fixed-factor-clock{smartreflex1_fck.fixed-factor-clock{sha0_fck.fixed-factor-clock{aes0_fck.fixed-factor-clock{rng_fck.fixed-factor-clock{ehrpwm0_tbclk@44e10664.ti,gate-clock$dehrpwm1_tbclk@44e10664.ti,gate-clock$dehrpwm2_tbclk@44e10664.ti,gate-clock$dclockdomainsinterrupt-controller@48200000ti,am33xx-intc*H KQedma@49000000 ti,edma3tpcctptc0tptc1tptc2ID@  ;K%Q%gpio@44e07000ti,omap4-gpiogpio1FV*Dp`gpio@4804c000ti,omap4-gpiogpio2FV*Hbgpio@481ac000ti,omap4-gpiogpio3FV*H gpio@481ae000ti,omap4-gpiogpio4FV*H>serial@44e09000ti,omap3-uartuart1;lD Hbokayi%%ntxrxxdefault&serial@48022000ti,omap3-uartuart2;lH I bdisabledi%%ntxrxserial@48024000ti,omap3-uartuart3;lH@ J bdisabledi%%ntxrxserial@481a6000ti,omap3-uartuart4;lH` , bdisabledserial@481a8000ti,omap3-uartuart5;lH - bdisabledserial@481aa000ti,omap3-uartuart6;lH . bdisabledi2c@44e0b000 ti,omap4-i2ci2c1DFbokayxdefault';serial_config1@20 nxp,pca9539 serial_config2@21 nxp,pca9539!tps@2d ti,tps65910-((((((((regulatorsregulator@0vrtcregulator@1vio vio_1v5,ddr`-`EWregulator@2vdd1 vdd1,mpu '-`EWKQregulator@3vdd2vdd2_1v1,core-EWregulator@4vdd3regulator@5vdig1regulator@6vdig2vdig2_1v8,vdds_pllw@-w@EWregulator@7vpllregulator@8vdacvdac_1v8,vddsw@-w@EWregulator@9 vaux1vaux1_1v8,usbw@-w@EWregulator@10 vaux2 vaux2_3v3,io2Z-2ZEWregulator@11 vaux33vaux33_3v3,usb2Z-2ZEWregulator@12 vmmc vmmc_3v3,io2Z-2ZEWregulator@13 vbbi2c@4802a000 ti,omap4-i2ci2c2HG bdisabledi2c@4819c000 ti,omap4-i2ci2c3H bdisabledmmc@48060000ti,omap4-hsmmcmmc1kxi%%ntxrx@&Hbokayxdefault)*mmc@481d8000ti,omap4-hsmmcmmc2xi%%ntxrx&Hbokayxdefault+*mmc@47810000ti,omap4-hsmmcmmc3x&G bdisabledspinlock@480ca000ti,omap4-hwspinlockH  spinlockwdt@44e35000 ti,omap3-wdt wd_timer2DP[can@481cc000ti,am3352-d_cand_can0H ,fck -D4 bdisabledcan@481d0000ti,am3352-d_cand_can1H .fck -D7 bdisabledmailbox@480C8000ti,omap4-mailboxH Mmailboxwkup_m3   +timer@44e31000ti,am335x-timer-1msDCtimer16timer@48040000ti,am335x-timerHDtimer2timer@48042000ti,am335x-timerH Etimer3timer@48044000ti,am335x-timerH@\timer4Etimer@48046000ti,am335x-timerH`]timer5Etimer@48048000ti,am335x-timerH^timer6Etimer@4804a000ti,am335x-timerH_timer7Ertc@44e3e000ti,am3352-rtcti,da830-rtcDKLrtcspi@48030000ti,omap4-mcspiHARspi0 i%%%%ntx0rx0tx1rx1 bdisabledspi@481a0000ti,omap4-mcspiH}Rspi1 i%*%+%,%-ntx0rx0tx1rx1 bdisabledusb@47400000ti,am33xx-usbG@' usb_otg_hsbokaycontrol@44e10620ti,am335x-usb-ctrl-moduleD DH`phy_ctrlwakeupbokayK/Q/usb-phy@47401300ti,am335x-usb-phyG@`phybokayj/K0Q0usb@47401000ti,musb-am33xxbokayG@G@ `mccontrolvmchost 0hi1111111111 1 1 1 1 11111111111 1 1 1 1 1nrx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15usb-phy@47401b00ti,am335x-usb-phyG@`phybokayj/K2Q2usb@47401800ti,musb-am33xxbokayG@G@ `mccontrolvmchost 2hi111111111111111111111111111111nrx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15dma-controller@47402000ti,am3359-cppi41 G@G@ G@0G@@@#`gluecontrollerschedulerqueuemgrvglue;bokayK1Q1epwmss@48300000ti,am33xx-pwmssH0epwmss0 bdisabled$'H0H0H0H0H0H0ecap@48300100ti,am33xx-ecapH0vecap0ecap0 bdisabledehrpwm@48300200ti,am33xx-ehrpwmH0ehrpwm0 bdisabledepwmss@48302000ti,am33xx-pwmssH0 epwmss1 bdisabled$'H0!H0!H0!H0!H0"H0"ecap@48302100ti,am33xx-ecapH0!/vecap1ecap1 bdisabledehrpwm@48302200ti,am33xx-ehrpwmH0"ehrpwm1 bdisabledepwmss@48304000ti,am33xx-pwmssH0@epwmss2 bdisabled$'H0AH0AH0AH0AH0BH0Becap@48304100ti,am33xx-ecapH0A=vecap2ecap2 bdisabledehrpwm@48304200ti,am33xx-ehrpwmH0Behrpwm2 bdisabledethernet@4a100000ti,cpswcpgmac034 fckcpts )@2 >ERbJJ&()*+'s-bokayxdefaultsleep5z6mdio@4a101000ti,davinci_mdio davinci_mdioB@Jbokayxdefaultsleep7z8K9Q9slave@4a1002009rmiislave@4a1003009rmiicpsw-phy-sel@44e10650ti,am3352-cpsw-phy-selDP `gmii-selocmcram@40300000 mmio-sram@0wkup_m3@44d00000ti,am3353-wkup-m3D@D wkup_m3elm@48080000ti,am3352-elmH elm bdisabledlcdc@4830e000ti,am33xx-tilcdcH0&$lcdc bdisabledtscadc@44e0d000ti,am3359-tscadcD&adc_tsc bdisabledtscti,am3359-tscadcti,am3359-adcgpmc@50000000ti,am3352-gpmcgpmcP d bdisabledsham@53100000ti,omap4-shamshamSmi%$nrxbokayaes@53500000 ti,omap4-aesaesSPgi%%ntxrxbokaymcasp@48038000ti,am33xx-mcasp-audiomcasp0H F@`mpudatPQvtxrx bdisabledi%% ntxrxmcasp@4803C000ti,am33xx-mcasp-audiomcasp1H F@@`mpudatRSvtxrx bdisabledi% % ntxrxrng@48310000 ti,omap4-rngrngH1 ofixedregulator@0regulator-fixedvbatLK@-LK@EK(Q(fixedregulator@1regulator-fixed vmmcsd_fixed2Z-2ZEK*Q* #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1device_typeregoperating-pointsvoltage-toleranceclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shiftti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsinterrupt-controller#interrupt-cells#dma-cellsgpio-controller#gpio-cellsstatusdmasdma-namespinctrl-namespinctrl-0vcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onti,dual-voltti,needs-special-resetti,needs-special-hs-handlingvmmc-supplybus-widthti,non-removable#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csreg-namesti,ctrl_modinterrupt-namesdr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsysconpinctrl-1dual_emacbus_freqmac-addressphy_idphy-modedual_emac_res_vlanrmii-clock-extti,no-reset-on-init#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpins