E8B(B,CSQ CS908 top set box2csq,cs908allwinner,sun6i-a31schosen=framebuffer@002allwinner,simple-framebuffersimple-framebufferDde_be0-lcd0-hdmiW ^disabledframebuffer@102allwinner,simple-framebuffersimple-framebuffer Dde_be0-lcd0W ^disabledaliases e/soc@01c00000/ethernet@01c30000memoryomemory{@timer2arm,armv7-timer0   n6cpusallwinner,sun6i-a31cpu@02arm,cortex-a7ocpu{cpu@12arm,cortex-a7ocpu{cpu@22arm,cortex-a7ocpu{cpu@32arm,cortex-a7ocpu{pmu%2arm,cortex-a7-pmuarm,cortex-a15-pmu0xyz{clocks=osc24M 2fixed-clockn6clk@0 2fixed-clockosc32kclk@01c200002allwinner,sun6i-a31-pll1-clk{Wpll1clk@01c200282allwinner,sun6i-a31-pll6-clk{(W pll6pll6x2cpu@01c200502allwinner,sun4i-a10-cpu-clk{PWcpuaxi@01c200502allwinner,sun4i-a10-axi-clk{PWaxiahb1@01c200542allwinner,sun6i-a31-ahb1-clk{TWahb1clk@01c20060#2allwinner,sun6i-a31-ahb1-gates-clk{`Wzahb1_mipidsiahb1_ssahb1_dmaahb1_mmc0ahb1_mmc1ahb1_mmc2ahb1_mmc3ahb1_nand1ahb1_nand0ahb1_sdramahb1_gmacahb1_tsahb1_hstimerahb1_spi0ahb1_spi1ahb1_spi2ahb1_spi3ahb1_otgahb1_ehci0ahb1_ehci1ahb1_ohci0ahb1_ohci1ahb1_ohci2ahb1_veahb1_lcd0ahb1_lcd1ahb1_csiahb1_hdmiahb1_de0ahb1_de1ahb1_fe0ahb1_fe1ahb1_mpahb1_gpuahb1_deu0ahb1_deu1ahb1_drc0ahb1_drc1  apb1@01c200542allwinner,sun4i-a10-apb0-clk{TWapb1  clk@01c20068#2allwinner,sun6i-a31-apb1-gates-clk{hW ?apb1_codecapb1_digital_micapb1_pioapb1_daudio0apb1_daudio1clk@01c200582allwinner,sun4i-a10-apb1-clk{XWapb2  clk@01c2006c#2allwinner,sun6i-a31-apb2-gates-clk{lW japb2_i2c0apb2_i2c1apb2_i2c2apb2_i2c3apb2_uart0apb2_uart1apb2_uart2apb2_uart3apb2_uart4apb2_uart5clk@01c200882allwinner,sun4i-a10-mmc-clk{ Wmmc0mmc0_outputmmc0_sampleclk@01c2008c2allwinner,sun4i-a10-mmc-clk{ Wmmc1mmc1_outputmmc1_sampleclk@01c200902allwinner,sun4i-a10-mmc-clk{ Wmmc2mmc2_outputmmc2_sampleclk@01c200942allwinner,sun4i-a10-mmc-clk{ Wmmc3mmc3_outputmmc3_sampleclk@01c200a02allwinner,sun4i-a10-mod0-clk{ Wspi0clk@01c200a42allwinner,sun4i-a10-mod0-clk{ Wspi1clk@01c200a82allwinner,sun4i-a10-mod0-clk{ Wspi2clk@01c200ac2allwinner,sun4i-a10-mod0-clk{ Wspi3  clk@01c200cc2allwinner,sun6i-a31-usb-clk{W9usb_phy0usb_phy1usb_phy2usb_ohci0usb_ohci1usb_ohci2clk@1 2fixed-clock}x@ mii_phy_tx  clk@2 2fixed-clocksY@ gmac_int_tx  clk@01c200d02allwinner,sun7i-a20-gmac-clk{W gmac_txsoc@01c00000 2simple-bus=dma-controller@01c020002allwinner,sun6i-a31-dma{  2W )mmc@01c0f0002allwinner,sun5i-a13-mmc{ W @ahbmmcoutputsampleLahb < ^disabledmmc@01c100002allwinner,sun5i-a13-mmc{ W @ahbmmcoutputsample Lahb = ^disabledmmc@01c110002allwinner,sun5i-a13-mmc{ W @ahbmmcoutputsample Lahb > ^disabledmmc@01c120002allwinner,sun5i-a13-mmc{  W @ahbmmcoutputsample Lahb ? ^disabledphy@01c194002allwinner,sun6i-a31-usb-phy{Xphy_ctrlpmu1pmu2W  @usb0_phyusb1_phyusb2_phy!Lusb0_resetusb1_resetusb2_reset^okaybusb@01c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci{ HW mrusb^okayusb@01c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci{ IW mrusb ^disabledusb@01c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci{ JW mrusb^okayusb@01c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci{ KW mrusb^okayusb@01c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci{ MW  ^disabledpinctrl@01c208002allwinner,sun6i-a31s-pinctrl{0 W|uart0@0 PH20PH21uart0i2c0@0 PH14PH15i2c0i2c1@0 PH16PH17i2c1i2c2@0 PH18PH19i2c2mmc0@0PF0PF1PF2PF3PF4PF5mmc0gmac_mii@0TPA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27gmacgmac_gmii@0PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27gmacgmac_rgmii@0FPA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27gmacusb1_vbus_pin@0PC27 gpio_outreset@01c202c02allwinner,sun6i-a31-ahb1-reset{ reset@01c202d0 2allwinner,sun6i-a31-clock-reset{reset@01c202d8 2allwinner,sun6i-a31-clock-reset{timer@01c20c002allwinner,sun4i-a10-timer{ <Wwatchdog@01c20ca02allwinner,sun6i-a31-wdt{ rtp@01c250002allwinner,sun6i-a31-ts{P serial@01c280002snps,dw-apb-uart{€ W,1rxtx^okay;defaultIserial@01c284002snps,dw-apb-uart{„ W,1rxtx ^disabledserial@01c288002snps,dw-apb-uart{ˆ W,1rxtx ^disabledserial@01c28c002snps,dw-apb-uart{Œ W,  1rxtx ^disabledserial@01c290002snps,dw-apb-uart{ W,  1rxtx ^disabledserial@01c294002snps,dw-apb-uart{” W,1rxtx ^disabledi2c@01c2ac002allwinner,sun6i-a31-i2c{¬ W ^disabledi2c@01c2b0002allwinner,sun6i-a31-i2c{° W ^disabledi2c@01c2b4002allwinner,sun6i-a31-i2c{´ W ^disabledi2c@01c2b8002allwinner,sun6i-a31-i2c{¸  W ^disabledethernet@01c300002allwinner,sun7i-a20-gmac{T RSmacirq W @stmmacethallwinner_gmac_tx Lstmmacethcl}^okay;defaultImiiethernet-phy@1{timer@01c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer{03456W spi@01c680002allwinner,sun6i-a31-spi{ƀ A W @ahbmod,1rxtx ^disabledspi@01c690002allwinner,sun6i-a31-spi{Ɛ B W @ahbmod,1rxtx ^disabledspi@01c6a0002allwinner,sun6i-a31-spi{Ơ C W @ahbmod,1rxtx ^disabledspi@01c6b0002allwinner,sun6i-a31-spi{ư D W  @ahbmod,1rxtx ^disabledinterrupt-controller@01c81000%2arm,cortex-a7-gicarm,cortex-a15-gic { @ `   rtc@01f000002allwinner,sun6i-a31-rtc{T()interrupt-controller@01f00c0c2allwinner,sun6i-a31-sc-nmi{ 8  prcm@01f014002allwinner,sun6i-a31-prcm{ar100_clk2allwinner,sun6i-a31-ar100-clkWar100!!ahb0_clk2fixed-factor-clockW!ahb0""apb0_clk2allwinner,sun6i-a31-apb0-clkW"apb0##apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clkW#Dapb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c$$ir_clk2allwinner,sun4i-a10-mod0-clkWir%%apb0_rst 2allwinner,sun6i-a31-clock-reset&&cpucfg@01f01c002allwinner,sun6i-a31-cpuconfig{ir@01f020002allwinner,sun5i-a13-ir W$%@apbir& %{ @^okay;defaultI'pinctrl@01f02c002allwinner,sun6i-a31-r-pinctrl{,-.W$&|ir@0PL4s_ir'' #address-cells#size-cellsinterrupt-parentmodelcompatiblerangesallwinner,pipelineclocksstatusethernet0device_typereginterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-method#clock-cellslinux,phandleclock-output-names#reset-cellsresets#dma-cellsassigned-clocksassigned-clock-parentsclock-namesreset-namesreg-names#phy-cellsphysphy-namesgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellsallwinner,pinsallwinner,functionallwinner,driveallwinner,pull#thermal-sensor-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0interrupt-namessnps,pblsnps,fixed-burstsnps,force_sf_dma_modephyphy-modeclock-divclock-mult