K8H(,Hl),Allwinner A31 APP4 EVB1 Evaluation Board(2allwinner,app4-evb1allwinner,sun6i-a31chosen=!Dearlyprintk console=ttyS0,115200framebuffer@002allwinner,simple-framebuffersimple-framebufferMde_be0-lcd0-hdmi` gdisabledframebuffer@102allwinner,simple-framebuffersimple-framebuffer Mde_be0-lcd0` gdisabledaliases n/soc@01c00000/ethernet@01c30000memoryxmemory@timer2arm,armv7-timer0   n6cpusallwinner,sun6i-a31cpu@02arm,cortex-a7xcpucpu@12arm,cortex-a7xcpucpu@22arm,cortex-a7xcpucpu@32arm,cortex-a7xcpupmu%2arm,cortex-a7-pmuarm,cortex-a15-pmu0xyz{clocks=osc24M 2fixed-clockn6clk@0 2fixed-clockosc32kclk@01c200002allwinner,sun6i-a31-pll1-clk`pll1clk@01c200282allwinner,sun6i-a31-pll6-clk(` pll6pll6x2cpu@01c200502allwinner,sun4i-a10-cpu-clkP`cpuaxi@01c200502allwinner,sun4i-a10-axi-clkP`axiahb1@01c200542allwinner,sun6i-a31-ahb1-clkT`ahb1clk@01c20060#2allwinner,sun6i-a31-ahb1-gates-clk``zahb1_mipidsiahb1_ssahb1_dmaahb1_mmc0ahb1_mmc1ahb1_mmc2ahb1_mmc3ahb1_nand1ahb1_nand0ahb1_sdramahb1_gmacahb1_tsahb1_hstimerahb1_spi0ahb1_spi1ahb1_spi2ahb1_spi3ahb1_otgahb1_ehci0ahb1_ehci1ahb1_ohci0ahb1_ohci1ahb1_ohci2ahb1_veahb1_lcd0ahb1_lcd1ahb1_csiahb1_hdmiahb1_de0ahb1_de1ahb1_fe0ahb1_fe1ahb1_mpahb1_gpuahb1_deu0ahb1_deu1ahb1_drc0ahb1_drc1  apb1@01c200542allwinner,sun4i-a10-apb0-clkT`apb1  clk@01c20068#2allwinner,sun6i-a31-apb1-gates-clkh` ?apb1_codecapb1_digital_micapb1_pioapb1_daudio0apb1_daudio1clk@01c200582allwinner,sun4i-a10-apb1-clkX`apb2  clk@01c2006c#2allwinner,sun6i-a31-apb2-gates-clkl` japb2_i2c0apb2_i2c1apb2_i2c2apb2_i2c3apb2_uart0apb2_uart1apb2_uart2apb2_uart3apb2_uart4apb2_uart5clk@01c200882allwinner,sun4i-a10-mmc-clk `mmc0mmc0_outputmmc0_sampleclk@01c2008c2allwinner,sun4i-a10-mmc-clk `mmc1mmc1_outputmmc1_sampleclk@01c200902allwinner,sun4i-a10-mmc-clk `mmc2mmc2_outputmmc2_sampleclk@01c200942allwinner,sun4i-a10-mmc-clk `mmc3mmc3_outputmmc3_sampleclk@01c200a02allwinner,sun4i-a10-mod0-clk `spi0clk@01c200a42allwinner,sun4i-a10-mod0-clk `spi1clk@01c200a82allwinner,sun4i-a10-mod0-clk `spi2clk@01c200ac2allwinner,sun4i-a10-mod0-clk `spi3clk@01c200cc2allwinner,sun6i-a31-usb-clk`9usb_phy0usb_phy1usb_phy2usb_ohci0usb_ohci1usb_ohci2clk@1 2fixed-clock}x@ mii_phy_tx  clk@2 2fixed-clocksY@ gmac_int_tx  clk@01c200d02allwinner,sun7i-a20-gmac-clk` gmac_txsoc@01c00000 2simple-bus=dma-controller@01c020002allwinner,sun6i-a31-dma  2` "2mmc@01c0f0002allwinner,sun5i-a13-mmc ` IahbmmcoutputsampleUahb < gdisabledmmc@01c100002allwinner,sun5i-a13-mmc ` Iahbmmcoutputsample Uahb = gdisabledmmc@01c110002allwinner,sun5i-a13-mmc ` Iahbmmcoutputsample Uahb > gdisabledmmc@01c120002allwinner,sun5i-a13-mmc  ` Iahbmmcoutputsample Uahb ? gdisabledphy@01c194002allwinner,sun6i-a31-usb-phyaphy_ctrlpmu1pmu2`  Iusb0_phyusb1_phyusb2_phy!Uusb0_resetusb1_resetusb2_resetgokaykvusb@01c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci H` usbgokayusb@01c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci I` usb gdisabledusb@01c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci J` usb gdisabledusb@01c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci K` usb gdisabledusb@01c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci M`  gdisabledpinctrl@01c208002allwinner,sun6i-a31-pinctrl0 `''uart0@0 PH20PH21uart0 i2c0@0 PH14PH15i2c0 i2c1@0 PH16PH17i2c1 i2c2@0 PH18PH19i2c2 mmc0@0PF0PF1PF2PF3PF4PF5mmc0 gmac_mii@0TPA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27gmac gmac_gmii@0PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27gmac gmac_rgmii@0FPA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27gmac ahci_pwr_pin@0PB8 gpio_out &&usb0_vbus_pin@0PB9 gpio_out ((usb1_vbus_pin@0PH27 gpio_out ))usb2_vbus_pin@0PH3 gpio_out **reset@01c202c02allwinner,sun6i-a31-ahb1-reset reset@01c202d0 2allwinner,sun6i-a31-clock-resetreset@01c202d8 2allwinner,sun6i-a31-clock-resettimer@01c20c002allwinner,sun4i-a10-timer <`watchdog@01c20ca02allwinner,sun6i-a31-wdt rtp@01c250002allwinner,sun6i-a31-tsP serial@01c280002snps,dw-apb-uart€ /9`FKrxtxgokayUdefaultcserial@01c284002snps,dw-apb-uart„ /9`FKrxtx gdisabledserial@01c288002snps,dw-apb-uartˆ /9`FKrxtx gdisabledserial@01c28c002snps,dw-apb-uartŒ /9`F  Krxtx gdisabledserial@01c290002snps,dw-apb-uart /9`F  Krxtx gdisabledserial@01c294002snps,dw-apb-uart” /9`FKrxtx gdisabledi2c@01c2ac002allwinner,sun6i-a31-i2c¬ ` gdisabledi2c@01c2b0002allwinner,sun6i-a31-i2c° ` gdisabledi2c@01c2b4002allwinner,sun6i-a31-i2c´ ` gdisabledi2c@01c2b8002allwinner,sun6i-a31-i2c¸ ` gdisabledethernet@01c300002allwinner,sun7i-a20-gmacT Rmmacirq ` Istmmacethallwinner_gmac_tx Ustmmaceth} gdisabledtimer@01c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer03456` spi@01c680002allwinner,sun6i-a31-spiƀ A ` IahbmodFKrxtx gdisabledspi@01c690002allwinner,sun6i-a31-spiƐ B ` IahbmodFKrxtx gdisabledspi@01c6a0002allwinner,sun6i-a31-spiƠ C ` IahbmodFKrxtx gdisabledspi@01c6b0002allwinner,sun6i-a31-spiư D ` IahbmodFKrxtx gdisabledinterrupt-controller@01c81000%2arm,cortex-a7-gicarm,cortex-a15-gic  @ `   rtc@01f000002allwinner,sun6i-a31-rtcT()interrupt-controller@01f00c0c2allwinner,sun6i-a31-sc-nmi 8 prcm@01f014002allwinner,sun6i-a31-prcmar100_clk2allwinner,sun6i-a31-ar100-clk`ar100  ahb0_clk2fixed-factor-clock` ahb0!!apb0_clk2allwinner,sun6i-a31-apb0-clk`!apb0""apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clk`"Dapb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c##ir_clk2allwinner,sun4i-a10-mod0-clk`ir$$apb0_rst 2allwinner,sun6i-a31-clock-reset%%cpucfg@01f01c002allwinner,sun6i-a31-cpuconfigir@01f020002allwinner,sun5i-a13-ir `#$Iapbir% % @ gdisabledpinctrl@01f02c002allwinner,sun6i-a31-r-pinctrl,-.`#%ir@0PL4s_ir ahci-5v2regulator-fixedUdefaultc&ahci-5vLK@LK@'' gdisabledusb0-vbus2regulator-fixedUdefaultc( usb0-vbusLK@LK@''  gdisabledusb1-vbus2regulator-fixedUdefaultc) usb1-vbusLK@LK@''gokayusb2-vbus2regulator-fixedUdefaultc* usb2-vbusLK@LK@'' gdisabledvcc3v02regulator-fixedvcc3v0--vcc3v32regulator-fixedvcc3v32Z2Zvcc5v02regulator-fixedvcc5v0LK@LK@ #address-cells#size-cellsinterrupt-parentmodelcompatiblerangesbootargsallwinner,pipelineclocksstatusethernet0device_typereginterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-method#clock-cellslinux,phandleclock-output-names#reset-cellsresets#dma-cellsassigned-clocksassigned-clock-parentsclock-namesreset-namesreg-names#phy-cellsusb1_vbus-supplyphysphy-namesgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellsallwinner,pinsallwinner,functionallwinner,driveallwinner,pull#thermal-sensor-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0interrupt-namessnps,pblsnps,fixed-burstsnps,force_sf_dma_modeclock-divclock-multregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpio