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Ibiuciuokayndefault |dwmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciuokayndefault |pmu@20004000,rockchip,rk3066-pmusyscon @grf@20008000,syscon   i2c@2002d000,rockchip,rk3066-i2c  ( i2cPokayndefault|ak8963@0d,asahi-kasei,ak8975 ndefault|mma8452@1d ,fsl,mma8452ndefault|i2c@2002f000,rockchip,rk3066-i2c  ) Qi2cokayndefault| tps@2d-!ndefault|"#"$.$:$F$R%^%j$v$ ,ti,tps65910regulatorsregulator@0vcc_rtcvrtcregulator@1vcc_io2Z2Zvio%%regulator@2vdd_arm '`vdd1<<regulator@3vcc_ddr '`vdd2regulator@5vcc18w@w@vdig1regulator@6vdd_11vdig2regulator@7vcc_25&%&%vpll11regulator@8 vccio_wlw@w@vdacregulator@9 vcc25_hdmi&%&% vaux1regulator@10vcca_332Z2Z vaux2regulator@11 vcc_rmii2Z2Z vaux33regulator@12 vcc28_cif** vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm F disabledndefault|&pwm@20030010,rockchip,rk2928-pwm Fokayndefault|'watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  Gokayndefault|(pwm@20050030,rockchip,rk2928-pwm 0G disabledndefault|)i2c@20056000,rockchip,rk3066-i2c ` * Ri2cokayndefault|*i2c@2005a000,rockchip,rk3066-i2c  + Si2cokayndefault|+i2c@2005e000,rockchip,rk3066-i2c  4 Ti2cokayndefault|,serial@20064000,snps,dw-apb-uart @ $Wabaudclkapb_pclkBNokayndefault|-serial@20068000,snps,dw-apb-uart  %Wabaudclkapb_pclkCOokayndefault |./0saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkokay1spi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk & &2 2 +txrxokayndefault|3456spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @&2 2 +txrx disabledndefault|789:cpus5rockchip,rk3066-smpcpu@0cpu,arm,cortex-a9C;(Tag8 s 'B@e@s<cpu@1cpu,arm,cortex-a9C;sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPi2s@10118000,rockchip,rk3066-i2s  ndefault|=&>>+txrxi2s_hclki2s_clkK disabledi2s@1011a000,rockchip,rk3066-i2s  ndefault|?&>>+txrxi2s_hclki2s_clkL disabledi2s@1011c000,rockchip,rk3066-i2s  ndefault|@&> > +txrxi2s_hclki2s_clkM disabledclock-controller@20000000,rockchip,rk3066a-cru  timer@2000e000,snps,dw-apb-timer-osc  .VD timerpclktimer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclkpinctrl,rockchip,rk3066a-pinctrl gpio0@20034000,rockchip,gpio-bank @ 6U1FJJgpio1@2003c000,rockchip,gpio-bank  7V1Fgpio2@2003e000,rockchip,gpio-bank  8W1Fgpio3@20080000,rockchip,gpio-bank  9X1FHHgpio4@20084000,rockchip,gpio-bank @ :Y1Fgpio6@2000a000,rockchip,gpio-bank  <Z1F!!pcfg_pull_defaultCCpcfg_pull_noneAAemacemac-xferAAAAAAAA  emac-mdio AA  rmii-rstB  emmcemmc-clkCemmc-cmd Cemmc-rst Ci2c0i2c0-xfer AAi2c1i2c1-xfer AA  i2c2i2c2-xfer AA**i2c3i2c3-xfer AA++i2c4i2c4-xfer AA,,pwm0pwm0-outA&&pwm1pwm1-outA''pwm2pwm2-outA((pwm3pwm3-outA))spi0spi0-clkC33spi0-cs0C66spi0-txC44spi0-rxC55spi0-cs1Cspi1spi1-clkC77spi1-cs0C::spi1-rxC99spi1-txC88spi1-cs1Cuart0uart0-xfer CCuart0-ctsCuart0-rtsCuart1uart1-xfer CCuart1-ctsCuart1-rtsCuart2uart2-xfer C C--uart3uart3-xfer CC..uart3-ctsC//uart3-rtsC00sd0sd0-clkCsd0-cmd Csd0-cdCsd0-wpCsd0-bus-width1 Csd0-bus-width4@ C C C Csd1sd1-clkCsd1-cmdCsd1-cdCsd1-wpCsd1-bus-width1Csd1-bus-width4@CCCCi2s0i2s0-busCC C C C C CCC==i2s1i2s1-bus`CCCCCC??i2s2i2s2-bus`CCCCCC@@pcfg-output-highBBak8963comp-intCirir-intCDDkeyspwr-keyCEEmma8452gsensor-intCmmcsdmmc-pwrCIIusb_hosthost-drvCKKhub-rstBsata-pwrCFFsata-reset Busb_otgotg-drvCLLtpspmic-intC""pwr-holdB##ir-receiver,gpio-ir-receiver !ndefault|Dgpio-keys ,gpio-keysbutton@0 ! GPIO Powertndefault|Evsys-regulator,regulator-fixedvsysLK@LK@$$5v-stdby-regulator,regulator-fixed 5v_stdbyLK@LK@GGemmc-regulator,regulator-fixed emmc_vccq-- $sata-regulator,regulator-fixed *ndefault|Fusb_5vLK@LK@ Gsdmmc-regulator,regulator-fixed *Hndefault|Ivcc_sd2Z2Z/ %usb-host-regulator,regulator-fixed *Jndefault|K host-pwrLK@LK@ Gusb-otg-regulator,regulator-fixed *Jndefault|Lvcc_otgLK@LK@ G #address-cells#size-cellsinterrupt-parentcompatiblemodeli2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfmax-speedphy-modephyphy-supplyfifo-depthbus-widthdisable-wpnum-slotsvmmc-supplybroken-cdnon-removablecap-mmc-highspeedvqmmc-supplyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplydmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencycpu0-supply#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highgpiosgpio-key,wakeuplabellinux,codevin-supplyenable-active-highgpiostartup-delay-us