HD8D(D(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066chosenaliases=/i2c@2002d000B/i2c@2002f000G/i2c@20056000L/i2c@2005a000Q/i2c@2005e000V/dwmmc@1021c000\/dwmmc@10214000b/dwmmc@10218000h/serial@10124000p/serial@10126000x/serial@20064000/serial@20068000/spi@20070000/spi@20074000memorymemory`@amba ,arm,amba-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclk--dma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclk""oscillator ,fixed-clockn6xin24ml2-cache-controller@10138000,arm,pl310-cache%++scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gic1Fserial@10124000,snps,dw-apb-uart@ "Wabaudclkapb_pclk@Lokayndefault|serial@10126000,snps,dw-apb-uart` #Wabaudclkapb_pclkAMokayndefault|usb@10180000,rockchip,rk3066-usbsnps,dwc2 otg disabledusb@101c0000 ,snps,dwc2 otg disabledethernet@10204000,rockchip,rk3066-emac @< D hclkmacrefdrmiiokayndefault | ethernet-phy@0 dwmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciu disabledndefault| dwmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciu disabledndefault|dwmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciu disabledpmu@20004000,rockchip,rk3066-pmusyscon @grf@20008000,syscon i2c@2002d000,rockchip,rk3066-i2c  (i2cP disabledndefault|i2c@2002f000,rockchip,rk3066-i2c  )Qi2cokayndefault|tps@2d- ,ti,tps65910regulatorsregulator@0!vcc_rtc0Dvrtcregulator@1!vcc_io0Dvioregulator@2!vdd_armY 'q`0Dvdd1regulator@3!vcc_ddrY 'q`0Dvdd2regulator@5 !vcc18_cif0Dvdig1regulator@6!vdd_110Dvdig2regulator@7!vcc_250Dvpllregulator@8!vcc_180Dvdacregulator@9 !vcc25_hdmi0 Dvaux1regulator@10!vcca_330 Dvaux2regulator@11 !vcc_rmii Dvaux33regulator@12 !vcc28_cif0 Dvmmcregulator@4Dvdd3regulator@13 Dvbbpwm@20030000,rockchip,rk2928-pwm F disabledndefault|pwm@20030010,rockchip,rk2928-pwm F disabledndefault|watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  G disabledndefault|pwm@20050030,rockchip,rk2928-pwm 0G disabledndefault|i2c@20056000,rockchip,rk3066-i2c ` *Ri2c disabledndefault|i2c@2005a000,rockchip,rk3066-i2c  +Si2c disabledndefault|i2c@2005e000,rockchip,rk3066-i2c  4Ti2c disabledndefault|serial@20064000,snps,dw-apb-uart @ $Wabaudclkapb_pclkBNokayndefault| serial@20068000,snps,dw-apb-uart  %Wabaudclkapb_pclkCOokayndefault|!saradc@2006c000,rockchip,saradc  GJsaradcapb_pclk disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk & " " txrx disabledndefault|#$%&spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @" " txrx disabledndefault|'()*cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a9+(ag8 s 'B@@cpu@1cpu,arm,cortex-a9+sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPi2s@10118000,rockchip,rk3066-i2s  ndefault|,--txrxi2s_hclki2s_clkK disabledi2s@1011a000,rockchip,rk3066-i2s  ndefault|.--txrxi2s_hclki2s_clkL disabledi2s@1011c000,rockchip,rk3066-i2s  ndefault|/- - txrxi2s_hclki2s_clkM disabledclock-controller@20000000,rockchip,rk3066a-cru timer@2000e000,snps,dw-apb-timer-osc  .VD timerpclktimer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclkpinctrl,rockchip,rk3066a-pinctrlgpio0@20034000,rockchip,gpio-bank @ 6U"1Fgpio1@2003c000,rockchip,gpio-bank  7V"1F  gpio2@2003e000,rockchip,gpio-bank  8W"1Fgpio3@20080000,rockchip,gpio-bank  9X"1F22gpio4@20084000,rockchip,gpio-bank @ :Y"1Fgpio6@2000a000,rockchip,gpio-bank  <Z"1Fpcfg_pull_default.11pcfg_pull_noneD00emacemac-xferQ00000000emac-mdio Q00  emmcemmc-clkQ1emmc-cmdQ 1emmc-rstQ 1i2c0i2c0-xfer Q00i2c1i2c1-xfer Q00i2c2i2c2-xfer Q00i2c3i2c3-xfer Q00i2c4i2c4-xfer Q00pwm0pwm0-outQ0pwm1pwm1-outQ0pwm2pwm2-outQ0pwm3pwm3-outQ0spi0spi0-clkQ1##spi0-cs0Q1&&spi0-txQ1$$spi0-rxQ1%%spi0-cs1Q1spi1spi1-clkQ1''spi1-cs0Q1**spi1-rxQ1))spi1-txQ1((spi1-cs1Q1uart0uart0-xfer Q11uart0-ctsQ1uart0-rtsQ1uart1uart1-xfer Q11uart1-ctsQ1uart1-rtsQ1uart2uart2-xfer Q1 1  uart3uart3-xfer Q11!!uart3-ctsQ1uart3-rtsQ1sd0sd0-clkQ1  sd0-cmdQ 1  sd0-cdQ1sd0-wpQ1sd0-bus-width1Q 1sd0-bus-width4@Q 1 1 1 1sd1sd1-clkQ1sd1-cmdQ1sd1-cdQ1sd1-wpQ1sd1-bus-width1Q1sd1-bus-width4@Q1111i2s0i2s0-busQ11 1 1 1 1 111,,i2s1i2s1-bus`Q111111..i2s2i2s2-bus`Q111111//lan8720aphy-intQ0  sdmmc-regulator,regulator-fixed !sdmmc-supplyY-q- _2duvsys-regulator,regulator-fixed!vsysYLK@qLK@ #address-cells#size-cellsinterrupt-parentcompatiblemodeli2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfmax-speedphy-modephyphy-supplyfifo-depthvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsdmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latency#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsgpiostartup-delay-usvin-supply