Π ών|8Μ(°”Qualcomm APQ8064/IFC6410"!qcom,apq8064-ifc6410qcom,apq8064,chosenaliasesmemory=memoryIcpuscpu@0 !qcom,kraitMqcom,kpss-acc-v1=cpuI[lucpu@1 !qcom,kraitMqcom,kpss-acc-v1=cpuI[lucpu@2 !qcom,kraitMqcom,kpss-acc-v1=cpuI[lucpu@3 !qcom,kraitMqcom,kpss-acc-v1=cpuI[l u l2-cache!cache~Šcpu-pmu!qcom,krait-pmu ˜ soc£ !simple-buspinctrl@800000!qcom,apq8064-pinctrlI€@ͺΊΖΫ ˜μdefaultϊ Šsdc4-gpiosŠpios*gpio63gpio64gpio65gpio66gpio67gpio68 sdc4ps_holdŠ  muxgpio78 ps_holdi2c1Š  muxgpio20gpio21 gsbi1card_detectŠmuxgpio26 gpiointerrupt-controller@2000000!qcom,msm-qgic2ΖΫI Štimer@200a000!qcom,kpss-timerqcom,msm-timer$˜I ›όΐ€/clock-controller@2088000!qcom,kpss-acc-v1I€€Šclock-controller@2098000!qcom,kpss-acc-v1I €€Šclock-controller@20a8000!qcom,kpss-acc-v1I €€Šclock-controller@20b8000!qcom,kpss-acc-v1I €€Š  regulator@2089000 !qcom,saw2I:Šregulator@2099000 !qcom,saw2I :Šregulator@20a9000 !qcom,saw2I :Šregulator@20b9000 !qcom,saw2I :Š  gsbi@12440000Dokay!qcom,gsbi-v1.0.0IDK “Riface£^i2c@12460000!qcom,i2c-qup-v1.1.1IF ˜ΒK Έ “ RcoreifaceDokay @ϊ μdefaulteeprom@52 !atmel,24c128IRh gsbi@12480000 Ddisabled!qcom,gsbi-v1.0.0IHK ”Riface£i2c@124a0000!qcom,i2c-qup-v1.1.1IJ ˜ΔK Ί ” Rcoreifacegsbi@16600000Dok!qcom,gsbi-v1.0.0I`K ™Riface£^serial@16640000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmId` ˜žK ¬ ™ RcoreifaceDokqcom,ssbi@500000 !qcom,ssbiIP qpmic-arbiterclock-controller@900000!qcom,gcc-apq8064I@†“Š  clock-controller@4000000!qcom,mmcc-apq8064I†“vsdcc-regulator!regulator-fixed  SDCC Power―)2ΰΗ)2ΰίŠdma@12402000!qcom,bam-v1.3.0I@ € ˜bK nRbam_clkσώŠdma@12182000!qcom,bam-v1.3.0I € ˜`K pRbam_clkσώŠdma@121c2000!qcom,bam-v1.3.0I € ˜_K qRbam_clkσώŠamba !arm,amba-bus£sdcc@12400000Dokay!arm,pl18xarm,primecell€I@  ˜hcmd_irqK x nRmclkapb_pclk-7ΈΨESdv‚‡txrxsdcc@12180000!arm,pl18xarm,primecell€DokayI  ˜fcmd_irqK z pRmclkapb_pclk-Sd7 q°‘v‚‡txrxμdefaultϊ šsdcc@121c0000!arm,pl18xarm,primecell€DokayI  ˜ecmd_irqK { qRmclkapb_pclk-Sd7άlv£‚‡txrxμdefaultϊ #address-cells#size-cellsmodelcompatibleinterrupt-parentdevice_typeregenable-methodnext-level-cacheqcom,accqcom,sawcache-levellinux,phandleinterruptsrangesgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinctrl-namespinctrl-0pinsfunctionbias-disableclock-frequencycpu-offsetregulatorstatusclocksclock-namesqcom,modepagesizeqcom,controller-type#clock-cells#reset-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#dma-cellsqcom,eearm,primecell-periphidinterrupt-namesbus-widthmax-frequencynon-removablecap-sd-highspeedcap-mmc-highspeedvmmc-supplydmasdma-namesno-1-8-vcd-gpiosvqmmc-supply