8l(4ti,omap5-uevmti,omap5&7TI OMAP5 uEVM boardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000 /connector@0memorymemorycpuscpu@0cpuarm,cortex-a15B@,`cpucpu@1cpuarm,cortex-a15thermal-zonescpu_thermal4Btripscpu_alertR^passivecpu_critRH^ criticalcooling-mapsmap0i ngpu_thermal4Btripsgpu_critRH^ criticalcore_thermal4Btripscore_critRH^ criticaltimerarm,armv7-timer0}   pmuarm,cortex-a15-pmu}interrupt-controller@48211000arm,cortex-a15-gic H!H! H!@ H!` socti,omap-inframpu ti,omap4-mpumpuocpti,omap4-l3-nocsimple-busl3_main_1l3_main_2l3_main_3D D0E@}  prm@4ae06000 ti,omap5-prmJ`0 } clockssys_clkin ti,mux-clock abe_dpll_bypass_clk_mux ti,mux-clockabe_dpll_clk_mux ti,mux-clock custefuse_sys_gfclk_divfixed-factor-clockdss_syc_gfclk_divfixed-factor-clock++wkupaon_iclk_mux ti,mux-clockl3instr_ts_gclk_divfixed-factor-clockgpio1_dbclkti,gate-clock8timer1_gfclk_mux ti,mux-clock@clockdomainscm_core_aon@4a004000ti,omap5-cm-core-aonJ@ clockspad_clks_src_ck fixed-clock pad_clks_ckti,gate-clock..secure_32k_clk_src_ck fixed-clock slimbus_src_clk fixed-clock slimbus_clkti,gate-clock ((sys_32k_ck fixed-clock virt_12000000_ck fixed-clock virt_13000000_ck fixed-clock ]@  virt_16800000_ck fixed-clock Y  virt_19200000_ck fixed-clock $  virt_26000000_ck fixed-clock   virt_27000000_ck fixed-clock   virt_38400000_ck fixed-clock Ixclk60mhsp1_ck fixed-clock \\xclk60mhsp2_ck fixed-clock ^^dpll_abe_ckti,omap4-dpll-m4xen-clockdpll_abe_x2_ckti,omap4-dpll-x2-clockdpll_abe_m2x2_ckti,divider-clockabe_24m_fclkfixed-factor-clock**abe_clkti,divider-clock%))abe_iclkti,divider-clock(;abe_lp_clk_divfixed-factor-clockdpll_abe_m3x2_ckti,divider-clockdpll_core_byp_mux ti,mux-clock,dpll_core_ckti,omap4-dpll-core-clock $,(dpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_h21x2_ckti,divider-clock?Pc2c_fclkfixed-factor-clock  c2c_iclkfixed-factor-clock dpll_core_h11x2_ckti,divider-clock?8dpll_core_h12x2_ckti,divider-clock?<!!dpll_core_h13x2_ckti,divider-clock?@dpll_core_h14x2_ckti,divider-clock?Daadpll_core_h22x2_ckti,divider-clock?Tdpll_core_h23x2_ckti,divider-clock?Xdpll_core_h24x2_ckti,divider-clock?\dpll_core_m2_ckti,divider-clock0dpll_core_m3x2_ckti,divider-clock433iva_dpll_hs_clk_divfixed-factor-clock!""dpll_iva_byp_mux ti,mux-clock"##dpll_iva_ckti,omap4-dpll-clock#$$dpll_iva_x2_ckti,omap4-dpll-x2-clock$%%dpll_iva_h11x2_ckti,divider-clock%?dpll_iva_h12x2_ckti,divider-clock%?mpu_dpll_hs_clk_divfixed-factor-clock!&&dpll_mpu_ckti,omap5-mpu-dpll-clock&`dlhdpll_mpu_m2_ckti,divider-clockpper_dpll_hs_clk_divfixed-factor-clockIIusb_dpll_hs_clk_divfixed-factor-clockOOl3_iclk_divti,divider-clock!%''gpu_l3_iclkfixed-factor-clock'l4_root_clk_divti,divider-clock'%slimbus1_slimbus_clkti,gate-clock( `aess_fclkti,divider-clock)(dmic_sync_mux_ck ti,mux-clock *+,8--dmic_gfclk ti,mux-clock -.(8mcasp_sync_mux_ck ti,mux-clock *+,@//mcasp_gfclk ti,mux-clock /.(@mcbsp1_sync_mux_ck ti,mux-clock *+,H00mcbsp1_gfclk ti,mux-clock 0.(Hmcbsp2_sync_mux_ck ti,mux-clock *+,P11mcbsp2_gfclk ti,mux-clock 1.(Pmcbsp3_sync_mux_ck ti,mux-clock *+,X22mcbsp3_gfclk ti,mux-clock 2.(Xtimer5_gfclk_mux ti,mux-clock+htimer6_gfclk_mux ti,mux-clock+ptimer7_gfclk_mux ti,mux-clock+xtimer8_gfclk_mux ti,mux-clock+dummy_ck fixed-clock clockdomainsscrm@4ae0a000ti,omap5-scrmJ clocksauxclk0_src_gate_ck ti,composite-no-wait-gate-clock355auxclk0_src_mux_ckti,composite-mux-clock 3466auxclk0_src_ckti,composite-clock5677auxclk0_ckti,divider-clock7DDauxclk1_src_gate_ck ti,composite-no-wait-gate-clock388auxclk1_src_mux_ckti,composite-mux-clock 3499auxclk1_src_ckti,composite-clock89::auxclk1_ckti,divider-clock:EEauxclk2_src_gate_ck ti,composite-no-wait-gate-clock3;;auxclk2_src_mux_ckti,composite-mux-clock 34<<auxclk2_src_ckti,composite-clock;<==auxclk2_ckti,divider-clock=FFauxclk3_src_gate_ck ti,composite-no-wait-gate-clock3>>auxclk3_src_mux_ckti,composite-mux-clock 34??auxclk3_src_ckti,composite-clock>?@@auxclk3_ckti,divider-clock@GGauxclk4_src_gate_ck ti,composite-no-wait-gate-clock3 AAauxclk4_src_mux_ckti,composite-mux-clock 34 BBauxclk4_src_ckti,composite-clockABCCauxclk4_ckti,divider-clockC HHauxclkreq0_ck ti,mux-clockDEFGHauxclkreq1_ck ti,mux-clockDEFGHauxclkreq2_ck ti,mux-clockDEFGHauxclkreq3_ck ti,mux-clockDEFGHclockdomainscm_core@4a008000ti,omap5-cm-coreJ0clocksdpll_per_byp_mux ti,mux-clockILJJdpll_per_ckti,omap4-dpll-clockJ@DLHKKdpll_per_x2_ckti,omap4-dpll-x2-clockKLLdpll_per_h11x2_ckti,divider-clockL?XRRdpll_per_h12x2_ckti,divider-clockL?\WWdpll_per_h14x2_ckti,divider-clockL?dbbdpll_per_m2_ckti,divider-clockKPTTdpll_per_m2x2_ckti,divider-clockLPSSdpll_per_m3x2_ckti,divider-clockLT44dpll_unipro1_ckti,omap4-dpll-clock MMdpll_unipro1_clkdcoldofixed-factor-clockMYYdpll_unipro1_m2_ckti,divider-clockMZZdpll_unipro2_ckti,omap4-dpll-clockNNdpll_unipro2_clkdcoldofixed-factor-clockNdpll_unipro2_m2_ckti,divider-clockNdpll_usb_byp_mux ti,mux-clockOPPdpll_usb_ckti,omap4-dpll-j-type-clockPQQdpll_usb_clkdcoldofixed-factor-clockQ``dpll_usb_m2_ckti,divider-clockQUUfunc_128m_clkfixed-factor-clockRccfunc_12m_fclkfixed-factor-clockSfunc_24m_clkfixed-factor-clockT,,func_48m_fclkfixed-factor-clockSVVfunc_96m_fclkfixed-factor-clockSXXl3init_60m_fclkti,divider-clockU;[[dss_32khz_clkti,gate-clock  dss_48mhz_clkti,gate-clockV  dss_dss_clkti,gate-clockW Gdss_sys_clkti,gate-clock+  gpio2_dbclkti,gate-clock`gpio3_dbclkti,gate-clockhgpio4_dbclkti,gate-clockpgpio5_dbclkti,gate-clockxgpio6_dbclkti,gate-clockgpio7_dbclkti,gate-clockgpio8_dbclkti,gate-clockiss_ctrlclkti,gate-clockX lli_txphy_clkti,gate-clockY lli_txphy_ls_clkti,gate-clockZ  mmc1_32khz_clkti,gate-clock(sata_ref_clkti,gate-clockusb_host_hs_hsic480m_p1_clkti,gate-clockU Xusb_host_hs_hsic480m_p2_clkti,gate-clockUXusb_host_hs_hsic480m_p3_clkti,gate-clockUXusb_host_hs_hsic60m_p1_clkti,gate-clock[ Xusb_host_hs_hsic60m_p2_clkti,gate-clock[ Xusb_host_hs_hsic60m_p3_clkti,gate-clock[Xutmi_p1_gfclk ti,mux-clock[\X]]usb_host_hs_utmi_p1_clkti,gate-clock]Xutmi_p2_gfclk ti,mux-clock[^X__usb_host_hs_utmi_p2_clkti,gate-clock_ Xusb_host_hs_utmi_p3_clkti,gate-clock[ Xusb_otg_ss_refclk960mti,gate-clock`usb_phy_cm_clk32kti,gate-clock@usb_tll_hs_usb_ch0_clkti,gate-clock[husb_tll_hs_usb_ch1_clkti,gate-clock[ husb_tll_hs_usb_ch2_clkti,gate-clock[ hfdif_fclkti,divider-clockR(gpu_core_gclk_mux ti,mux-clockab gpu_hyd_gclk_mux ti,mux-clockab hsi_fclkti,divider-clockS8mmc1_fclk_mux ti,mux-clockcS(ddmmc1_fclkti,divider-clockd(mmc2_fclk_mux ti,mux-clockcS0eemmc2_fclkti,divider-clocke0timer10_gfclk_mux ti,mux-clock(timer11_gfclk_mux ti,mux-clock0timer2_gfclk_mux ti,mux-clock8timer3_gfclk_mux ti,mux-clock@timer4_gfclk_mux ti,mux-clockHtimer9_gfclk_mux ti,mux-clockPclockdomainsl3init_clkdmti,clockdomainQcounter@4ae04000ti,omap-counter32kJ@@ counter_32kpinmux@4a002840 ti,omap5-padconfpinctrl-singleJ(@Zxdefaultfgpinmux_twl6040_pins~llpinmux_mcpdm_pins(B\^`b||pinmux_mcbsp1_pins LN PR }}pinmux_mcbsp2_pins TVXZ~~pinmux_i2c1_pinsjjpinmux_i2c5_pinsqqpinmux_mcspi2_pins sspinmux_mcspi3_pins xz|~ttpinmux_mcspi4_pins dhjluupinmux_usbhost_pins0pnffpinmux_led_gpio_pinsggpinmux_uart1_pins `bdfvvpinmux_uart3_pinswwpinmux_uart5_pins prtvxxpinmux_dss_hdmi_pinspinmux_tpd12s015_pinspinmux@4ae0c840 ti,omap5-padconfpinctrl-singleJ@8Zxdefaulthpinmux_usbhost_wkup_pinshhtisyscon@4a002da0sysconJ-iipbias_regulatorti,pbias-omap`ipbias_mmc_omap5pbias_mmc_omap5w@-yyocmcram@40300000 mmio-sram@0dma-controller@4a056000ti,omap4430-sdmaJ`0}   rrgpio@4ae10000ti,omap4-gpioJ }gpio1,>Ngpio@48055000ti,omap4-gpioHP }gpio2>Ngpio@48057000ti,omap4-gpioHp }gpio3>Ngpio@48059000ti,omap4-gpioH } gpio4>Ngpio@4805b000ti,omap4-gpioH }!gpio5>Nmmgpio@4805d000ti,omap4-gpioH }"gpio6>Ngpio@48051000ti,omap4-gpioH }#gpio7>Ngpio@48053000ti,omap4-gpioH0 }ygpio8>Ngpmc@50000000ti,omap4430-gpmcP }Zfgpmc'fcki2c@48070000 ti,omap4-i2cH }8i2c1defaultj palmas@48 ti,palmas }&Hxkkpalmas_usbti,palmas-usb-vidpalmas_clk32k@1ti,palmas-clk32kgaudiopppalmas_pmicti,palmas-pmic&k} short-irqregulatorssmps123smps123 '`smps45smps45 '0smps6smps6OOsmps7smps7w@w@nnsmps8smps8 '0smps9smps9  oosmps10_out2 smps10_out2LK@LK@smps10_out1 smps10_out1LK@LK@ldo1ldo1`w@ldo2ldo2** !disabledldo3ldo3`` !disabledldo4ldo4`w@ldo5ldo5w@w@ldo6ldo6OOldo7ldo7 !disabledldo8ldo8-- !disabledldo9ldo9w@-zzldolnldolnw@w@ldousbldousb1P1Pregen3regen3twl@4b ti,twl6040Kdefaultl }w& (m 9nDoPpclk32ki2c@48072000 ti,omap4-i2cH  }9i2c2i2c@48060000 ti,omap4-i2cH }=i2c3i2c@4807a000 ti,omap4-i2cH }>i2c4i2c@4807c000 ti,omap4-i2cH }<i2c5defaultq gpio@22 ti,tca6424">Nspinlock@4a0f6000ti,omap4-hwspinlockJ` spinlockcspi@48098000ti,omap4-mcspiH  }Amcspi1q@r#r$r%r&r'r(r)r* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap4-mcspiH  }Bmcspi2q r+r,r-r.tx0rx0tx1rx1defaultsspi@480b8000ti,omap4-mcspiH  }[mcspi3qrrtx0rx0defaulttspi@480ba000ti,omap4-mcspiH  }0mcspi4qrFrGtx0rx0defaultuserial@4806a000ti,omap4-uartHHuart1 ldefaultvserial@4806c000ti,omap4-uartHIuart2 lserial@48020000ti,omap4-uartHJuart3 ldefaultwserial@4806e000ti,omap4-uartHFuart4 lserial@48066000ti,omap4-uartH`iuart5 ldefaultxserial@48068000ti,omap4-uartHjuart6 lmmc@4809c000ti,omap4-hsmmcH  }Smmc1r=r>txrxyzmmc@480b4000ti,omap4-hsmmcH @ }Vmmc2r/r0txrx{mmc@480ad000ti,omap4-hsmmcH  }^mmc3rMrNtxrxmmc@480d1000ti,omap4-hsmmcH  }`mmc4r9r:txrx !disabledmmc@480d5000ti,omap4-hsmmcH P };mmc5r;r<txrx !disabledmmu@4a066000ti,omap4-iommuJ` }mmu_dspmmu@55082000ti,omap4-iommuU  }dmmu_ipukeypad@4ae1c000ti,omap4-keypadJkbdmcpdm@40132000ti,omap4-mcpdm@ I mpudma }pmcpdmrArBup_linkdn_link!okaydefault|dmic@4012e000ti,omap4-dmic@Impudma }rdmicrCup_link !disabledmcbsp@40122000ti,omap4-mcbsp@ I mpudma }common*mcbsp1r!r"txrx!okaydefault}mcbsp@40124000ti,omap4-mcbsp@@I@mpudma }common*mcbsp2rrtxrx!okaydefault~mcbsp@40126000ti,omap4-mcbsp@`I`mpudma }common*mcbsp3rrtxrx !disabledmailbox@4a0f4000ti,omap4-mailboxJ@ }mailbox9EWmbox_ipu i tmbox_dsp i ttimer@4ae18000ti,omap5430-timerJ }%timer1timer@48032000ti,omap5430-timerH  }&timer2timer@48034000ti,omap5430-timerH@ }'timer3timer@48036000ti,omap5430-timerH` }(timer4timer@40138000ti,omap5430-timer@I })timer5timer@4013a000ti,omap5430-timer@I }*timer6timer@4013c000ti,omap5430-timer@I }+timer7timer@4013e000ti,omap5430-timer@I },timer8timer@4803e000ti,omap5430-timerH }-timer9timer@48086000ti,omap5430-timerH` }.timer10timer@48088000ti,omap5430-timerH }/timer11wdt@4ae14000ti,omap5-wdtti,omap3-wdtJ@ }P wd_timer2dmm@4e000000 ti,omap5-dmmN }qdmmemif@4c000000 ti,emif-4d5emif1L }nemif@4d000000 ti,emif-4d5emif2M }ocontrol-phy@4a002300ti,control-phy-usb2J#powercontrol-phy@4a002370ti,control-phy-pipe3J#ppoweromap_dwc3@4a020000ti,dwc3 usb_otg_ssJ }] dwc3@4a030000 snps,dwc3J }\ %usb2-phyusb3-phy /peripheral7ocp2scp@4a080000ti,omap-ocp2scpJ  ocp2scp1usb2phy@4a084000 ti,omap-usb2J@|FwkupclkrefclkRusb3phy@4a084400 ti,omap-usb3JDJHdJL@phy_rxphy_txpll_ctrlF wkupclksysclkrefclkRusbhstll@4a062000 ti,usbhs-tllJ  }N usb_tll_hsusbhshost@4a064000ti,usbhs-hostJ@ usb_host_hs [\^3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ]ehci-hsic hehci-hsicohci@4a064800ti,ohci-omap3JH& }Lehci@4a064c00 ti,ehci-omapJL& }M  bandgap@4a0021e0 J! J#, J#,J#< }~ti,omap5430-bandgapscontrol-phy@4a002374ti,control-phy-pipe3J#tpowersysclkocp2scp@4a090000ti,omap-ocp2scpJ  ocp2scp3phy@4a096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrlFsysclkrefclkRsata@4a141100snps,dwc-ahciJJ }6  %sata-physatadss@58000000 ti,omap5-dssX!ok dss_corefckdispc@58001000ti,omap5-dispcX } dss_dispcfckencoder@58002000ti,omap5-rfbiX  !disabled dss_rfbi'fckickencoder@58004000 ti,omap5-dsiX@XB@XC@protophypll }5 !disabled dss_dsi1 fcksys_clkencoder@58005000 ti,omap5-dsiXX@X@protophypll }7 !disabled dss_dsi2 fcksys_clkencoder@58060000ti,omap5-hdmi XXXXwppllphycore }e!ok dss_hdmi fcksys_clkrL audio_txdefaultportendpointregulator-abb-mpu ti,abb-v2abb_mpu2 J|J`J!J3base-addressint-addressefuse-addressldo-address0 ,regulator-abb-mm ti,abb-v2abb_mm2 J|J`J!J3base-addressint-addressefuse-addressldo-addressƀ0 fixedregulator-mmcsdregulator-fixed vmmcsd_fixed--{{hsusb2_phyusb-nop-xceiv E main_clk $hsusb3_phyusb-nop-xceiv leds gpio-ledsled@1#omap5:blue:usr1 m )heartbeat?offencoder@0 ti,tpd12s015default$portsport@0endpoint@0port@1endpoint@0connector@0hdmi-connector#hdmibportendpointsoundti,abe-twl6040 Momap5-uevmV$clwHeadset StereophoneHSOLHeadset StereophoneHSORLine OutAUXLLine OutAUXRHSMICHeadset MicHeadset MicHeadset Mic BiasAFMLLine InAFMRLine In #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3serial4serial5display0device_typeregoperating-pointsclocksclock-namesclock-latencycooling-min-levelcooling-max-level#cooling-cellscpu0-supplylinux,phandlepolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceinterruptsinterrupt-controller#interrupt-cellsti,hwmodssramranges#clock-cellsti,index-starts-at-oneclock-multclock-divti,bit-shiftclock-frequencyti,max-divti,index-power-of-twoti,dividersti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpmc,num-csgpmc,num-waitpinsti,system-power-controllerti,enable-vbus-detectionti,enable-id-detectionti,wakeupinterrupt-nameti,ldo6-vibratorregulator-always-onregulator-boot-onti,smps-rangestatusti,audpwron-gpiovio-supplyv2v1-supplyenable-active-high#hwlock-cellsti,spi-num-csdmasdma-namesinterrupts-extendedti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removableti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-size#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmti,no-idle-on-initphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertutmi-modeextconvbus-supplyphysphy-namesdr_modetx-fifo-resizectrl-module#phy-cellsport2-modeport3-mode#thermal-sensor-cellsvdda-supplyremote-endpointti,settling-timeti,clock-cyclesti,tranxdone-status-maskti,ldovbb-override-maskti,ldovbb-vset-maskti,abb_inforeset-gpioslabellinux,default-triggerdefault-stateti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routing