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Vper_abe_nc_fclkrti,divider-clockž ‰œN Naes1_fckrti,gate-clockž‰ aes2_fckrti,gate-clockž‰¨dss_sys_clkrti,gate-clockž" ‰ › ›dss_tv_clkrti,gate-clockžH ‰ š šdss_dss_clkrti,gate-clockžI‰ 9™ ™dss_48mhz_clkrti,gate-clockžJ ‰  fdif_fckrti,divider-clockž4œ‰(ügpio2_dbclkrti,gate-clockž+‰`gpio3_dbclkrti,gate-clockž+‰hgpio4_dbclkrti,gate-clockž+‰pgpio5_dbclkrti,gate-clockž+‰xgpio6_dbclkrti,gate-clockž+‰€sgx_clk_muxr ti,mux-clockžKL‰ hsi_fckrti,divider-clockžEœ‰8üiss_ctrlclkrti,gate-clockžM‰ mcbsp4_sync_mux_ckr ti,mux-clockžMN‰àO Oper_mcbsp4_gfclkr ti,mux-clockžO%‰àhsmmc1_fclkr ti,mux-clockžPM‰(hsmmc2_fclkr ti,mux-clockžPM‰0ocp2scp_usb_phy_phy_48mrti,gate-clockžQ‰àsha2md5_fckrti,gate-clockž‰Èslimbus2_fclk_1rti,gate-clockžR ‰8slimbus2_fclk_0rti,gate-clockžS‰8slimbus2_slimbus_clkrti,gate-clockžT ‰8smartreflex_core_fckrti,gate-clockžU‰8smartreflex_iva_fckrti,gate-clockžU‰0smartreflex_mpu_fckrti,gate-clockžU‰(cm2_dm10_muxr ti,mux-clockž+‰(cm2_dm11_muxr ti,mux-clockž+‰0cm2_dm2_muxr ti,mux-clockž+‰8cm2_dm3_muxr ti,mux-clockž+‰@cm2_dm4_muxr ti,mux-clockž+‰Hcm2_dm9_muxr ti,mux-clockž+‰Pusb_host_fs_fckrti,gate-clockžJ‰Ð_ _utmi_p1_gfclkr ti,mux-clockžVW‰XX Xusb_host_hs_utmi_p1_clkrti,gate-clockžX‰Xutmi_p2_gfclkr ti,mux-clockžVY‰XZ Zusb_host_hs_utmi_p2_clkrti,gate-clockžZ ‰Xusb_host_hs_utmi_p3_clkrti,gate-clockžV ‰Xusb_host_hs_hsic480m_p1_clkrti,gate-clockžG ‰Xusb_host_hs_hsic60m_p1_clkrti,gate-clockžV ‰Xusb_host_hs_hsic60m_p2_clkrti,gate-clockžV ‰Xusb_host_hs_hsic480m_p2_clkrti,gate-clockžG‰Xusb_host_hs_func48mclkrti,gate-clockžJ‰Xusb_host_hs_fckrti,gate-clockžV‰Xotg_60m_gfclkr ti,mux-clockž[\‰`] ]usb_otg_hs_xclkrti,gate-clockž]‰`usb_otg_hs_ickrti,gate-clockž‰`usb_phy_cm_clk32krti,gate-clockž+‰@• •usb_tll_hs_usb_ch2_clkrti,gate-clockžV ‰husb_tll_hs_usb_ch0_clkrti,gate-clockžV‰husb_tll_hs_usb_ch1_clkrti,gate-clockžV ‰husb_tll_hs_ickrti,gate-clockž^‰hclockdomainsl3_init_clkdmti,clockdomainžC_scrm@4a30a000ti,omap4-scrm‰J0  clocksauxclk0_src_gate_ckr ti,composite-no-wait-gate-clockž`‰b bauxclk0_src_mux_ckrti,composite-mux-clock ž`a‰c cauxclk0_src_ckrti,composite-clockžbcd dauxclk0_ckrti,divider-clockždœ‰t tauxclk1_src_gate_ckr ti,composite-no-wait-gate-clockž`‰e eauxclk1_src_mux_ckrti,composite-mux-clock ž`a‰f fauxclk1_src_ckrti,composite-clockžefg gauxclk1_ckrti,divider-clockžgœ‰u uauxclk2_src_gate_ckr ti,composite-no-wait-gate-clockž`‰h hauxclk2_src_mux_ckrti,composite-mux-clock ž`a‰i iauxclk2_src_ckrti,composite-clockžhij jauxclk2_ckrti,divider-clockžjœ‰v vauxclk3_src_gate_ckr ti,composite-no-wait-gate-clockž`‰k kauxclk3_src_mux_ckrti,composite-mux-clock ž`a‰l lauxclk3_src_ckrti,composite-clockžklm mauxclk3_ckrti,divider-clockžmœ‰w wauxclk4_src_gate_ckr ti,composite-no-wait-gate-clockž`‰ n nauxclk4_src_mux_ckrti,composite-mux-clock ž`a‰ o oauxclk4_src_ckrti,composite-clockžnop pauxclk4_ckrti,divider-clockžpœ‰ x xauxclk5_src_gate_ckr ti,composite-no-wait-gate-clockž`‰$q qauxclk5_src_mux_ckrti,composite-mux-clock ž`a‰$r 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#address-cells#size-cellscompatibleinterrupt-parenti2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1device_typeregnext-level-cacheclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsregulator-always-onusb-supply#pwm-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csdmasdma-namesti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthstatusnon-removablecap-power-off-cardti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-modephysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabelgpioslinux,default-triggerti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingstartup-delay-usregulator-boot-onreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus