8(Gtechnexion,omap3-thundertechnexion,omap3-tao3530ti,omap34xxti,omap3&,7TI OMAP3 Thunder baseboard with TAO3530 SOMchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/display@0memorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busyh l3_mainaes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocksvirt_16_8m_ck fixed-clockY  osc_sys_ck ti,mux-clock} y @  sys_ckti,divider-clock} %yp0 sys_clkout1ti,gate-clock} y pdpll3_x2_ckfixed-factor-clock} GRdpll3_m2x2_ckfixed-factor-clock} GR dpll4_x2_ckfixed-factor-clock}GRcorex2_fckfixed-factor-clock}GR wkup_l4_ickfixed-factor-clock}GR BBcorex2_d3_fckfixed-factor-clock}GR yycorex2_d5_fckfixed-factor-clock}GR zzclockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock 22virt_12m_ck fixed-clock virt_13m_ck fixed-clock]@ virt_19200000_ck fixed-clock$ virt_26000000_ck fixed-clock virt_38_4m_ck fixed-clockI  dpll4_ckti,omap3-dpll-per-clock}y D 0 dpll4_m2_ckti,divider-clock}%?y H0 dpll4_m2x2_mul_ckfixed-factor-clock}GR dpll4_m2x2_ckti,gate-clock}y \ omap_96m_alwon_fckfixed-factor-clock}GR dpll3_ckti,omap3-dpll-core-clock}y @ 0  dpll3_m3_ckti,divider-clock} %y@0 dpll3_m3x2_mul_ckfixed-factor-clock}GR dpll3_m3x2_ckti,gate-clock} y \ emu_core_alwon_ckfixed-factor-clock}GR VVsys_altclk fixed-clock  mcbsp_clks fixed-clock 99dpll3_m2_ckti,divider-clock} %y @0  core_ckfixed-factor-clock} GR dpll1_fckti,divider-clock}%y @0 dpll1_ckti,omap3-dpll-clock}y  $ @ 4 dpll1_x2_ckfixed-factor-clock}GR dpll1_x2m2_ckti,divider-clock}%y D0 ..cm_96m_fckfixed-factor-clock}GR omap_96m_fck ti,mux-clock}y @ 77dpll4_m3_ckti,divider-clock}% y@0 dpll4_m3x2_mul_ckfixed-factor-clock}GR dpll4_m3x2_ckti,gate-clock}y \ omap_54m_fck ti,mux-clock} y @ **cm_96m_d2_fckfixed-factor-clock}GR !!omap_48m_fck ti,mux-clock}! y @ ""omap_12m_fckfixed-factor-clock}"GR ;;dpll4_m4_ckti,divider-clock}% y@0 ##dpll4_m4x2_mul_ckti,fixed-factor-clock}#r $$dpll4_m4x2_ckti,gate-clock}$y \ }}dpll4_m5_ckti,divider-clock}%?y@0 %%dpll4_m5x2_mul_ckti,fixed-factor-clock}%r &&dpll4_m5x2_ckti,gate-clock}&y \ ^^dpll4_m6_ckti,divider-clock}%?y@0 ''dpll4_m6x2_mul_ckfixed-factor-clock}'GR ((dpll4_m6x2_ckti,gate-clock}(y \ ))emu_per_alwon_ckfixed-factor-clock})GR WWclkout2_src_gate_ck ti,composite-no-wait-gate-clock}y p ++clkout2_src_mux_ckti,composite-mux-clock}*y p ,,clkout2_src_ckti,composite-clock}+, --sys_clkout2ti,divider-clock}-%@y pmpu_ckfixed-factor-clock}.GR //arm_fckti,divider-clock}/y $%emu_mpu_alwon_ckfixed-factor-clock}/GR XXl3_ickti,divider-clock}%y @0 00l4_ickti,divider-clock}0%y @0 11rm_ickti,divider-clock}1%y @0gpt10_gate_fckti,composite-gate-clock} y  33gpt10_mux_fckti,composite-mux-clock}2y @ 44gpt10_fckti,composite-clock}34gpt11_gate_fckti,composite-gate-clock} y  55gpt11_mux_fckti,composite-mux-clock}2y @ 66gpt11_fckti,composite-clock}56core_96m_fckfixed-factor-clock}7GR 88mmchs2_fckti,wait-gate-clock}8y  mmchs1_fckti,wait-gate-clock}8y  i2c3_fckti,wait-gate-clock}8y  i2c2_fckti,wait-gate-clock}8y  i2c1_fckti,wait-gate-clock}8y  mcbsp5_gate_fckti,composite-gate-clock}9 y  mcbsp1_gate_fckti,composite-gate-clock}9 y  core_48m_fckfixed-factor-clock}"GR ::mcspi4_fckti,wait-gate-clock}:y  mcspi3_fckti,wait-gate-clock}:y  mcspi2_fckti,wait-gate-clock}:y  mcspi1_fckti,wait-gate-clock}:y  uart2_fckti,wait-gate-clock}:y  uart1_fckti,wait-gate-clock}:y   core_12m_fckfixed-factor-clock};GR <<hdq_fckti,wait-gate-clock}<y  core_l3_ickfixed-factor-clock}0GR ==sdrc_ickti,wait-gate-clock}=y  ~~gpmc_fckfixed-factor-clock}=GRcore_l4_ickfixed-factor-clock}1GR >>mmchs2_ickti,omap3-interface-clock}>y  mmchs1_ickti,omap3-interface-clock}>y  hdq_ickti,omap3-interface-clock}>y  mcspi4_ickti,omap3-interface-clock}>y  mcspi3_ickti,omap3-interface-clock}>y  mcspi2_ickti,omap3-interface-clock}>y  mcspi1_ickti,omap3-interface-clock}>y  i2c3_ickti,omap3-interface-clock}>y  i2c2_ickti,omap3-interface-clock}>y  i2c1_ickti,omap3-interface-clock}>y  uart2_ickti,omap3-interface-clock}>y  uart1_ickti,omap3-interface-clock}>y   gpt11_ickti,omap3-interface-clock}>y   gpt10_ickti,omap3-interface-clock}>y   mcbsp5_ickti,omap3-interface-clock}>y   mcbsp1_ickti,omap3-interface-clock}>y   omapctrl_ickti,omap3-interface-clock}>y  dss_tv_fckti,gate-clock}*y dss_96m_fckti,gate-clock}7y dss2_alwon_fckti,gate-clock}y dummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock}y  ??gpt1_mux_fckti,composite-mux-clock}2y @ @@gpt1_fckti,composite-clock}?@aes2_ickti,omap3-interface-clock}>y  wkup_32k_fckfixed-factor-clock}2GR AAgpio1_dbckti,gate-clock}Ay  sha12_ickti,omap3-interface-clock}>y  wdt2_fckti,wait-gate-clock}Ay  wdt2_ickti,omap3-interface-clock}By  wdt1_ickti,omap3-interface-clock}By  gpio1_ickti,omap3-interface-clock}By  omap_32ksync_ickti,omap3-interface-clock}By  gpt12_ickti,omap3-interface-clock}By  gpt1_ickti,omap3-interface-clock}By  per_96m_fckfixed-factor-clock}GR per_48m_fckfixed-factor-clock}"GR CCuart3_fckti,wait-gate-clock}Cy  gpt2_gate_fckti,composite-gate-clock}y DDgpt2_mux_fckti,composite-mux-clock}2y@ EEgpt2_fckti,composite-clock}DEgpt3_gate_fckti,composite-gate-clock}y FFgpt3_mux_fckti,composite-mux-clock}2y@ GGgpt3_fckti,composite-clock}FGgpt4_gate_fckti,composite-gate-clock}y HHgpt4_mux_fckti,composite-mux-clock}2y@ IIgpt4_fckti,composite-clock}HIgpt5_gate_fckti,composite-gate-clock}y JJgpt5_mux_fckti,composite-mux-clock}2y@ KKgpt5_fckti,composite-clock}JKgpt6_gate_fckti,composite-gate-clock}y LLgpt6_mux_fckti,composite-mux-clock}2y@ MMgpt6_fckti,composite-clock}LMgpt7_gate_fckti,composite-gate-clock}y NNgpt7_mux_fckti,composite-mux-clock}2y@ OOgpt7_fckti,composite-clock}NOgpt8_gate_fckti,composite-gate-clock} y PPgpt8_mux_fckti,composite-mux-clock}2y@ QQgpt8_fckti,composite-clock}PQgpt9_gate_fckti,composite-gate-clock} y RRgpt9_mux_fckti,composite-mux-clock}2y@ SSgpt9_fckti,composite-clock}RSper_32k_alwon_fckfixed-factor-clock}2GR TTgpio6_dbckti,gate-clock}Ty gpio5_dbckti,gate-clock}Ty gpio4_dbckti,gate-clock}Ty gpio3_dbckti,gate-clock}Ty gpio2_dbckti,gate-clock}Ty  wdt3_fckti,wait-gate-clock}Ty  per_l4_ickfixed-factor-clock}1GR UUgpio6_ickti,omap3-interface-clock}Uy gpio5_ickti,omap3-interface-clock}Uy gpio4_ickti,omap3-interface-clock}Uy gpio3_ickti,omap3-interface-clock}Uy gpio2_ickti,omap3-interface-clock}Uy  wdt3_ickti,omap3-interface-clock}Uy  uart3_ickti,omap3-interface-clock}Uy  uart4_ickti,omap3-interface-clock}Uy gpt9_ickti,omap3-interface-clock}Uy  gpt8_ickti,omap3-interface-clock}Uy  gpt7_ickti,omap3-interface-clock}Uy gpt6_ickti,omap3-interface-clock}Uy gpt5_ickti,omap3-interface-clock}Uy gpt4_ickti,omap3-interface-clock}Uy gpt3_ickti,omap3-interface-clock}Uy gpt2_ickti,omap3-interface-clock}Uy mcbsp2_ickti,omap3-interface-clock}Uy mcbsp3_ickti,omap3-interface-clock}Uy mcbsp4_ickti,omap3-interface-clock}Uy mcbsp2_gate_fckti,composite-gate-clock}9y mcbsp3_gate_fckti,composite-gate-clock}9y mcbsp4_gate_fckti,composite-gate-clock}9y emu_src_mux_ck ti,mux-clock}VWXy@ YYemu_src_ckti,clkdm-gate-clock}Y ZZpclk_fckti,divider-clock}Z%y@0pclkx2_fckti,divider-clock}Z%y@0atclk_fckti,divider-clock}Z%y@0traceclk_src_fck ti,mux-clock}VWXy@ [[traceclk_fckti,divider-clock}[ %y@0secure_32k_fck fixed-clock \\gpt12_fckfixed-factor-clock}\GRwdt1_fckfixed-factor-clock}\GRsecurity_l4_ick2fixed-factor-clock}1GR ]]aes1_ickti,omap3-interface-clock}]y rng_ickti,omap3-interface-clock}]y sha11_ickti,omap3-interface-clock}]y des1_ickti,omap3-interface-clock}]y cam_mclkti,gate-clock}^ycam_ick!ti,omap3-no-wait-interface-clock}1y csi2_96m_fckti,gate-clock}8y security_l3_ickfixed-factor-clock}0GR __pka_ickti,omap3-interface-clock}_y icr_ickti,omap3-interface-clock}>y des2_ickti,omap3-interface-clock}>y mspro_ickti,omap3-interface-clock}>y mailboxes_ickti,omap3-interface-clock}>y ssi_l4_ickfixed-factor-clock}1GR ffsr1_fckti,wait-gate-clock}y sr2_fckti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}1GRdpll2_fckti,divider-clock}%y@0 ``dpll2_ckti,omap3-dpll-clock}`y$@4 aadpll2_m2_ckti,divider-clock}a%yD0 bbiva2_ckti,wait-gate-clock}by modem_fckti,omap3-interface-clock}y  sad2d_ickti,omap3-interface-clock}0y  mad2d_ickti,omap3-interface-clock}0y  mspro_fckti,wait-gate-clock}8y ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock}y  ccssi_ssr_div_fck_3430es2ti,composite-divider-clock}y @$ ddssi_ssr_fck_3430es2ti,composite-clock}cd eessi_sst_fck_3430es2fixed-factor-clock}eGR hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock}=y  ssi_ick_3430es2ti,omap3-ssi-interface-clock}fy  usim_gate_fckti,composite-gate-clock}7 y  qqsys_d2_ckfixed-factor-clock}GR hhomap_96m_d2_fckfixed-factor-clock}7GR iiomap_96m_d4_fckfixed-factor-clock}7GR jjomap_96m_d8_fckfixed-factor-clock}7GR kkomap_96m_d10_fckfixed-factor-clock}7GR  lldpll5_m2_d4_ckfixed-factor-clock}gGR mmdpll5_m2_d8_ckfixed-factor-clock}gGR nndpll5_m2_d16_ckfixed-factor-clock}gGR oodpll5_m2_d20_ckfixed-factor-clock}gGR ppusim_mux_fckti,composite-mux-clock(}hijklmnopy @0 rrusim_fckti,composite-clock}qrusim_ickti,omap3-interface-clock}By   dpll5_ckti,omap3-dpll-clock}y  $ L 4 ssdpll5_m2_ckti,divider-clock}s%y P0 ggsgx_gate_fckti,composite-gate-clock}y  {{core_d3_ckfixed-factor-clock}GR ttcore_d4_ckfixed-factor-clock}GR uucore_d6_ckfixed-factor-clock}GR vvomap_192m_alwon_fckfixed-factor-clock}GR wwcore_d2_ckfixed-factor-clock}GR xxsgx_mux_fckti,composite-mux-clock }tuvwxyzy @ ||sgx_fckti,composite-clock}{|sgx_ickti,wait-gate-clock}0y  cpefuse_fckti,gate-clock}y  ts_fckti,gate-clock}2y  usbtll_fckti,wait-gate-clock}gy  usbtll_ickti,omap3-interface-clock}>y  mmchs3_ickti,omap3-interface-clock}>y  mmchs3_fckti,wait-gate-clock}8y  dss1_alwon_fck_3430es2ti,dss-gate-clock}}y dss_ick_3430es2ti,omap3-dss-interface-clock}1y usbhost_120m_fckti,gate-clock}gy usbhost_48m_fckti,dss-gate-clock}"y usbhost_ickti,omap3-dss-interface-clock}1y clockdomainscore_l3_clkdmti,clockdomain}~dpll3_clkdmti,clockdomain} dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}Zdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}ad2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}ssgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }scrm@48002000ti,omap3-scrmyH clocksmcbsp5_mux_fckti,composite-mux-clock}89y mcbsp5_fckti,composite-clock}mcbsp1_mux_fckti,composite-mux-clock}89yt mcbsp1_fckti,composite-clock}mcbsp2_mux_fckti,composite-mux-clock}9yt mcbsp2_fckti,composite-clock}mcbsp3_mux_fckti,composite-mux-clock}9y mcbsp3_fckti,composite-clock}mcbsp4_mux_fckti,composite-mux-clock}9y mcbsp4_fckti,composite-clock}clockdomainscounter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH  dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH` ! .` pinmux@48002030 ti,omap3-padconfpinctrl-singleyH 08;Ypinmux_hsusbb2_pins`v          pinmux_mmc1_pinsPv "$& pinmux_mmc2_pins0v(*,.02 pinmux_wlan_gpiov^pinmux_uart3_pinsvnAp pinmux_i2c3_pinsv pinmux_mcspi1_pins v pinmux_mcspi3_pins v pinmux_mcbsp3_pins v<>@B pinmux_twl4030_pinsvA pinmux_dss_dpi_pinsv pinmux_lte430_pinsv8 pinmux_backlight_pinsv: pinmux@48002a00 ti,omap3-padconfpinctrl-singleyH*\;Ypinmux_twl4030_vpins v tisyscon@48002270sysconyH"p pbias_regulatorti,pbias-omapypbias_mmc_omap2430pbias_mmc_omap2430w@- gpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5 gpio@49058000ti,omap3-gpioyI"gpio6 serial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3ldefault i2c@48070000 ti,omap3-i2cyH8txrxi2c1'@twl@48yH& ti,twl4030default audioti,twl4030-audio codecrtcti,twl4030-rtc bciti,twl4030-bci *watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 vdd_ehciw@w@8regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 '  regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0 regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5 regulator-vusb1v8ti,twl4030-vusb1v8 regulator-vusb3v1ti,twl4030-vusb3v1 regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@8regulator-vsimti,twl4030-vsimw@- gpioti,twl4030-gpioLXc twl4030-usbti,twl4030-usb p~ pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrxi2c2i2c@48060000 ti,omap3-i2cyH=txrxi2c3default mailbox@48094000ti,omap3-mailboxmailboxyH @ dsp  )spi@48098000ti,omap2-mcspiyH Amcspi14@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3default spidev@0spidevBlyTspi@4809a000ti,omap2-mcspiyH Bmcspi24 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [mcspi34 tx0rx0tx1rx1default spidev@0spidevBlyTspi@480ba000ti,omap2-mcspiyH 0mcspi44FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1]=>txrxjdefault w mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrxdefault wmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxokay mcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxokaydefault mcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5txrx disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11timer@48304000ti,omap3430-timeryH0@_timer12) disabledusbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs 9ehci-phyohci@48064400ti,ohci-omap3yHD&Lehci@48064800 ti,ehci-omapyHH&MDgpmc@6e000000ti,omap3430-gpmcgpmcynIUnand@0,0 ygvsw$$$ 0*9HJH[6jx-loader@0 |X-Loaderybootloaders@80000|U-Bootybootloaders_env@260000 |U-Boot Envy&kernel@280000|Kernely(@filesystem@680000 |File Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs D usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fckdefault dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu }e ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$;Yhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z p hsusb2_phyusb-nop-xceiv  soundti,omap-twl4030  omap3beagleregulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 (' display@0samsung,lte430wq-f0cpanel-dpi|lcddefault  : portendpoint panel-timingT@GOWdp*z backlightgpio-backlightdefault    #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsrangesdmasdma-namesstatus#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cells#dma-cellsdma-channelsdma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplycd-gpiosbus-widthnon-removablecap-power-off-cardti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspti,codecenable-active-lowenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on