^8( Fcompulab,omap3-sbc-t3730compulab,omap3-cm-t3730ti,omap36xxti,omap3&!7CompuLab SBC-T3730 with CM-T3730chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000 l/connector@0 u/connector@1memory~memorycpuscpu@0arm,cortex-a8~cpucpus 'O 57pmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-bush l3_mainaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocksvirt_16_8m_ck fixed-clockY  osc_sys_ck ti,mux-clock  @  sys_ckti,divider-clock "/p:sys_clkout1ti,gate-clock  p"dpll3_x2_ckfixed-factor-clock Q\dpll3_m2x2_ckfixed-factor-clock Q\dpll4_x2_ckfixed-factor-clockQ\corex2_fckfixed-factor-clockQ\wkup_l4_ickfixed-factor-clockQ\BBcorex2_d3_fckfixed-factor-clockQ\yycorex2_d5_fckfixed-factor-clockQ\zzclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock22virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockI  dpll4_ckti,omap3-dpll-per-j-type-clock D 0dpll4_m2_ckti,divider-clock/? H:dpll4_m2x2_mul_ckfixed-factor-clockQ\dpll4_m2x2_ckti,hsdiv-gate-clock" fomap_96m_alwon_fckfixed-factor-clockQ\dpll3_ckti,omap3-dpll-core-clock @ 0  dpll3_m3_ckti,divider-clock "/@:dpll3_m3x2_mul_ckfixed-factor-clockQ\dpll3_m3x2_ckti,hsdiv-gate-clock"  femu_core_alwon_ckfixed-factor-clockQ\VVsys_altclk fixed-clock  mcbsp_clks fixed-clock99dpll3_m2_ckti,divider-clock "/ @:  core_ckfixed-factor-clock Q\dpll1_fckti,divider-clock"/ @:dpll1_ckti,omap3-dpll-clock  $ @ 4dpll1_x2_ckfixed-factor-clockQ\dpll1_x2m2_ckti,divider-clock/ D:..cm_96m_fckfixed-factor-clockQ\omap_96m_fck ti,mux-clock" @77dpll4_m3_ckti,divider-clock"/ @:dpll4_m3x2_mul_ckfixed-factor-clockQ\dpll4_m3x2_ckti,hsdiv-gate-clock" fomap_54m_fck ti,mux-clock " @**cm_96m_d2_fckfixed-factor-clockQ\!!omap_48m_fck ti,mux-clock! " @""omap_12m_fckfixed-factor-clock"Q\;;dpll4_m4_ckti,divider-clock/ @:##dpll4_m4x2_mul_ckti,fixed-factor-clock#|$$dpll4_m4x2_ckti,gate-clock$" f}}dpll4_m5_ckti,divider-clock/?@:%%dpll4_m5x2_mul_ckti,fixed-factor-clock%|&&dpll4_m5x2_ckti,hsdiv-gate-clock&" f^^dpll4_m6_ckti,divider-clock"/?@:''dpll4_m6x2_mul_ckfixed-factor-clock'Q\((dpll4_m6x2_ckti,hsdiv-gate-clock(" f))emu_per_alwon_ckfixed-factor-clock)Q\WWclkout2_src_gate_ck ti,composite-no-wait-gate-clock" p++clkout2_src_mux_ckti,composite-mux-clock* p,,clkout2_src_ckti,composite-clock+,--sys_clkout2ti,divider-clock-"/@ pmpu_ckfixed-factor-clock.Q\//arm_fckti,divider-clock/ $/emu_mpu_alwon_ckfixed-factor-clock/Q\XXl3_ickti,divider-clock/ @:00l4_ickti,divider-clock0"/ @:11rm_ickti,divider-clock1"/ @:gpt10_gate_fckti,composite-gate-clock"  33gpt10_mux_fckti,composite-mux-clock2" @44gpt10_fckti,composite-clock34gpt11_gate_fckti,composite-gate-clock"  55gpt11_mux_fckti,composite-mux-clock2" @66gpt11_fckti,composite-clock56core_96m_fckfixed-factor-clock7Q\88mmchs2_fckti,wait-gate-clock8 "mmchs1_fckti,wait-gate-clock8 "i2c3_fckti,wait-gate-clock8 "i2c2_fckti,wait-gate-clock8 "i2c1_fckti,wait-gate-clock8 "mcbsp5_gate_fckti,composite-gate-clock9"  mcbsp1_gate_fckti,composite-gate-clock9"  core_48m_fckfixed-factor-clock"Q\::mcspi4_fckti,wait-gate-clock: "mcspi3_fckti,wait-gate-clock: "mcspi2_fckti,wait-gate-clock: "mcspi1_fckti,wait-gate-clock: "uart2_fckti,wait-gate-clock: "uart1_fckti,wait-gate-clock: " core_12m_fckfixed-factor-clock;Q\<<hdq_fckti,wait-gate-clock< "core_l3_ickfixed-factor-clock0Q\==sdrc_ickti,wait-gate-clock= "~~gpmc_fckfixed-factor-clock=Q\core_l4_ickfixed-factor-clock1Q\>>mmchs2_ickti,omap3-interface-clock> "mmchs1_ickti,omap3-interface-clock> "hdq_ickti,omap3-interface-clock> "mcspi4_ickti,omap3-interface-clock> "mcspi3_ickti,omap3-interface-clock> "mcspi2_ickti,omap3-interface-clock> "mcspi1_ickti,omap3-interface-clock> "i2c3_ickti,omap3-interface-clock> "i2c2_ickti,omap3-interface-clock> "i2c1_ickti,omap3-interface-clock> "uart2_ickti,omap3-interface-clock> "uart1_ickti,omap3-interface-clock> " gpt11_ickti,omap3-interface-clock> " gpt10_ickti,omap3-interface-clock> " mcbsp5_ickti,omap3-interface-clock> " mcbsp1_ickti,omap3-interface-clock> " omapctrl_ickti,omap3-interface-clock> "dss_tv_fckti,gate-clock*"dss_96m_fckti,gate-clock7"dss2_alwon_fckti,gate-clock"dummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock" ??gpt1_mux_fckti,composite-mux-clock2 @@@gpt1_fckti,composite-clock?@aes2_ickti,omap3-interface-clock>" wkup_32k_fckfixed-factor-clock2Q\AAgpio1_dbckti,gate-clockA "sha12_ickti,omap3-interface-clock> "wdt2_fckti,wait-gate-clockA "wdt2_ickti,omap3-interface-clockB "wdt1_ickti,omap3-interface-clockB "gpio1_ickti,omap3-interface-clockB "omap_32ksync_ickti,omap3-interface-clockB "gpt12_ickti,omap3-interface-clockB "gpt1_ickti,omap3-interface-clockB "per_96m_fckfixed-factor-clockQ\per_48m_fckfixed-factor-clock"Q\CCuart3_fckti,wait-gate-clockC" gpt2_gate_fckti,composite-gate-clock"DDgpt2_mux_fckti,composite-mux-clock2@EEgpt2_fckti,composite-clockDEgpt3_gate_fckti,composite-gate-clock"FFgpt3_mux_fckti,composite-mux-clock2"@GGgpt3_fckti,composite-clockFGgpt4_gate_fckti,composite-gate-clock"HHgpt4_mux_fckti,composite-mux-clock2"@IIgpt4_fckti,composite-clockHIgpt5_gate_fckti,composite-gate-clock"JJgpt5_mux_fckti,composite-mux-clock2"@KKgpt5_fckti,composite-clockJKgpt6_gate_fckti,composite-gate-clock"LLgpt6_mux_fckti,composite-mux-clock2"@MMgpt6_fckti,composite-clockLMgpt7_gate_fckti,composite-gate-clock"NNgpt7_mux_fckti,composite-mux-clock2"@OOgpt7_fckti,composite-clockNOgpt8_gate_fckti,composite-gate-clock" PPgpt8_mux_fckti,composite-mux-clock2"@QQgpt8_fckti,composite-clockPQgpt9_gate_fckti,composite-gate-clock" RRgpt9_mux_fckti,composite-mux-clock2"@SSgpt9_fckti,composite-clockRSper_32k_alwon_fckfixed-factor-clock2Q\TTgpio6_dbckti,gate-clockT"gpio5_dbckti,gate-clockT"gpio4_dbckti,gate-clockT"gpio3_dbckti,gate-clockT"gpio2_dbckti,gate-clockT" wdt3_fckti,wait-gate-clockT" per_l4_ickfixed-factor-clock1Q\UUgpio6_ickti,omap3-interface-clockU"gpio5_ickti,omap3-interface-clockU"gpio4_ickti,omap3-interface-clockU"gpio3_ickti,omap3-interface-clockU"gpio2_ickti,omap3-interface-clockU" wdt3_ickti,omap3-interface-clockU" uart3_ickti,omap3-interface-clockU" uart4_ickti,omap3-interface-clockU"gpt9_ickti,omap3-interface-clockU" gpt8_ickti,omap3-interface-clockU" gpt7_ickti,omap3-interface-clockU"gpt6_ickti,omap3-interface-clockU"gpt5_ickti,omap3-interface-clockU"gpt4_ickti,omap3-interface-clockU"gpt3_ickti,omap3-interface-clockU"gpt2_ickti,omap3-interface-clockU"mcbsp2_ickti,omap3-interface-clockU"mcbsp3_ickti,omap3-interface-clockU"mcbsp4_ickti,omap3-interface-clockU"mcbsp2_gate_fckti,composite-gate-clock9"mcbsp3_gate_fckti,composite-gate-clock9"mcbsp4_gate_fckti,composite-gate-clock9"emu_src_mux_ck ti,mux-clockVWX@YYemu_src_ckti,clkdm-gate-clockYZZpclk_fckti,divider-clockZ"/@:pclkx2_fckti,divider-clockZ"/@:atclk_fckti,divider-clockZ"/@:traceclk_src_fck ti,mux-clockVWX"@[[traceclk_fckti,divider-clock[" /@:secure_32k_fck fixed-clock\\gpt12_fckfixed-factor-clock\Q\wdt1_fckfixed-factor-clock\Q\security_l4_ick2fixed-factor-clock1Q\]]aes1_ickti,omap3-interface-clock]" rng_ickti,omap3-interface-clock] "sha11_ickti,omap3-interface-clock] "des1_ickti,omap3-interface-clock] "cam_mclkti,gate-clock^"cam_ick!ti,omap3-no-wait-interface-clock1"csi2_96m_fckti,gate-clock8"security_l3_ickfixed-factor-clock0Q\__pka_ickti,omap3-interface-clock_ "icr_ickti,omap3-interface-clock> "des2_ickti,omap3-interface-clock> "mspro_ickti,omap3-interface-clock> "mailboxes_ickti,omap3-interface-clock> "ssi_l4_ickfixed-factor-clock1Q\ffsr1_fckti,wait-gate-clock "sr2_fckti,wait-gate-clock "sr_l4_ickfixed-factor-clock1Q\dpll2_fckti,divider-clock"/@:``dpll2_ckti,omap3-dpll-clock`$@4aadpll2_m2_ckti,divider-clocka/D:bbiva2_ckti,wait-gate-clockb"modem_fckti,omap3-interface-clock "sad2d_ickti,omap3-interface-clock0 "mad2d_ickti,omap3-interface-clock0 "mspro_fckti,wait-gate-clock8 "ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock" ccssi_ssr_div_fck_3430es2ti,composite-divider-clock" @$ddssi_ssr_fck_3430es2ti,composite-clockcdeessi_sst_fck_3430es2fixed-factor-clockeQ\hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock= "ssi_ick_3430es2ti,omap3-ssi-interface-clockf "usim_gate_fckti,composite-gate-clock7"  qqsys_d2_ckfixed-factor-clockQ\hhomap_96m_d2_fckfixed-factor-clock7Q\iiomap_96m_d4_fckfixed-factor-clock7Q\jjomap_96m_d8_fckfixed-factor-clock7Q\kkomap_96m_d10_fckfixed-factor-clock7Q\ lldpll5_m2_d4_ckfixed-factor-clockgQ\mmdpll5_m2_d8_ckfixed-factor-clockgQ\nndpll5_m2_d16_ckfixed-factor-clockgQ\oodpll5_m2_d20_ckfixed-factor-clockgQ\ppusim_mux_fckti,composite-mux-clock(hijklmnop" @:rrusim_fckti,composite-clockqrusim_ickti,omap3-interface-clockB " dpll5_ckti,omap3-dpll-clock  $ L 4ssdpll5_m2_ckti,divider-clocks/ P:ggsgx_gate_fckti,composite-gate-clock" {{core_d3_ckfixed-factor-clockQ\ttcore_d4_ckfixed-factor-clockQ\uucore_d6_ckfixed-factor-clockQ\vvomap_192m_alwon_fckfixed-factor-clockQ\wwcore_d2_ckfixed-factor-clockQ\xxsgx_mux_fckti,composite-mux-clock tuvwxyz @||sgx_fckti,composite-clock{|sgx_ickti,wait-gate-clock0 "cpefuse_fckti,gate-clock "ts_fckti,gate-clock2 "usbtll_fckti,wait-gate-clockg "usbtll_ickti,omap3-interface-clock> "mmchs3_ickti,omap3-interface-clock> "mmchs3_fckti,wait-gate-clock8 "dss1_alwon_fck_3430es2ti,dss-gate-clock}"dss_ick_3430es2ti,omap3-dss-interface-clock1"usbhost_120m_fckti,gate-clockg"usbhost_48m_fckti,dss-gate-clock""usbhost_ickti,omap3-dss-interface-clock1"uart4_fckti,wait-gate-clockC"clockdomainscore_l3_clkdmti,clockdomain~dpll3_clkdmti,clockdomain dpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainZdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainad2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainssgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain scrm@48002000ti,omap3-scrmH clocksmcbsp5_mux_fckti,composite-mux-clock89"mcbsp5_fckti,composite-clockmcbsp1_mux_fckti,composite-mux-clock89"tmcbsp1_fckti,composite-clockmcbsp2_mux_fckti,composite-mux-clock9"tmcbsp2_fckti,composite-clockmcbsp3_mux_fckti,composite-mux-clock9mcbsp3_fckti,composite-clockmcbsp4_mux_fckti,composite-mux-clock9"mcbsp4_fckti,composite-clockclockdomainscounter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  + 8`pinmux@48002030 ti,omap3-padconfpinctrl-singleH 08Ecdefaultpinmux_uart3_pinsnppinmux_mmc1_pins0pinmux_green_led_pins  pinmux_dss_dpi_pins_commonpinmux_dss_dpi_pins_cm_t35x0pinmux_ads7846_pinspinmux_mcspi1_pins pinmux_i2c1_pinspinmux_mcbsp2_pins  pinmux_smsc1_pinsjpinmux_hsusb0_pins`rtvxz|~pinmux_twl4030_pinsApinmux_mmc2_pins0(*,.02pinmux_wl12xx_gpio4pinmux_smsc2_pinspinmux_tfp410_pinspinmux_i2c3_pinspinmux_sb_t35_audio_amppinmux_sb_t35_usb_hub_pinspinmux@48002a00 ti,omap3-padconfpinctrl-singleH*\Ecpinmux_twl4030_vpins pinmux_dss_dpi_pins_cm_t37300 tisyscon@48002270sysconH"ppbias_regulatorti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-gpio@48310000ti,omap3-gpioH1gpio1gpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5gpio@49058000ti,omap3-gpioI"gpio6serial@4806a000ti,omap3-uartH  H12txrxuart1lserial@4806c000ti,omap3-uartH I34txrxuart2lserial@49020000ti,omap3-uartI J56txrxuart3ldefaulti2c@48070000 ti,omap3-i2cH8txrxi2c1defaultat24@50 at24,24c024Ptwl@48H& ti,twl4030defaultaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci =watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioKW  twl4030-usbti,twl4030-usb bp~pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad$0iglj. madcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9txrxi2c2i2c@48060000 ti,omap3-i2cH=txrxi2c3defaultat24@50 at24,24c024Pmailbox@48094000ti,omap3-mailboxmailboxH @ dsp  (spi@48098000ti,omap2-mcspiH Amcspi13@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3defaultads7846@0default ti,ads7846AL`& ^kt} spi@4809a000ti,omap2-mcspiH Bmcspi23 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi33 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi43FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxdefaultmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxdefault,:mmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx Mdisabledmmu@480bd400ti,omap2-iommuH mmu_ispTmmu@5d000000ti,omap2-iommu]mmu_iva Mdisabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@dmpu ;< ncommontxrx~mcbsp1 txrx Mdisabledmcbsp@49022000ti,omap3-mcbspI I dmpusidetone>?ncommontxrxsidetone~mcbsp2mcbsp2_sidetone!"txrxMokdefaultmcbsp@49024000ti,omap3-mcbspI@I dmpusidetoneYZncommontxrxsidetone~mcbsp3mcbsp3_sidetonetxrx Mdisabledmcbsp@49026000ti,omap3-mcbspI`dmpu 67 ncommontxrx~mcbsp4txrx Mdisabledmcbsp@48096000ti,omap3-mcbspH `dmpu QR ncommontxrx~mcbsp5txrx Mdisabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs ehci-phy ehci-phyohci@48064400ti,ohci-omap3HD&Lehci@48064800 ti,ehci-omapHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcn0,-nand@0,0  sw0>xPxbqxxZZH<x%x6HZpartition@0`xloaderpartition@0x80000`ubootpartition@0x260000`uboot environment&partition@0x2a0000`linux*@partition@0x6a0000`rootfsjethernet@gpmcsmsc,lan9221smsc,lan9115fq0>Pbq(--%xKKH6 default& ethernet@4,0smsc,lan9221smsc,lan9115default& fq0>Pbq(--%xKKH6 usb_otg_hs@480ab000ti,omap3-musbH \]nmcdma usb_otg_hs,7? defaultHW _usb2-phyi2dss@48050000 ti,omap3-dssHMok dss_corefckdefaultdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H dprotophypll Mdisabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH Mdisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH Mok dss_vencfcktv_dac_clkoportendpoint{  portendpoint{ssi-controller@48058000 ti,omap3-ssissiMokHHdsysgddGngdd_mpu e ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHdtxrx&CDssi-port@4805b000ti,omap3-ssi-portHHdtxrx&EFserial@49042000ti,omap3-uartI PQRtxrxuart4lregulator-abb-mpu ti,abb-v1 abb_mpu_ivaH0rH0hdbase-addressint-address`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\Ecleds gpio-ledsdefault ledb `cm-t3x:green  heartbeathsusb1_power_regregulator-fixed hsusb1_vbus2Z2Z p  hsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z p  hsusb1_phyusb-nop-xceivA  # hsusb2_phyusb-nop-xceivA  # ads7846-regregulator-fixed ads7846-reg2Z2Zconnector@1svideo-connector`tvportendpoint{ soundti,omap-twl4030 /cm-t35 8 Aregulator-vddvarioregulator-fixed vddvario Jregulator-vdd33aregulator-fixedvdd33a Jwl12xx_vmmc2regulator-fixedvw1271defaultw@w@ f  N  ^wl12xx_vaux2regulator-fixedvwl1271_vaux2w@w@ qencoder@0 ti,tfp410 |defaultportsport@0endpoint@0{port@1endpoint@0{connector@0dvi-connector`dviportendpoint{audio_ampregulator-fixed audio_ampdefault f  J #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3display0display1device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsrangesdmasdma-names#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cells#dma-cellsdma-channelsdma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesizebci3v1-supplyti,use-ledsti,pullupsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-replinux,wakeupti,dual-voltpbias-supplybus-widthvmmc-supplyvmmc_aux-supplynon-removablecap-power-off-cardstatusti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channelsdata-lines#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infogpioslinux,default-triggerstartup-delay-usreset-gpiosti,modelti,mcbspti,codecregulator-always-onenable-active-highvin-supplypowerdown-gpiosenable-active-low