#8( _-compulab,omap3-cm-t3730ti,omap36xxti,omap3&7CompuLab CM-T3730chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000memorylmemoryxcpuscpu@0arm,cortex-a8lcpux|cpus 'O 57pmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainaes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_ck fixed-clockY  osc_sys_ck ti,mux-clock| x @  sys_ckti,divider-clock| xp(sys_clkout1ti,gate-clock| x pdpll3_x2_ckfixed-factor-clock| ?Jdpll3_m2x2_ckfixed-factor-clock| ?Jdpll4_x2_ckfixed-factor-clock|?Jcorex2_fckfixed-factor-clock|?Jwkup_l4_ickfixed-factor-clock|?JBBcorex2_d3_fckfixed-factor-clock|?Jyycorex2_d5_fckfixed-factor-clock|?Jzzclockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock22virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockI  dpll4_ckti,omap3-dpll-per-j-type-clock|x D 0dpll4_m2_ckti,divider-clock|?x H(dpll4_m2x2_mul_ckfixed-factor-clock|?Jdpll4_m2x2_ckti,hsdiv-gate-clock|x Tomap_96m_alwon_fckfixed-factor-clock|?Jdpll3_ckti,omap3-dpll-core-clock|x @ 0  dpll3_m3_ckti,divider-clock| x@(dpll3_m3x2_mul_ckfixed-factor-clock|?Jdpll3_m3x2_ckti,hsdiv-gate-clock| x Temu_core_alwon_ckfixed-factor-clock|?JVVsys_altclk fixed-clock  mcbsp_clks fixed-clock99dpll3_m2_ckti,divider-clock| x @(  core_ckfixed-factor-clock| ?Jdpll1_fckti,divider-clock|x @(dpll1_ckti,omap3-dpll-clock|x  $ @ 4dpll1_x2_ckfixed-factor-clock|?Jdpll1_x2m2_ckti,divider-clock|x D(..cm_96m_fckfixed-factor-clock|?Jomap_96m_fck ti,mux-clock|x @77dpll4_m3_ckti,divider-clock| x@(dpll4_m3x2_mul_ckfixed-factor-clock|?Jdpll4_m3x2_ckti,hsdiv-gate-clock|x Tomap_54m_fck ti,mux-clock| x @**cm_96m_d2_fckfixed-factor-clock|?J!!omap_48m_fck ti,mux-clock|! x @""omap_12m_fckfixed-factor-clock|"?J;;dpll4_m4_ckti,divider-clock| x@(##dpll4_m4x2_mul_ckti,fixed-factor-clock|#jx$$dpll4_m4x2_ckti,gate-clock|$x T}}dpll4_m5_ckti,divider-clock|?x@(%%dpll4_m5x2_mul_ckti,fixed-factor-clock|%jx&&dpll4_m5x2_ckti,hsdiv-gate-clock|&x T^^dpll4_m6_ckti,divider-clock|?x@(''dpll4_m6x2_mul_ckfixed-factor-clock|'?J((dpll4_m6x2_ckti,hsdiv-gate-clock|(x T))emu_per_alwon_ckfixed-factor-clock|)?JWWclkout2_src_gate_ck ti,composite-no-wait-gate-clock|x p++clkout2_src_mux_ckti,composite-mux-clock|*x p,,clkout2_src_ckti,composite-clock|+,--sys_clkout2ti,divider-clock|-@x pmpu_ckfixed-factor-clock|.?J//arm_fckti,divider-clock|/x $emu_mpu_alwon_ckfixed-factor-clock|/?JXXl3_ickti,divider-clock|x @(00l4_ickti,divider-clock|0x @(11rm_ickti,divider-clock|1x @(gpt10_gate_fckti,composite-gate-clock| x 33gpt10_mux_fckti,composite-mux-clock|2x @44gpt10_fckti,composite-clock|34gpt11_gate_fckti,composite-gate-clock| x 55gpt11_mux_fckti,composite-mux-clock|2x @66gpt11_fckti,composite-clock|56core_96m_fckfixed-factor-clock|7?J88mmchs2_fckti,wait-gate-clock|8x mmchs1_fckti,wait-gate-clock|8x i2c3_fckti,wait-gate-clock|8x i2c2_fckti,wait-gate-clock|8x i2c1_fckti,wait-gate-clock|8x mcbsp5_gate_fckti,composite-gate-clock|9 x mcbsp1_gate_fckti,composite-gate-clock|9 x core_48m_fckfixed-factor-clock|"?J::mcspi4_fckti,wait-gate-clock|:x mcspi3_fckti,wait-gate-clock|:x mcspi2_fckti,wait-gate-clock|:x mcspi1_fckti,wait-gate-clock|:x uart2_fckti,wait-gate-clock|:x uart1_fckti,wait-gate-clock|:x  core_12m_fckfixed-factor-clock|;?J<<hdq_fckti,wait-gate-clock|<x core_l3_ickfixed-factor-clock|0?J==sdrc_ickti,wait-gate-clock|=x ~~gpmc_fckfixed-factor-clock|=?Jcore_l4_ickfixed-factor-clock|1?J>>mmchs2_ickti,omap3-interface-clock|>x mmchs1_ickti,omap3-interface-clock|>x hdq_ickti,omap3-interface-clock|>x mcspi4_ickti,omap3-interface-clock|>x mcspi3_ickti,omap3-interface-clock|>x mcspi2_ickti,omap3-interface-clock|>x mcspi1_ickti,omap3-interface-clock|>x i2c3_ickti,omap3-interface-clock|>x i2c2_ickti,omap3-interface-clock|>x i2c1_ickti,omap3-interface-clock|>x uart2_ickti,omap3-interface-clock|>x uart1_ickti,omap3-interface-clock|>x  gpt11_ickti,omap3-interface-clock|>x  gpt10_ickti,omap3-interface-clock|>x  mcbsp5_ickti,omap3-interface-clock|>x  mcbsp1_ickti,omap3-interface-clock|>x  omapctrl_ickti,omap3-interface-clock|>x dss_tv_fckti,gate-clock|*xdss_96m_fckti,gate-clock|7xdss2_alwon_fckti,gate-clock|xdummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock|x ??gpt1_mux_fckti,composite-mux-clock|2x @@@gpt1_fckti,composite-clock|?@aes2_ickti,omap3-interface-clock|>x wkup_32k_fckfixed-factor-clock|2?JAAgpio1_dbckti,gate-clock|Ax sha12_ickti,omap3-interface-clock|>x wdt2_fckti,wait-gate-clock|Ax wdt2_ickti,omap3-interface-clock|Bx wdt1_ickti,omap3-interface-clock|Bx gpio1_ickti,omap3-interface-clock|Bx omap_32ksync_ickti,omap3-interface-clock|Bx gpt12_ickti,omap3-interface-clock|Bx gpt1_ickti,omap3-interface-clock|Bx per_96m_fckfixed-factor-clock|?Jper_48m_fckfixed-factor-clock|"?JCCuart3_fckti,wait-gate-clock|Cx gpt2_gate_fckti,composite-gate-clock|xDDgpt2_mux_fckti,composite-mux-clock|2x@EEgpt2_fckti,composite-clock|DEgpt3_gate_fckti,composite-gate-clock|xFFgpt3_mux_fckti,composite-mux-clock|2x@GGgpt3_fckti,composite-clock|FGgpt4_gate_fckti,composite-gate-clock|xHHgpt4_mux_fckti,composite-mux-clock|2x@IIgpt4_fckti,composite-clock|HIgpt5_gate_fckti,composite-gate-clock|xJJgpt5_mux_fckti,composite-mux-clock|2x@KKgpt5_fckti,composite-clock|JKgpt6_gate_fckti,composite-gate-clock|xLLgpt6_mux_fckti,composite-mux-clock|2x@MMgpt6_fckti,composite-clock|LMgpt7_gate_fckti,composite-gate-clock|xNNgpt7_mux_fckti,composite-mux-clock|2x@OOgpt7_fckti,composite-clock|NOgpt8_gate_fckti,composite-gate-clock| xPPgpt8_mux_fckti,composite-mux-clock|2x@QQgpt8_fckti,composite-clock|PQgpt9_gate_fckti,composite-gate-clock| xRRgpt9_mux_fckti,composite-mux-clock|2x@SSgpt9_fckti,composite-clock|RSper_32k_alwon_fckfixed-factor-clock|2?JTTgpio6_dbckti,gate-clock|Txgpio5_dbckti,gate-clock|Txgpio4_dbckti,gate-clock|Txgpio3_dbckti,gate-clock|Txgpio2_dbckti,gate-clock|Tx wdt3_fckti,wait-gate-clock|Tx per_l4_ickfixed-factor-clock|1?JUUgpio6_ickti,omap3-interface-clock|Uxgpio5_ickti,omap3-interface-clock|Uxgpio4_ickti,omap3-interface-clock|Uxgpio3_ickti,omap3-interface-clock|Uxgpio2_ickti,omap3-interface-clock|Ux wdt3_ickti,omap3-interface-clock|Ux uart3_ickti,omap3-interface-clock|Ux uart4_ickti,omap3-interface-clock|Uxgpt9_ickti,omap3-interface-clock|Ux gpt8_ickti,omap3-interface-clock|Ux gpt7_ickti,omap3-interface-clock|Uxgpt6_ickti,omap3-interface-clock|Uxgpt5_ickti,omap3-interface-clock|Uxgpt4_ickti,omap3-interface-clock|Uxgpt3_ickti,omap3-interface-clock|Uxgpt2_ickti,omap3-interface-clock|Uxmcbsp2_ickti,omap3-interface-clock|Uxmcbsp3_ickti,omap3-interface-clock|Uxmcbsp4_ickti,omap3-interface-clock|Uxmcbsp2_gate_fckti,composite-gate-clock|9xmcbsp3_gate_fckti,composite-gate-clock|9xmcbsp4_gate_fckti,composite-gate-clock|9xemu_src_mux_ck ti,mux-clock|VWXx@YYemu_src_ckti,clkdm-gate-clock|YZZpclk_fckti,divider-clock|Zx@(pclkx2_fckti,divider-clock|Zx@(atclk_fckti,divider-clock|Zx@(traceclk_src_fck ti,mux-clock|VWXx@[[traceclk_fckti,divider-clock|[ x@(secure_32k_fck fixed-clock\\gpt12_fckfixed-factor-clock|\?Jwdt1_fckfixed-factor-clock|\?Jsecurity_l4_ick2fixed-factor-clock|1?J]]aes1_ickti,omap3-interface-clock|]x rng_ickti,omap3-interface-clock|]x sha11_ickti,omap3-interface-clock|]x des1_ickti,omap3-interface-clock|]x cam_mclkti,gate-clock|^xcam_ick!ti,omap3-no-wait-interface-clock|1xcsi2_96m_fckti,gate-clock|8xsecurity_l3_ickfixed-factor-clock|0?J__pka_ickti,omap3-interface-clock|_x icr_ickti,omap3-interface-clock|>x des2_ickti,omap3-interface-clock|>x mspro_ickti,omap3-interface-clock|>x mailboxes_ickti,omap3-interface-clock|>x ssi_l4_ickfixed-factor-clock|1?Jffsr1_fckti,wait-gate-clock|x sr2_fckti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|1?Jdpll2_fckti,divider-clock|x@(``dpll2_ckti,omap3-dpll-clock|`x$@4aadpll2_m2_ckti,divider-clock|axD(bbiva2_ckti,wait-gate-clock|bxmodem_fckti,omap3-interface-clock|x sad2d_ickti,omap3-interface-clock|0x mad2d_ickti,omap3-interface-clock|0x mspro_fckti,wait-gate-clock|8x ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock|x ccssi_ssr_div_fck_3430es2ti,composite-divider-clock|x @$ddssi_ssr_fck_3430es2ti,composite-clock|cdeessi_sst_fck_3430es2fixed-factor-clock|e?Jhsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock|=x ssi_ick_3430es2ti,omap3-ssi-interface-clock|fx usim_gate_fckti,composite-gate-clock|7 x qqsys_d2_ckfixed-factor-clock|?Jhhomap_96m_d2_fckfixed-factor-clock|7?Jiiomap_96m_d4_fckfixed-factor-clock|7?Jjjomap_96m_d8_fckfixed-factor-clock|7?Jkkomap_96m_d10_fckfixed-factor-clock|7?J lldpll5_m2_d4_ckfixed-factor-clock|g?Jmmdpll5_m2_d8_ckfixed-factor-clock|g?Jnndpll5_m2_d16_ckfixed-factor-clock|g?Joodpll5_m2_d20_ckfixed-factor-clock|g?Jppusim_mux_fckti,composite-mux-clock(|hijklmnopx @(rrusim_fckti,composite-clock|qrusim_ickti,omap3-interface-clock|Bx  dpll5_ckti,omap3-dpll-clock|x  $ L 4ssdpll5_m2_ckti,divider-clock|sx P(ggsgx_gate_fckti,composite-gate-clock|x {{core_d3_ckfixed-factor-clock|?Jttcore_d4_ckfixed-factor-clock|?Juucore_d6_ckfixed-factor-clock|?Jvvomap_192m_alwon_fckfixed-factor-clock|?Jwwcore_d2_ckfixed-factor-clock|?Jxxsgx_mux_fckti,composite-mux-clock |tuvwxyzx @||sgx_fckti,composite-clock|{|sgx_ickti,wait-gate-clock|0x cpefuse_fckti,gate-clock|x ts_fckti,gate-clock|2x usbtll_fckti,wait-gate-clock|gx usbtll_ickti,omap3-interface-clock|>x mmchs3_ickti,omap3-interface-clock|>x mmchs3_fckti,wait-gate-clock|8x dss1_alwon_fck_3430es2ti,dss-gate-clock|}xdss_ick_3430es2ti,omap3-dss-interface-clock|1xusbhost_120m_fckti,gate-clock|gxusbhost_48m_fckti,dss-gate-clock|"xusbhost_ickti,omap3-dss-interface-clock|1xuart4_fckti,wait-gate-clock|Cxclockdomainscore_l3_clkdmti,clockdomain|~dpll3_clkdmti,clockdomain| dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|Zdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|ad2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|ssgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |scrm@48002000ti,omap3-scrmxH clocksmcbsp5_mux_fckti,composite-mux-clock|89xmcbsp5_fckti,composite-clock|mcbsp1_mux_fckti,composite-mux-clock|89xtmcbsp1_fckti,composite-clock|mcbsp2_mux_fckti,composite-mux-clock|9xtmcbsp2_fckti,composite-clock|mcbsp3_mux_fckti,composite-mux-clock|9xmcbsp3_fckti,composite-clock|mcbsp4_mux_fckti,composite-mux-clock|9xmcbsp4_fckti,composite-clock|clockdomainscounter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  &`pinmux@48002030 ti,omap3-padconfpinctrl-singlexH 083Qpinmux_uart3_pinsnnppinmux_mmc1_pins0npinmux_green_led_pinsnpinmux_dss_dpi_pins_commonnpinmux_dss_dpi_pins_cm_t35x0npinmux_ads7846_pinsnpinmux_mcspi1_pins npinmux_i2c1_pinsnpinmux_mcbsp2_pins n pinmux_smsc1_pinsnjpinmux_hsusb0_pins`nrtvxz|~pinmux_twl4030_pinsnApinmux_mmc2_pins0n(*,.02pinmux_wl12xx_gpion4  pinmux@48002a00 ti,omap3-padconfpinctrl-singlexH*\3Qpinmux_twl4030_vpins npinmux_dss_dpi_pins_cm_t37300n tisyscon@48002270sysconxH"ppbias_regulatorti,pbias-omapxpbias_mmc_omap2430pbias_mmc_omap2430w@-gpio@48310000ti,omap3-gpioxH1gpio1gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3  gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5gpio@49058000ti,omap3-gpioxI"gpio6serial@4806a000ti,omap3-uartxH H12txrxuart1lserial@4806c000ti,omap3-uartxHI34txrxuart2lserial@49020000ti,omap3-uartxIJ56txrxuart3l defaulti2c@48070000 ti,omap3-i2cxH8txrxi2c1 defaultat24@50 at24,24c02"xPtwl@48xH& ti,twl4030 defaultaudioti,twl4030-audio  codecrtcti,twl4030-rtc bciti,twl4030-bci +watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2  regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio9Etwl4030-usbti,twl4030-usb P^lzpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad$0iglj. madcti,twl4030-madci2c@48072000 ti,omap3-i2cxH 9txrxi2c2i2c@48060000 ti,omap3-i2cxH=txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxxH @dsp   spi@48098000ti,omap2-mcspixH Amcspi1!@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3 defaultads7846@0 default ti,ads7846/x:`& LYbkt} spi@4809a000ti,omap2-mcspixH Bmcspi2! +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3! tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4!FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrx defaultmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx default (mmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx ;disabledmmu@480bd400ti,omap2-iommuxH mmu_ispBmmu@5d000000ti,omap2-iommux]mmu_iva ;disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@Rmpu ;< \commontxrxlmcbsp1 txrx ;disabledmcbsp@49022000ti,omap3-mcbspxI I Rmpusidetone>?\commontxrxsidetonelmcbsp2mcbsp2_sidetone!"txrx;ok default  mcbsp@49024000ti,omap3-mcbspxI@I RmpusidetoneYZ\commontxrxsidetonelmcbsp3mcbsp3_sidetonetxrx ;disabledmcbsp@49026000ti,omap3-mcbspxI`Rmpu 67 \commontxrxlmcbsp4txrx ;disabledmcbsp@48096000ti,omap3-mcbspxH `Rmpu QR \commontxrxlmcbsp5txrx ;disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1{timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5timer@4903a000ti,omap3430-timerxI*timer6timer@4903c000ti,omap3430-timerxI+timer7timer@4903e000ti,omap3430-timerxI,timer8timer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11timer@48304000ti,omap3430-timerxH0@_timer12{usbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hs ehci-phy ehci-phyohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxn ,nand@0,0 xsw,x>xP_xrxZZH<xx$6Zpartition@0Nxloaderxpartition@0x80000Nubootxpartition@0x260000Nuboot environmentx&partition@0x2a0000Nlinuxx*@partition@0x6a0000Nrootfsxjethernet@gpmcsmsc,lan9221smsc,lan9115T_y,>P_r(--xKK6$ default& xusb_otg_hs@480ab000ti,omap3-musbxH \]\mcdma usb_otg_hs%-  default6E Musb2-phy~W2dss@48050000 ti,omap3-dssxH;ok dss_core|fck defaultdispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H Rprotophypll ;disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH ;disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH ;ok dss_venc|fcktv_dac_clk]portendpointiyssi-controller@48058000 ti,omap3-ssissi;okxHHRsysgddG\gdd_mpu |e ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portxHHRtxrx&CDssi-port@4805b000ti,omap3-ssi-portxHHRtxrx&EFserial@49042000ti,omap3-uartxI PQRtxrxuart4lregulator-abb-mpu ti,abb-v1 abb_mpu_ivaxH0rH0hRbase-addressint-address|`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singlexH%\3Qleds gpio-leds defaultledb Ncm-t3x:green  heartbeathsusb1_power_regregulator-fixed hsusb1_vbus2Z2Zphsusb2_power_regregulator-fixed hsusb2_vbus2Z2Zphsusb1_phyusb-nop-xceiv/ hsusb2_phyusb-nop-xceiv/ ads7846-regregulator-fixed ads7846-reg2Z2Zconnector@1svideo-connectorNtvportendpointisoundti,omap-twl4030 cm-t35   $ regulator-vddvarioregulator-fixed vddvario -regulator-vdd33aregulator-fixedvdd33a -wl12xx_vmmc2regulator-fixedvw1271 default w@w@ T N  Awl12xx_vaux2regulator-fixedvwl1271_vaux2w@w@ T  #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsrangesdmasdma-names#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cells#dma-cellsdma-channelsdma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0pagesizebci3v1-supplyti,use-ledsti,pullupsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-replinux,wakeupti,dual-voltpbias-supplybus-widthvmmc-supplyvmmc_aux-supplynon-removablecap-power-off-cardstatusti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channels#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infogpioslinux,default-triggerstartup-delay-usreset-gpiosti,modelti,mcbspti,codecregulator-always-onenable-active-highvin-supply