8(4samsung,smdk5410samsung,exynos5410samsung,exynos5&+7Samsung SMDK5410 board based on EXYNOS5410chosen=console=ttySAC2,115200aliasesF/soc/serial@12C00000N/soc/serial@12C10000V/soc/serial@12C20000memory^memoryj@cpuscpu@0^cpuarm,cortex-a15jn_^cpu@1^cpuarm,cortex-a15jn_^cpu@2^cpuarm,cortex-a15jn_^cpu@3^cpuarm,cortex-a15jn_^soc simple-bus~interrupt-controller@10440000samsung,exynos4210-combiner jD interrupt-controller@10481000%arm,cortex-a15-gicarm,cortex-a9-gic jHH H@ H`   chipid@10000000samsung,exynos4210-chipidjsystem-controller@10040000samsung,exynos5410-pmusysconjPmct@101C0000samsung,exynos4210-mctj &0  ; fin_pllmctinterrupt-mapxyz{   sysram@02020000 mmio-sramj@ ~@smp-sysram@0samsung,exynos4210-sysramjsmp-sysram@53000samsung,exynos4210-sysram-nsj0clock-controller@10010000samsung,exynos5410-clockjmmc@12200000samsung,exynos5250-dw-mshcj  K_biuciuokay"4>Phmmc@12210000samsung,exynos5250-dw-mshcj! L`biuciu disabledmmc@12220000samsung,exynos5250-dw-mshcj" Mabiuciuokay>Phserial@12C00000samsung,exynos4210-uartj 3uartclk_uart_baud0okayserial@12C10000samsung,exynos4210-uartj 4uartclk_uart_baud0okayserial@12C20000samsung,exynos4210-uartj 5uartclk_uart_baud0okayxxti fixed-clocknn6fin_pllfirmware@02037000samsung,secure-firmwarejp #address-cells#size-cellscompatibleinterrupt-parentmodelbootargsserial0serial1serial2device_typeregclock-frequencyranges#interrupt-cellsinterrupt-controllersamsung,combiner-nrinterruptslinux,phandleclocksclock-namesinterrupt-map#clock-cellsfifo-depthstatusnum-slotscap-mmc-highspeedbroken-cdcard-detect-delaysamsung,dw-mshc-ciu-divsamsung,dw-mshc-sdr-timingsamsung,dw-mshc-ddr-timingbus-widthcap-sd-highspeeddisable-wpclock-output-names