Ð þíB›8>Ô(Ç>œMarvell Armada 385 GP4!marvell,a385-gpmarvell,armada388marvell,armada380chosen,console=ttyS0,115200 5/soc/internal-regs/serial@12000aliasesA/soc/internal-regs/gpio@18100G/soc/internal-regs/gpio@18140"M/soc/internal-regs/ethernet@70000"W/soc/internal-regs/ethernet@30000"a/soc/internal-regs/ethernet@34000memorykmemoryw€soc"!marvell,armada380-mbussimple-bus{†—à©è ºðñÿðbootrom!marvell,bootrom w devbus-bootcs!marvell,mvebu-devbus wðº/ÿÿÿÿÁ Èdisableddevbus-cs0!marvell,mvebu-devbus wðº>ÿÿÿÿÁ Èdisableddevbus-cs1!marvell,mvebu-devbus wðº=ÿÿÿÿÁ Èdisableddevbus-cs2!marvell,mvebu-devbus wðº;ÿÿÿÿÁ Èdisableddevbus-cs3!marvell,mvebu-devbus wð º7ÿÿÿÿÁ Èdisabledinternal-regs !simple-busºðcache-controller@8000!arm,pl310-cachew€ÏÝscu@c000!arm,cortex-a9-scuwÀXtimer@c600!arm,cortex-a9-twd-timerwÆ  é Áinterrupt-controller@d000!arm,cortex-a9-gicôwÐÁ spi@10600!marvell,orion-spiwP( éÁÈokay3defaultAspi-flash@0 !st,m25p128wKúð€]spi@10680!marvell,orion-spiw€P( é?Á Èdisabledi2c@11000!marvell,mv64xxx-i2cw  élèÁÈokay3defaultAw† pca9555@20 !nxp,pca95553defaultA†é‡—ôw  pca9555@21 !nxp,pca95553default†é‡—ôw!! !i2c@11100!marvell,mv64xxx-i2cw  élèÁ Èdisabledserial@12000!snps,dw-apb-uartw £ é ­ÁÈokay3defaultAserial@12100!snps,dw-apb-uartw!£ é ­Á Èdisabledpinctrl@18000w€ !marvell,mv88f6828-pinctrlge-rgmii-pins-0Dºmpp6mpp7mpp8mpp9mpp10mpp11mpp12mpp13mpp14mpp15mpp16mpp17Çge0 ge-rgmii-pins-1Hºmpp21mpp27mpp28mpp29mpp30mpp31mpp32mpp37mpp38mpp39mpp40mpp41Çge1  i2c-pins-0 ºmpp2mpp3Çi2c0 mdio-pins ºmpp4mpp5Çge ref-clk-pins-0ºmpp45Çref ref-clk-pins-1ºmpp46Çrefspi-pins-0ºmpp22mpp23mpp24mpp25Çspi0 spi-pins-1ºmpp56mpp57mpp58mpp59Çspi1uart-pins-0 ºmpp0mpp1Çua0 uart-pins-1 ºmpp19mpp20Çua1sdhci-pins<ºmpp48mpp49mpp50mpp52mpp53mpp54mpp55mpp57mpp58mpp59Çsd0 sata-pins-0ºmpp20Çsata0 sata-pins-1ºmpp19Çsata1 sata-pins-2ºmpp47Çsata2 sata-pins-3ºmpp44Çsata3 pca0_pinsºmpp18Çgpio gpio@18100!marvell,orion-gpiow@Ø ‡—ô0é5678 gpio@18140!marvell,orion-gpiow@@؇—ô0é:;<=system-controller@18200M!marvell,armada-380-system-controllermarvell,armada-370-xp-system-controllerw‚clock-gating-control@18220 !marvell,armada-380-gating-clockw‚ Áß  mvebu-sar@18600!marvell,armada-380-core-clockw†ß mbus-controller@20000!marvell,mbus-controllerw€  interrupt-controller@20000 !marvell,mpicw ÐpXôì é  timer@203001!marvell,armada-380-timermarvell,armada-xp-timerw0@0Pû      Á  nbclkfixedwatchdog@20300!marvell,armada-380-wdtw4‚` Á  nbclkfixedcpurst@20800!marvell,armada-370-cpu-resetwmpcore-soc-ctrl@20d20#!marvell,armada-380-mpcore-soc-ctrlw lcoherency-fabric@21010$!marvell,armada-380-coherency-fabricwpmsu@22000!marvell,armada-380-pmsuw ethernet@30000!marvell,armada-370-netaw@û Á Èokay3defaultA   rgmii-idethernet@34000!marvell,armada-370-netaw@@û Á  Èdisabledusb@50000!marvell,orion-ehciw€ éÁ Èokay(xor@60800!marvell,orion-xorw Á Èokayxor00 é3Axor01 é3ALxor@60900!marvell,orion-xorw  Á Èokayxor10 éA3Axor11 éB3ALethernet@70000!marvell,armada-370-netaw@û Á Èokay3defaultA rgmii-idmdio@72004!marvell,orion-mdiow Á 3defaultAethernet-phy@1w ethernet-phy@0w  rtc@a3800!marvell,armada-380-rtcw 8 „   Zrtcrtc-soc ésata@a8000!marvell,armada-380-ahciw €  éÁ Èokay3defaultAsata-port@0wdsata-port@1wdsata@e0000!marvell,armada-380-ahciw  éÁ Èokay3defaultAsata-port@0wdsata-port@1wdclock@e4250!!marvell,armada-380-corediv-clockwBP ßÁrnand thermal@e8078!marvell,armada380-thermalw@x@tÈokayflash@d0000!marvell,armada370-nandw T éTÁ Èdisabledsdhci@d8000!marvell,armada-380-sdhciw € À éÁ …Èokay3defaultA ›¤­¹usb3@f0000!marvell,armada-380-xhciw@@@ éÁ Èokay(usb3@f8000!marvell,armada-380-xhciw€@À@ éÁ Èokay( pcie-controller!marvell,armada-370-pcieÈokaykpcià ÎÿPº‚ð ‚ð ‚@ð@ ‚€ð€ ‚èà‚èà‚ØЂ¸°pcie@1,0kpciØ‚ wô@º‚‚ë þ Á Èokaypcie@2,0kpciØ‚ wô@º‚‚ë þ! Á Èokaypcie@3,0kpciØ‚@ wô@º‚‚ë þF Á Èokaypcie@4,0kpciØ‚€ w ô@º‚‚ë þG Á  Èdisabledgpio-fan !gpio-fan Ù!0 ¸clocksmainpll !fixed-clockßww5” oscillator !fixed-clockßw}x@  cpusCmarvell,armada-380-smpcpu@0kcpu!arm,cortex-a9wcpu@1kcpu!arm,cortex-a9wusb3-vbus!regulator-fixed Qusb3-vbus`LK@xLK@£ ·!  v5-vbus0!regulator-fixed Qv5.0-vbus0`LK@xLK@£ ·! v5-vbus1!regulator-fixed Qv5.0-vbus1`LK@xLK@£ · pwr-sata0!regulator-fixed Qpwr_en_sata0£" "v5-sata0!regulator-fixed Qv5.0-sata0`LK@xLK@£¼" v12-sata0!regulator-fixed Qv12.0-sata0`·x·£¼"pwr-sata1 Qpwr_en_sata1!regulator-fixed`·x·£ ·# #v5-sata1!regulator-fixed Qv5.0-sata1`LK@xLK@£¼# v12-sata1!regulator-fixed Qv12.0-sata1`·x·£¼#pwr-sata2!regulator-fixed Qpwr_en_sata2£ · $ $v5-sata2!regulator-fixed Qv5.0-sata2`LK@xLK@£¼$ v12-sata2!regulator-fixed Qv12.0-sata2`·x·£¼$pwr-sata3!regulator-fixed Qpwr_en_sata3£ · % %v5-sata3!regulator-fixed Qv5.0-sata3`LK@xLK@£¼% v12-sata3!regulator-fixed Qv12.0-sata3`·x·£¼% #address-cells#size-cellsmodelcompatiblebootargsstdout-pathgpio0gpio1ethernet0ethernet1ethernet2device_typeregcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelinterrupts#interrupt-cellsinterrupt-controllerlinux,phandlecell-indexpinctrl-namespinctrl-0spi-max-frequencym25p,fast-readtimeout-msclock-frequencygpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionngpios#clock-cellsmsi-controllerinterrupts-extendedclock-namesphyphy-modevcc-supplydmacap,memcpydmacap,xordmacap,memsetreg-namestarget-supplyclock-output-namesmrvl,clk-delay-cyclescd-gpiosno-1-8-vwp-invertedbus-widthmsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanegpio-fan,speed-mapenable-methodregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highregulator-always-ongpiovin-supply