Ð þí3æ80ø(î0À2Marvell Armada 385 Access Point Development Board7!marvell,a385-db-apmarvell,armada385marvell,armada38xchosen,console=ttyS0,115200 5/soc/internal-regs/serial@12100aliasesA/soc/internal-regs/gpio@18100G/soc/internal-regs/gpio@18140"M/soc/internal-regs/ethernet@70000"W/soc/internal-regs/ethernet@30000"a/soc/internal-regs/ethernet@34000memorykmemoryw€soc"!marvell,armada380-mbussimple-bus{†—à©è ºðñÿðbootrom!marvell,bootrom w devbus-bootcs!marvell,mvebu-devbus wðº/ÿÿÿÿÁ Èdisableddevbus-cs0!marvell,mvebu-devbus wðº>ÿÿÿÿÁ Èdisableddevbus-cs1!marvell,mvebu-devbus wðº=ÿÿÿÿÁ Èdisableddevbus-cs2!marvell,mvebu-devbus wðº;ÿÿÿÿÁ Èdisableddevbus-cs3!marvell,mvebu-devbus wð º7ÿÿÿÿÁ Èdisabledinternal-regs !simple-busºðcache-controller@8000!arm,pl310-cachew€ÏÝscu@c000!arm,cortex-a9-scuwÀXtimer@c600!arm,cortex-a9-twd-timerwÆ  é Áinterrupt-controller@d000!arm,cortex-a9-gicôwÐÁ spi@10600!marvell,orion-spiwP( éÁ Èdisabledspi@10680!marvell,orion-spiw€P( é?ÁÈokay3defaultAspi-flash@0 !st,m25p128wK7ù€i2c@11000!marvell,mv64xxx-i2cw  é]èÁÈokay3defaultAi2c@11100!marvell,mv64xxx-i2cw  é]èÁ Èdisabledserial@12000!snps,dw-apb-uartw h é rÁÈokay3defaultAserial@12100!snps,dw-apb-uartw!h é rÁÈokay3defaultApinctrl@18000w€ !marvell,mv88f6820-pinctrlge-rgmii-pins-0Dmpp6mpp7mpp8mpp9mpp10mpp11mpp12mpp13mpp14mpp15mpp16mpp17Œge0  ge-rgmii-pins-1Hmpp21mpp27mpp28mpp29mpp30mpp31mpp32mpp37mpp38mpp39mpp40mpp41Œge1i2c-pins-0 mpp2mpp3Œi2c0 mdio-pins mpp4mpp5Œge ref-clk-pins-0mpp45Œref ref-clk-pins-1mpp46Œrefspi-pins-0mpp22mpp23mpp24mpp25Œspi0spi-pins-1mpp56mpp57mpp58mpp59Œspi1 uart-pins-0 mpp0mpp1Œua0 uart-pins-1 mpp19mpp20Œua1 sdhci-pins<mpp48mpp49mpp50mpp52mpp53mpp54mpp55mpp57mpp58mpp59Œsd0sata-pins-0mpp20Œsata0sata-pins-1mpp19Œsata1sata-pins-2mpp47Œsata2sata-pins-3mpp44Œsata3gpio@18100!marvell,orion-gpiow@ ¤´ô0é5678gpio@18140!marvell,orion-gpiow@@¤´ô0é:;<=system-controller@18200M!marvell,armada-380-system-controllermarvell,armada-370-xp-system-controllerw‚clock-gating-control@18220 !marvell,armada-380-gating-clockw‚ ÁÀ  mvebu-sar@18600!marvell,armada-380-core-clockw†À mbus-controller@20000!marvell,mbus-controllerw€  interrupt-controller@20000 !marvell,mpicw ÐpXôÍ é timer@203001!marvell,armada-380-timermarvell,armada-xp-timerw0@0PÜ    Á  ðnbclkfixedwatchdog@20300!marvell,armada-380-wdtw4‚` Á  ðnbclkfixedcpurst@20800!marvell,armada-370-cpu-resetwmpcore-soc-ctrl@20d20#!marvell,armada-380-mpcore-soc-ctrlw lcoherency-fabric@21010$!marvell,armada-380-coherency-fabricwpmsu@22000!marvell,armada-380-pmsuw ethernet@30000!marvell,armada-370-netaw@Ü Á Èokayü sgmiiethernet@34000!marvell,armada-370-netaw@@Ü Á Èokayü sgmiiusb@50000!marvell,orion-ehciw€ éÁ  Èdisabledxor@60800!marvell,orion-xorw Á Èokayxor00 é xor01 é "xor@60900!marvell,orion-xorw  Á Èokayxor10 éA xor11 éB "ethernet@70000!marvell,armada-370-netaw@ÜÁ Èokay3defaultA ü rgmii-idmdio@72004!marvell,orion-mdiow Á 3defaultAethernet-phy@1w ethernet-phy@4w  ethernet-phy@6w  rtc@a3800!marvell,armada-380-rtcw 8 „   0rtcrtc-soc ésata@a8000!marvell,armada-380-ahciw €  éÁ  Èdisabledsata@e0000!marvell,armada-380-ahciw  éÁ  Èdisabledclock@e4250!!marvell,armada-380-corediv-clockwBP ÀÁ:nand thermal@e8078!marvell,armada380-thermalw@x@tÈokayflash@d0000!marvell,armada370-nandw T éTÁ Èdisabledsdhci@d8000!marvell,armada-380-sdhciw € À éÁ M Èdisabledusb3@f0000!marvell,armada-380-xhciw@@@ éÁ  Èdisabledusb3@f8000!marvell,armada-380-xhciw€@À@ éÁ  Èdisabledpcie-controller!marvell,armada-370-pcieÈokaykpcicnÿPº‚ð ‚ð ‚@ð@ ‚€ð€ ‚èà‚èà‚ØЂ¸°pcie@1,0kpcix‚ wô@º‚‚‹ ž¬¾Á Èokaypcie@2,0kpcix‚ wô@º‚‚‹ ž!¬¾Á Èokaypcie@3,0kpcix‚@ wô@º‚‚‹ žF¬¾Á Èokaypcie@4,0kpcix‚€ w ô@º‚‚‹ žG¬¾Á  Èdisabledclocksmainpll !fixed-clockÀÐw5” oscillator !fixed-clockÀÐ}x@  cpusàmarvell,armada-380-smpcpu@0kcpu!arm,cortex-a9wcpu@1kcpu!arm,cortex-a9w #address-cells#size-cellsmodelcompatiblebootargsstdout-pathgpio0gpio1ethernet0ethernet1ethernet2device_typeregcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelinterrupts#interrupt-cellsinterrupt-controllerlinux,phandlecell-indexpinctrl-namespinctrl-0spi-max-frequencytimeout-msreg-shiftreg-io-widthmarvell,pinsmarvell,functionngpiosgpio-controller#gpio-cells#clock-cellsmsi-controllerinterrupts-extendedclock-namesphyphy-modedmacap,memcpydmacap,xordmacap,memsetreg-namesclock-output-namesmrvl,clk-delay-cyclesmsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneclock-frequencyenable-method